TWI739857B - Method of fabricating semiconductor device and semiconductor device fabricating equipment - Google Patents

Abstract

A method of fabricating a semiconductor device includes feeding a suppression gas, a source gas, a reactive gas, and a purge gas including an inert gas, into a process chamber in which a substrate is disposed. The suppression gas suppresses the physical adsorption of the source gas onto the substrate. As a result, a thin film is formed on the substrate.

Description

Method for manufacturing semiconductor device and semiconductor device manufacturing equipment

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a thin film of a semiconductor device in an opening having a high aspect ratio.

As semiconductor devices become highly integrated and miniaturized, there is an increasing need for technologies for increasing the capacitance of dynamic random access memory (DRAM) devices. In order to increase the capacitance in a limited area, various methods can be used, such as using a high-k dielectric material as the dielectric layer, reducing the thickness of the dielectric layer and increasing the effective area of the lower electrode.

In order to increase the effective area of the lower electrode, the lower electrode may be integrally formed, and the height of the lower electrode may be increased. That is, a cylindrical, laminated, or concave lower electrode can be formed. In these cases, the lower electrode may have a relatively large size in all three dimensions and have an interior with a relatively high aspect ratio (height-to-width ratio). However, it is difficult to form a thin film with a uniform thickness on a three-dimensional (3D) lower electrode with a high aspect ratio inside.

According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device, the method comprising: providing a substrate, and forming a thin film on the substrate using the following process, the process including feeding a suppressing gas onto the substrate, A source gas is fed, a reaction gas is fed, and a purge gas including an inert gas is fed, and wherein the suppression gas suppresses the source gas from being physically adsorbed by the substrate.

According to another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device, the method comprising forming a lower electrode layer having a three-dimensional (3D) cylindrical structure on a substrate, and forming a dielectric conformally on the lower electrode layer. An electrical layer, and an upper electrode layer is conformally formed on the dielectric layer, and wherein the forming the upper electrode layer includes feeding a halogen-containing suppressing gas on the substrate, feeding a source gas containing titanium, and feeding a source gas containing titanium The reaction gas of nitrogen and the purge gas containing inert gas are fed.

According to another aspect of the inventive concept, there is provided a method of manufacturing a semiconductor device, the method comprising supporting a structure in which an opening having a certain aspect ratio is defined in a processing chamber, and on the structure, included in the A film formation process for forming a film in the opening. The structure has an upper surface and the opening extends from the upper surface in the structure such that the inner bottom surface of the structure defines the bottom of the opening and the inner side surface of the structure defines the sides of the opening. The film forming process includes forming a film conformally on the top surface and the inner bottom surface of the structure on the structure, and includes feeding a source gas into a processing chamber, and wherein the source gas is The precursor of the film and at least a part of the source gas is adsorbed by the structure at the top surface and the inner bottom surface of the structure; the reaction gas is fed into the processing chamber, and wherein the reaction gas is the precursor of the film And feed the suppressed gas into the processing chamber, and wherein the suppressed gas is not a precursor of the film, does not react with the source gas, and at least a part of the suppressed gas is affected by the structure The top surface and the inner bottom surface of the adsorption; and the inert gas is fed into the processing chamber to purge at least a part of the gas in the processing chamber of the chamber, and wherein the fed inert gas is in the film The forming process is performed at one or more points after the source gas has been fed into the processing chamber.

According to another aspect of the inventive concept, there is provided a semiconductor device manufacturing equipment including: a chamber; a substrate support disposed in the chamber and on which a substrate is mounted; and a source gas is supplied to A source gas supplier in the chamber; a reaction gas supplier that supplies reaction gas to the chamber; a suppression gas supply to a suppression gas supplier in the chamber, the suppression gas suppresses the source gas Physical adsorption onto the substrate; and supplying the first purge gas to the first purge gas supplier in the chamber.

Hereinafter, examples of the inventive concept will be described with reference to the drawings.

FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 2 is a diagram illustrating the principle of a method of manufacturing a semiconductor device according to some examples of the inventive concept. 3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. 4A and 4B are cross-sectional views illustrating a thin film formed by a method of manufacturing a semiconductor device according to some examples of the inventive concept.

1, an example of a method of manufacturing a semiconductor device according to the inventive concept includes feeding a suppressing gas (step S11), feeding a source gas (step S15), and feeding a reaction gas (step S19) into a processing chamber. The method of manufacturing a semiconductor device according to the concept of the present invention may further include feeding a first purge gas (step S13), feeding a second purge gas (step S17), and feeding a third purge gas (step S20) into the processing chamber .

More specifically, the method of manufacturing a semiconductor device according to the concept of the present invention may include feeding a suppressing gas onto a substrate disposed in a chamber (step S11), and purging the suppressing gas adsorbed on the substrate with a first purge gas (Step S13), feed the source gas into the chamber (Step S15), purge the source gas not adsorbed on the substrate by feeding the second purge gas (Step S17), and feed the reaction gas (Step S19) to make The reaction gas reacts with the source gas adsorbed on the substrate, and a third purge gas is fed (step S20) to purge the unreacted source gas and the reaction gas, and thereby form a thin film including an electrode layer on the substrate. The method of manufacturing a semiconductor device according to the concept of the present invention may be performed by, but not limited to, atomic layer deposition (ALD).

That is, the method of manufacturing a semiconductor device according to the inventive concept may include forming a thin film. For example, the method of manufacturing a semiconductor device according to the inventive concept may form an electrode layer on a substrate or a dielectric layer. The electrode layer may include a compound containing Ti and N, such as, for example, TiN, TiSiN, TiAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN, TiOCN, or TiSiCN.

Hereinafter, the method of manufacturing a semiconductor device according to the concept of the present invention will be described by taking the formation of a TiN layer as an example. However, the inventive concept is not limited to forming TiN layers.

The source gas and the reaction gas are precursors of the TiN film to be formed. Therefore, feeding the source gas (ie, step S15) may include feeding a source gas containing a titanium-based compound. For example, the titanium-based compound may be, but is not limited to, TiCl ₄ . Feeding the reaction gas (that is, step S19) may include feeding a reaction gas containing a nitride-based compound. For example, the nitride-based compound may be, but is not limited to, NH ₃ .

The suppression gas has a different composition from the source gas and may not be a precursor of the film. The suppression gas may not react chemically with the reaction gas either. Specifically, the suppressing gas may include a compound containing a halogen atom or a compound containing an unsaturated bond. For example, the suppressing gas may include at least one of alkyl halides, alkenyl halides, alkynyl halides, alkenes, alkynes, and combinations thereof. For example, the suppression gas may include tetrachloropropane or dichloroethylene.

In some examples, each of the alkyl halide, alkenyl halide, and alkynyl halide may include a linear, branched, or cyclic halogenated hydrocarbon group containing 1 to 10 carbon atoms. In addition, each of the alkene and the alkyne may include a linear, branched, or cyclic hydrocarbon group containing 1 to 10 carbon atoms.

In the case where the number of carbon atoms of the halogenated hydrocarbon group or the hydrocarbon group exceeds 10, the suppressing gas may not easily suppress the source gas from being physically adsorbed on the substrate.

In some examples, the alkyl halide, alkenyl halide, and alkynyl halide may each contain 1 to 10 halogen atoms.

In the case where the number of halogen atoms of each of the alkyl halide, alkenyl halide, and alkynyl halide exceeds 10, the suppressing gas may not easily suppress the physical adsorption of the source gas on the substrate.

The suppression gas can suppress the physical adsorption of the source gas onto the substrate. Therefore, in the case where the source gas is TiCl4, the suppression gas may not contain oxygen and nitrogen and may be a gas that does not react with the source gas.

Therefore, step S11 can reduce the rate at which the source gas is adsorbed onto the substrate on which the thin film is to be formed.

Figure 2 shows the relationship between the deposition rate and the purge time after the suppression gas is fed. Referring to Figure 2, the reference character "a" indicates _{the deposition rate when TiCl 4} source gas and NH ₃ reaction gas are used, but the suppressor gas is not used for ALD, and the reference character "b" indicates when TiCl ₄ source gas, The deposition rate when the NH ₃ reaction gas and the tetrachloropropane suppression gas are used for ALD, and the reference character "c" represents the deposition rate when the TiCl ₄ source gas, the NH ₃ reaction gas, and the ethylene dichloride suppression gas are used for ALD.

The growth rate of the film when the suppressed gas is used is lower than that when the suppressed gas is not used. That is, according to the concept of the present invention, the gas is suppressed from being adsorbed onto the substrate and thus over-adsorption of the source gas can be suppressed. Therefore, the growth rate of the thin film can be suppressed, and a conformal thin film can be formed. Figure 2 shows that after feeding the suppressing gas, the deposition rate does not increase with the purge time, and this means that the suppressing gas is not easily "desorbed" and therefore its effect will not be greatly reduced over time.

Hereinafter, the formation of a conformal thin film using the method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIGS. 3A and 3B.

The cross-sectional view of FIG. 3A shows the degree of adsorption of the source gas during the film formation period using the source gas and the reaction gas but the suppressing gas is not used, and the cross-sectional view of FIG. The degree of gas adsorption.

3A and 3B, the substrate 10 has a hole 11 with a high aspect ratio, and the upper surface A, the lower surface C and the side wall B are exposed. The length of the arrow shown in each of FIGS. 3A and 3B indicates the degree of adsorption of the source gas.

That is, as illustrated in FIG. 3A, when a thin film is formed without using a suppressing gas, the degree of adsorption a1 of the source gas at the upper surface A becomes higher with time than the degree of adsorption of the source gas at the lower surface C c1.

However, as illustrated in FIG. 3B, when a thin film is formed using suppressed gas according to the concept of the present invention, the degree of adsorption a2 of the source gas at the upper surface A becomes similar to that of the source gas at the lower surface C over time. The degree of adsorption c2. This is because the excessive adsorption of the source gas at the upper surface A is suppressed by the suppressed gas. More specifically, the excessive adsorption of the source gas, which may occur due to the source gas being physically adsorbed on the upper surface A, can be suppressed by the suppressing gas.

4A and 4B respectively show the uniformity of the thin film 21 formed in the case shown in FIG. 3A and the uniformity of the thin film 21 formed in the case shown in FIG. 3B. 4A and 4B, the thickness of the thin film 21 formed by suppressing excessive adsorption of the source gas at the upper surface A of the substrate 10 by using the suppressing gas (see FIG. 4B) is greater than the thickness of the film 21 formed without using the suppressing gas ( See Figure 4A) Uniformity. Specifically, as shown in FIG. 4A, the thickness ta1 of the film 21 formed on the upper surface A is significantly larger than the thickness tc1 of the film 21 formed on the bottom surface C and the thickness tb1 of the film on the side wall surface B. On the other hand, as shown in FIG. 4B, the thickness ta2 of the film 21 formed on the upper surface A and the thickness tc2 of the film 21 formed on the bottom surface C are substantially the same. In addition, the thickness ta2 of the film 21 formed on the upper surface A is substantially the same as the thickness tb2 of the film on the side wall surface B.

The photos provided in FIGS. 5A and 5B show the thickness of the film formed as shown in FIGS. 4A and 4B. More specifically, FIG. 5A is a photograph of a thin film L1 formed by performing ALD using a source gas and a reaction gas but not using a suppressor gas, and FIG. 5B is a photograph of a thin film L2 formed by performing ALD using a suppressor gas, source gas, and reactive gas Photo.

Referring to FIG. 5A, the film L1 is relatively thin inside the trench H1 and relatively thick outside the trench H1. On the other hand, as shown in FIG. 5B, the thin film L2 has a relatively uniform thickness on the inside and outside of the trench H2.

That is, the method of manufacturing a semiconductor device according to some examples of the inventive concept can form a thin film having a uniform thickness in a trench region having a high aspect ratio. The thin film may be a thin film formed in a region defining any intermediate structure of openings having a certain aspect ratio, especially openings having a high aspect ratio. Therefore, the method for manufacturing a semiconductor device according to the concept of the present invention is suitable for the combination of shallow trench isolation (STI), interlayer dielectric layer (ILD), and inter-metal dielectric layer (inter-metal dielectric layer). The dielectric layer (IMD) or the structure of the cylindrical capacitor area forms a thin film.

Hereinafter, some examples of the method of manufacturing a semiconductor device according to the concept of the present invention will be described by taking the manufacturing of a cylindrical capacitor as an example. However, as already mentioned above, the inventive concept is not limited to the manufacture of semiconductor devices including cylindrical capacitors. That is, the method of manufacturing a semiconductor device according to the concept of the present invention is suitable for forming a thin film in a plurality of different kinds of regions that define an opening having a high aspect ratio.

Hereinafter, an example of a method of manufacturing a semiconductor device according to the inventive concept will be described in more detail with reference to FIGS. 1 and 6 to 18.

6 to 18 are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to the inventive concept.

Referring to FIG. 6, a semiconductor device obtained by a method of manufacturing a semiconductor device according to the concept of the present invention may include a substrate 100, a first ILD 135, a second interlayer dielectric layer (second ILD) 137, an etching stop layer 140, and a conductive metal layer. 150. The capacitor CP1 and the cover layer 220.

For example, the substrate 100 may have a memory cell array area and a surrounding area. A field oxide layer 130 may be formed on the substrate 100 to separate each element, and a gate electrode 120 having a spacer 125 may also be formed on the substrate 100.

The substrate 100 may be formed of at least one semiconductor material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP, and a silicon-on-insulator (SOI) substrate may be used as the substrate 100.

The first interlayer dielectric layer (first ILD) 135 may be formed on the entire surface of the substrate 100 where the gate electrode 120 is formed. A bitline contact 162 may be formed to be inserted between the gate electrodes 120 to penetrate the first ILD 135. The bit line contact window 162 connects the substrate 100 and the bit line 164, and the bit line 164 connected to the substrate 100 through the bit line contact window 162 may be formed on the first ILD 135.

A second ILD 137 may be formed on the first ILD 135. A storage node contact window 172 may be formed, and the storage node contact window 172 is connected to the substrate 100 via the first ILD 135 and the second ILD 137. For example, the storage node contact window 172 may include a stack of polysilicon plugs, TiN and Ti barrier layers, but the concept of the present invention is not limited to this example.

An etch stop layer 140 may be formed on the second ILD 137 and the storage node contact window 172. More specifically, the etching stop layer 140 can prevent the etching of the mold layer (the mold layer 145 of FIG. 9) formed on the etching stop layer 140 from proceeding to below the etching stop layer 140.

For example, the etch stop layer 140 may include, but is not limited to, silicon nitride. The etch stop layer 140 may include a different material from the mold layer (the mold layer 145 of FIG. 9) to prevent the etching process performed on the mold layer (the mold layer 145 of FIG. 9) from proceeding under the etch stop layer 140.

The conductive metal layer 150 may be disposed at the bottom of the storage node hole (the storage node hole 153 of FIG. 11 ), which is formed above the storage node contact window 172. That is, the conductive metal layer 150 may be disposed between the storage node hole (storage node hole 153 of FIG. 11) and the lower electrode layer 200a. The conductive metal layer 150 may include, but is not limited to, one of Ag, Au, Pt, Al, and Cu. However, in some examples of capacitors formed according to the concept of the present invention, the conductive metal layer 150 may be omitted.

In one example, the capacitor CP1 may be a one-cylinder-storage (OCS) type capacitor. More specifically, the capacitor CP1 may be formed around the storage node hole (the storage node hole 153 of FIG. 11), which has a substantially uniform width at the top and bottom of the capacitor CP1, and therefore, the capacitor CP1 The capacitor CP1 may also have a substantially uniform width at the top and bottom. As used herein, the expression that an element or feature has a "substantially uniform width" means that within a predetermined range of errors that may occur due to the inherent characteristics of the manufacturing method during the formation of the element or feature, the element or feature The width is basically uniform. Alternatively, the width of the capacitor CP1 may be different from the top to the bottom of the capacitor CP1.

The capacitor CP1 may include a lower electrode layer 200a, a dielectric layer 205a, and an upper electrode layer 210a.

The lower electrode layer 200a may include a cylindrical lower electrode as the lower electrode of the capacitor CP1.

The lower electrode layer 200a may include a conductive oxide. For example, the lower electrode layer 200a may include Pt, Ru, Ir, PtO, RuO 2, IrO 2, SrRuO 3, BaRuO 3, CaRuO 3 , and / or (Ba, Sr) RuO ₃ and may be formed as a single layer or two Layers or laminates of more than two layers.

The lower electrode layer 200a may further include a metal having refractive power or a refractory metal nitride. For example, the lower electrode layer 200a may include Ti, TiN, W, WN, Ta, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN and/or TiSiCN and may be formed It is in the form of a single layer or a stack of two or more layers.

In the case where the lower electrode layer 200 a is formed on the conductive metal layer 150, the lower electrode layer 200 a may include a different material from the conductive metal layer 150. In other words, the lower electrode layer 200a and the conductive metal layer 150 may include different materials so as to be completely different from each other, and at the same time, they will not affect each other physically or chemically.

A dielectric layer 205a may be formed on the lower electrode layer 200a. More specifically, the dielectric layer 205a may be formed on the outer sidewall, inner sidewall, and inner bottom surface of the lower electrode layer 200a and on the etching stop layer 140.

The dielectric layer 205a may include three or more than three component dielectric materials. For example, the dielectric layer 205a may include (Ba, Sr)TiO ₃ (BST), SrTiO ₃ , BaTiO ₃ , PZT, PLZT, (Ba, Sr)(Zr, Ti)O ₃ (BSZTO), Sr(Zr) , Ti)O ₃ (SZTO), Ba(Zr, Ti)O ₃ (BZTO), (Ba, Sr)ZrO ₃ (BSZO), SrZrO ₃ or BaZrO ₃ . Alternatively, the dielectric layer 205a may include a two-component dielectric material, such as ZrO ₂ , HfO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ or TiO ₂ , and can be achieved by using only any one of these materials or stacking these materials Two types or more than two types are formed.

The upper electrode layer 210a may include the upper electrode of the capacitor CP1.

More specifically, the upper electrode layer 210a may conformally cover the dielectric layer 205a and may have the same surface profile as the dielectric layer 205a.

The upper electrode layer 210a may include a material having a high work function, such as Pt, Ru, or Ir. In an example where the upper electrode layer 210a contains a material having a high work function, the difference in work function between the upper electrode layer 210a and the dielectric layer 205a may increase, and therefore, the leakage current of the capacitor CP1 may be controlled.

The upper electrode layer 210a may include a conductive oxide. For example, the upper electrode layer 210a may include Pt, Ru, Ir, PtO, RuO 2, IrO 2, SrRuO 3, BaRuO 3, CaRuO 3 , and / or (Ba, Sr) RuO ₃ and may be formed as a single layer or two Layers or laminates of more than two layers.

A cap layer 220 may be formed on the upper electrode layer 210a to suppress the growth and coalescence of crystal grains of the upper electrode layer 210a. To this end, the capping layer 220 may include ZrO ₂ , Al ₂ O ₃ , HfO ₂ , LaAlO ₃ , BaZrO ₃ , SrZrO ₃ , BST, SrTiO ₃ , BaTiO ₃ , TiO ₂ and/or SiO ₂ , and may be formed as a single unit The form of a layer or a stack of two or more layers.

The example of the basic structure of the semiconductor device manufactured by the method of manufacturing the semiconductor device according to the inventive concept has been described above with reference to FIG. 6. Hereinafter, the lower electrode layer 200a, the dielectric layer 205a, and the upper electrode layer 210a will be described in more detail with reference to FIGS. 7 to 18.

Referring to FIG. 7, the contact hole is formed by partially etching the second ILD 137 formed on the substrate 100. Subsequently, the top surface of the second ILD 137 is exposed by filling the contact hole with a conductive material and performing planarization, thereby forming the storage node contact window 172.

Although not shown, the structure depicted in FIG. 7 includes all structures below the etching stop layer 140 shown in FIG. 6. That is to say, FIG. 7 is used to illustrate the commonly used process, and then the etching stop layer 140 is formed.

Referring to FIG. 8, an etch stop layer 140 is formed on the second ILD 137.

For example, the etch stop layer 140 may be formed of, but not limited to, silicon nitride. The etch stop layer 140 may be formed by depositing silicon nitride through chemical vapor deposition (CVD).

Referring to FIG. 9, a mold layer 145 is formed on the etching stop layer 140.

The mold layer 145 is provided to form the lower electrode of the capacitor CP1. Therefore, the molded layer 145 may be formed as high as or higher than the lower electrode of the capacitor CP1.

The mold layer 145 may be formed of a material that has etching selectivity to the etch stop layer 140, that is, etches at a higher rate in the presence of a given etchant. The mold layer 145 may also be formed of a material that can be easily removed using a wet etching method (described later). For example, the mold layer 145 may be formed of, but not limited to, polysilicon.

Referring to FIG. 10, a mask pattern 147 is formed on the mold layer 145.

More specifically, the formed mask pattern 147 used as a mask during the etching of the mold layer 145 may have an opening having substantially the same width as the storage node hole (storage node hole 153 of FIG. 13) passing therethrough. As used herein, the expression that two elements or features have "substantially the same width" is used to describe the range of errors that may occur due to inherent characteristics in the manufacturing method during the formation of these two elements or features. The widths of the two elements or features are substantially equal.

Referring to FIGS. 11 and 12, the mold layer 145 is etched using the mask pattern 147 as an etching mask.

More specifically, the mold layer 145 is wet-etched by using the mask pattern 147 as an etching mask to expose the top surface of the storage node contact window 172. Subsequently, a conductive metal layer 150 may be formed on the exposed top surface of the storage node contact window 172, but the inventive concept is not limited to this example. That is, the conductive metal layer 150 can be omitted.

After the storage node holes 153 are formed, the mask pattern 147 may be removed.

Referring to FIG. 13, the first electrode layer 200 is formed along the side and bottom of the storage node hole (the storage node hole 153 of FIG. 12) and the top surface of the mold layer 145.

More specifically, the formed first electrode layer 200 may have the same contour as the top surfaces of the storage node holes 153 and the mold layer 145 and do not fill the storage node holes 153.

The first electrode layer 200 may include, but is not limited to, metal and/or conductive oxide. That is, the first electrode layer 200 may include Pt, Ru, Ir, PtO, RuO 2, IrO 2, SrRuO 3, BaRuO 3, CaRuO 3 , and / or (Ba, Sr) RuO ₃ and may be formed as a single layer or Two-layer or more than two-layer laminated form.

The first electrode layer 200 may further include metal nitride. For example, the first electrode layer 200 may include Ti, TiN, W, WN, Ta, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN and/or TiSiCN and may It is formed into a single layer or a laminated form of two or more layers.

The first electrode layer 200 may be formed by ALD, CVD, or physical vapor deposition (PVD). The first electrode layer 200 is preferably formed by ALD, thereby providing excellent step coverage characteristics.

That is, the first electrode layer 200 may be formed using the method of manufacturing a semiconductor device according to the inventive concept.

More specifically and referring to FIGS. 1 and 13, forming the first electrode layer 200 on the side and bottom of the storage node hole 153 and the top surface of the mold layer 145 may include feeding a suppressing gas into the chamber of the ALD device And a substrate 100 is placed in the chamber (step S11).

Feeding the suppressing gas (ie, step S11) may include feeding a suppressing gas including a halogen atom-containing compound or an unsaturated bond-containing compound. For example, the suppressing gas may include at least one of alkyl halides, alkenyl halides, alkynyl halides, alkenes, alkynes, and combinations thereof. The suppression gas does not contain oxygen and nitrogen, and may be a gas that does not react with the source gas.

The suppression gas is fed into the chamber for a predetermined amount of time, which is sufficient for at least a portion of the suppression gas to be physically and/or chemically adsorbed to the sides and bottom of the storage node hole 153的surface and the top surface of the molding layer 145. A portion of the inhibiting gas fed into the chamber may remain unadsorbed in the chamber, that is, not physically and/or chemically adsorbed to the surface of the side and bottom of the storage node hole 153 and the surface of the molding layer 145 On the top surface.

Subsequently, the suppression gas that is not physically and/or chemically adsorbed to the surfaces of the side and bottom defining the storage node holes 153 and the top surface of the molding layer 145 is purged by feeding the first purge gas (step S13) . An inert gas can be used as the first purge gas and can be Ar, He, Kr, Xe, N ₂ or a combination thereof. Alternatively, the suppression gas may be purged by performing a suction process (for example, a vacuum suction process in which a vacuum pump attached to an outlet of the processing chamber generates a vacuum or negative pressure in the processing chamber). As yet another alternative, the suppression gas may be purged by simultaneously performing the feeding and suction processes of the first purge gas.

Subsequently, the source gas is fed into the chamber (step S15).

The source gas is fed into the chamber for a predetermined period of time, which is sufficient for at least a portion of the source gas to react with the side and bottom surfaces defining the storage node holes 153 and the top surface of the molding layer 145, or adsorb chemically To the surface. Another part of the source gas can remain unadsorbed in the chamber.

Since the suppression gas has been adsorbed on the surfaces defining the side and bottom of the storage node hole 153 and the top surface of the molding layer 145, the physical adsorption of the source gas can be suppressed.

Feeding the source gas may include feeding a source gas containing a titanium-based compound. For example, the titanium-based compound may be, but is not limited to, TiCl ₄ . The inert gas can be fed together with the source gas. For example, the inert gas may be Ar, He, Kr, Xe, N ₂ or a combination thereof.

In order to purge the source gas that has not reacted with the substrate 100, a second purge gas may be fed (step S17).

The purge of the source gas can be performed by feeding the second purge gas. Inert gas can be used as the second purge gas. For example, the inert gas may be Ar, He, Kr, Xe, N ₂ or a combination thereof. Alternatively, the source gas can be purged by performing a suction process. As another alternative, the source gas may be purged by simultaneously performing the feeding and sucking process of the second purge gas.

Subsequently, by applying a bias to the substrate 100, an electric field perpendicular to the substrate 100 is formed. The application of the bias voltage to the substrate 100 can be performed in various ways. For example, an electric field perpendicular to the substrate 100 can be formed by applying a bias voltage to electrodes installed at the top and bottom of the processing chamber. Alternatively, an electric field perpendicular to the substrate 100 can be formed by applying a bias to the top and bottom of the chuck on which the substrate 100 is carried. The direction of the electric field intended to be formed will typically depend on the type of reaction gas intended to be fed.

Subsequently, the reaction gas is fed into the chamber (step S19).

The reaction gas may be fed into the chamber, and then may be converted into plasma in the presence of an electric field formed perpendicular to the substrate 100.

The reaction gas converted into plasma may have an unstable energy state, but may have higher reactivity.

The reaction gas converted into plasma reacts with the electric field formed perpendicular to the substrate 100 and the source gas adsorbed on the sidewall and bottom surface of the storage node hole 153 and the top surface of the mold layer 145, and thereby form the first electrode layer 200 .

Purge the unreacted part of the reaction gas. An example of a method of manufacturing a semiconductor device according to the inventive concept includes repeating the steps described above, that is, performing more than one cycle until a thin film having a desired thickness is formed, each of the cycles including the steps described above.

It has been described that a thin film is formed by forming an electric field perpendicular to the substrate 100 (not the upper surface thereof), but in order to deposit the thin film more efficiently, the electric field may also be formed in a direction inclined with respect to the substrate 100 (not the upper surface thereof).

14 and 15, the sacrificial layer 203 is formed on the first electrode layer 200 to fill the storage node hole (the storage node hole 153 of FIG. 12).

The sacrificial layer 203 may be formed of a material having the same characteristics as the material of the molding layer 145.

After the sacrificial layer 203 is formed, the sacrificial layer 203 and the first electrode layer 200 are planarized until the top surface of the mold layer 145 is exposed. The planarization of the sacrificial layer 203 and the first electrode layer 200 may include a chemical mechanical polishing (CMP) process.

After the sacrificial layer 203 and the first electrode layer 200 are planarized, the cylindrical lower electrode layer 200a may be formed. The lower electrode layer 200a may serve as a lower electrode of an OCS type capacitor.

After the lower electrode layer 200a is formed, the lower electrode layer 200a may be subjected to a heat treatment process.

More specifically, by performing a heat treatment process, the crystal grains of the lower electrode layer 200a can be fully grown before the dielectric layer (dielectric layer 205a in FIG. 17) is formed. In other words, after the dielectric layer (dielectric layer 205a in FIG. 17) is formed, the crystal grains of the lower electrode layer 200a may no longer grow, and the characteristics of the dielectric layer (dielectric layer 205a in FIG. 17) It may not change during the manufacturing process.

Referring to FIG. 16, the mold layer 145 and the sacrificial layer 203 are removed.

The mold layer 145 and the sacrificial layer 203 are preferably removed by a wet etching method, thereby not causing plasma-induced attack, thereby preventing damage to the lower electrode layer 200a.

By removing the mold layer 145 and the sacrificial layer 203, both the outer sidewall and the inner sidewall of the lower electrode layer 200a can be exposed.

Referring to FIG. 17, the dielectric layer 205a may be formed by depositing a two-component dielectric material including a metal oxide on the lower electrode layer 200a and the etching stop layer 140. The dielectric layer 205a may include a high-k dielectric material (that is, may have higher dielectric properties).

The dielectric layer 205a may be formed by ALD, CVD, or PVD. The dielectric layer 205a can also be formed using a thin film forming method according to the concept of the present invention.

After the dielectric layer 205a is formed, the upper electrode layer 210a may be formed by depositing a material including metal on the dielectric layer 205a. The upper electrode layer 210a may also be formed using a thin film forming method according to the concept of the present invention.

The upper electrode layer 210a may be formed along the surface profile of the dielectric layer 205a, thereby not completely filling the gap between the lower electrode layer 200a and another lower electrode layer 200a.

The upper electrode layer 210a may be formed by ALD, CVD, or PVD. The upper electrode layer 210a may also be formed using a thin film forming method according to the concept of the present invention.

Referring to FIG. 18, a capping layer 220 is formed that covers the entire top surface of the upper electrode layer 210a. The capping layer 220 may be formed for suppressing grain growth and coalescence of the upper electrode layer 210a. In order to effectively suppress the grain growth of the upper electrode layer 210a using the capping layer 220, the capping layer 220 may be formed to fill a gap between the lower electrode layer 200a and another lower electrode layer 200a.

The capping layer 220 may be formed by one of ALD, CVD, PVD, and spin coating methods (in the case where the capping layer 220 is, for example, spin on glass (SOG)).

By forming the cap layer 220 in the above-mentioned manner, the semiconductor device of FIG. 6 can be manufactured.

In short, the lower electrode layer 200a and the upper electrode layer 210a can be formed by the method according to the concept of the present invention. Therefore, the lower electrode layer 200a and the upper electrode layer 210a having a predetermined width may be formed in a hole having a high aspect ratio (ie, the storage node hole 153).

As described above, the inventive concept is not limited to forming a conformal thin film in the storage node hole 153. That is, the concept of the present invention is also applicable to forming a conformal thin film in a hole or trench with a high aspect ratio. Therefore, the term "opening" can describe any of these features (storage node holes or other types of holes or trenches) or other examples of features of a semiconductor device.

Hereinafter, an example of a method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIG. 19.

The example of FIG. 19 is basically the same as the example of FIG. 1, except that the suppression gas is fed after the source gas is fed. Therefore, the following description of the example of FIG. 19 will mainly focus on the differences between this example and the example of FIG. 1.

19, the method of manufacturing a semiconductor device according to the concept of the present invention includes feeding a source gas (step S21), feeding a first purge gas (step S23), feeding a suppressing gas (step S25), and feeding a second purge gas (step S25). S27) and feeding reaction gas (step S29).

Steps S21, S23, S25, S27, and S29 are basically the same as steps S15, S13, S11, S17, and S19 of FIG. 1, respectively.

However, unlike the example of FIG. 1, feeding the suppressing gas (ie, step S25) is performed after feeding the source gas (ie, step S21). That is, in this example of the inventive concept, the feeding of the suppressing gas is performed after the source gas is adsorbed to the substrate, and therefore, the suppressing gas can drive off the source gas that has been adsorbed on the substrate and be adsorbed to the substrate. superior. In this example of the inventive concept, as in the example of FIG. 1, the suppressing gas adsorbed on the substrate can prevent excessive adsorption of the source gas in a specific area.

Therefore, this example of the method of manufacturing a semiconductor device according to the inventive concept can also form a conformal thin film having a substantially uniform thickness on the substrate.

Hereinafter, an example of a method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIG. 20.

The example of FIG. 20 is basically the same as the example of FIG. 1, except that the suppression gas is fed after the reaction gas is fed. Therefore, the following description of the example of FIG. 20 will mainly focus on the differences between this example and the example of FIG. 1.

20, the method of manufacturing a semiconductor device according to the concept of the present invention includes feeding a source gas (step S31), feeding a first purge gas (step S33), feeding a reaction gas (step S35), and feeding a second purge gas (step S35). S37) and feeding suppression gas (step S39).

Steps S31, S33, S35, S37, and S39 are basically the same as steps S15, S13, S19, S17, and S11 of FIG. 1, respectively.

Feeding the suppressing gas (ie, step S39) is performed after feeding the reaction gas (ie, step S35). The suppression gas can drive off excessively adsorbed source gas and reaction gas on the substrate. Therefore, this example of the method of manufacturing a semiconductor device according to the inventive concept can also form a conformal thin film having a substantially uniform thickness on the substrate.

Hereinafter, another example of a method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIG. 21.

The example of FIG. 21 is basically the same as the example of FIG. 1, except that the source gas and the suppression gas are fed together. Therefore, the following description of the example of FIG. 21 will mainly focus on the differences between this example and the example of FIG. 1.

Referring to FIG. 21, the method of manufacturing a semiconductor device according to the concept of the present invention includes feeding a source gas and a suppressing gas (step S41), feeding a first purge gas (step S43), and feeding a reaction gas (step S45).

Steps S41, S43, and S45 are basically the same as steps S15 and S11, S13 and S19 of FIG. 1, respectively.

In this example of the inventive concept, the source gas and the suppression gas may be fed together (step S41). The suppression gas can be adsorbed to the substrate while suppressing the source gas to be adsorbed to the substrate. Therefore, this example of the method of manufacturing a semiconductor device according to the inventive concept can form a conformal thin film having a substantially uniform thickness on a substrate.

Hereinafter, another example of a method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIG. 22.

The example of FIG. 22 is basically the same as the example of FIG. 1, except that the reaction gas and the suppression gas are fed together. Therefore, the following description of the example of FIG. 22 will mainly focus on the differences between this example and the example of FIG. 1.

Referring to FIG. 22, the method of manufacturing a semiconductor device according to the inventive concept includes feeding a source gas (step S51), feeding a first purge gas (step S53), and feeding a reaction gas and a suppressing gas (step S55).

Steps S51, S53, and S55 are basically the same as steps S15, S13, and S19 and S11 of FIG. 1, respectively.

In this example of the inventive concept, the reaction gas and the suppression gas may be fed together (step S55). The suppression gas can desorb the source gas already adsorbed on the substrate and purge the excessively adsorbed source gas on the substrate. Therefore, this example of the method of manufacturing a semiconductor device according to the inventive concept can form a conformal thin film on a substrate.

Hereinafter, an example of a semiconductor device manufacturing apparatus according to the inventive concept will be described with reference to FIGS. 23 and 24.

Hereinafter, some examples of semiconductor device manufacturing equipment according to the concept of the present invention will be described by using plasma to form a thin film as an example. However, the inventive concept is not limited to the use of plasma to form thin films. That is, the semiconductor device manufacturing equipment according to the concept of the present invention is also applicable to semiconductor device manufacturing equipment that does not use plasma to form a thin film, for example, semiconductor device manufacturing equipment that uses heat to form a thin film.

FIG. 23 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept.

23, the semiconductor device manufacturing equipment includes a chamber 310, a substrate support 320, a gas injector 330, a suppression gas supplier 410, a source gas supplier 420, a reaction gas supplier 430, and a purge gas supplier 440.

The chamber 310 may have a cylindrical shape and may contain a reaction space. The chamber 310 may additionally include a pump 340, a pressure controller 312, and a heater 314.

The pump 340 may be connected to the chamber 310 to pump out impurities and reaction byproducts in the chamber 310. In addition, the pump 340 may form and maintain a vacuum in the chamber 310.

The pressure controller 312 can control the pressure inside the chamber 310. In addition, the heater 314 may heat the inside of the chamber 310 to improve reactivity. Although not specifically illustrated, the chamber 310 may additionally include a cooler for cooling the heated chamber 310.

The substrate support 320 may be disposed in the chamber 310 to accommodate the substrate S. The substrate support 320 may be fixed to the lower part of the chamber 310, and may be elevated and/or rotated within the chamber 310 as needed.

The substrate S may be a silicon substrate, but the concept of the invention is not limited thereto. That is, various other substrates that can be formed into thin films can be used as the substrate S.

Although not specifically illustrated, the substrate support 320 may include a device for loading the substrate S on the top surface of the substrate support 320. For example, the substrate support 320 may include a plurality of lift pin parts for loading and unloading the substrate S.

The substrate support 320 may be connected to the lower power source 325. The lower power source 325 may be connected to the substrate support 320 to provide voltage to the substrate support 320. The lower power supply 325 may be an alternating current (AC) power supply, but the concept of the present invention is not limited to this. That is, alternatively, the lower power source 325 may be a direct current (DC) power source.

The gas injector 330 may be disposed in the chamber 310 and may inject gas into the chamber 310. More specifically, the gas injector 330 may be connected to the source gas supplier 420, the reaction gas supplier 430, the suppression gas supplier 410, or the purge gas supplier 440 to inject various gases into the chamber 310. The gas injector 330 may be fixed to the upper part of the chamber 310, and may be raised and/or rotated within the chamber 310 as needed.

The gas injector 330 may be connected to the upper power source 335. The upper power source 335 may be connected to the gas injector 330 to provide voltage to the gas injector 330. The upper power source 335 may be an AC power source, but the inventive concept is not limited thereto. That is, alternatively, the upper power source 335 may be a DC power source.

In some examples, the lower power source 325 and the upper power source 335 may form an electric field inside the chamber 310. For example, the lower power source 325 and the upper power source 335 may form an electric field passing through the substrate support 320 and the gas injector 330 inside the chamber 310.

Therefore, the gas injected into the chamber 310 may be plasmatized. For example, the reaction gas supplied into the chamber 310 may be plasma-ized under the action of the electric field formed by the lower power source 325 and the upper power source 335. The plasmaized gas may have an unstable energy state, but may have higher reactivity.

The suppression gas supplier 410 may be connected to the chamber 310 and may supply the suppression gas into the chamber 310. In some examples, the suppression gas supplier 410 may be controlled by the first valve 410V and may be connected to the gas injector 330 to supply the suppression gas into the chamber 310.

The source gas supplier 420 may be connected to the chamber 310 and may supply source gas into the chamber 310. In some examples, the source gas supplier 420 may be controlled by the second valve 420V and may be connected to the gas injector 330 to supply the source gas into the chamber 310.

The reaction gas supplier 430 may be connected to the chamber 310 and may supply the reaction gas into the chamber 310. In some examples, the reaction gas supplier 430 may be controlled by the third valve 430V and may be connected to the gas injector 330 to supply the reaction gas into the chamber 310.

The purge gas supplier 440 may be connected to the chamber 310 and may supply the purge gas into the chamber 310. In some examples, the purge gas supplier 440 may be controlled by the first valve 410V, the second valve 420V, and the third valve 430V and may be connected to the gas injector 330 to supply the purge gas into the chamber 310.

The semiconductor device manufacturing equipment may include a suppressed gas controller 412 for controlling the vapor pressure of the suppressed gas. The suppressed gas controller 412 may be connected to the suppressed gas supplier 410 to control the vapor pressure of the suppressed gas.

More specifically, the suppressed gas controller 412 may include a device for heating or cooling the suppressed gas. In the case where the suppressed gas controller 412 heats the suppressed gas, the vapor pressure of the suppressed gas can be increased. In this case, the suppression gas can suppress excessive adsorption of the source gas to a large extent. On the other hand, when the suppressed gas controller 412 cools the suppressed gas, the vapor pressure of the suppressed gas can be lowered. In this case, the suppression gas can suppress excessive adsorption of the source gas to a relatively low degree. That is, the suppression gas controller 412 can control the suppression gas supplied into the chamber 310 and thus can control the formation of the conformal thin film.

Hereinafter, the operation of the semiconductor device manufacturing equipment will be described with reference to FIG. 24.

FIG. 24 is a timing chart explaining the operation of the semiconductor device manufacturing equipment of FIG. 23. More specifically, FIG. 24 may be, for example, a timing diagram showing the timing of supplying gas into the chamber 310 during the atomic layer deposition period.

Referring to Fig. 24, the first valve 410V may provide a pipe for suppressing gas. That is, the suppression gas can be supplied from the suppression gas supplier 410 onto the substrate S in the chamber 310.

After that, the first valve 410V, the second valve 420V, and the third valve 430V can block the suppression gas and provide a pipe for the first purge gas. That is, the first purge gas may be supplied from the purge gas supplier 440 onto the substrate S in the chamber 310. The first purge gas can purge the suppression gas that is not adsorbed on the substrate S.

After that, the second valve 420V can block the first purge gas and provide a pipe for the source gas. That is, the source gas may be supplied from the source gas supplier 420 onto the substrate S in the chamber 310.

After that, the first valve 410V, the second valve 420V, and the third valve 430V can block the source gas and provide a pipe for the second purge gas. That is, the second purge gas may be supplied from the purge gas supplier 440 to the substrate S in the chamber 310. The second purge gas can purge the source gas that is not adsorbed on the substrate S.

After that, the third valve 430V can block the second purge gas and provide a pipe for the reaction gas. That is, the reaction gas may be supplied from the reaction gas supplier 430 onto the substrate S in the chamber 310. Therefore, the reaction gas can react with the source gas adsorbed on the substrate S. Then, the reaction gas can be plasmaized in the chamber 310 under the action of the lower power source 325 and the upper power source 335. The plasma reaction gas can better react with the source gas. However, as described above, the use of plasma to form a thin film is only exemplary. For example, the heat supplied to the chamber 310 may be used to react the reaction gas with the source gas.

After that, the first valve 410V, the second valve 420V, and the third valve 430V can block the reaction gas and provide a pipe for the third purge gas. That is, the third purge gas may be supplied from the purge gas supplier 440 onto the substrate S in the chamber 310. Therefore, the third purge gas can purge unreacted source gas and reaction gas.

Therefore, the semiconductor device manufacturing equipment can provide a semiconductor device with improved reliability.

Hereinafter, an example of semiconductor device manufacturing equipment according to the inventive concept will be described with reference to FIG. 25.

FIG. 25 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept.

Hereinafter, the semiconductor device manufacturing equipment of the example of FIG. 25 will be mainly focused on describing the difference between the example of FIG. 25 and the examples of FIGS. 23 and 24.

Referring to FIG. 25, the semiconductor device manufacturing equipment includes a first purge gas supplier 440a, a second purge gas supplier 440b, and a third purge gas supplier 440c.

The first purge gas supplier 440a, the second purge gas supplier 440b, and the third purge gas supplier 440c may be connected to the suppression gas supplier 410, the source gas supplier 420, and the reaction gas supplier 430, respectively.

More specifically, the first purge gas supplier 440a may be connected to the chamber 310 and the suppression gas supplier 410. Therefore, the first purge gas supplier 440a may supply the first purge gas to purge the suppression gas in the chamber 310.

The first valve 410V′ may be connected to the first purge gas supplier 440a and the suppression gas supplier 410. That is, the first valve 410V' can provide a pipe for the first purge gas or suppression gas. For example, the first valve 410V' can block the first purge gas and provide a pipe for the suppression gas, or can block the suppression gas and provide a pipe for the first purge gas.

The second purge gas supplier 440b may be connected to the chamber 310 and the source gas supplier 420. Therefore, the second purge gas supplier 440b may supply the second purge gas to purge the source gas in the chamber 310.

The second valve 420V′ may be connected to the second purge gas supplier 440b and the source gas supplier 420. That is, the second valve 420V' can provide a pipe for the second purge gas or source gas. For example, the second valve 420V' may block the second purge gas and provide a pipe for the source gas, or may block the source gas and provide a pipe for the second purge gas.

The third purge gas supplier 440c may be connected to the chamber 310 and the reaction gas supplier 430. Therefore, the third purge gas supplier 440c may supply the third purge gas to purge the reaction gas in the chamber 310.

The third valve 430V′ may be connected to the third purge gas supplier 440c and the reaction gas supplier 430. That is, the third valve 430V' can provide a pipe for the third purge gas or reaction gas. For example, the third valve 430V' may block the third purge gas and provide a pipe for the reaction gas, or may block the reaction gas and provide a pipe for the third purge gas.

Hereinafter, semiconductor device manufacturing equipment according to some examples of the inventive concept will be described with reference to FIG. 26.

FIG. 26 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept.

Hereinafter, the semiconductor device manufacturing equipment according to the example of FIG. 26 will be described mainly focusing on differences from the semiconductor device manufacturing equipment according to any one of the examples of FIGS. 23 to 25.

Referring to FIG. 26, the semiconductor device manufacturing equipment includes a gas box 500.

The suppression gas supplier 410 and the source gas supplier 420 are installed in the gas box 500. That is, the gas box 500 can provide at least one of the suppressed gas and the source gas to the chamber 310.

More specifically, the gas tank 500 may include a fourth valve 500V. The fourth valve 500V may be connected to the suppression gas supplier 410 and the source gas supplier 420. In other words, the fourth valve 500V can provide a pipe for at least one of the suppressed gas and the source gas. For example, the fourth valve 500V may block the source gas and provide a pipe for the suppressed gas, or may block the suppressed gas and provide a pipe for the source gas. Alternatively, the fourth valve 500V can provide pipes for both the suppressed gas and the source gas at the same time. In addition, the semiconductor device manufacturing facility includes a first valve 410V', a second valve 420V', and a third valve 430V'.

The first purge gas supplier 440a' may be connected to the chamber 310 and the gas box 500. More specifically, the first purge gas supplier 440a' may be connected to the suppression gas supplier 410 and the source gas supplier 420. Therefore, the first purge gas supplier 440a' can purge at least one of the suppression gas and the source gas supplied into the chamber 310.

Although the concept of the invention has been specifically shown and described with reference to the examples of the concept of the invention, those of ordinary skill in the art should understand that without departing from the spirit and scope of the concept of the invention as defined by the appended claims, they can Various modifications have been made to the form and details of the disclosed examples. Therefore, it is expected that the disclosed examples are to be regarded as illustrative and non-limiting in all aspects, and reference to the appended claims rather than the foregoing description indicates the scope of the inventive concept.

10‧‧‧Base 11‧‧‧Hole 100‧‧‧Base 120‧‧‧Gate electrode 125‧‧‧Interstitial Wall 130‧‧‧Field oxide layer 135‧‧‧The first interlayer dielectric layer 137‧‧‧Second interlayer dielectric layer 140‧‧‧Etching stop layer 145‧‧‧molded layer 147‧‧‧Mask pattern 150‧‧‧Conductive metal layer 153‧‧‧Storage node hole 162‧‧‧Bit line contact window 164‧‧‧Bit Line 172‧‧‧Storage Node Contact Window 200‧‧‧First electrode layer 200a‧‧‧Lower electrode layer 203‧‧‧Sacrifice layer 205a‧‧‧Dielectric layer 210a‧‧‧Upper electrode layer 220‧‧‧Cover layer 310‧‧‧ Chamber 312‧‧‧Pressure Controller 314‧‧‧Heater 320‧‧‧Base support 325‧‧‧Lower power supply 330‧‧‧Gas injector 335‧‧‧Upper power supply 340‧‧‧Pump 410‧‧‧Suppression gas supply 410V‧‧‧First valve 410V'‧‧‧First valve 412‧‧‧Suppressing Gas Controller 420‧‧‧Source Gas Supply 420V‧‧‧Second valve 420V'‧‧‧Second valve 430‧‧‧Reactive Gas Supply 430V‧‧‧Third valve 430V'‧‧‧Third valve 440‧‧‧Purge gas supply 440a‧‧‧First purge gas supply 440a'‧‧‧First purge gas supply 440b‧‧‧Second purge gas supply 440c‧‧‧Third purge gas supply 500‧‧‧Gas Box 500V‧‧‧Fourth valve A‧‧‧Upper surface B‧‧‧Sidewall C‧‧‧Lower surface a1‧‧‧Adsorption degree a2‧‧‧Adsorption degree c1‧‧‧Adsorption degree c2‧‧‧Adsorption degree ta1‧‧‧Thickness ta2‧‧‧Thickness tb1‧‧‧Thickness tb2‧‧‧Thickness tc1‧‧‧Thickness tc2‧‧‧Thickness CP1‧‧‧Capacitor H1‧‧‧Groove H2‧‧‧Groove L1‧‧‧Film L2‧‧‧Film S‧‧‧Base S11, S13, S15, S17, S19, S20, S21, S23, S25, S27, S29, S31, S33, S35, S37, S39, S41, S43, S45, S51, S53, S55‧‧‧Steps

FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 2 is a diagram illustrating the principle of a method of manufacturing a semiconductor device according to some examples of the inventive concept. 3A and 3B are cross-sectional views illustrating an example of a method of manufacturing a semiconductor device according to the concept of the present invention (FIG. 3A) and a method of manufacturing a semiconductor device (FIG. 3B) for comparison. 4A and 4B are cross-sectional views illustrating an example of a thin film formed by a method of manufacturing a semiconductor device according to the concept of the present invention (FIG. 4B) and an example of a thin film formed by a method for comparison (FIG. 4A ). 5A and 5B provide photos showing a thin film formed by an example of a method of manufacturing a semiconductor device according to the inventive concept (FIG. 5B) and a thin film formed by a method for comparison with the method according to the inventive concept (FIG. 5A). 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, and FIG. 18 are cross-sectional views of the semiconductor device during the manufacturing process and At the same time, an example of a method of manufacturing the semiconductor device according to the concept of the present invention is explained. FIG. 19 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 20 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 21 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 22 is a flowchart illustrating a method of manufacturing a semiconductor device according to some examples of the inventive concept. FIG. 23 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept. FIG. 24 is a timing diagram illustrating the operation of the semiconductor device manufacturing equipment of FIG. 23. FIG. 25 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept. FIG. 26 is a schematic diagram illustrating semiconductor device manufacturing equipment according to some examples of the inventive concept.

S11, S13, S15, S17, S19, S20‧‧‧Step

Claims (8)

A method of manufacturing a semiconductor device includes: providing a substrate; and forming a thin film on the substrate using the following process, the process including: feeding a suppressing gas onto the substrate; feeding a source gas; feeding a reaction gas; and feeding includes A purge gas of an inert gas, wherein the suppression gas suppresses the source gas from being physically adsorbed by the substrate, the source gas includes a titanium compound, the reaction gas includes a nitride compound, and the suppression gas includes an alkyl group. At least one of halide, alkenyl halide, alkynyl halide, alkene and alkyne, said alkyl halide, said alkenyl halide, said alkynyl halide, said alkene and said alkyne The hydrocarbons each include a hydrocarbon group containing 1 to 10 carbon atoms, and the alkyl halide, the alkenyl halide, and the alkynyl halide each further contain 1 to 10 halogen atoms. The method of manufacturing a semiconductor device as described in claim 1, wherein the feeding of the suppressing gas includes feeding the suppressing gas after the feeding of the reaction gas. The method of manufacturing a semiconductor device according to the first item of the scope of patent application, wherein the purge gas includes a first purge gas, a second purge gas, and a third purge gas, and The feeding of the purge gas includes feeding the first purge gas after the feeding of the suppression gas, feeding the second purge gas after the feeding of the source gas, and after the feeding The reaction gas is then fed with the third purge gas. The method of manufacturing a semiconductor device as described in claim 1, wherein the suppression gas is fed together with the source gas. The method of manufacturing a semiconductor device as described in the scope of patent application 1, wherein the suppression gas is fed together with the reaction gas. A method of manufacturing a semiconductor device includes: forming a lower electrode layer having a three-dimensional (3D) cylindrical structure on a substrate; forming a dielectric layer conformally on the lower electrode layer; The upper electrode layer is formed in a manner, wherein the forming of the upper electrode layer includes feeding a halogen-containing suppressing gas on the substrate, feeding a source gas containing titanium, feeding a reaction gas containing nitrogen, and feeding a purge gas containing an inert gas The source gas includes a titanium compound, the reaction gas includes a nitride compound, and the suppression gas includes at least one of an alkyl halide, an alkenyl halide, an alkynyl halide, alkene, and an alkyne, so The alkyl halide, the alkenyl halide, the alkynyl halide, the alkene, and the alkyne each include a hydrocarbon group containing 1 to 10 carbon atoms, and the alkyl halide, the The alkenyl halide and the alkynyl halide each further contain 1 to 10 halogen atoms. A method of manufacturing a semiconductor device includes: An intermediate structure of the semiconductor device is supported in the processing chamber, the intermediate structure having an upper surface and an opening extending from the upper surface therein and thereby having a certain aspect ratio, wherein the intermediate structure includes a bottom defining the opening The inner bottom surface and the inner side surface defining the side surface of the opening; and on the intermediate structure, the top surface of the intermediate structure and the inner bottom surface are conformally formed with a substantially uniform A process for forming a film with a thickness of a film, the film forming process includes: feeding a source gas into the processing chamber, the source gas is a precursor of the film, and at least a part of the source gas is in the middle The top surface and the inner bottom surface of the structure are adsorbed by the intermediate structure, and the reaction gas is fed into the processing chamber. The reaction gas is the precursor of the film and interacts with the source gas. Chemical reaction, and the suppression gas is fed into the processing chamber, the suppression gas is not a precursor of the film, does not react with the source gas, and at least a part of the suppression gas is affected by the intermediate structure The top surface and the inner bottom surface adsorb, and feed an inert gas into the processing chamber to purge at least a part of the gas in the processing chamber of the processing chamber, wherein the inert gas The feeding of the gas is performed at one or more points after the source gas has been fed into the processing chamber in the film formation process, wherein the source gas includes a titanium compound, and the reaction gas includes Nitride compounds, the suppressing gas includes at least one of alkyl halides, alkenyl halides, alkynyl halides, alkenes and alkynes, The alkyl halide, the alkenyl halide, the alkynyl halide, the alkene, and the alkyne each include a hydrocarbon group containing 1 to 10 carbon atoms, and the alkyl halide, the alkyne The alkenyl halide and the alkynyl halide each further contain 1 to 10 halogen atoms. A semiconductor device manufacturing equipment includes: a chamber; a substrate support arranged in the chamber and on which a substrate is placed; a source gas supplier in the chamber is supplied with a source gas; and a reaction gas is supplied to A reactive gas supplier in the chamber; supplying a suppressing gas to a suppressing gas supplier in the chamber, the suppressing gas suppressing the physical adsorption of the source gas onto the substrate; and purging the first The gas is supplied to the first purge gas supplier in the chamber, wherein the source gas includes a titanium-based compound, the reaction gas includes a nitride-based compound, and the suppression gas includes an alkyl halide, an alkenyl halide At least one of alkyne, alkynyl halide, alkene, and alkyne, and the alkyl halide, the alkenyl halide, the alkynyl halide, the alkene, and the alkyne each include 1 to A hydrocarbon group of 10 carbon atoms, and the alkyl halide, the alkenyl halide, and the alkynyl halide each further contain 1 to 10 halogen atoms.

Images