TWI739430B - Cache and method for managing cache - Google Patents

Abstract

A cache and a method for managing a cache are provided. The cache includes a first level cache, a second level cache and a register. The first level cache includes a first control circuit. The second level cache includes a second control circuit. The register is coupled to the first control circuit and the second control circuit. The first control circuit and the second control circuit refer to a register value of the register to respectively control the first level cache and the second level cache to operate in an inclusive mode or an exclusive mode.

Description

Cache memory and management method of cache memory

This case is about cache memory, especially about multi-level cache memory.

FIG. 1 is a structural diagram of a conventional electronic device. The electronic device 100 includes a processor 110, a first level (L1) cache memory 120, a second level (L2) cache memory 130 and a system memory 140. L1 cache memory 120 and L2 cache memory 130 are usually static random-access memory (SRAM), and system memory 140 is usually dynamic random-access memory (Dynamic Random-Access Memory). ,DRAM). The L2 cache memory 130 includes a control circuit 132 and a storage circuit 136. The control circuit 132 writes data into the storage circuit 136 or reads data from the storage circuit 136. The data structure of the storage circuit 136 and the algorithm used by the control circuit 132 to access the storage circuit 136 are well known to those with ordinary knowledge in the art, so they will not be described in detail. The following discusses the problems encountered by the electronic device 100 in the inclusive mode and the exclusive mode of the cache memory respectively. The tolerance mode and the proprietary mode are well-known to those with ordinary knowledge in the technical field, so they will not be described in detail.

FIG. 2 is a partial flowchart of the electronic device 100 operating in the containment mode. During data access, when data is missed in L1 cache memory 120, L1 cache memory The body 120 requests data from the L2 cache 130 (step S210). In step S220, the control circuit 132 checks whether the storage circuit 136 stores the data requested by the L1 cache 120. Assuming that the data requested by the L1 cache 120 is not stored in the storage circuit 136 (that is, the L2 cache is not hit), the control circuit 132 requests the data from the system memory 140 (step S230). Then, the L2 cache 130 obtains the data from the system memory 140 (step S240), and then the L2 cache 130 replies the data to the L1 cache 120 (step S250). After receiving the data replies from the L2 cache 130, the L1 cache 120 stores the data. Finally, the L1 cache memory 120 broadcasts data to the L2 cache memory 130 (step S260). In step S260, the control circuit 132 needs to check the tag of the storage circuit 136 and write data into the storage circuit 136. Because the capacity of the L2 cache memory 130 is generally greater than the capacity of the L1 cache memory 120, accessing the storage circuit 136 is also relatively time-consuming. For example, if access to the L1 cache 120 requires 1 system clock cycle, then access to the storage circuit 136 may require 2 to 3 cycles. Since step S260 is relatively time-consuming, the next access command that the control circuit 132 cannot process immediately causes the processor 110 to stall.

FIG. 3 is a partial flowchart of the electronic device 100 operating in the proprietary mode. During the data access process, when data is missed in the L1 cache 120, the L1 cache 120 requests data from the L2 cache 130 (step S310). In step S320, the control circuit 132 checks whether the storage circuit 136 stores the data requested by the L1 cache 120. Assuming that the storage circuit 136 stores the data requested by the L1 cache 120 (that is, the L2 cache hit), the control circuit 132 replies the data to the L1 cache 120 (step S330). Then, the L1 cache memory 120 evicts a line of data to the L2 cache memory 130 (step S340). In step S340, the control circuit 132 must check the storage circuit 136 And write the row data into the appropriate location of the storage circuit 136. Since accessing the storage circuit 136 is relatively time-consuming, step S340 may make the next access command that the control circuit 132 cannot process immediately, causing the processor 110 to stall.

In view of the shortcomings of the prior art, one purpose of this project is to provide a cache memory and a method for managing the cache memory to improve the performance of the electronic device.

This case discloses a cache memory, including a first-level cache memory, a second-level cache memory, and a register. The first level cache includes a first control circuit. The second-level cache includes a second control circuit. The register is coupled to the first control circuit and the second control circuit. The first control circuit and the second control circuit refer to a temporary value of the register to respectively control the first-level cache and the second-level cache to operate in an inclusive mode Or an exclusive mode.

This case discloses a method for managing cache memory, which is used in a cache memory. The cache memory includes a first-level cache memory, a second-level cache memory, and a register. The management method includes the following steps: reading a temporary value of the register; controlling the first-level cache and the second-level cache to operate in an inclusive mode or a dedicated mode according to the temporary value. There are modes (exclusive mode).

The features, implementation, and effects of this case are described in detail as follows in conjunction with the drawings as examples.

100, 400, 70: electronic device

110, 410, 72: processor

120, 420, 724, 734: L1 cache

130, 430, 74: L2 cache

140, 440: System memory

132, 432, 7241, 7341, 742: control circuit

136, 436, 7242, 7342, 746: storage circuit

434, 744: snubber circuit

720, 730: Core

722, 732: processing unit

76: register

S210~S260, S310~S340, S510~S580, S610~S640: steps

[Figure 1] is a structural diagram of a conventional electronic device. [Figure 2] is a partial flow chart of the conventional electronic device operating in an inclusive mode; [Figure 3] is a partial flow chart of the conventional electronic device operating in a proprietary mode; [Figure 4] is an embodiment of the electronic device of the present invention [Fig. 5] is a flowchart of an embodiment of the method for managing cache memory in this case; [Fig. 6] is a flowchart of an embodiment of step S540 in Fig. 5; and [Fig. 7] is this case The architecture diagram of another embodiment of the electronic device.

The technical terms used in the following description refer to the customary terms in the technical field. If part of the terms is described or defined in this specification, the explanation of the part of the terms is based on the description or definition of this specification.

The disclosure of this case includes the cache memory and the management method of the cache memory. Since some of the components included in the cache memory in this case may be known components alone, the following description will give details of the known components without affecting the full disclosure and implementability of the device embodiments. Abridged. In addition, part or all of the process of the cache management method of this case can be in the form of software and/or firmware, and can be executed by the cache or its equivalent device of this case, without affecting the method Under the premise of full disclosure and implementability of the embodiments, the description of the following method embodiments will focus on the content of the steps rather than the hardware.

FIG. 4 is a structural diagram of an embodiment of the electronic device of the present invention. The electronic device 400 includes a processor 410, an L1 cache memory 420, an L2 cache memory 430, and a system memory 440. The L2 cache memory 430 includes a control circuit 432, a buffer circuit 434, and a storage circuit 436. The buffer circuit 434 stores data in a first-in first-out (FIFO) manner, while the storage circuit 436 does not store data in a first-in first-out manner. In some embodiments, the capacity of the buffer circuit 434 is smaller than the capacity of the storage circuit 436. As a result, the access speed of the control circuit 432 to the buffer circuit 434 can be greater than the access speed of the storage circuit 436. The storage circuit 436 stores a plurality of tags and a plurality of data corresponding to the tags. The data structure of the storage circuit 436 is well-known to those skilled in the art, so it will not be described in detail. The buffer circuit 434 can be implemented by SRAM or a register (such as a flip-flop), and the storage circuit 436 can be implemented by SRAM. The L1 cache memory 420 and the L2 cache memory 430 can be operated in an inclusive mode or a proprietary mode.

FIG. 5 is a flowchart of an embodiment of the method for managing the cache memory of the present application. The process in Figure 5 is applicable to both the inclusive model and the proprietary model. When the control circuit 432 obtains the target data from the L1 cache memory 420 or the system memory 440 and wants to store the target data, the control circuit 432 writes the target data into the buffer circuit 434 without checking the tag of the storage circuit 436 (step S510) . Next, the control circuit 432 determines whether the L2 cache 430 is in an idle state (step S520). If step S520 is no, the control circuit 432 further determines whether there is another target data to be written into the L2 cache 430 (step S530). If step S530 is yes, the control circuit 432 writes the other target data to the buffer circuit 434 (step S510); if step S530 is no, the control circuit 432 searches for and/or responds to the data (including the access buffer circuit 434 and /Or storage circuit 436) (step S540). After step S540 ends, the flow returns to step S520.

When the L2 cache 430 is in an idle state (Yes in step S520), The control circuit 432 determines whether the buffer circuit 434 is empty (step S550). If the buffer circuit 434 does not store any data (that is, YES in step S550), go back to step S520. If the buffer circuit 434 is not empty (that is, no in step S550), the control circuit 432 searches for storage space in the storage circuit 436 (step S560), and then reads the target data from the buffer circuit 434 and writes it into the storage circuit 436 (Step S570). In other words, the purpose of step S560 and step S570 is to move the target data from the buffer circuit 434 to the storage circuit 436. After being moved, the target data only exists in the storage circuit 436 and does not exist in the buffer circuit 434. In other words, the buffer circuit 434 and the storage circuit 436 do not store the same line of data at the same time. After step S570 is completed, the control circuit 432 finishes writing the target data into the L2 cache memory 430 (step S580), and then the flow returns to step S520.

In step S560, the storage space may be an unoccupied space or a space occupied by data to be removed. The control circuit 432 can find the data to be kicked out according to the algorithm (for example, Least Recently Used (LRU)) and the tag in the storage circuit 436.

It can be seen from the flow of FIG. 5 that the buffer circuit 434 may store a plurality of target data at the same time, and the control circuit 432 sequentially reads and writes the target data into the storage circuit 436 in a first-in-first-out manner. In some embodiments, the data in the buffer circuit 434 has the same format as the data in the storage circuit 436 (for example, the format of all line data), so as to simplify step S570.

Because the control circuit 432 does not need to check the label of the storage circuit 436 in step S510 to find a suitable storage space (whether it is empty storage space or the space occupied by the data to be kicked out), theoretically step S510 only It takes 1 cycle of the system clock to complete. For comparison, because the control circuit 432 needs to write the target data into the storage circuit 436 The tag must be checked first, so the control circuit 432 directly writes the target data into the storage circuit 436 requires at least 2 cycles of the system clock (depending on the size of the storage circuit 436). In other words, the buffer circuit 434 can increase the speed of the L2 cache 430.

The idle state of step S520 includes: (1) when the control circuit 432 has no pending read/write operations; and (2) when the L2 cache memory 430 is missed, the control circuit 432 requests data from the system memory 440 until it is received. Until the system memory 440 responds. Because the number of cycles of the system clock required for one access of the system memory 440 is usually much larger than the number of cycles of the system clock required by the control circuit 432 to write data into the storage circuit 436, the control circuit 432 is in case (2) There is sufficient time to execute steps S560 and S570.

To sum up, because whether the L2 cache 430 misses in the containment mode or hits in the proprietary mode, from the perspective of the processor 410, the operation of the L2 cache 430 only requires 1 system time. Therefore, the processor 410 will not be stalled due to the pulse cycle, thus greatly increasing the performance of the electronic device 400.

FIG. 6 is a flowchart of an embodiment of step S540 in FIG. 5. When the L1 cache 420 misses and requests data from the L2 cache 430, the control circuit 432 checks whether the buffer circuit 434 and the storage circuit 436 store the target data (step S610). If it hits (that is, the buffer circuit 434 or the storage circuit 436 stores the target data, step S620 is YES), the control circuit 432 reads the target data, and replies the target data to the L1 cache 420 (step S630) . If there is a miss (that is, neither the buffer circuit 434 nor the storage circuit 436 has stored the target data, step S620 is No), the control circuit 432 requests data from the system memory 440 (step S640).

FIG. 7 is a structural diagram of another embodiment of the electronic device of the present invention. Electronic device 70 It includes a processor 72, an L2 cache 74, and a register 76. The processor 72 includes a core 720 and a core 730. The core 720 includes a processing unit 722 and an L1 cache memory 724. The L1 cache memory 724 includes a control circuit 7241 and a storage circuit 7242. The core 730 includes a processing unit 732 and an L1 cache memory 734. The L1 cache memory 734 includes a control circuit 7341 and a storage circuit 7342. In short, the processor 72 has a multi-core architecture. The core 720 and the core 730 have their own L1 cache memory (724 and 734 respectively), and share the L2 cache memory 74. The L2 cache memory 74 includes a control circuit 742, a buffer circuit 744, and a storage circuit 746. The functions of the control circuit 742, the buffer circuit 744, and the storage circuit 746 are similar to those of the control circuit 432, the buffer circuit 434, and the storage circuit 436, respectively, so they will not be described again. The control circuit 7241, the control circuit 7341, and the control circuit 742 are coupled to the register 76, and the register value in the register 76 can be read.

The control circuit 7241 of the L1 cache memory 724, the control circuit 7341 of the L1 cache memory 734, and the control circuit 742 of the L2 cache memory 74, refer to the temporary value of the register 76 to control the L1 cache memory 724, respectively. , L1 cache memory 734 and L2 cache memory 74 operate in inclusive mode or proprietary mode. In other words, the L1 cache and the L2 cache can be switched between the tolerance mode and the exclusive mode in a programmable manner. In this way, the electronic device 70 does not need to determine the operation mode of the L1 cache memory 724, the L1 cache memory 734, and the L2 cache memory 74 at the design stage. Instead, the user can use the actual operation mode after the circuit is completed. The application (that is, dynamic adjustment) sets the temporary value of the register 76. In some embodiments, the register 76 may be a control register of the processor 72.

The following is an application example of the electronic device 70.

Example 1: When the core 720 and the core 730 are processed in parallel (that is, the same program is executed), the temporary value of the register 76 can be set to a first value (for example, 1), so that L1 The cache memory 724, the L1 cache memory 734, and the L2 cache memory 74 operate in the containment mode.

Example 2: When the core 720 and the core 730 execute the first program and the second program, and the first program and the second program share commands and/or data, the temporary value of the register 76 can be set to the first value (For example, 1), the L1 cache memory 724, the L1 cache memory 734, and the L2 cache memory 74 are made to operate in the containment mode.

Example 3: When the core 720 and the core 730 execute the first program and the second program respectively, and the first program and the second program do not share commands and/or data (that is, the first program and the second program are independent programs) , The temporary value of the register 76 can be set to a second value (for example, 0), so that the L1 cache memory 724, the L1 cache memory 734, and the L2 cache memory 74 operate in the exclusive mode.

In Examples 1 and 2, the containment mode helps to reduce the number of data movement (that is, to increase the hit rate), so the performance of the electronic device 70 can be improved. In the third example, the proprietary mode helps L1 cache memory 724, L1 cache memory 734, and L2 cache memory 74 to store more commands and/or data, so the performance of the electronic device 70 can be improved .

In some embodiments, the aforementioned control circuit 432, control circuit 7241, control circuit 7341, and control circuit 742 may be implemented by a finite state machine (including a plurality of logic circuits).

Since those with ordinary knowledge in the art can understand the implementation details and changes of the method embodiment of this case through the disclosure content of the device embodiment of this case, in order to avoid redundant text, it will not affect the disclosure requirements and the disclosure requirements of the method embodiment. Under the premise of feasibility, the repeated description is abbreviated here. Please note that the shapes, sizes, ratios, and sequence of steps in the preceding figures are only for illustration, and are provided for those skilled in the art to understand this case, and are not intended to be limiting. Make this case.

Although the embodiments of this case are as described above, these embodiments are not used to limit the case. Those with ordinary knowledge in the technical field can apply changes to the technical features of the case based on the explicit or implicit content of the case, and all such changes All of them may fall into the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be subject to the scope of the patent application in this specification.

70: electronic device

72: processor

724, 734: L1 cache

74: L2 cache

7241, 7341, 742: control circuit

7242, 7342, 746: storage circuit

744: snubber circuit

720, 730: Core

722, 732: processing unit

76: register

Claims (10)

A cache memory includes: a first level cache memory, including a first control circuit; a second level cache memory, including a second control circuit; and a register, coupled to the first control circuit A control circuit and the second control circuit; wherein the first control circuit and the second control circuit refer to a temporary value of the register to control the first-level cache and the second-level cache, respectively The memory operates in an inclusive mode or an exclusive mode. The cache memory described in claim 1, wherein the second-level cache memory is shared by a first core and a second core of a processor, and the first core executes a first program and The second core executes a second program. When the first program and the second program are programs that share commands or data, the temporary value should contain a pattern. The cache memory described in claim 1, wherein the second-level cache memory is shared by a first core and a second core of a processor, and the first core executes a first program and The second core executes a second program. When the first program and the second program are not programs that share commands or data, the temporary storage value corresponds to a proprietary mode. For the cache memory described in item 1 of the scope of patent application, the second-level cache memory further includes: a storage circuit; and a buffer circuit for storing a data in a first-in first-out manner; Wherein, the second control circuit is used to find a storage space in the storage circuit and write the data into the storage space. The cache memory described in item 4 of the scope of patent application, wherein when the second control circuit checks whether the second level cache memory contains a target data, the second control circuit checks the storage circuit and the buffer Whether the circuit stores the target data. For the cache memory described in item 4 of the scope of patent application, when a target data is written into the second-level cache memory, the second control circuit writes the target data into the buffer circuit without Check the storage circuit. In the cache memory described in item 4 of the scope of patent application, the capacity of the buffer circuit is smaller than the capacity of the storage circuit. A method for managing cache memory is used in a cache memory. The cache memory includes a first-level cache memory, a second-level cache memory, and a register. The management method includes: reading a temporary value of the register; controlling the first-level cache and the second-level cache to operate in an inclusive mode or a dedicated mode according to the temporary value. There are modes (exclusive mode). For the management method described in claim 8, wherein the second-level cache is shared by a first core and a second core of a processor, the first core executes a first program and the second core The second core executes a second program. When the first program and the second program are programs that share commands or data, the temporary value should contain a pattern. For the management method described in claim 8, wherein the second-level cache is shared by a first core and a second core of a processor, the first core executes a first program and the second core The second core executes a second program. When the first program and the second program are not programs that share commands or data, the temporary value corresponds to the proprietary mode.

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