TWI739056B - Array substrate and manufacturing method thereof, and display panel - Google Patents

Abstract

An array substrate includes: a substrate; a mask layer arranged on the substrate; a first insulating layer arranged on the mask layer; an active layer for driving a thin film transistor is arranged on the first insulating layer Above the layer, the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap; and a conductive structure, the conductive structure being disposed on the active layer And coupled to the mask layer. The invention also discloses a display device including the array substrate and a method of manufacturing the array substrate.

Description

Array substrate and manufacturing method thereof, and display panel

The embodiments of the present invention relate to an array substrate, a manufacturing method thereof, and a display panel.

Currently, organic light emitting diode (OLED) display devices have been widely used. Thin Film Transistor (TFT) is an important element that constitutes the pixel unit of the OLED display device.

At least one embodiment of the present invention provides an array substrate, including: a substrate; a mask layer disposed on the substrate; a first insulating layer disposed on the mask layer; Layer, disposed on the first insulating layer, the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap; and a conductive structure, the conductive The structure is disposed on the active layer and coupled to the mask layer.

In an embodiment of the present invention, the conductive structure may include a source electrode, a drain electrode or a gate electrode of the driving thin film transistor.

In an embodiment of the present invention, the array substrate further includes a second insulating layer disposed on the active layer.

In an embodiment of the present invention, the conductive structure is disposed on the second insulating layer and formed as a gate electrode of the driving thin film transistor.

In an embodiment of the present invention, the array substrate further includes a first through hole passing through the first and second insulating layers, and the gate is coupled to the mask layer through the first through hole.

In an embodiment of the present invention, the array substrate further includes a gate electrode provided on the second insulating layer, and a third insulating layer provided on the gate electrode and the second insulating layer.

In an embodiment of the present invention, the conductive structure is disposed on the third insulating layer and formed as the source or drain of the thin film transistor.

In an embodiment of the present invention, the array substrate further includes a second through hole passing through the first, second, and third insulating layers, and the source electrode is coupled to the mask layer through the second through hole .

In an embodiment of the present invention, the array substrate further includes a third through hole passing through the first, second, and third insulating layers, and the drain is coupled to the mask layer through the third through hole.

In an embodiment of the present invention, the array substrate further includes a power line disposed on the third insulating layer, and the power line is coupled to the source.

In an embodiment of the present invention, the array substrate further includes a fourth insulating layer disposed on the third insulating layer, and a light-emitting element disposed on the fourth insulating layer, wherein the light-emitting element is coupled to the driving thin film circuit. The drain of the crystal.

In one embodiment of the present invention, the mask layer is made of metal or alloy.

At least one embodiment of the present invention provides a display panel including any of the above-mentioned array substrates.

At least one embodiment of the present invention provides a method of manufacturing an array substrate, the method comprising: forming a mask layer on the substrate, forming a first insulating layer on the mask layer, and An active layer driving a thin film transistor is formed on the substrate, wherein the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap, and the method further includes A conductive structure is formed on the active layer, wherein the conductive structure is coupled to the mask layer.

In at least one embodiment of the present invention, the conductive structure includes a source electrode, a drain electrode or a gate electrode of the driving thin film transistor.

In at least one embodiment of the present invention, the method further includes: forming a second insulating layer on the active layer.

In at least one embodiment of the present invention, the conductive structure is formed on the second insulating layer and is formed as a gate electrode of the driving thin film transistor.

In at least one embodiment of the present invention, the method further includes: forming a first through hole passing through the first insulating layer and the second insulating layer, and the gate is coupled to the mask layer through the first through hole .

In at least one embodiment of the present invention, the method further includes: forming a gate electrode on the second insulating layer, and forming a third insulating layer on the gate electrode and the second insulating layer.

In at least one embodiment of the present invention, the conductive structure is formed on the third insulating layer and constitutes the source or drain of the driving thin film transistor.

In at least one embodiment of the present invention, the method may further include forming a second through hole passing through the first insulating layer, the second insulating layer, and the third insulating layer, and the source electrode is coupled through the second through hole To the mask layer.

In at least one embodiment of the present invention, the method may further include forming a third through hole passing through the first insulating layer, the second insulating layer, and the third insulating layer, and the drain is coupled through the first through hole To the mask layer.

In at least one embodiment of the present invention, the method further includes forming a power line on the third insulating layer, the power line being coupled to the source.

In at least one embodiment of the present invention, the method further includes: forming a fourth insulating layer on the third insulating layer, and forming a light emitting element on the fourth insulating layer, wherein the light emitting element is coupled to The drain electrode of the driving thin film transistor is coupled.

In at least one embodiment of the present invention, the mask layer may be made of metal or alloy.

In order to make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

When introducing elements of the present invention and the embodiments thereof, the articles "a", "an", "the" and "said" are intended to mean that there are one or more elements. The terms "comprising", "including", "containing" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

For the purpose of superficial description below, the terms "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", and the direction indicated in the drawings The derivative word should involve public. The terms "overlying", "on top of", "positioned on top" or "positioned on top of" mean that a first element such as a first structure is present on a second element such as a second structure, Among them, there may be an intermediate element such as an interface structure between the first element and the second element. The term "contact" means to couple a first element such as a first structure and a second element such as a second structure, and there may or may not be other elements at the interface of the two elements.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject of the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the specification and related technologies, and will not be interpreted in an idealized or overly formal form, Unless explicitly defined otherwise herein. As used herein, the statement that two or more parts are "coupled" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate elements. In addition, terms such as “first” and “second” are only used to distinguish one element (or a part of an element) from another element (or another part of an element).

Figure 1 shows an exemplary circuit diagram of a commonly used OLED pixel unit. As shown in Figure 1, the OLED pixel unit may include a driving transistor T2, a switching transistor T1, a storage capacitor C, and an OLED light-emitting element.

The driving transistor is usually affected by the light incident on it, resulting in performance degradation. In the array substrate of the OLED display device, a mask layer is usually provided under the driving transistor of each pixel unit to shield the influence of ambient light on the driving transistor.

Fig. 2A schematically shows a partial plan view of the OLED array substrate known by the inventor, and Fig. 2B is a cross-sectional view along the line A-A' in Fig. 2A.

As shown in FIG. 2A, a mask layer 201 is provided under the driving transistor T2. Figure 2B schematically shows the layered structure of the OLED array substrate. A mask layer 201 is provided on the substrate 101, and a buffer layer 102 is provided on the mask layer 201. The active layer 202 is disposed on the buffer layer 102, and its orthographic projection on the substrate 101 falls into the orthographic projection of the mask layer 201 on the substrate 101. A driving transistor T2 is formed on the active layer 202. The driving transistor T2 is coupled to the light-emitting element 401 through a fourth through hole 504 passing through the passivation layer 105 and the planarization layer 106. Therefore, in Figure 2B, the mask layer 201 is a floating structure. The suspended mask layer 201 is likely to accumulate charges under the influence of the conductive structure in the array substrate, which causes the threshold voltage of the driving transistor T2 to shift.

At least one embodiment of the present invention provides an array substrate, including a substrate, a mask layer, a first insulating layer, an active layer, and a conductive structure. A mask layer is provided on the substrate, and a mask layer is provided on the mask layer. There is a first insulating layer, and an active layer for driving the thin film transistor is arranged on the first insulating layer, and the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap, and the conductive structure is arranged on the active Above the layer and coupled to the mask layer.

In the array substrate according to the embodiment of the present invention, the mask layer is coupled to the conductive structure, and the charges accumulated on the mask layer can be released through the conductive structure, so as not to affect the performance of driving the thin film transistor.

In an embodiment of the present invention, the conductive structure includes at least one of a gate electrode 203, a source electrode 204, and a drain electrode 205 for driving a thin film transistor.

Hereinafter, the array substrate according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3A shows a partial plan view of an array substrate according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view along the line A-A' in FIG. 3A.

As shown in FIGS. 3A and 3B, the mask layer 201 is disposed under the driving thin film transistor T2, and the orthographic projection of the driving thin film transistor T2 on the substrate 101 falls into the front of the mask layer 201 on the substrate. Within the projection, the mask layer 201 is coupled to the gate electrode 203 of the driving thin film transistor T2.

In the layered structure of the array substrate shown in FIG. 3B, a mask layer 201 is provided on the substrate 101. In the embodiment of the present invention, the mask layer 201 may be made of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or an alloy thereof. In addition, in the embodiment of the present invention, the mask layer 201 may be a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure, etc. Further, a first insulating layer 102 is provided on the mask layer 201. In an embodiment of the present invention, the first insulating layer 102 is a buffer layer. In another embodiment of the present invention, the first insulating layer 102 may be a single-layer structure, which may be made of silicon nitride or silicon oxide. In still another embodiment of the present invention, the first insulating layer 102 may be a multilayer structure, such as a silicon oxide\silicon nitride structure. The active layer 202 is disposed on the first insulating layer 102, and the orthographic projection of the active layer 202 on the substrate 101 falls within the orthographic projection of the mask layer 201 on the substrate 101. Optionally, the orthographic projection of the active layer 202 on the substrate 101 may also partially overlap with the orthographic projection of the mask layer 201 on the substrate 101.

In an embodiment of the present invention, the active layer 202 may be made of amorphous silicon material, polysilicon material, or metal oxide (for example, indium gallium zinc oxide IGZO).

Further, the array substrate further includes a second insulating layer 103 provided on the active layer 202 and the first insulating layer 102. In an embodiment of the present invention, the second insulating layer 103 is a gate insulating layer. In an embodiment of the present invention, the second insulating layer 103 may be a single-layer structure, which may be made of silicon nitride or silicon oxide. In another embodiment of the present invention, the second insulating layer 103 may be a multilayer structure, such as a silicon oxide\silicon nitride structure.

As shown in FIG. 3B, a gate electrode 203 for driving a thin film transistor is provided on the second insulating layer 103. In the embodiment of the present invention, the gate electrode 203 may be made of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or an alloy thereof. In addition, in the embodiment of the present invention, the gate electrode 203 may be a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure, etc. Further, a first through hole 501 passing through the first insulating layer 102 and the second insulating layer 103 is provided between the gate electrode 203 and the mask layer 201. The mask layer 201 is coupled to the gate electrode 203 through the first through hole 501. In this way, the electric charge accumulated on the mask layer 201 can be discharged.

Further, in the embodiment of the present invention, the array substrate further includes a third insulating layer 104 provided on the gate electrode 203 and the second insulating layer 103. In the embodiment of the present invention, the third insulating layer 104 is an interlayer insulating layer, which can be made of silicon nitride or silicon oxide. In addition, the third insulating layer 104 may have a single-layer structure or a multi-layer structure, such as a silicon oxide\silicon nitride structure.

Further, a power line 301, a source electrode (not shown) and a drain electrode 205 for driving the thin film transistor are provided on the third insulating layer 104. In the embodiment of the present invention, the source electrode of the driving thin film transistor refers to the electrode coupled with the power line 301. The source of the driving thin film transistor is coupled to the active layer 202 through corresponding through holes passing through the second insulating layer 103 and the third insulating layer 104.

In the embodiment of the present invention, the source and drain of the driving thin film transistor can be made of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), etc., or their alloys. manufacture. In addition, in the embodiment of the present invention, the source and drain of the driving thin film transistor may be a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure Wait.

Further, a fourth insulating layer 107 is provided on the third insulating layer 104 and the source and drain electrodes 205 of the driving thin film transistor. In the embodiment of the present invention, the fourth insulating layer 107 includes a passivation layer and a planarization layer. The passivation layer can be made of silicon nitride or silicon oxide. In addition, the passivation layer may be a single-layer structure or a multi-layer structure, such as a silicon oxide\silicon nitride structure. In the embodiment of the present invention, the flat layer may be made of, for example, a resin material.

Additionally or alternatively, a light-emitting element 401 is provided on the fourth insulating layer 107. In an embodiment of the present invention, the light-emitting element 401 includes an anode layer, a cathode layer, and an organic light-emitting layer disposed between the anode layer and the cathode layer. The anode layer may be a single-layer structure manufactured using, for example, indium tin oxide (ITO), or may be a multilayer structure, such as a multilayer structure manufactured using indium tin oxide and silver (Ag). The cathode layer can be made of metal such as aluminum or silver. In an embodiment of the present invention, the light emitting element 401 is coupled to the drain electrode 205 of the driving thin film transistor through the fourth through hole 504 passing through the fourth insulating layer 107.

FIG. 4A shows a partial plan view of an array substrate according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view along the line A-A' in FIG. 4A. In this embodiment, the mask layer is coupled to the source of the driving thin film transistor, and the source is coupled to the power line.

The hierarchical structure of the array substrate of this embodiment is similar to the hierarchical structure of the array substrate shown in FIG. 3B. Therefore, for the same parts as those in the previous embodiment, the description thereof is appropriately omitted here. Referring to FIG. 4B, the source electrode 204 and the drain electrode 205 for driving the thin film transistor are provided on the third insulating layer 104. The source electrode 204 is coupled to the active layer 202 through corresponding through holes passing through the second insulating layer 103 and the third insulating layer 104. In addition, a power line 301 is also provided on the third insulating layer 104, which is coupled to the source 204.

Further, a second through hole 502 passing through the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104 is provided between the mask layer 201 and the source electrode 204. Through the second through hole 502, the mask layer 201 is coupled to the source electrode 204, so as to release the charges accumulated on the mask layer 201.

FIG. 5A shows a partial plan view of an array substrate according to another embodiment of the present invention, and FIG. 5B is a cross-sectional view along the line A-A' in FIG. 5A. In this embodiment, the mask layer is coupled to the drain of the driving thin film transistor, and the drain is coupled to the light-emitting element through the third through hole.

The hierarchical structure of the array substrate according to this embodiment is basically the same as the hierarchical structure of the array substrate shown in FIG. 3B or 4B. Therefore, for the same parts as in the previous embodiment, the description thereof is appropriately omitted here. Referring to FIG. 5B, a third through hole 503 passing through the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104 is provided between the mask layer 201 and the drain electrode 205 of the driving thin film transistor. The mask layer 201 is coupled to the drain electrode 205 through the third through hole 503. In this way, the electric charge accumulated on the mask layer 201 can be discharged.

Although in the embodiment shown in FIG. 5B, the orthographic projections of the third through hole 503 and the fourth through hole 504 on the substrate 101 coincide, it should be understood that the third through hole 503 and the fourth through hole 504 are The size and/or location can be different.

At least one embodiment of the present invention provides a method of manufacturing an array substrate. FIG. 6 shows a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention. This method is suitable for manufacturing the array substrate as shown in Fig. 3B, Fig. 4B or Fig. 5B.

As shown in FIG. 6, in step 610, a mask layer 201 is formed on the substrate 101. In an embodiment of the present invention, the mask layer 201 may be formed of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or an alloy thereof. In addition, in an embodiment of the present invention, the mask layer 201 may be formed in a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure, etc.

In step 620, a first insulating layer 102 is formed on the mask layer 201. In the embodiment of the present invention, the first insulating layer 102 may be formed as a single-layer structure, which may be made of silicon nitride or silicon oxide. Of course, the first insulating layer 102 can be formed as a multilayer structure, such as a silicon oxide\silicon nitride structure.

In step 630, an active layer 202 for driving the thin film transistor is formed on the first insulating layer 102, so that the orthographic projection of the active layer 202 on the substrate 101 and the orthographic projection of the mask layer 201 on the substrate 101 at least partially overlap. In the embodiment of the present invention, the active layer 202 may be formed such that the orthographic projection on the substrate 101 falls within the orthographic projection of the mask layer 201 on the substrate 101. In the embodiment of the present invention, the active layer 202 may be formed of an amorphous silicon material, a polysilicon material, or a metal oxide (for example, indium gallium zinc oxide IGZO).

In step 640, a conductive structure is formed on the active layer 202, and the conductive structure is coupled to the mask layer 201.

The conductive structure includes a source 204, a drain 205, or a gate 203 that drives the thin film transistor.

In one embodiment of the present invention, in the manufacture of the array substrate as shown in FIG. 3B, after the active layer 202 is formed, the second insulating layer 103 is formed on the active layer 202 and formed through the first insulating layer 103. The insulating layer 102 and the first through hole 501 of the second insulating layer 103. Then, a gate electrode 203 for driving the thin film transistor is formed on the second insulating layer 103, and the gate electrode 203 is coupled to the mask layer 201 through the first through hole 501. In an embodiment of the present invention, the second insulating layer 103 may be formed as a single-layer structure, which may be made of silicon nitride or silicon oxide. In another embodiment of the present invention, the second insulating layer 103 may be formed as a multilayer structure, such as a silicon oxide\silicon nitride structure. In an embodiment of the present invention, the gate electrode 203 may be formed of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or an alloy thereof. In addition, in another embodiment of the present invention, the gate electrode 203 may be formed in a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure, etc.

Further, a third insulating layer 104 is formed on the gate electrode 203 and the second insulating layer 103. In an embodiment of the present invention, the third insulating layer 104 may be formed as a single-layer structure, which may be made of silicon nitride or silicon oxide. In another embodiment of the present invention, the third insulating layer 104 may be formed as a multilayer structure, such as a silicon oxide\silicon nitride structure.

Then, a power line 301, a source 204 and a drain 205 for driving the thin film transistor are formed on the third insulating layer 104, wherein the power line 301 is coupled to the source 204. In an embodiment of the present invention, the source electrode 204 and the drain electrode 205 may be made of metals such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or alloys thereof. In another embodiment of the present invention, the source electrode 204 and the drain electrode 205 may have a single-layer structure or a multi-layer structure, such as Mo\Al\Mo structure, Ti\Cu\Ti structure, Mo\Ti\Cu structure, etc. In addition, corresponding through holes passing through the second insulating layer 103 and the third insulating layer 104 may be formed, and then the source electrode 204 and the drain electrode 205 may be formed. Thus, the source 204 and the drain 205 are coupled to the active layer 202 through corresponding through holes.

In addition, a fourth insulating layer 107 is formed on the third insulating layer 104, the power supply line 301, the source electrode 204, and the drain electrode 205. In an embodiment of the present invention, the fourth insulating layer 107 includes a passivation layer and a planarization layer. The passivation layer can be formed of silicon nitride or silicon oxide. In addition, the passivation layer can be formed as a single-layer structure or a multi-layer structure, such as a silicon oxide\silicon nitride structure. In an embodiment of the present invention, the flat layer may be formed of, for example, a resin material.

Additionally or alternatively, a light-emitting element 401 is formed on the fourth insulating layer 107. In one embodiment of the present invention, an anode layer is formed on the fourth insulating layer 107. In some embodiments, the anode layer may be formed as a single-layer structure made of, for example, indium tin oxide (ITO). In other embodiments, the anode layer may be formed in a multilayer structure, for example, a multilayer structure made of indium tin oxide and silver (Ag). Before forming the anode layer, a fourth through hole 504 is formed through the third insulating layer 104 and the fourth insulating layer 107, so that the anode layer is coupled to the drain electrode 205 of the driving thin film transistor. Then, an organic light-emitting layer is formed on the anode layer, and a cathode layer is formed on the organic light-emitting layer. In an embodiment of the present invention, the cathode layer may be formed of a metal such as aluminum or silver.

In the embodiment of the present invention, the manufacturing process of the array substrate shown in FIG. 4B is similar to the manufacturing process of the array substrate shown in FIG. 3B, and therefore, the description of the same parts is omitted here as appropriate. In manufacturing the array substrate as shown in FIG. 4B, the first through hole 501 is not formed, but the second through hole 502 passing through the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104 is formed. Then, a source 204 and a drain 205 for driving the thin film transistor are formed, and the source 204 is coupled to the mask layer 201 through the second through hole 502.

In the embodiment of the present invention, the manufacturing process of the array substrate shown in Figure 5B is similar to the manufacturing process of the array substrate shown in Figure 3B or Figure 4B. Therefore, the same parts are omitted here as appropriate. Its description.

In manufacturing the array substrate as shown in FIG. 5B, the first through hole 501 is not formed, but the third through hole 503 is formed through the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104. Then, a source 204 and a drain 205 for driving the thin film transistor are formed, and the drain 205 is coupled to the mask layer 201 through the third through hole 503.

In addition, FIG. 7 shows a schematic block diagram of a display panel according to an embodiment of the present invention. As shown in FIG. 7, the display panel 700 may include the aforementioned array substrate 701 as shown in FIG. 3B, FIG. 4B, or FIG. 5B.

The display panel according to the embodiment of the present invention can be used for any product or element having a display function. Such products or components include but are not limited to display devices, wearable devices, mobile phones, tablet computers, televisions, notebook computers, digital photo frames, navigators, etc.

The above descriptions are only exemplary embodiments of the present invention, and are not used to limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the scope of the attached patent application.

101: substrate 102: The first insulating layer (buffer layer) 103: second insulating layer 104: third insulating layer 105: passivation layer 106: flat layer 201: Mask layer 202: active layer 203: Gate 204: Source 205: Dip pole 301: Power cord 302: Data Line 303: Gate Line 401: Light-emitting element 501: first through hole 502: second through hole 503: third through hole 504: fourth through hole 610: Step 620: step 630: step 640: step 700: display panel 701: Array substrate T1: switching transistor T2: drive transistor C: storage capacitor

Figure 1 is an exemplary circuit diagram of an OLED pixel unit known to the inventor; Figure 2A is a schematic plan view of an OLED array substrate known by the inventor; Figure 2B is a cross-sectional view taken along the line A-A' in Figure 2A; FIG. 3A is a schematic plan view of an array substrate according to an embodiment of the present invention; and Figure 3B is a cross-sectional view taken along the line A-A' in Figure 3A; 4A is a schematic plan view of an array substrate according to another embodiment of the present invention; Figure 4B is a cross-sectional view taken along the line A-A' in Figure 4A; FIG. 5A is a schematic plan view of an array substrate according to another embodiment of the present invention; Figure 5B is a cross-sectional view taken along the line A-A' in Figure 5A; FIG. 6 is a schematic flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention; and FIG. 7 is a schematic block diagram of a display panel according to an embodiment of the present invention.

201: Mask layer

202: active layer

203: Gate

204: Source

205: Dip pole

301: Power cord

302: Data Line

303: Gate Line

401: Light-emitting element

501: first through hole

504: fourth through hole

T1: switching transistor

T2: drive transistor

Claims (8)

An array substrate comprising: a substrate; a mask layer arranged on the substrate; a first insulating layer arranged on the mask layer; an active layer for driving a thin film transistor is arranged on the first insulating layer Above the layer, the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap; and a conductive structure, the conductive structure being disposed on the active layer And coupled to the mask layer, wherein the conductive structure includes a gate electrode of the driving thin film transistor, the gate electrode of the driving thin film transistor is coupled to the mask layer, the driving thin film transistor The source electrode and the mask layer are not in contact with each other and are insulated from each other, and the drain electrode of the driving thin film transistor is not in contact with the mask layer and is insulated from each other. According to the first item of the scope of patent application, the array substrate further includes a second insulating layer, and the second insulating layer is disposed on the active layer. The array substrate according to the second item of the scope of patent application, wherein the conductive structure is the gate electrode of the driving thin film transistor, and is arranged on the second insulating layer. The array substrate according to item 3 of the scope of patent application, further comprising a first through hole, the first through hole passes through the first insulating layer and the second insulating layer, and the gate electrode passes through the The first through hole is coupled to the mask layer. The array substrate according to item 2 of the scope of patent application, further comprising: a gate electrode, which is arranged on the second insulating layer; and a third insulating layer, which is arranged on the gate electrode and the second insulating layer superior. The array substrate according to the first item of the scope of patent application, wherein the mask layer is made of metal or alloy. A display panel including the array as described in any one of items 1 to 6 in the scope of patent application Substrate. A method of manufacturing an array substrate includes: forming a mask layer on the substrate; forming a first insulating layer on the mask layer; forming an active layer for driving a thin film transistor on the first insulating layer, Wherein the orthographic projection of the active layer on the substrate and the orthographic projection of the mask layer on the substrate at least partially overlap; and a conductive structure is formed on the active layer, wherein the conductive structure is coupled Connected to the mask layer, wherein the conductive structure includes the gate electrode of the driving thin film transistor, the gate electrode of the driving thin film transistor is coupled to the mask layer, and the source of the driving thin film transistor The electrode is not in contact with the mask layer and insulated from each other, and the drain of the driving thin film transistor is not in contact with the mask layer and insulated from each other.

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