TWI737883B - Trench metal oxide semiconductor device - Google Patents

Trench metal oxide semiconductor device Download PDF

Info

Publication number
TWI737883B
TWI737883B TW107100812A TW107100812A TWI737883B TW I737883 B TWI737883 B TW I737883B TW 107100812 A TW107100812 A TW 107100812A TW 107100812 A TW107100812 A TW 107100812A TW I737883 B TWI737883 B TW I737883B
Authority
TW
Taiwan
Prior art keywords
trench
electrode
lower electrode
substrate
metal oxide
Prior art date
Application number
TW107100812A
Other languages
Chinese (zh)
Other versions
TW201931603A (en
Inventor
陳勁甫
Original Assignee
力智電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力智電子股份有限公司 filed Critical 力智電子股份有限公司
Priority to TW107100812A priority Critical patent/TWI737883B/en
Priority to CN201810182898.7A priority patent/CN110021656A/en
Publication of TW201931603A publication Critical patent/TW201931603A/en
Application granted granted Critical
Publication of TWI737883B publication Critical patent/TWI737883B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A trench metal oxide semiconductor device including a substrate, first trench electrode structures, and second trench electrode structure is provided. The substrate is defined to have an active region. The first trench electrode structures are disposed in the substrate of the active region. Each of the first trench electrode structures includes a first lower electrode and an upper electrode located on the first lower electrode. The substrate, the first lower electrode and the upper electrode are electrically isolated from each other. The second trench electrode structure is disposed in the substrate of the active region. The second trench electrode structure includes a second lower electrode and a dielectric layer located on the second lower electrode. A top surface of the dielectric layer is substantially coplanar with the top surface of the substrate. The substrate and the second lower electrode are electrically isolated from each other.

Description

溝槽金氧半導體元件 Trench metal oxide semiconductor device

本發明是有關於一種半導體元件，且特別是有關於一種溝槽金氧半導體元件。 The present invention relates to a semiconductor device, and more particularly to a trench metal oxide semiconductor device.

隨著半導體產業的發展與產品需求，具有屏蔽閘極的溝槽金氧半導體元件被廣泛地應用在電源開關(power switch)元件中。由於此種屏蔽閘極溝槽金氧半場效電晶體(shielded gate trench MOSFET)元件具有許多優良的性能，相較傳統的金氧半電晶體開關結構，屏蔽閘極溝槽金氧半場效電晶體元件具有較低的電晶體閘漏電容，較小的導通電阻，並且提供較高的崩潰電壓(breakdown voltage)。 With the development of the semiconductor industry and product demand, trench metal oxide semiconductor devices with shielded gates are widely used in power switch devices. Since this shielded gate trench MOSFET device has many excellent performances, compared with the traditional MOSFET switch structure, the shielded gate trench MOSFET has many excellent performances. The device has lower transistor gate leakage capacitance, lower on-resistance, and provides higher breakdown voltage.

一般來說，傳統屏蔽閘極溝槽金氧半場效電晶體元件在溝槽中具有下部電極與上部電極，且下部電極作為屏蔽閘極。然而，相鄰兩溝槽的上部電極之間會產生寄生電容，而降低元件的反應速度。 Generally speaking, the traditional shielded gate trench MOSFET device has a lower electrode and an upper electrode in the trench, and the lower electrode serves as a shielding gate. However, a parasitic capacitance is generated between the upper electrodes of two adjacent trenches, which reduces the reaction speed of the device.

本發明提供一種溝槽金氧半導體元件，其相鄰兩個上部電極之間的寄生電容較低，而具有較快的反應速度。 The present invention provides a trench metal oxide semiconductor element, which has a lower parasitic capacitance between two adjacent upper electrodes and a faster reaction speed.

本發明提出一種溝槽金氧半導體元件，包括基底、多個第一溝槽電極結構與第二溝槽電極結構。基底定義有主動區。第一溝槽電極結構設置於主動區的基底中。每個第一溝槽電極結構包括第一下部電極與位於第一下部電極上的上部電極。基底、第一下部電極與上部電極彼此電性隔離。第二溝槽電極結構設置於主動區的基底中。第二溝槽電極結構包括第二下部電極與位於第二下部電極上的介電層。介電層的頂面實質上與基底的頂面共平面。基底與第二下部電極彼此電性隔離。 The present invention provides a trench metal oxide semiconductor device, which includes a substrate, a plurality of first trench electrode structures and a second trench electrode structure. The active area is defined on the base. The first trench electrode structure is disposed in the substrate of the active area. Each first trench electrode structure includes a first lower electrode and an upper electrode located on the first lower electrode. The substrate, the first lower electrode and the upper electrode are electrically isolated from each other. The second trench electrode structure is disposed in the substrate of the active area. The second trench electrode structure includes a second lower electrode and a dielectric layer on the second lower electrode. The top surface of the dielectric layer is substantially coplanar with the top surface of the substrate. The substrate and the second lower electrode are electrically isolated from each other.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二溝槽電極結構位於相鄰兩個第一溝槽電極結構之間。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the second trench electrode structure is located between two adjacent first trench electrode structures.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，介電層的寬度等於或大於第二下部電極的寬度。 According to an embodiment of the present invention, in the trench MOS device, the width of the dielectric layer is equal to or greater than the width of the second lower electrode.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，介電層接觸第二下部電極。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the dielectric layer contacts the second lower electrode.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二下部電極的頂面與第一下部電極的頂面可等高。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the top surface of the second lower electrode and the top surface of the first lower electrode may be the same height.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二下部電極與第一下部電極具有相同的寬度。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the second lower electrode and the first lower electrode have the same width.

依照本發明的一實施例所述，在上述溝槽金氧半導體元 件中，第二溝槽電極結構更包括第二絕緣層。第二絕緣層設置於基底與第二下部電極之間。 According to an embodiment of the present invention, in the trench metal oxide semiconductor element In the article, the second trench electrode structure further includes a second insulating layer. The second insulating layer is disposed between the substrate and the second lower electrode.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二絕緣層更延伸至基底與介電層之間。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the second insulating layer further extends between the substrate and the dielectric layer.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二下部電極的頂面可高於所述第二絕緣層的頂面。 According to an embodiment of the present invention, in the trench MOS device, the top surface of the second lower electrode may be higher than the top surface of the second insulating layer.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二絕緣層的材料與介電層的材料可相同或不同。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the material of the second insulating layer and the material of the dielectric layer may be the same or different.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，每個第一溝槽電極結構更包括第三絕緣層。第三絕緣層設置於上部電極與基底之間以及上部電極與第一下部電極之間。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, each first trench electrode structure further includes a third insulating layer. The third insulating layer is disposed between the upper electrode and the substrate and between the upper electrode and the first lower electrode.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第二溝槽電極結構更包括第四絕緣層。第四絕緣層設置於介電層與第二下部電極之間。 According to an embodiment of the present invention, in the above-mentioned trench metal oxide semiconductor device, the second trench electrode structure further includes a fourth insulating layer. The fourth insulating layer is disposed between the dielectric layer and the second lower electrode.

依照本發明的一實施例所述，在上述溝槽金氧半導體元件中，第四絕緣層更延伸至基底與介電層之間。 According to an embodiment of the present invention, in the trench MOS device, the fourth insulating layer further extends between the substrate and the dielectric layer.

基於上述，在本發明所提出的溝槽金氧半導體元件中，由於第二溝槽電極結構位於相鄰兩個第一溝槽電極結構之間，在第二溝槽電極結構的第二下部電極上設置介電層，且介電層的頂面實質上與基底的頂面共平面，因此可藉由介電層增加相鄰兩個第一溝槽電極結構的上部電極之間的距離，以降低相鄰兩個上部 電極之間的寄生電容，進而提高溝槽金氧半導體元件的反應速度。 Based on the above, in the trench metal oxide semiconductor device proposed in the present invention, since the second trench electrode structure is located between two adjacent first trench electrode structures, the second lower electrode of the second trench electrode structure A dielectric layer is provided on the upper surface, and the top surface of the dielectric layer is substantially coplanar with the top surface of the substrate. Therefore, the distance between the upper electrodes of two adjacent first trench electrode structures can be increased by the dielectric layer to Lower two adjacent upper parts The parasitic capacitance between the electrodes further increases the reaction speed of the trench metal oxide semiconductor device.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10、20、30、40:溝槽金氧半導體元件 10, 20, 30, 40: trench metal oxide semiconductor device

100:基底 100: base

100a:矽基板 100a: Silicon substrate

100b:磊晶矽層 100b: epitaxial silicon layer

102、110:下部電極 102, 110: lower electrode

104:上部電極 104: Upper electrode

106、108、114、116、314、316、416:絕緣層 106, 108, 114, 116, 314, 316, 416: insulating layer

112、212、312、412:介電層 112, 212, 312, 412: Dielectric layer

AA:主動區 AA: active area

TS1、TS2:溝槽電極結構 TS1, TS2: trench electrode structure

圖1為本發明一實施例的溝槽金氧半導體元件的剖面圖。 FIG. 1 is a cross-sectional view of a trench metal oxide semiconductor device according to an embodiment of the invention.

圖2為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 2 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

圖3為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 3 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

圖4為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 4 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

圖1為本發明一實施例的溝槽金氧半導體元件的剖面圖。 FIG. 1 is a cross-sectional view of a trench metal oxide semiconductor device according to an embodiment of the invention.

請參照圖1，溝槽金氧半導體元件10包括基底100、多個溝槽電極結構TS1與溝槽電極結構TS2。基底100定義有主動區AA。基底100可包括矽基板100a與設置於矽基板100a上的磊晶矽層100b，但本發明並不以此為限。 1, the trench metal oxide semiconductor device 10 includes a substrate 100, a plurality of trench electrode structures TS1, and a trench electrode structure TS2. The substrate 100 is defined with an active area AA. The base 100 may include a silicon substrate 100a and an epitaxial silicon layer 100b disposed on the silicon substrate 100a, but the invention is not limited thereto.

溝槽電極結構TS1設置於主動區AA的基底100中。每個溝槽電極結構TS1包括下部電極102與上部電極104，且更包括絕緣層106與絕緣層108中的至少一者。上部電極104位於下部電極102上。上部電極104的頂面實質上與基底100的頂面共 平面。在一實施例中，上部電極104的寬度大於下部電極102的寬度。下部電極102的材料與上部電極104的材料分別為摻雜多晶矽或金屬(如，鎢、銅或鋁)等導體材料。 The trench electrode structure TS1 is disposed in the substrate 100 in the active area AA. Each trench electrode structure TS1 includes a lower electrode 102 and an upper electrode 104, and further includes at least one of an insulating layer 106 and an insulating layer 108. The upper electrode 104 is located on the lower electrode 102. The top surface of the upper electrode 104 is substantially the same as the top surface of the substrate 100 flat. In an embodiment, the width of the upper electrode 104 is greater than the width of the lower electrode 102. The material of the lower electrode 102 and the material of the upper electrode 104 are conductive materials such as doped polysilicon or metal (eg, tungsten, copper, or aluminum).

絕緣層106設置於基底100與下部電極102之間。絕緣層108設置於上部電極104與基底100之間以及上部電極104與下部電極102之間。絕緣層106的材料與絕緣層108的材料分別為氧化矽或氮化矽等介電材料。基底100、下部電極102與上部電極104可藉由絕緣層106與絕緣層108而彼此電性隔離。 The insulating layer 106 is disposed between the substrate 100 and the lower electrode 102. The insulating layer 108 is disposed between the upper electrode 104 and the substrate 100 and between the upper electrode 104 and the lower electrode 102. The material of the insulating layer 106 and the material of the insulating layer 108 are dielectric materials such as silicon oxide or silicon nitride, respectively. The substrate 100, the lower electrode 102, and the upper electrode 104 can be electrically isolated from each other by the insulating layer 106 and the insulating layer 108.

溝槽電極結構TS2設置於主動區AA的基底100中。溝槽電極結構TS2包括下部電極110與介電層112，且更包括絕緣層114與絕緣層116中的至少一者。溝槽電極結構TS2位於相鄰兩個溝槽電極結構TS1之間。 The trench electrode structure TS2 is disposed in the substrate 100 in the active area AA. The trench electrode structure TS2 includes a lower electrode 110 and a dielectric layer 112, and further includes at least one of an insulating layer 114 and an insulating layer 116. The trench electrode structure TS2 is located between two adjacent trench electrode structures TS1.

在一實施例中，下部電極110的頂面與下部電極102的頂面等高，且下部電極110與下部電極102具有相同的寬度。下部電極110的材料為摻雜多晶矽或金屬(如，鎢、銅或鋁)等導體材料。 In one embodiment, the top surface of the lower electrode 110 is the same height as the top surface of the lower electrode 102, and the lower electrode 110 and the lower electrode 102 have the same width. The material of the lower electrode 110 is a conductive material such as doped polysilicon or metal (eg, tungsten, copper, or aluminum).

介電層112位於下部電極110上。介電層112的頂面實質上與基底100的頂面共平面。介電層112可位於相鄰兩個上部電極104之間。介電層112的寬度可等於或大於下部電極110的寬度。在此實施例中，介電層112的寬度是以等於下部電極110的寬度為例來進行說明。介電層112的材料分別為氧化矽或氮化矽等介電材料。 The dielectric layer 112 is located on the lower electrode 110. The top surface of the dielectric layer 112 is substantially coplanar with the top surface of the substrate 100. The dielectric layer 112 may be located between two adjacent upper electrodes 104. The width of the dielectric layer 112 may be equal to or greater than the width of the lower electrode 110. In this embodiment, the width of the dielectric layer 112 is equal to the width of the lower electrode 110 as an example for description. The material of the dielectric layer 112 is a dielectric material such as silicon oxide or silicon nitride.

絕緣層114設置於介電層112與下部電極110之間。絕緣層114的材料與介電層112的材料可相同或不同。絕緣層116設置於所述基底100與下部電極110之間，且更延伸至基底100與所述介電層112之間。絕緣層116的材料與介電層112的材料可相同或不同。基底100與下部電極110可藉由絕緣層116而彼此電性隔離。絕緣層114與絕緣層116的材料為氧化矽或氮化矽等介電材料。 The insulating layer 114 is disposed between the dielectric layer 112 and the lower electrode 110. The material of the insulating layer 114 and the material of the dielectric layer 112 may be the same or different. The insulating layer 116 is disposed between the substrate 100 and the lower electrode 110 and further extends between the substrate 100 and the dielectric layer 112. The material of the insulating layer 116 and the material of the dielectric layer 112 may be the same or different. The substrate 100 and the lower electrode 110 can be electrically isolated from each other by the insulating layer 116. The insulating layer 114 and the insulating layer 116 are made of dielectric materials such as silicon oxide or silicon nitride.

圖2為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 2 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

請參照圖2，圖2的溝槽金氧半導體元件20與圖1的溝槽金氧半導體元件10的差異在於：溝槽金氧半導體元件20的介電層212接觸下部電極110。亦即，在介電層212與下部電極110之間不具有如圖1所示的絕緣層114。介電層212的材料可為氧化矽或氮化矽等介電材料。此外，溝槽金氧半導體元件20與溝槽金氧半導體元件10中相同的構件以相同的符號表示，且於上述實施例中已詳盡地進行說明，於此不再重複說明。 Please refer to FIG. 2, the difference between the trench MOSFET 20 of FIG. 2 and the trench MOSFET 10 of FIG. 1 is that the dielectric layer 212 of the trench MOSFET 20 contacts the lower electrode 110. That is, there is no insulating layer 114 as shown in FIG. 1 between the dielectric layer 212 and the lower electrode 110. The material of the dielectric layer 212 may be a dielectric material such as silicon oxide or silicon nitride. In addition, the same components in the trench MOSFET 20 and the trench MOSFET 10 are denoted by the same symbols, and have been described in detail in the above-mentioned embodiments, and the description will not be repeated here.

圖3為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 3 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

請參照圖3，圖3的溝槽金氧半導體元件30與圖1的溝槽金氧半導體元件10的差異如下。在溝槽金氧半導體元件30中，介電層312的寬度大於下部電極110的寬度。絕緣層314設置於介電層312與下部電極110之間，且更延伸至基底100與介電層312之間。 絕緣層316的頂面可低於介電層312的底面。此外，溝槽金氧半導體元件30與溝槽金氧半導體元件10中相同的構件以相同的符號表示，且於上述實施例中已詳盡地進行說明，於此不再重複說明。 Please refer to FIG. 3, the differences between the trench MOS device 30 of FIG. 3 and the trench MOS device 10 of FIG. 1 are as follows. In the trench metal oxide semiconductor device 30, the width of the dielectric layer 312 is greater than the width of the lower electrode 110. The insulating layer 314 is disposed between the dielectric layer 312 and the lower electrode 110 and further extends between the substrate 100 and the dielectric layer 312. The top surface of the insulating layer 316 may be lower than the bottom surface of the dielectric layer 312. In addition, the same components in the trench MOSFET 30 and the trench MOSFET 10 are denoted by the same symbols, and have been described in detail in the above-mentioned embodiments, and the description will not be repeated here.

圖4為本發明另一實施例的溝槽金氧半導體元件的剖面圖。 4 is a cross-sectional view of a trench metal oxide semiconductor device according to another embodiment of the invention.

請參照圖4，圖4的溝槽金氧半導體元件40與圖1的溝槽金氧半導體元件10的差異如下。在溝槽金氧半導體元件40中，介電層412接觸下部電極110。亦即，在介電層412與下部電極110之間不具有如圖1所示的絕緣層114。介電層412的材料可為氧化矽或氮化矽等介電材料。下部電極110的頂面高於絕緣層416的頂面。此外，溝槽金氧半導體元件40與溝槽金氧半導體元件10中相同的構件以相同的符號表示，且於上述實施例中已詳盡地進行說明，於此不再重複說明。 Please refer to FIG. 4, the difference between the trench MOS device 40 of FIG. 4 and the trench MOS device 10 of FIG. 1 is as follows. In the trench metal oxide semiconductor device 40, the dielectric layer 412 contacts the lower electrode 110. That is, there is no insulating layer 114 as shown in FIG. 1 between the dielectric layer 412 and the lower electrode 110. The material of the dielectric layer 412 can be a dielectric material such as silicon oxide or silicon nitride. The top surface of the lower electrode 110 is higher than the top surface of the insulating layer 416. In addition, the same components in the trench MOSFET 40 and the trench MOSFET 10 are denoted by the same symbols, and have been described in detail in the above embodiments, and the description will not be repeated here.

基於上述各實施例可知，在溝槽金氧半導體元件10、20、30、40中，由於溝槽電極結構TS2位於相鄰兩個溝槽電極結構TS1之間，在溝槽電極結構TS2的下部電極110上設置介電層112、212、312、412，且介電層112、212、312、412的頂面實質上與基底100的頂面共平面，因此可藉由介電層112、212、312、412增加相鄰兩個溝槽電極結構TS1的上部電極104之間的距離，以降低相鄰兩個上部電極104之間的寄生電容，進而提高溝槽金氧半導體元件10、20、30、40的反應速度。 Based on the foregoing embodiments, it can be seen that in the trench metal oxide semiconductor devices 10, 20, 30, and 40, since the trench electrode structure TS2 is located between two adjacent trench electrode structures TS1, the trench electrode structure TS2 is located below the trench electrode structure TS2. The electrode 110 is provided with dielectric layers 112, 212, 312, 412, and the top surface of the dielectric layers 112, 212, 312, 412 is substantially coplanar with the top surface of the substrate 100, so the dielectric layers 112, 212 can be used , 312, 412 increase the distance between the upper electrodes 104 of two adjacent trench electrode structures TS1 to reduce the parasitic capacitance between the two adjacent upper electrodes 104, thereby increasing the trench MOS device 10, 20, The reaction speed of 30 and 40.

綜上所述，上述實施例的溝槽金氧半導體元件可藉由介電層增加相鄰兩個溝槽電極結構的上部電極之間的距離，藉此可使得溝槽金氧半導體元件的相鄰兩個上部電極之間的寄生電容較低，而具有較快的反應速度。並且，下部電極間的間距並未被拉開，故溝槽金氧半導體元件的崩潰電壓仍維持原本的水準。 In summary, the trench metal oxide semiconductor device of the above embodiment can increase the distance between the upper electrodes of two adjacent trench electrode structures through the dielectric layer, thereby enabling the phase of the trench metal oxide semiconductor device to be increased. The parasitic capacitance between the two adjacent upper electrodes is lower, and the reaction speed is faster. In addition, the distance between the lower electrodes has not been stretched, so the breakdown voltage of the trench MOS device still maintains the original level.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

20:溝槽金氧半導體元件 20: Trench metal oxide semiconductor components

100:基底 100: base

100a:矽基板 100a: Silicon substrate

100b:磊晶矽層 100b: epitaxial silicon layer

102、110:下部電極 102, 110: lower electrode

104:上部電極 104: Upper electrode

106、108、116:絕緣層 106, 108, 116: insulating layer

212:介電層 212: Dielectric layer

AA:主動區 AA: active area

TS1、TS2:溝槽電極結構 TS1, TS2: trench electrode structure

Claims (12)

一種溝槽金氧半導體元件，包括:基底，定義有主動區；多個第一溝槽電極結構，設置於所述主動區的所述基底中，且每個第一溝槽電極結構包括第一下部電極與位於所述第一下部電極上的上部電極，其中所述基底、所述第一下部電極與所述上部電極彼此電性隔離；以及第二溝槽電極結構，設置於所述主動區的所述基底中，且所述第二溝槽電極結構包括第二下部電極與位於所述第二下部電極上的介電層，其中所述介電層的頂面實質上與所述基底的頂面共平面，所述基底與所述第二下部電極彼此電性隔離，其中所述第二溝槽電極結構位於相鄰兩個第一溝槽電極結構之間。 A trench metal oxide semiconductor device, comprising: a substrate with an active region defined; a plurality of first trench electrode structures arranged in the substrate of the active region, and each first trench electrode structure includes a first trench electrode structure. The lower electrode and the upper electrode located on the first lower electrode, wherein the substrate, the first lower electrode and the upper electrode are electrically isolated from each other; and the second trench electrode structure is arranged on the In the substrate of the active region, and the second trench electrode structure includes a second lower electrode and a dielectric layer on the second lower electrode, wherein the top surface of the dielectric layer is substantially the same as the top surface of the dielectric layer. The top surface of the substrate is coplanar, the substrate and the second lower electrode are electrically isolated from each other, and the second trench electrode structure is located between two adjacent first trench electrode structures. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述介電層的寬度等於或大於所述第二下部電極的寬度。 According to the trench metal oxide semiconductor device described in claim 1, wherein the width of the dielectric layer is equal to or greater than the width of the second lower electrode. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述介電層接觸所述第二下部電極。 The trench metal oxide semiconductor device according to the first item of the patent application, wherein the dielectric layer is in contact with the second lower electrode. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述第二下部電極的頂面與所述第一下部電極的頂面等高。 In the trench metal oxide semiconductor device described in the first item of the scope of the patent application, the top surface of the second lower electrode is the same height as the top surface of the first lower electrode. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述第二下部電極與所述第一下部電極具有相同的寬度。 The trench metal oxide semiconductor device described in the first item of the scope of patent application, wherein the second lower electrode and the first lower electrode have the same width. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述第二溝槽電極結構更包括第二絕緣層，設置於所述基底與所述第二下部電極之間。 According to the trench metal oxide semiconductor device described in claim 1, wherein the second trench electrode structure further includes a second insulating layer disposed between the substrate and the second lower electrode. 如申請專利範圍第6項所述的溝槽金氧半導體元件，其中所述第二絕緣層更延伸至所述基底與所述介電層之間。 According to the trench metal oxide semiconductor device described in claim 6, wherein the second insulating layer further extends between the substrate and the dielectric layer. 如申請專利範圍第6項所述的溝槽金氧半導體元件，其中所述第二下部電極的頂面高於所述第二絕緣層的頂面。 According to the trench metal oxide semiconductor device described in the scope of patent application, the top surface of the second lower electrode is higher than the top surface of the second insulating layer. 如申請專利範圍第6項所述的溝槽金氧半導體元件，其中所述第二絕緣層的材料與所述介電層的材料相同或不同。 According to the trench metal oxide semiconductor device described in item 6 of the scope of patent application, the material of the second insulating layer is the same as or different from the material of the dielectric layer. 如申請專利範圍第1項所述的溝槽金氧半導體元件，每個第一溝槽電極結構更包括第三絕緣層，設置於所述上部電極與所述基底之間以及所述上部電極與所述第一下部電極之間。 According to the trench metal oxide semiconductor device described in the first item of the scope of patent application, each first trench electrode structure further includes a third insulating layer disposed between the upper electrode and the substrate and between the upper electrode and the substrate. Between the first lower electrodes. 如申請專利範圍第1項所述的溝槽金氧半導體元件，其中所述第二溝槽電極結構更包括第四絕緣層，設置於所述介電層與所述第二下部電極之間。 According to the trench metal oxide semiconductor device described in claim 1, wherein the second trench electrode structure further includes a fourth insulating layer disposed between the dielectric layer and the second lower electrode. 如申請專利範圍第11項所述的溝槽金氧半導體元件，其中所述第四絕緣層更延伸至所述基底與所述介電層之間。 In the trench metal oxide semiconductor device described in claim 11, the fourth insulating layer further extends between the substrate and the dielectric layer.
TW107100812A 2018-01-09 2018-01-09 Trench metal oxide semiconductor device TWI737883B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107100812A TWI737883B (en) 2018-01-09 2018-01-09 Trench metal oxide semiconductor device
CN201810182898.7A CN110021656A (en) 2018-01-09 2018-03-06 Groove metal-oxide-semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107100812A TWI737883B (en) 2018-01-09 2018-01-09 Trench metal oxide semiconductor device

Publications (2)

Publication Number Publication Date
TW201931603A TW201931603A (en) 2019-08-01
TWI737883B true TWI737883B (en) 2021-09-01

Family

ID=67188246

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107100812A TWI737883B (en) 2018-01-09 2018-01-09 Trench metal oxide semiconductor device

Country Status (2)

Country Link
CN (1) CN110021656A (en)
TW (1) TWI737883B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120187474A1 (en) * 2011-01-20 2012-07-26 Rexer Christopher L Trench Power MOSFET With Reduced On-Resistance
US8836024B2 (en) * 2012-03-20 2014-09-16 Semiconductor Components Industries, Llc Electronic device including a trench and a conductive structure therein having a contact within a Schottky region and a process of forming the same
US8889512B2 (en) * 2009-10-26 2014-11-18 Infineon Technologies Austria Ag Method and device including transistor component having a field electrode
TWI471982B (en) * 2011-12-14 2015-02-01 Nanya Technology Corp Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof
TWI481038B (en) * 2011-09-22 2015-04-11 Alpha & Omega Semiconductor Trench mosfet with integrated schottky barrier diode

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8889512B2 (en) * 2009-10-26 2014-11-18 Infineon Technologies Austria Ag Method and device including transistor component having a field electrode
US20120187474A1 (en) * 2011-01-20 2012-07-26 Rexer Christopher L Trench Power MOSFET With Reduced On-Resistance
TWI481038B (en) * 2011-09-22 2015-04-11 Alpha & Omega Semiconductor Trench mosfet with integrated schottky barrier diode
TWI471982B (en) * 2011-12-14 2015-02-01 Nanya Technology Corp Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof
US8836024B2 (en) * 2012-03-20 2014-09-16 Semiconductor Components Industries, Llc Electronic device including a trench and a conductive structure therein having a contact within a Schottky region and a process of forming the same

Also Published As

Publication number Publication date
TW201931603A (en) 2019-08-01
CN110021656A (en) 2019-07-16

Similar Documents

Publication Publication Date Title
US20170263761A1 (en) Semiconductor device capable of high-voltage operation
US10879389B2 (en) Semiconductor device capable of high-voltage operation
US20080224233A1 (en) Igfet Device Having a Rf Capability
JP2010187015A (en) Lateral power mosfet for high switching speed
US9502511B2 (en) Trench insulated gate bipolar transistor and edge terminal structure including an L-shaped electric plate capable of raising a breakdown voltage
WO2019159351A1 (en) Silicon carbide semiconductor device
TWI455311B (en) Laterally diffused metal-oxide-semiconductor device
JP7474214B2 (en) Semiconductor Device
JP2014063771A (en) Semiconductor device
US9941357B2 (en) Power MOSFET
TWI737883B (en) Trench metal oxide semiconductor device
TWI587483B (en) Semiconductor device and manufacturing method thereof
TW201543687A (en) Termination structure of semiconductor device and method for manufacturing thereof
TWI429073B (en) Semiconductor structure and method for forming the same
KR20120004954A (en) Semiconductor device
JP2022046240A (en) Semiconductor device
KR950021792A (en) Insulated Semiconductor Device
US10374076B2 (en) Shield indent trench termination for shielded gate MOSFETs
TW201931600A (en) Trench metal oxide semiconductor device
US9059283B1 (en) Semiconductor structure
TWI812318B (en) Transistor structure
JP7201005B2 (en) semiconductor equipment
US10847610B2 (en) Semiconductor device
TWI742221B (en) Trench metal oxide semiconductor device and manufacuring method thereof
TWI724834B (en) Semiconductor device having floating conductive layer