TWI735325B - Driving apparatus and driving method - Google Patents

Abstract

A driving apparatus is applied to a display panel. The driving apparatus includes a compensation circuit and a source driving circuit. The compensation circuit generates, according to a n-th data and a (n+1)-th data which a data line is transmitting in order, a first gray level compensation signal and a second gray level compensation signal respectively. The first gray level compensation signal is having a first least significant bit. The second gray level compensation signal is having a second least significant bit. The source driving circuit receives the first gray level compensation signal and the second gray level compensation signal, and the source driving circuit includes a judge circuit which generates, according to the first least significant bit and the second least significant bit, a judgment signal. When the judgment signal is having a first logic level, the source driving circuit, according to the judgment signal, output a n-th driving voltage signal and a (n+1)-th driving voltage signal based on a first gamma curve. A driving method is also disclosed herein.

Description

Driving device and driving method

The present disclosure relates to a driving device, and more particularly to a driving device used in a display panel.

With the evolution of the liquid crystal display technology, the size of the liquid crystal display panel has become larger and larger, but the impedance value in the liquid crystal display panel has also become larger, resulting in the generation of a resistance capacitance delay (RC delay) effect. For a new generation of liquid crystal display panels with high resolution and high update frequency, this phenomenon will cause the pixels of the liquid crystal display panel to be unable to smoothly charge or discharge within the limited charging or discharging time to the required display screen. The voltage value affects the image quality of the display screen.

An embodiment of the present disclosure relates to a driving device suitable for a display panel, including a compensation circuit and a source driving circuit. The compensation circuit is used for generating a first gray-scale compensation signal and a second gray-scale compensation signal according to an n-th data and a (n+1)-th data sequentially transmitted in a data line, wherein the first gray-scale compensation The signal has a first least significant bit, and the second gray-scale compensation signal has a second least significant bit, where n is a positive integer. The source driving circuit is used for receiving the first gray-scale compensation signal and the second gray-scale compensation signal, and includes a judging circuit, wherein the judging circuit generates a judging signal according to the first least significant bit and the second least significant bit. When the judgment signal has a first logic level, the source driving circuit is used for outputting an nth driving voltage signal and (n+1)th data corresponding to the nth data based on a first gamma curve according to the judgment signal Corresponding to the (n+1)th drive voltage signal. When the judgment signal has a second logic level, the source driving circuit is used to output the nth driving voltage signal and the (n+1)th driving voltage signal based on a second gamma curve according to the judgment signal, wherein the second gamma The curve is different from the first gamma curve.

An embodiment of the present disclosure relates to a driving method, including: judging by a compensation circuit based on an nth data and an (n+1)th data sequentially transmitted in a data line among a plurality of data lines Whether the n data and the (n+1)th data are lower than a first gray-scale threshold, higher than a second gray-scale threshold, or between the first gray-scale threshold and the second gray-scale threshold, where the first gray-scale threshold The first gray-level threshold is lower than the second gray-level threshold, where n is a positive integer; the compensation circuit is used to compare the first gray-level threshold and the second gray-level according to the nth data and the (n+1)th data respectively. The relationship between the critical values generates a first gray-scale compensation signal and a second gray-scale compensation signal, wherein the first gray-scale compensation signal has a first least significant bit, and the second gray-scale compensation signal has a second least significant bit Yuan; Receive the first gray-scale compensation signal and the second gray-scale compensation signal by a source drive circuit, and a judgment circuit in the source drive circuit generates a first least significant bit and a second least significant bit Determining signal; and outputting an nth driving voltage signal corresponding to the nth data and a (n+1)th data corresponding to the (n+1)th data based on a first gamma curve by the source driving circuit according to the determining signal ) Drive voltage signal.

The terms used in this specification generally have their ordinary meanings in the technical field and specific context in which each term is used. The use of examples in this specification, including examples of any items discussed herein, is only illustrative, and in no way limits the scope and meaning of this disclosure or any exemplary terms. Likewise, the present disclosure is not limited to the multiple embodiments given in this specification.

The terms "include", "include", "have", "include", "involved" and similar words used in this article will be understood as changeable, that is, not limited to but means including.

In general, references to "one embodiment," "an embodiment," or "some embodiments" in this specification mean that a specific feature, structure, implementation, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the use of the phrase "in one embodiment", "in one embodiment" or "in some embodiments" in various places in this specification may not all refer to the same embodiment. Moreover, specific features, structures, implementations or characteristics in one or more embodiments can be combined in any suitable manner.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a display device 100 according to some embodiments of the present disclosure. As shown in FIG. 1, the display device 100 includes a display panel DP, a source driving circuit 120, a gate driving circuit 140, and a compensation circuit 180. The display panel DP includes a plurality of pixel circuits 160. Structurally, the display panel DP is coupled to the source driving circuit 120 and the gate driving circuit 140. The source driving circuit 120 is coupled to the compensation circuit 180. Specifically, the pixel circuit 160 in the display panel DP is coupled to the source driving circuit 120 through the data lines DL1-DLn. The pixel circuit 160 in the display panel DP is coupled to the gate driving circuit 140 through the scan lines SL1-SLn. The compensation circuit 180 is used for transmitting grayscale data and gamma voltage to the source driving circuit 120. The source driving circuit 120 is used for receiving the gamma voltage to output a driving voltage signal corresponding to the grayscale data based on the corresponding gamma curve. In some embodiments, the compensation circuit 180 includes a transmitter (not shown). In some embodiments, the source driving circuit 120 includes a receiver (not shown).

FIG. 2 is a schematic diagram of gray scale compensation performed in the compensation circuit 180 according to some embodiments of the present disclosure. As shown in FIG. 2, in some embodiments, the compensation circuit 180 is used to increase or decrease the original grayscale value to the desired brightness grayscale value. For example, when the original grayscale value is above L240, the compensation circuit 180 is used to increase the original grayscale value to L255, so that the pixels in the display panel DP can be charged to the required voltage value during the charging time . When the original grayscale value is below L16, the compensation circuit 180 is used to reduce the original grayscale value to L0. In some embodiments, the range in which the compensation circuit 180 increases the original grayscale value is not limited to L240 or more, and the range of other original grayscale values is within the scope of the embodiment of the present disclosure. In some embodiments, the range of the original gray-scale value reduced by the compensation circuit 180 is not limited to below L16, and the range of other gray-scale values is within the scope of the present disclosure.

FIG. 3A is a schematic diagram illustrating a gray-scale optimization compensation operation performed in the source driving circuit 120 according to some embodiments of the present disclosure. As shown in FIG. 3A, in some embodiments, when the source drive circuit 120 receives the compensated grayscale data output from the compensation circuit 180, and the two pieces of compensated grayscale data meet the starting conditions, the source drive circuit 120 An optimized compensation operation is performed on the corresponding compensated grayscale data, so that the source driving circuit 120 can output a corresponding driving voltage signal based on the corresponding gamma curve. For example, as shown in Figure 3A, when the grayscale values of the two successive compensation grayscale data are in the range of L0～L16 and L240～L255 respectively, or are in the range of L240～L255 and L0～L16 respectively , That is, the above-mentioned startup conditions are met, and the source driving circuit 120 will perform an optimized compensation operation on the corresponding compensation gray-scale data at this time.

FIG. 3B is a gamma curve diagram of the gray-scale optimization compensation operation performed in the source driving circuit 120 according to some embodiments of the present disclosure. As shown in FIG. 3B, in some embodiments, when two pieces of compensated gray-scale data meet the activation conditions, the source driving circuit 120 is used to receive the compensated gray-scale data and receive a voltage level higher than the voltage level AVDD1 The gamma voltage corresponding to AVDD2 outputs the driving voltage signal corresponding to the compensated grayscale data based on the second gamma curve, so that the charging efficiency is improved. In some embodiments, when the two pieces of compensated grayscale data do not meet the activation conditions, the source driving circuit 120 is used to receive the gamma voltage corresponding to the voltage level AVDD1 to output the compensated grayscale data based on the first gamma curve Corresponding to the driving voltage signal, the first gamma curve is different from the second gamma curve.

In a general practice, the source driving circuit 120 is used to receive the compensated gray-scale data generated by the compensation circuit 180 after increasing the original gray-scale value or decreasing the original gray-scale value for gray-scale optimization. However, the compensation circuit 180 compensates The range overlaps with the range of the gray-scale optimization compensation operation of the source driving circuit 120 in some cases, and this overlapping situation causes the source driving circuit 120 to not need to perform the gray-scale optimization compensation operation.

For example, the brightness of the gray scale value L216 in a data line (such as the data line DL1 in the data lines DL1-DLn) is originally lower than the brightness of the gray scale value L224 in adjacent data. However, after the gray level value L216 is subjected to the gray level compensation of the compensation circuit 180 and the gray level optimization compensation operation of the source drive circuit 120, the gray level value L216 may be relatively higher than the gray level value L224 in the adjacent data. Drive voltage signal. The above situation will make the final brightness displayed by the grayscale value L216 higher than the brightness displayed by the grayscale value L224 in the adjacent data.

Compared with the above-mentioned method, in the embodiment of the present invention, the compensation circuit 180 is used to generate a gray-scale compensation signal, and the source driving circuit 120 outputs a driving voltage signal based on the corresponding gamma curve according to the gray-scale compensation signal, instead of Outputting the driving voltage signal based on the wrong gamma curve causes problems such as gray scale inversion. In this way, the gray-scale compensation of the compensation circuit 180 and the gray-scale optimization compensation operations of the source driving circuit 120 can exist at the same time without conflicting with each other.

FIG. 4A is a schematic diagram illustrating gray-scale compensation and gray-scale optimization compensation operations according to some embodiments of the present disclosure. Figure 4A shows the nth data DATA_N, the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N sequentially transmitted in a data line (for example, the data line DL1 among the data lines DL1-DLn) +2, where n is a positive integer. In some embodiments, the nth data DATA_N, the (n+1)th data DATA_N+1, and the (n+2)th data DATA_N+2 may be the second row, the third row, and the fourth row in the display panel DP. data of. In some embodiments, the nth data DATA_N, the (n+1)th data DATA_N+1, and the (n+2)th data DATA_N+2 are not limited to the signals in the second, third, and fourth rows, and other rows The data of is within the thinking and scope of the embodiments of the present disclosure. In some embodiments, the gray scale value of the gray scale region A is smaller than the gray scale value of the gray scale region B and the gray scale value of the gray scale region B is smaller than the gray scale value of the gray scale region C. In some embodiments, at least one of gray-scale area A, gray-scale area B, and gray-scale area C may further include multiple gray-scale areas (not shown), gray-scale area A, gray-scale area B, and gray-scale areas. The number of regions with different gray levels in the region C is within the scope of the embodiment of the present disclosure.

Please refer to Figure 1 and Figure 6 together. In some embodiments, the compensation circuit 180 in Figure 1 is used to perform grayscale compensation for the nth data DATA_N, the (n+1)th data DATA_N+1, and the (n+2)th data DATA_N+2 to respectively Generate a first gray-scale compensation signal SN, a second gray-scale compensation signal S(N+1), and a third gray-scale compensation signal S(N+2), where the first gray-scale compensation signal SN and the second gray-scale compensation signal S(N+1) and the third gray-scale compensation signal S(N+2) respectively have data corresponding to the nth data DATA_N, the (n+1)th data DATA_N+1, and the (n+2)th data DATA_N+2 The gray scale value is the least significant bit (LSB) generated according to the gray scale area where the nth data DATA_N, the (n+1)th data DATA_N+1, and the (n+2)th data DATA_N+2 are located. The source driving circuit 120 is used for optimizing the gray level of the first gray level compensation signal SN and the second gray level compensation signal S(N+1), so as to output the nth driving voltage signal and the second gamma curve based on the corresponding gamma curve. (N+1) Drive the voltage signal to the corresponding data line, or optimize the gray scale for the second gray-scale compensation signal S(N+1) and the third gray-scale compensation signal S(N+2) to Output the (n+1)th driving voltage signal and the (n+2)th driving voltage signal to the corresponding data line based on the corresponding gamma curve.

FIG. 4B is a truth table corresponding to the gray-scale compensation and gray-scale optimization compensation operations of FIG. 4A according to some embodiments of the present disclosure. As shown in FIG. 4B, the gray-scale areas A, B, and C in the truth table correspond to the gray-scale areas A, B, and C shown in FIG. 4A. In some embodiments, the grayscale value Lmin in the truth table may be 0, and the grayscale value LD may be 16. The grayscale value LE in the truth table can be 240, and the grayscale value Lmax can be 255. In some embodiments, the grayscale values Lmin, LD, LE, and Lmax are positive integers, and other grayscale values Lmin, LD, LE, and Lmax are within the scope of the embodiments of the present disclosure.

In some embodiments, the least significant bit LSB corresponds to the data size of the gray scale value received by the self-compensation circuit 180, where the data size of the gray scale value can be 8 bits, 9 bits, 10 bits, or other bits. The number of yuan. In some embodiments, the first gray-scale compensation signal SN, the second gray-scale compensation signal S(N+1), and the third gray-scale compensation signal S(N+2) output by the compensation circuit 180 include 8-bit size The gray scale value and the least significant bit LSB of 1 bit size. In some embodiments, the range of the gray scale region C includes gray scale value LD to gray scale value 255 (8 bits), gray scale value LD to gray scale value 512 (9 bits) and/or gray scale value LD to The grayscale value is 1023 (10 bits). The range of the gray-scale area C is only an example, and the range of other gray-scale areas C is within the scope of the present disclosure.

In some embodiments, as shown in FIGS. 4A and 4B, for example, when the gray scale value corresponding to the nth data DATA_N is located in the gray scale area A, the compensation circuit 180 is used to generate the first gray scale compensation signal SN The least significant bit SN(B) has a logic level of "1". When the gray scale value corresponding to the n-th data DATA_N is located in the gray scale region B, the least significant bit SN(B) of the compensation circuit 180 for generating the first gray scale compensation signal SN has the logic level “0”. When the gray scale value corresponding to the n-th data DATA_N is located in the gray scale region C, the least significant bit SN(B) of the compensation circuit 180 for generating the first gray scale compensation signal SN has a logic level of “1”. The foregoing embodiment in which the first gray-scale compensation signal SN has a corresponding logic level because the n-th data DATA_N corresponds to the gray-scale regions A, B, and C is also applicable to the (n+1)th data DATA_N+1 and the (n+1)th data DATA_N+1 +2) Data DATA_N+2, so the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N+2 will not be repeated here.

The logic levels ("1" or "0") corresponding to the gray-scale regions A, B, and C are only examples. In different embodiments, the gray-scale regions A, B, and C can correspond to those shown in Fig. 4B. Show the different logic levels.

FIG. 5 is a truth table diagram corresponding to the grayscale optimization compensation operation of FIG. 4A according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 5, when the gray level value corresponding to the nth data DATA_N is located in the gray level area A and the gray level value corresponding to the (n+1)th data DATA_N+1 is located in the gray level area At C, the least significant bit SN(B) corresponding to the nth data DATA_N has a logic level of "1", and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 ) Has a logic level of "1", so that the source driving circuit 120 is used to output the nth driving voltage signal and the nth driving voltage signal corresponding to the nth data DATA_N and the (n+1)th data DATA_N+1 respectively based on the second gamma curve (n+1) Drive voltage signal. When the grayscale value corresponding to the (n+1)th data DATA_N+1 is located in the grayscale area C and the grayscale value corresponding to the (n+2)th data DATA_N+2 is located in the grayscale area A, the (n+ 1) The least significant bit S(N+1)(B) corresponding to the data DATA_N+1 has a logic level of "1", and the least significant bit S(N+2) corresponding to the (n+2) data DATA_N+2 ) (B) has a logic level of "1", so that the source driving circuit 120 is used to output the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N+ respectively based on the second gamma curve 2. The (n+1)th drive voltage signal and the (n+2)th drive voltage signal.

When the gray level value corresponding to the nth data DATA_N is in the gray level area B and the gray level value corresponding to the (n+1)th data DATA_N+1 is in the gray level area C, the least significant bit corresponding to the nth data DATA_N SN(B) has a logic level of "0" and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 has a logic level of "1", so that the source drive circuit 120 is used for outputting respectively the nth driving voltage signal and the (n+1)th driving voltage signal corresponding to the nth data DATA_N and the (n+1)th data DATA_N+1 based on the first gamma curve. When the gray level value corresponding to the nth data DATA_N is in the gray level area A and the gray level value corresponding to the (n+1)th data DATA_N+1 is in the gray level area B, the least significant bit corresponding to the nth data DATA_N SN(B) has a logic level of "1" and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 has a logic level of "0", so that the source drive circuit 120 is used for outputting respectively the nth driving voltage signal and the (n+1)th driving voltage signal corresponding to the nth data DATA_N and the (n+1)th data DATA_N+1 based on the first gamma curve. When the gray level value corresponding to the nth data DATA_N is in the gray level area B and the gray level value corresponding to the (n+1)th data DATA_N+1 is in the gray level area B, the least significant bit corresponding to the nth data DATA_N SN(B) has a logic level of "0" and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 has a logic level of "0", so that the source drive circuit 120 is used for outputting respectively the nth driving voltage signal and the (n+1)th driving voltage signal corresponding to the nth data DATA_N and the (n+1)th data DATA_N+1 based on the first gamma curve.

When the grayscale value corresponding to the (n+1)th data DATA_N+1 is located in the grayscale area C and the grayscale value corresponding to the (n+2)th data DATA_N+2 is located in the grayscale area B, the (n+ 1) The least significant bit S(N+1)(B) corresponding to the data DATA_N+1 has a logic level of "1" and the least significant bit S(N+2) corresponding to the (n+2)th data DATA_N+2 ) (B) has a logic level of "0", so that the source driving circuit 120 is used to output data corresponding to the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N+2 respectively based on the gamma curve The (n+1)th drive voltage signal and the (n+2)th drive voltage signal. When the grayscale value corresponding to the (n+1)th data DATA_N+1 is located in the grayscale area B and the grayscale value corresponding to the (n+2)th data DATA_N+2 is located in the grayscale area A, the (n+ 1) The least significant bit S(N+1)(B) corresponding to the data DATA_N+1 has a logic level of "0" and the least significant bit S(N+2) corresponding to the (n+2)th data DATA_N+2 ) (B) has a logic level of "1", so that the source driving circuit 120 is used to output the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N+ respectively based on the first gamma curve 2. The (n+1)th drive voltage signal and the (n+2)th drive voltage signal. When the (n+1)th data DATA_N+1 corresponds to the grayscale value in the grayscale area B and the (n+2)th data DATA_N+2 corresponds to the grayscale value in the grayscale area B, the (n+1)th ) The least significant bit S(N+1)(B) corresponding to the data DATA_N+1 has a logic level "0" and the least significant bit S(N+2) corresponding to the (n+2)th data DATA_N+2 (B) It has a logic level "0", so that the source driving circuit 120 is used to output the (n+1)th data DATA_N+1 and the (n+2)th data DATA_N+2 respectively based on the first gamma curve (N+1)th drive voltage signal and (n+2)th drive voltage signal.

FIG. 6 is a schematic block diagram of some specific circuits of the compensation circuit 180 and the source driving circuit 120 in the display device 100 according to some embodiments of the present disclosure. As shown in Figure 6, in some embodiments, as described above, the compensation circuit 180 is used to transmit the corresponding first gray-scale compensation signal SN, second gray-scale compensation signal S(N+1), and/or third The gray scale compensation signal S(N+2) is sent to the source driving circuit 120. The source drive circuit 120 includes a judgment circuit 520, which is based on the first gray-scale compensation signal SN, the second gray-scale compensation signal S(N+1), and/or the third gray-scale compensation signal S transmitted by the self-compensation circuit 180 (N+2) A judgment signal JDS is generated, and the source driving circuit 120 is used for outputting a driving voltage signal according to the judgment signal JDS. In some embodiments, the judgment circuit 520 includes an AND gate 540, and the gate 540 is used to respond to the first gray-scale compensation signal SN, the second gray-scale compensation signal S(N+1), and/or the third gray-scale The least significant bit of the compensation signal S (N+2) performs an AND logic operation to output the judgment signal JDS. The specific description is given in the embodiment shown in Fig. 5 below.

In some embodiments, the display panel DP in Figure 1 is divided into a proximal end and a distal end (not shown). When the remote end of the display panel DP performs a grayscale optimization compensation operation, the source driving circuit 120 outputs a driving voltage signal according to the judgment signal JDS. The near end of the display panel DP does not perform gamma curve compensation, and the source driving circuit 120 outputs a driving voltage signal based on the first gamma curve.

In some embodiments, after the judgment circuit 520 generates the judgment signal JDS regarding the first gamma curve or the second gamma curve, the source driving circuit 120 generates the corresponding gamma curve based on the look-up table (not shown). The driving voltage signal of the far end or the near end in the display panel DP. In some embodiments, after the judgment circuit 520 generates the judgment signal JDS regarding the first gamma curve or the second gamma curve, the source driving circuit 120 generates the corresponding Gamma curve through a resistor string (R-string) (not shown). The driving voltage signal in the Ma curve.

Please refer to Figure 5. As shown in Figure 5, in some embodiments, when the least significant bit SN(B) corresponding to the nth data DATA_N is at the logic level "1" and the (n+1)th data DATA_N+1 corresponds to When the least significant bit S(N+1)(B) is the logic level "1", or when the (n+1)th data DATA_N+1 corresponds to the least significant bit S(N+1)(B ) Is the logic level "1" and the least significant bit S(N+2)(B) corresponding to the (n+2)th data DATA_N+2 is the logic level "1", the judgment circuit 520 is used to generate The judgment signal JDS with logic level "1".

When the least significant bit SN(B) corresponding to the nth data DATA_N is logic level "0" and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 When it is the logic level "1", when the least significant bit SN(B) corresponding to the nth data DATA_N is the logic level "1" and the least significant bit corresponding to the (n+1)th data DATA_N+1 When S(N+1)(B) is the logic level "0", or when the least significant bit SN(B) corresponding to the nth data DATA_N is the logic level "0" and the (n+1)th data When the least significant bit S(N+1)(B) corresponding to DATA_N+1 is the logic level “0”, the judgment circuit 520 is used to generate the judgment signal JDS with the logic level “0”.

When the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 is logic level "0" and the least significant bit corresponding to the (n+2)th data DATA_N+2 When the bit S(N+2)(B) is the logic level "1", when the (n+1)th data DATA_N+1 corresponds to the least significant bit S(N+1)(B) is the logic level Bit "1" and the least significant bit S(N+2)(B) corresponding to the (n+2)th data DATA_N+2 is the logic level "0", or when the (n+1)th data DATA_N The least significant bit S(N+1)(B) corresponding to +1 is the logic level "0" and the least significant bit S(N+2)( B) When the logic level is “0”, the judgment circuit 520 is used to generate the judgment signal JDS with the logic level “0”.

In some embodiments, when the judgment signal JDS has a logic level of “0”, the source driving circuit 120 is used to output the nth driving voltage signal corresponding to the nth data DATA_N based on the first gamma curve according to the judgment signal JDS and The (n+1)th drive voltage signal corresponding to the (n+1)th data DATA_N+1. When the judgment signal JDS has the logic level “0”, the source driving circuit 120 is used to output the (n+1)th data DATA_N+1 corresponding to the (n+1)th data DATA_N+1 according to the judgment signal JDS based on the first gamma curve The driving voltage signal and the (n+2)th driving voltage signal corresponding to the (n+2)th data DATA_N+2. When the judgment signal JDS has the logic level "1", the source driving circuit 120 is used to output the nth driving voltage signal and the (n+1)th drive voltage signal corresponding to the nth data DATA_N based on the second gamma curve according to the judgment signal JDS The (n+1)th driving voltage signal corresponding to the data DATA_N+1. When the judgment signal JDS has the logic level "1", the source driving circuit 120 is used to output the (n+1)th data DATA_N+1 corresponding to the (n+1)th data DATA_N+1 according to the judgment signal JDS based on the second gamma curve. The driving voltage signal and the (n+2)th driving voltage signal corresponding to the (n+2)th data DATA_N+2.

FIG. 7 is a flowchart illustrating a driving method used in the display device 100 according to some embodiments of the present disclosure. It should be understood that the steps mentioned in this embodiment can be adjusted according to actual needs, and can even be executed simultaneously or partially at the same time, unless the order is specifically stated. The driving method in FIG. 7 can be applied to the block diagrams shown in FIG. 1 and FIG. 6, but is not limited to this. For the sake of clarity, the driving method in Fig. 7 below is illustrated in conjunction with the block diagrams shown in Figs. 1 and 6.

First, in step 710, the compensation circuit 180 is used to sequentially transmit the nth data DATA_N and the (n+ 1) Data DATA_N+1 determines whether the nth data DATA_N and the (n+1)th data DATA_N+1 are lower than the first gray-scale threshold, higher than the second gray-scale threshold, or the first gray-scale threshold and the second Among the gray-scale critical values, the first gray-scale critical value is lower than the second gray-scale critical value. The compensation circuit 180 generates the first gray-scale compensation signal SN and the second gray-scale compensation signal SN according to the relationship between the n-th data DATA_N and the (n+1)-th data DATA_N+1 with respect to the first gray-scale threshold and the second gray-scale threshold, respectively. Grayscale compensation signal S(N+1), where the first grayscale compensation signal SN has the corresponding least significant bit SN(B), and the second grayscale compensation signal S(N+1) has the corresponding least significant bit S(N+1)(B). When the nth data DATA_N is lower than the first grayscale threshold or higher than the second grayscale threshold, the compensation circuit 180 sets the least significant bit SN(B) corresponding to the nth data DATA_N as the logic level" 1". When the (n+1)th data DATA_N+1 is lower than the first grayscale threshold or higher than the second grayscale threshold, the compensation circuit 180 sets the lowest value corresponding to the (n+1)th data DATA_N+1 The valid bit S(N+1)(B) is the logic level "1". When the n-th data DATA_N is between the first gray-scale threshold and the second gray-scale threshold, the compensation circuit 180 sets the least significant bit SN(B) corresponding to the n-th data DATA_N as the logic level "0 ". When the (n+1)th data DATA_N+1 is between the first grayscale threshold and the second grayscale threshold, the compensation circuit 180 sets the least effective corresponding to the (n+1)th data DATA_N+1 The bit S(N+1)(B) is the logic level "0".

Next, in step 720, the first gray-scale compensation signal SN and the second gray-scale compensation signal S(N+1) are received by the source drive circuit 120, and the judgment circuit 520 in the source drive circuit 120 corresponds to the first The least significant bit SN(B) of the n data DATA_N and the least significant bit S(N+1)(B) corresponding to the (n+1)th data DATA_N+1 generate the judgment signal JDS. In some embodiments, the determination circuit 520 is based on the logic level "1" corresponding to the least significant bit SN(B) of the nth data DATA_N and the least significant bit corresponding to the (n+1)th data DATA_N+1 The logic level "1" of the bit S(N+1)(B) sets the judgment signal JDS to the logic level "1". By the judgment circuit 520 according to the logic level “0” corresponding to the least significant bit SN(B) of the nth data DATA_N and the least significant bit S(N+) corresponding to the (n+1)th data DATA_N+1 1) The logic level "1" of (B) sets the judgment signal JDS to the logic level "0". By the judgment circuit 520 according to the logic level “1” corresponding to the least significant bit SN(B) of the nth data DATA_N and the least significant bit S(N+) corresponding to the (n+1)th data DATA_N+1 1) The logic level "0" of (B) sets the judgment signal JDS to the logic level "0". By the judgment circuit 520 according to the logic level “0” corresponding to the least significant bit SN(B) of the nth data DATA_N and the least significant bit S(N+) corresponding to the (n+1)th data DATA_N+1 1) The logic level "0" of (B) sets the judgment signal JDS to the logic level "0". If the judgment signal JDS is the logic level “1”, the process goes to step 730, and if the judgment signal JDS is the logic level “0”, the process goes to step 740.

In this case, in step 730, the source driving circuit 120 outputs the nth driving voltage signal corresponding to the nth data DATA_N and the first ( n+1) The (n+1)th driving voltage signal corresponding to the data DATA_N+1.

On the other hand, in step 740, the source driving circuit 120 outputs the nth driving voltage signal corresponding to the nth data DATA_N and the (n+th 1) The (n+1)th drive voltage signal corresponding to the data DATA_N+1.

The features of several embodiments are summarized above, so that those familiar with the art can better understand the aspect of the present disclosure. Those familiar with the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures in order to perform the same purpose and/or achieve the same advantages of the embodiments described herein. Those familiar with the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and can produce various changes, substitutions and alterations in this article without departing from the spirit and scope of the present disclosure.

100: display device 120: Source drive circuit 140: Gate drive circuit 160: pixel circuit 180: Compensation circuit 520: Judgment Circuit 540: and gate 710, 720, 730, 740: steps SN: First gray-scale compensation signal S(N+1): The second gray-scale compensation signal S (N+2): third gray scale compensation signal DATA_N: nth data DATA_N+1: (n+1)th data DATA_N+2: the (n+2) data LSB: Least Significant Bit SN(B), S(N+1)(B), S(N+2)(B): the least significant bit JDS: Judgment signal DP: display panel DL1-DLn: data line SL1-SLn: scan line AVDD1: voltage level AVDD2: voltage level Lmin, LD, LE, Lmax: grayscale value A: Grayscale area B: Grayscale area C: Grayscale area

When read in conjunction with the accompanying drawings, the aspect of the present disclosure will be best understood from the following detailed description. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for the purpose of clarity of discussion, the size of each feature can be increased or decreased arbitrarily. FIG. 1 is a schematic diagram of a display device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram showing gray-scale compensation in the compensation circuit according to some embodiments of the present disclosure. FIG. 3A is a schematic diagram illustrating a gray-scale optimization compensation operation performed in the source driving circuit according to some embodiments of the present disclosure. FIG. 3B is a gamma curve diagram of a grayscale optimization compensation operation performed in the source driving circuit according to some embodiments of the present disclosure. FIG. 4A is a schematic diagram illustrating gray-scale compensation and gray-scale optimization compensation operations according to some embodiments of the present disclosure. FIG. 4B is a truth table corresponding to the gray-scale compensation and gray-scale optimization compensation operations of FIG. 4A according to some embodiments of the present disclosure. FIG. 5 is a truth table diagram corresponding to the grayscale optimization compensation operation of FIG. 4A according to some embodiments of the present disclosure. FIG. 6 is a block diagram of some specific circuits of the compensation circuit and the source driving circuit in the display device according to some embodiments of the present disclosure. FIG. 7 is a flowchart of a driving method used in a display device according to some embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) none Foreign hosting information (please note in the order of hosting country, institution, date, and number) none

100: display device

120: Source drive circuit

140: Gate drive circuit

160: pixel circuit

180: Compensation circuit

DP: display panel

DL1-DLn: data line

SL1-SLn: scan line

Claims (10)

A driving device suitable for a display panel, comprising: a compensation circuit for respectively generating a first gray-scale compensation signal according to an nth data and an (n+1)th data sequentially transmitted in a data line And a second gray-scale compensation signal, wherein the first gray-scale compensation signal has a first least significant bit, and the second gray-scale compensation signal has a second least significant bit, where n is a positive integer; and a The source driving circuit is used to receive the first gray-scale compensation signal and the second gray-scale compensation signal, and includes a judging circuit, wherein the judging circuit is based on the first least significant bit and the second least significant bit A judgment signal is generated; wherein when the judgment signal has a first logic level, the source driving circuit is used for outputting an nth driving voltage corresponding to the nth data based on a first gamma curve according to the judgment signal Signal and a (n+1)th drive voltage signal corresponding to the (n+1)th data; when the judgment signal has a second logic level, the source drive circuit is used for the judgment signal based on a The second gamma curve outputs the nth driving voltage signal and the (n+1)th driving voltage signal, wherein the second gamma curve is different from the first gamma curve. The driving device according to claim 1, wherein the gray scale value of a first gray scale region is smaller than the gray scale value of a second gray scale region and the gray scale value of the second gray scale region is smaller than a third gray scale In the case of the grayscale value of the area, When the grayscale value corresponding to the nth data is in the first grayscale area and the grayscale value corresponding to the (n+1)th data is in the third grayscale area, or when the nth data is When the corresponding gray-scale value is in the third gray-scale region and the gray-scale value corresponding to the (n+1)th data is in the first gray-scale region, the determining circuit is used to generate a second logic level The judgment signal. The driving device according to claim 1, wherein the gray scale value of a first gray scale region is smaller than the gray scale value of a second gray scale region and the gray scale value of the second gray scale region is smaller than a third gray scale In the case of the gray-scale value of the region, when the gray-scale value corresponding to the n-th data is located in the first gray-scale area and the gray-scale value corresponding to the (n+1)-th data is located in the third gray-scale area , Or when the gray level value corresponding to the nth data is located in the third gray level area and the gray level value corresponding to the (n+1)th data is located in the first gray level area, the compensation circuit is used for Generating the first gray-scale compensation signal having the first least significant bit of the second logic level and the second gray-scale compensation signal having the second least significant bit of the second logic level, and The judgment signal has the second logic level. The driving device according to claim 1, wherein the gray scale value of a first gray scale region is smaller than the gray scale value of a second gray scale region and the gray scale value of the second gray scale region is smaller than a third gray scale In the case of the grayscale value of the area, when the grayscale value corresponding to the nth data is located in the first grayscale area, The first least significant bit of the first gray-scale compensation signal has the second logic level; when the gray-scale value corresponding to the n-th data is located in the second gray-scale region, the first gray-scale compensation signal The first least significant bit has the first logic level; when the gray scale value corresponding to the nth data is located in the third gray scale region, the first least significant bit of the first gray scale compensation signal The yuan has the second logic level. The driving device according to claim 1, wherein the judgment circuit includes: an AND gate for performing an AND logic operation on the first least significant bit and the second least significant bit, To output the judgment signal. A driving method includes: judging the nth data and the (n+ 1) Whether the data is lower than a first gray-scale threshold, higher than a second gray-scale threshold, or between the first gray-scale threshold and the second gray-scale threshold, where the first gray-scale threshold The value is lower than the second gray-scale threshold, where n is a positive integer; the compensation circuit is used to compare the first gray-scale threshold and the second gray-scale threshold according to the nth data and the (n+1)th data respectively. The relationship between the gray scale critical value Generating a first gray-scale compensation signal and a second gray-scale compensation signal, wherein the first gray-scale compensation signal has a first least significant bit, and the second gray-scale compensation signal has a second least significant bit; The first gray-scale compensation signal and the second gray-scale compensation signal are received by a source drive circuit, and a judgment circuit in the source drive circuit is based on the first least significant bit and the second least significant bit Element generates a judgment signal; and the source driving circuit outputs an nth driving voltage signal corresponding to the nth data and the (n+1)th data corresponding to the nth data based on a first gamma curve based on the judgment signal One of the (n+1)th drive voltage signals. The driving method according to claim 6, further comprising: when the n-th data is lower than the first gray-scale threshold or higher than the second gray-scale threshold, the compensation circuit sets the first least significant bit Is a second logic level; when the (n+1)th data is lower than the first gray-scale threshold or higher than the second gray-scale threshold, the compensation circuit sets the second least significant bit as The second logic level; when the nth data is between the first gray-scale threshold and the second gray-scale threshold, the compensation circuit sets the first least significant bit to a first logic level And when the (n+1)th data is between the first gray-scale threshold and the second gray-scale threshold, the compensation circuit sets the second least significant bit as the first logic level; Wherein between the first gray-scale critical value and the second gray-scale critical value, at least one gray-scale critical value is included. The driving method according to claim 7, further comprising: using the judging circuit according to the first least significant bit set to the second logic level and the second least significant bit set to the second logic level Bit sets the judgment signal to a logic high level; and the source drive circuit outputs the nth drive voltage signal and the (n+1)th drive based on a second gamma curve based on the judgment signal of the logic high level Voltage signal. The driving method according to claim 7, further comprising: using the judging circuit according to the first least significant bit set to the first logic level and the second least significant bit set to the second logic level Bit sets the judgment signal to a logic low level; by the judgment circuit according to the first least significant bit set to the second logic level and the second least significant bit set to the first logic level Set the judgment signal to a logic low level; the judgment circuit sets the first least significant bit set to the first logic level and the second least significant bit set to the first logic level The determination signal is a logic low potential; and the source driving circuit outputs the nth driving voltage signal and the (n+1)th driving voltage signal based on the first gamma curve according to the determination signal of the logic low potential. The driving method according to claim 6, further comprising: receiving the first least significant bit and the second least significant bit through one of the judging circuits and the (AND) gate to perform an AND logic operation to output The judgment signal.

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