TWI734261B - High density ball grid array (bga) package capacitor design - Google Patents

High density ball grid array (bga) package capacitor design Download PDF

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Publication number
TWI734261B
TWI734261B TW108141537A TW108141537A TWI734261B TW I734261 B TWI734261 B TW I734261B TW 108141537 A TW108141537 A TW 108141537A TW 108141537 A TW108141537 A TW 108141537A TW I734261 B TWI734261 B TW I734261B
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Taiwan
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integrated circuit
contact
ball
coupled
terminal
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TW108141537A
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Chinese (zh)
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TW202021078A (en
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史考特 克爾曼
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美商谷歌有限責任公司
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    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.

Description

高密度球格陣列封裝電容器設計Design of High Density Ball Grid Array Packaged Capacitor

一球格陣列(BGA)係用於具有大量互連件之積體電路之一類型之封裝。一BGA封裝在一底側上包含數個電接觸件以在積體電路與其上安裝BGA封裝之一印刷電路板(PCB)之間提供電連接件。該等接觸件在BGA封裝之底側上之銅墊上呈焊球或「接觸球」之形式。接觸球將電壓及功率供應至積體電路，且提供供電信號往返於積體電路行進之路徑。BGA封裝之一頂側上之可用面積受多個因素限制，諸如：電路組件、用於底部填充環氧樹脂之面積、用於一蓋或結構環附接之面積及用於黏合劑滲出之面積。BGA封裝之一底側上之面積受通常密集接觸球陣列限制。傳統上，其上安裝BGA封裝之PCB包含用於使電源電壓中之漣波平滑化之電容器。A ball grid array (BGA) is a type of package used for integrated circuits with a large number of interconnects. A BGA package includes electrical contacts on a bottom side to provide electrical connections between an integrated circuit and a printed circuit board (PCB) on which the BGA package is mounted. These contacts are in the form of solder balls or "contact balls" on the copper pads on the bottom side of the BGA package. The contact ball supplies voltage and power to the integrated circuit, and provides a path for the power supply signal to travel to and from the integrated circuit. The usable area on one of the top sides of the BGA package is limited by a number of factors, such as: circuit components, area for underfill epoxy, area for attachment of a cover or structural ring, and area for adhesive bleeding . The area on one of the bottom sides of the BGA package is limited by the usual dense contact ball array. Traditionally, the PCB on which the BGA package is mounted includes a capacitor for smoothing ripples in the power supply voltage.

根據本發明之一項實施方案，一種積體電路封裝包含：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；及一球格陣列，其經形成於該基板之該第一側上。該球格陣列包含配置成一圖案之多個接觸球。該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入。該積體電路封裝亦包含一電容器，該電容器經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子。According to an embodiment of the present invention, an integrated circuit package includes: a substrate having a first side and a second side opposite to the first side; and an integrated circuit component coupled to the substrate The second side; and a ball grid array formed on the first side of the substrate. The ball grid array includes a plurality of contact balls arranged in a pattern. Each of the first subgroup of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of the second subgroup of the contact balls is electrically coupled to the integrated circuit One of the circuit components is the second voltage input. The integrated circuit package also includes a capacitor mounted to the first side and having a first terminal coupled to one of the first contact balls in the first subgroup of the contact balls and coupled to the A second terminal of a second contact ball in the second subgroup of contact balls.

在上述積體電路封裝之一些實施方案中，該第一電壓輸入係一互補金屬氧化物半導體電路之一汲極電壓輸入，且該第二電壓輸入係該互補金屬氧化物半導體電路之一汲電(sink)電壓輸入。在上述積體電路封裝之一些實施方案中，該球格陣列具有1.27毫米或更小之一節距。在上述積體電路封裝之一些實施方案中，該第一接觸球及該第二接觸球係該球格陣列中之相鄰者。在上述積體電路封裝之一些實施方案中，該第一接觸球及該第二接觸球在該球格陣列中沿相對於該圖案之一對角方向彼此相鄰。在一些實施方案中，上述積體電路封裝進一步包含一橋接器，該橋接器電耦合一第三接觸球與該第一接觸球或該第二接觸球之至少一者。在上述積體電路封裝之一些實施方案中，該電容器包含一電容器主體，該電容器主體經安置於該基板之該第一側上之一絕緣層上方。在上述積體電路封裝之一些實施方案中，各接觸球具有自該基板之該第一側延伸遠於該電容器之一高度之一高度。在上述積體電路封裝之一些實施方案中，該電容器之各端子透過一接觸墊與該接觸球電接觸，且該接觸墊經安置於沈積於該基板之該第一側上之一介電層上方且經安置於沈積於該介電層上方之一絕緣層下方。在上述積體電路封裝之一些實施方案中，一第三接觸球與該第一端子之間的一間隙避免該接觸球與該第一端子之間的電弧效應。In some embodiments of the integrated circuit package described above, the first voltage input is a drain voltage input of a complementary metal oxide semiconductor circuit, and the second voltage input is a drain voltage input of the complementary metal oxide semiconductor circuit (sink) Voltage input. In some embodiments of the integrated circuit package described above, the ball grid array has a pitch of 1.27 millimeters or less. In some embodiments of the integrated circuit package described above, the first contact ball and the second contact ball are adjacent ones in the ball grid array. In some embodiments of the integrated circuit package described above, the first contact ball and the second contact ball are adjacent to each other in a diagonal direction with respect to the pattern in the ball grid array. In some embodiments, the integrated circuit package further includes a bridge that electrically couples a third contact ball and at least one of the first contact ball or the second contact ball. In some implementations of the integrated circuit package described above, the capacitor includes a capacitor body disposed over an insulating layer on the first side of the substrate. In some embodiments of the integrated circuit package described above, each contact ball has a height extending from the first side of the substrate farther than a height of the capacitor. In some implementations of the integrated circuit package described above, each terminal of the capacitor is in electrical contact with the contact ball through a contact pad, and the contact pad is disposed on a dielectric layer deposited on the first side of the substrate Above and below an insulating layer deposited above the dielectric layer. In some embodiments of the integrated circuit package described above, a gap between a third contact ball and the first terminal prevents arcing effects between the contact ball and the first terminal.

根據本發明之一項實施方案，一種系統包含：一印刷電路板；及一積體電路封裝，其經安裝於該印刷電路板上。該積體電路封裝包含：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；及一球格陣列，其經形成於該基板之該第一側上。該球格陣列包含配置成一圖案之多個接觸球。該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入。該積體電路封裝亦包含一電容器，該電容器經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子。According to an embodiment of the present invention, a system includes: a printed circuit board; and an integrated circuit package mounted on the printed circuit board. The integrated circuit package includes: a substrate having a first side and a second side opposite to the first side; an integrated circuit component coupled to the second side of the substrate; and a ball The grid array is formed on the first side of the substrate. The ball grid array includes a plurality of contact balls arranged in a pattern. Each of the first subgroup of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of the second subgroup of the contact balls is electrically coupled to the integrated circuit One of the circuit components is the second voltage input. The integrated circuit package also includes a capacitor mounted to the first side and having a first terminal coupled to one of the first contact balls in the first subgroup of the contact balls and coupled to the A second terminal of a second contact ball in the second subgroup of contact balls.

在上述系統之一項實施方案中，在該積體電路封裝中，該第一電壓輸入係一互補金屬氧化物半導體電路之一汲極電壓輸入，且該第二電壓輸入係該互補金屬氧化物半導體電路之一汲電電壓輸入。在上述系統之一項實施方案中，在該積體電路封裝中，該球格陣列具有1.27毫米或更小之一節距。在上述系統之一項實施方案中，在該積體電路封裝中，該第一接觸球及該第二接觸球係該球格陣列中之相鄰者。在上述系統之一項實施方案中，該積體電路封裝進一步包含一橋接器，該橋接器電耦合一第三接觸球與該第一接觸球或該第二接觸球之至少一者。在上述系統之一項實施方案中，在該積體電路封裝中，該電容器包含一電容器主體，該電容器主體經安置於該基板之該第一側上之一絕緣層上方。在一項實施方案中，上述系統進一步包含一記憶體電路封裝，該記憶體電路封裝經安裝於該印刷電路板上，該記憶體電路封裝儲存指令或資料以供該記憶體電路封裝之該積體電路組件處理。在一項實施方案中，上述系統進一步包含一板電容器，該板電容器經安裝於該印刷電路板上，該板電容器具有：一汲極電壓端子，其與將一汲極電壓提供至該積體電路組件之一第一電源端子耦合；及一汲電電壓端子，其與將一汲電電壓提供至該積體電路組件之一第二電源端子耦合。在一項實施方案中，上述系統進一步包含：一第一電源端子，其經安裝於該印刷電路板上且經耦合至該第一接觸球；及一第二電源端子，其經安裝於該印刷電路板上且經耦合至該第二接觸球。在一項實施方案中，上述系統進一步包含一記憶體電路封裝，該記憶體電路封裝經安裝於該印刷電路板上，其中該記憶體電路封裝在一底側處包含一第二球格陣列，該第二球格陣列包含多個接觸球，其中該第二球格陣列包含一第二電容器，該第二電容器具有：一汲極電壓端子，其與一汲極電壓接觸球耦合；及一汲電電壓端子，其與一汲電電壓接觸球耦合，且其中該汲極電壓接觸球，及該汲電電壓接觸球選自該第二球格陣列。In an embodiment of the above system, in the integrated circuit package, the first voltage input is a drain voltage input of a complementary metal oxide semiconductor circuit, and the second voltage input is the complementary metal oxide One of the semiconductor circuits draws voltage input. In one embodiment of the above system, in the integrated circuit package, the ball grid array has a pitch of 1.27 mm or less. In one embodiment of the above system, in the integrated circuit package, the first contact ball and the second contact ball are adjacent ones in the ball grid array. In an embodiment of the above system, the integrated circuit package further includes a bridge that electrically couples a third contact ball and at least one of the first contact ball or the second contact ball. In one embodiment of the above system, in the integrated circuit package, the capacitor includes a capacitor body disposed over an insulating layer on the first side of the substrate. In one embodiment, the above-mentioned system further includes a memory circuit package mounted on the printed circuit board, and the memory circuit package stores instructions or data for the product of the memory circuit package. Body circuit assembly processing. In one embodiment, the above-mentioned system further includes a plate capacitor mounted on the printed circuit board, the plate capacitor having: a drain voltage terminal and a drain voltage to the integrated body One of the circuit components is coupled to a first power terminal; and a drain voltage terminal is coupled to a second power terminal that provides a drain voltage to the integrated circuit component. In one embodiment, the above-mentioned system further includes: a first power terminal mounted on the printed circuit board and coupled to the first contact ball; and a second power terminal mounted on the printed circuit board. The circuit board is coupled to the second contact ball. In one embodiment, the above system further includes a memory circuit package mounted on the printed circuit board, wherein the memory circuit package includes a second ball grid array at a bottom side, The second ball grid array includes a plurality of contact balls, wherein the second ball grid array includes a second capacitor having: a drain voltage terminal coupled with a drain voltage contact ball; and a drain The electric voltage terminal is coupled with a drain voltage contact ball, wherein the drain voltage contact ball, and the drain voltage contact ball are selected from the second ball grid array.

相關申請案之交叉參考Cross reference of related applications

本申請案主張2018年11月15日申請之美國臨時專利申請案第62/767,922號之權益，該案之全部內容及主旨以引用的方式併入本文中。This application claims the rights and interests of U.S. Provisional Patent Application No. 62/767,922 filed on November 15, 2018. The entire content and subject matter of the case are incorporated herein by reference.

在下文詳細描述中，闡述眾多特定細節以提供對本發明之一全面理解。然而，對於一般技術者將顯而易見的是，可在沒有一些此等特定細節之情況下實踐本發明之實施方案。在其他情況下，未詳細展示熟知結構及技術以免模糊本發明。In the following detailed description, numerous specific details are set forth to provide a comprehensive understanding of one of the present invention. However, it will be obvious to those of ordinary skill that the embodiments of the present invention can be practiced without some of these specific details. In other cases, well-known structures and technologies are not shown in detail so as not to obscure the present invention.

本文中所揭示之系統係關於積體電路封裝。更具體而言，本文中所揭示之系統提供用於在封裝之一「底側」上具有增加電容以支援高頻率及高電流操作條件之積體電路之封裝解決方案。The system disclosed in this article is about integrated circuit packaging. More specifically, the system disclosed herein provides a packaging solution for an integrated circuit with increased capacitance on the "bottom side" of the package to support high frequency and high current operating conditions.

現代大型積體電路裝置(諸如特定應用積體電路(ASIC)及通用處理器)可在高頻率、高功率規格下操作，由此需要耦合至電路以避免電感效應之額外電容性資源，此可在至積體電路之電流急劇增加時(諸如在一運算密集型程序開始時)降低電源電壓。所得電壓降可降低電路之速度，增加干擾且增加錯誤率。旁路電容器用來減少至積體電路之電源連接件上之此電壓漣波。該等電容器在電路中越接近負載(即，積體電路)，效率越高。通常用於具有諸多互連件及大功率要求之積體電路之球格陣列(BGA)封裝具有待放置電容器之有限面積。用來在一BGA封裝中將電容器放置成更接近積體電路之先前方法涉及移除BGA封裝之一底側上之接觸球。然而，自BGA封裝移除接觸球對總電路效能具有一負面效應，此係因為BGA中保留之較少接觸球中之增加電流輸送量。除電流輸送量之一基本限制以外，接觸球中之不可逆效應亦使封裝式電路之長期可靠性受到威脅。若延長超過一定時間週期，甚至接觸球之規格內之連續高電流輸送量可能損壞接觸球。此外，期望未來積體電路設計在增加之功率下操作，從而需要更多電流來進行晶片操作。據此，在將來，增加積體電路封裝之電容資源之問題將可能惡化。Modern large-scale integrated circuit devices (such as application-specific integrated circuits (ASICs) and general-purpose processors) can operate at high frequency and high power specifications, which require additional capacitive resources coupled to the circuit to avoid inductive effects. When the current to the integrated circuit increases sharply, such as at the beginning of a computationally intensive program, the power supply voltage is reduced. The resulting voltage drop can reduce the speed of the circuit, increase interference and increase the error rate. The bypass capacitor is used to reduce this voltage ripple to the power connection of the integrated circuit. The closer the capacitors are to the load in the circuit (ie, the integrated circuit), the higher the efficiency. Ball grid array (BGA) packages, which are generally used for integrated circuits with many interconnects and high power requirements, have a limited area for capacitors to be placed. Previous methods used to place capacitors closer to integrated circuits in a BGA package involved removing contact balls on one of the bottom sides of the BGA package. However, removing the contact balls from the BGA package has a negative effect on the overall circuit performance because of the increased current delivery in the fewer contact balls remaining in the BGA. In addition to one of the basic limitations of current delivery, the irreversible effect in the contact ball also threatens the long-term reliability of the packaged circuit. If it is extended beyond a certain period of time, even the continuous high current delivery within the specifications of the contact ball may damage the contact ball. In addition, it is expected that future integrated circuit designs will operate at increased power, which will require more current for chip operations. Accordingly, in the future, the problem of increasing the capacitor resources of the integrated circuit package may worsen.

如本文中所揭示之實施方案將一電容器墊及一BGA墊組合成單個單元，使得可將封裝電容器放置於電路封裝之底側上而無需移除接觸球。此允許封裝設計者接近負載(例如，積體電路)添加電容而不會危害接觸球之長期可靠性。在一些實施方案中，BGA墊及電容器墊與橋接相鄰接觸球之電容器組合。在兩端子電容器中，一個端子經連接至電源(例如，一汲極電壓VDD)且另一端子經連接至接地(例如，一汲電源電壓VSS)。相鄰BGA墊同樣可經設計為具有組合墊結構之電源及接地，因此電容器可經放置於墊之間而無需自BGA移除接觸球。The implementation as disclosed herein combines a capacitor pad and a BGA pad into a single unit, so that the packaged capacitor can be placed on the bottom side of the circuit package without removing the contact ball. This allows package designers to add capacitance close to the load (eg, integrated circuit) without compromising the long-term reliability of the contact ball. In some implementations, BGA pads and capacitor pads are combined with capacitors that bridge adjacent contact balls. In a two-terminal capacitor, one terminal is connected to the power supply (for example, a drain voltage VDD) and the other terminal is connected to the ground (for example, a drain power voltage VSS). Adjacent BGA pads can also be designed as power and ground with a combined pad structure, so capacitors can be placed between the pads without removing the contact ball from the BGA.

BGA設計通常遵循標準間距規則，例如一1.27 mm或1.0 mm節距。不同尺寸之標準電容器可與此等不同BGA節距一起使用。再者，客製BGA節距可與各種電容器尺寸對準。BGA designs usually follow standard spacing rules, such as a 1.27 mm or 1.0 mm pitch. Standard capacitors of different sizes can be used with these different BGA pitches. Furthermore, the customized BGA pitch can be aligned with various capacitor sizes.

圖1繪示根據一些實施方案之一積體電路封裝10之一底側。在一些實施方案中，積體電路封裝10可包含經組態以在作為一電子設備之部分之一系統中執行一特定應用(例如，一行動裝置中之一基於GPS之應用)之一積體電路組件，諸如一ASIC。形成於一矽基板105之一第一側101上之一BGA 150包含配置成一圖案之多個接觸球110。一些接觸球110經電耦合至一積體電路組件113之一第一電壓輸入121，且一些接觸球110經電耦合至積體電路組件113之一第二電壓輸入122。積體電路組件113經安置於矽基板105中與第一側相對之一第二側102上。一些接觸球110將輸入/輸出信號耦合至積體電路封裝。在不限制本發明之情況下，球格陣列150之圖案可為正方形、矩形、對角、菱形或任何其他格子組態。在一些實施方案中，BGA 150之圖案可為非對稱的或具有一有限對稱性。更一般而言，BGA 150之尺寸之一量度可為一節距155，在一正方形格子之情況下該節距155可被定義為該格子中之單位單元之一橫向側。FIG. 1 illustrates a bottom side of an integrated circuit package 10 according to some embodiments. In some implementations, the integrated circuit package 10 may include an integrated circuit configured to execute a specific application (for example, a GPS-based application in a mobile device) in a system that is part of an electronic device Circuit components, such as an ASIC. A BGA 150 formed on a first side 101 of a silicon substrate 105 includes a plurality of contact balls 110 arranged in a pattern. Some contact balls 110 are electrically coupled to a first voltage input 121 of an integrated circuit component 113, and some contact balls 110 are electrically coupled to a second voltage input 122 of an integrated circuit component 113. The integrated circuit component 113 is disposed on a second side 102 of the silicon substrate 105 opposite to the first side. Some contact balls 110 couple input/output signals to the integrated circuit package. Without limiting the present invention, the pattern of the ball grid array 150 can be square, rectangular, diagonal, diamond or any other grid configuration. In some embodiments, the pattern of the BGA 150 may be asymmetric or have a finite symmetry. More generally, a measure of the size of the BGA 150 can be a pitch 155. In the case of a square grid, the pitch 155 can be defined as one of the lateral sides of the unit cell in the grid.

在一些實施方案中，積體電路封裝10包含一電容器100，該電容器100具有與一第一接觸球110-1 (其與第一電壓輸入121電耦合)耦合之一第一端子及與一第二鄰近接觸球110-2 (其與第二電壓輸入122電耦合)耦合之一第二端子。在一些實施方案中，第一接觸球110-1及第二接觸球110-2可為BGA 150中最接近之相鄰者。在一些實施方案中，第一接觸球110-1及第二接觸球110-2可在球格陣列中沿一對角方向彼此相鄰。In some embodiments, the integrated circuit package 10 includes a capacitor 100 having a first terminal coupled to a first contact ball 110-1 (which is electrically coupled to the first voltage input 121) and a first terminal Two adjacent contact balls 110-2 (which are electrically coupled to the second voltage input 122) are coupled to a second terminal. In some embodiments, the first contact ball 110-1 and the second contact ball 110-2 may be the closest neighbors in the BGA 150. In some embodiments, the first contact ball 110-1 and the second contact ball 110-2 may be adjacent to each other along a diagonal direction in the ball grid array.

在一些實施方案中，第一電壓輸入121經耦合至積體電路組件113之一互補金屬氧化物半導體(CMOS)裝置中之一汲極電壓(VDD)，且第二電壓輸入122經耦合至積體電路組件113之一CMOS裝置中之一汲電電壓(VSS)。In some implementations, the first voltage input 121 is coupled to a drain voltage (VDD) in a complementary metal oxide semiconductor (CMOS) device of the integrated circuit component 113, and the second voltage input 122 is coupled to the product A drain voltage (VSS) in a CMOS device of the bulk circuit component 113.

圖2A繪示根據一些實施方案之用於積體電路封裝20之一底側201上之一電容器之接觸墊之一平面視圖，該積體電路封裝20在相鄰接觸球210a與210b (下文中統稱為「接觸球210」)之間包含一電容器200。接觸球210經由接觸墊220電耦合至ASIC封裝20之相對側上之電路組件。接觸球210a及210b可在一正方形BGA 250中彼此對角相鄰(例如，接觸球210a及210b係沿一對角方向之相鄰者)，由此允許電容器200之長度適合BGA 250而無需移除接觸球210。此允許封裝設計者調整電容器200以將一所期望電容添加至ASIC封裝20而不會危害接觸球210之長期可靠性。在本發明中，BGA墊220及電容器墊經組合成合併墊220a及220b，因此電容器200可經放置於接觸球210a與210b之間。在一典型兩端子電容器中，一個端子(例如，端子201a)可經電耦合至電源(例如，一汲極電壓VDD)，且另一端子(例如，端子201b)可經電耦合至接地(例如，一汲電電壓VSS、接地或一「體」電壓)。端子211a及端子211b在下文中將統稱為「端子211」。相鄰合併墊220a及220b經設計為使能夠在BGA墊220之間放置電容器200而不會縮減接觸球210之電源及接地接觸墊。一電容器主體212將體電容提供至電容器200。在一些實施方案中，電容器主體212包含與電容器端子接觸且藉由一介電材料隔開之多個導電(例如，金屬)指狀物。FIG. 2A shows a plan view of a contact pad for a capacitor on a bottom side 201 of an integrated circuit package 20 according to some embodiments. The integrated circuit package 20 has adjacent contact balls 210a and 210b (hereinafter Collectively referred to as "contact ball 210") a capacitor 200 is included in between. The contact ball 210 is electrically coupled to the circuit components on the opposite side of the ASIC package 20 via the contact pad 220. The contact balls 210a and 210b can be diagonally adjacent to each other in a square BGA 250 (for example, the contact balls 210a and 210b are adjacent in a diagonal direction), thereby allowing the length of the capacitor 200 to fit the BGA 250 without moving In addition to the contact ball 210. This allows the package designer to adjust the capacitor 200 to add a desired capacitance to the ASIC package 20 without compromising the long-term reliability of the contact ball 210. In the present invention, the BGA pad 220 and the capacitor pad are combined into combined pads 220a and 220b, so the capacitor 200 can be placed between the contact balls 210a and 210b. In a typical two-terminal capacitor, one terminal (e.g., terminal 201a) can be electrically coupled to a power source (e.g., a drain voltage VDD), and the other terminal (e.g., terminal 201b) can be electrically coupled to ground (e.g., , A drain voltage VSS, ground or a "body" voltage). The terminal 211a and the terminal 211b will be collectively referred to as "terminal 211" hereinafter. The adjacent merged pads 220a and 220b are designed to enable the capacitor 200 to be placed between the BGA pads 220 without reducing the power and ground contact pads of the contact ball 210. A capacitor body 212 provides bulk capacitance to the capacitor 200. In some implementations, the capacitor body 212 includes a plurality of conductive (eg, metal) fingers that are in contact with the capacitor terminals and separated by a dielectric material.

在一些實施方案中，藉由考量電容器端子211與接觸球210之間的一間隙距離251及252而將電容器200放置於BGA 250中。給定BGA 250之對稱性，間隙距離251可大於間隙距離252，且兩者可大於一最小值以避免電弧效應；即，與接觸球210具有電壓差之電容器端子201之間的電擊穿。在一些實施方案中，期望間隙252小於間隙251，此係因為端子211b事實上經由合併墊220b電耦合至接觸球210b。在一些實施方案中，間隙距離251可為約0.330 mm且間隙距離252可為約0.090 mm或更大。在一些實施方案中，252之一最小間隙可為0 mm，此係因為BGA球及電容器端子可經電耦合。In some implementations, the capacitor 200 is placed in the BGA 250 by considering a gap distance 251 and 252 between the capacitor terminal 211 and the contact ball 210. Given the symmetry of the BGA 250, the gap distance 251 can be greater than the gap distance 252, and both can be greater than a minimum value to avoid arcing effects; that is, electrical breakdown between the capacitor terminals 201 that have a voltage difference with the contact ball 210. In some embodiments, it is desirable that the gap 252 is smaller than the gap 251 because the terminal 211b is in fact electrically coupled to the contact ball 210b via the merge pad 220b. In some embodiments, the gap distance 251 can be about 0.330 mm and the gap distance 252 can be about 0.090 mm or greater. In some implementations, one of the minimum gaps of 252 can be 0 mm, because the BGA ball and capacitor terminals can be electrically coupled.

圖2B繪示圖2A中所展示之積體電路封裝20之底側201之另一平面視圖，其中移除電容器200。圖2B展示根據一些實施方案之積體電路封裝20之底側201上之接觸墊220之基本細節。接觸墊220可包含BGA墊且亦包含合併墊220a及220b，包含用於電容器之端子(例如電容器200中之端子211)之接觸區域230a及230b (下文中統稱為「接觸區域230」)。一接觸區域係積體電路封裝20之底側之一部分，其中絕緣體層經移除以允許與一電容器端子接觸。接觸區域230可具有具一寬度243及一長度249之一矩形形狀。合併墊220可包含具有一寬度260之一突片。合併墊220a及220b之突片可分離達一間隙241，從而形成電容器200之一總長度245。一間隙247經形成於與電容器200電絕緣之一接觸球210之間。FIG. 2B shows another plan view of the bottom side 201 of the integrated circuit package 20 shown in FIG. 2A with the capacitor 200 removed. FIG. 2B shows basic details of the contact pads 220 on the bottom side 201 of the integrated circuit package 20 according to some implementations. The contact pad 220 may include a BGA pad and also includes merged pads 220a and 220b, including contact areas 230a and 230b (hereinafter collectively referred to as "contact areas 230") for the terminals of the capacitor (for example, the terminal 211 in the capacitor 200). A contact area is a part of the bottom side of the integrated circuit package 20 in which the insulator layer is removed to allow contact with a capacitor terminal. The contact area 230 may have a rectangular shape with a width 243 and a length 249. The merging pad 220 may include a tab having a width 260. The tabs of the combined pads 220a and 220b can be separated by a gap 241, thereby forming a total length 245 of the capacitor 200. A gap 247 is formed between a contact ball 210 that is electrically insulated from the capacitor 200.

在不限制的情況下，BGA 250可遵循不同間距規則。例如，相鄰接觸球之間的一節距255可為1.27 mm或更小(例如，1.0 mm或甚至更小)。在此等組態中，電容器200可包含不同標準尺寸(例如，長度249)。一些實施方案包含按需實現各種電容器長度249之一客製BGA節距255。Without limitation, the BGA 250 can follow different spacing rules. For example, the pitch 255 between adjacent contact balls may be 1.27 mm or less (for example, 1.0 mm or even less). In these configurations, capacitor 200 may include different standard sizes (e.g., length 249). Some implementations include customizing the BGA pitch 255 to achieve one of various capacitor lengths 249 as needed.

圖2C繪示根據一些實施方案之在相鄰接觸球210a與210b之間包含電容器200之積體電路封裝20之一截面視圖。接觸球210及電容器200經安置於矽基板205之底側201上。矽基板具有與底側201相對之一頂側202。該等接觸球分離達一節距255。積體電路組件213可經安置於矽基板205之前側202上。積體電路封裝20中之其他尺寸包含接觸球210之接觸區域之一寬度257、電容器200之端子211之接觸區域之一寬度253及一電容器端子與一最接近接觸球的接觸區域之間填充有一絕緣層270之一間距259。在一些實施方案中，節距255可在0.425 mm與1.78 mm之間。在一些實施方案中，一寬度257可在0.18 mm與0.75 mm之間。在一些實施方案中，寬度253可在0.1 mm與0.25 mm之間。在一些實施方案中，一高度280可在0.3 mm與0.6 mm之間。在一些實施方案中，一寬度245可在0.4 mm與1.0 mm之間。在一些實施方案中，一高度281可在0.2 mm與0.8 mm之間。在一些實施方案中，一間隙259可在0 mm (即，連接)與0.135 mm之間。2C shows a cross-sectional view of an integrated circuit package 20 including a capacitor 200 between adjacent contact balls 210a and 210b according to some embodiments. The contact ball 210 and the capacitor 200 are placed on the bottom side 201 of the silicon substrate 205. The silicon substrate has a top side 202 opposite to the bottom side 201. The contact balls are separated by a pitch of 255. The integrated circuit component 213 can be placed on the front side 202 of the silicon substrate 205. Other dimensions in the integrated circuit package 20 include a width 257 of the contact area of the contact ball 210, a width 253 of the contact area of the terminal 211 of the capacitor 200, and a filling between a capacitor terminal and a contact area closest to the contact ball. The insulating layer 270 has a pitch 259. In some embodiments, the pitch 255 may be between 0.425 mm and 1.78 mm. In some embodiments, a width 257 can be between 0.18 mm and 0.75 mm. In some embodiments, the width 253 may be between 0.1 mm and 0.25 mm. In some embodiments, a height 280 can be between 0.3 mm and 0.6 mm. In some embodiments, a width 245 can be between 0.4 mm and 1.0 mm. In some embodiments, a height 281 can be between 0.2 mm and 0.8 mm. In some embodiments, a gap 259 can be between 0 mm (ie, connected) and 0.135 mm.

電容器主體212包含一電絕緣封裝內之導體及介電材料之交替層。電容器200經安裝於積體電路封裝20之底側201上方，在一些情況下經安裝於絕緣層270 (諸如一焊料遮罩)上方。電容器200具有兩個端子211a及211b，該兩個端子211a及211b經焊接至合併墊220a及220b，該等合併墊220a及220b亦提供至接觸球210之一電連接件。電容器200相對於底側201之一高度280低於接觸球210之一輪廓281。端子211透過形成於一矽基板205上方及ASIC封裝20之底側201上之絕緣層270下方之合併墊220a及220b與接觸球210電接觸，在一些實施方案中，該矽基板包含電路組件。The capacitor body 212 includes alternating layers of conductor and dielectric materials in an electrically insulating package. The capacitor 200 is mounted above the bottom side 201 of the integrated circuit package 20, and in some cases is mounted above the insulating layer 270 (such as a solder mask). The capacitor 200 has two terminals 211a and 211b, and the two terminals 211a and 211b are soldered to the merging pads 220a and 220b, and the merging pads 220a and 220b are also provided to an electrical connection member of the contact ball 210. A height 280 of the capacitor 200 relative to the bottom side 201 is lower than a profile 281 of the contact ball 210. The terminals 211 are in electrical contact with the contact balls 210 through bonding pads 220a and 220b formed above a silicon substrate 205 and below the insulating layer 270 on the bottom side 201 of the ASIC package 20. In some embodiments, the silicon substrate includes circuit components.

圖3A至圖3D分別包含積體電路封裝30A、30B、30C及30D (下文中統稱為「積體電路封裝30」)之底側之部分視圖，包含與本文中所揭示之實施方案一致之不同電容器配置。積體電路封裝30包含接觸墊320，該等接觸墊320亦包含用於攜載一第一電壓之第一電容器端子及第一接觸球之合併墊320a及攜載一第二電壓之第二電容器端子及第二接觸球之合併墊320b (為了清楚起見，圖中未展示接觸球及電容器)。FIGS. 3A to 3D respectively include partial views of the bottom side of integrated circuit packages 30A, 30B, 30C, and 30D (hereinafter collectively referred to as "integrated circuit package 30"), including the differences consistent with the implementation disclosed herein Capacitor configuration. The integrated circuit package 30 includes contact pads 320. The contact pads 320 also include a first capacitor terminal for carrying a first voltage and a combined pad 320a for the first contact ball and a second capacitor for carrying a second voltage The combined pad 320b of the terminal and the second contact ball (for clarity, the contact ball and capacitor are not shown in the figure).

圖3A繪示根據一些實施方案之包含用於呈一第一圖案之多個電容器之接觸墊320之積體電路封裝30A之底側之一部分視圖。第一圖案包含跨作為對角相鄰者之接觸球耦合之電容器。在一些實施方案中，BGA 350係具有交替地按行耦合至正電壓輸入及負電壓輸入之接觸球之一正方形格子。3A shows a partial view of the bottom side of an integrated circuit package 30A including contact pads 320 for a plurality of capacitors in a first pattern according to some implementations. The first pattern includes capacitors coupled across contact balls that are diagonally adjacent. In some embodiments, the BGA 350 has a square grid of contact balls that are alternately coupled to the positive voltage input and the negative voltage input in rows.

圖3B繪示根據一些實施方案之包含用於呈一第二圖案之多個電容器之接觸墊320之積體電路封裝30B之底側之一部分視圖。第二圖案包含跨作為對角相鄰者之接觸球耦合之電容器。在一些實施方案中，BGA 350係一正方形或菱形格子且接觸墊320a及320b交替地按列耦合至正電壓輸入及負電壓輸入。3B shows a partial view of the bottom side of an integrated circuit package 30B including contact pads 320 for a plurality of capacitors in a second pattern according to some implementations. The second pattern includes capacitors coupled across contact balls that are diagonally adjacent. In some implementations, the BGA 350 is a square or diamond grid and the contact pads 320a and 320b are alternately coupled to the positive voltage input and the negative voltage input in columns.

圖3C繪示根據一些實施方案之包含用於呈一橋接圖案之多個電容器之接觸墊320之積體電路封裝30C之底側之一部分視圖。橋接圖案包含跨作為對角相鄰者之接觸球耦合之電容器。在一些實施方案中，BGA 350係具有交替地按列耦合至正電壓輸入及負電壓輸入之接觸球之一正方形或菱形格子。另外，橋接圖案包含正橋接器330a及負橋接器330b (下文中統稱為「橋接器330」)。橋接器330將一個以上接觸墊320電耦合至一給定電容器端子，此可允許單個電容器將電容提供至一個以上接觸球。然而，在諸多情況下，橋接器330可為冗餘的，此係因為在該封裝內VDD墊將彼此連接，VSS墊亦將如此。3C shows a partial view of the bottom side of an integrated circuit package 30C including contact pads 320 for a plurality of capacitors in a bridge pattern according to some implementations. The bridge pattern includes capacitors coupled across contact balls that are diagonally adjacent. In some embodiments, the BGA 350 has a square or diamond lattice with contact balls that are alternately coupled to the positive voltage input and the negative voltage input in columns. In addition, the bridge pattern includes a positive bridge 330a and a negative bridge 330b (hereinafter collectively referred to as "bridge 330"). The bridge 330 electrically couples more than one contact pad 320 to a given capacitor terminal, which may allow a single capacitor to provide capacitance to more than one contact ball. However, in many cases, the bridge 330 can be redundant because the VDD pads will be connected to each other in the package, and so will the VSS pads.

圖3D繪示根據一些實施方案之包含呈一第二橋接圖案之多個電容器之積體電路封裝30D之底側之一部分視圖。第二橋接圖案包含橋接作為對角相鄰者之接觸球之電容器。在一些實施方案中，BGA 350係具有可交替地按列耦合至正電壓輸入、負電壓輸入及/或接地電壓輸入之接觸墊之一正方形或菱形格子。另外，橋接圖案包含並列耦合電容器端子之正橋接器330a及負橋接器330b (下文中統稱為「橋接器330」)。據此，與積體電路封裝30D一致之實施方案可包含一增加之電容。3D shows a partial view of the bottom side of an integrated circuit package 30D including a plurality of capacitors in a second bridge pattern according to some implementations. The second bridge pattern includes a capacitor that bridges contact balls that are diagonally adjacent. In some implementations, the BGA 350 has a square or diamond grid with contact pads that can be alternately coupled to a positive voltage input, a negative voltage input, and/or a ground voltage input in columns. In addition, the bridge pattern includes a positive bridge 330a and a negative bridge 330b (hereinafter collectively referred to as "bridge 330") that are coupled to the capacitor terminals in parallel. Accordingly, the implementation consistent with the integrated circuit package 30D can include an increased capacitance.

圖4繪示根據一些實施方案之一系統400之一截面視圖，該系統400包含安裝於一印刷電路板(PCB) 415上之一積體電路封裝40A及一記憶體電路40B。系統400包含儲存資料及/或指令之一記憶體電路封裝40B及包含一積體電路451之一積體電路封裝40A，該積體電路451經組態以執行指令或處理儲存於記憶體電路封裝40B中之資料。積體電路封裝40A包含形成於積體電路封裝40A中之一矽基板405之一底側401上之一球格陣列450-1。在一些實施方案中，球格陣列450-1包含配置成一圖案之多個接觸球410 (例如，球格陣列150及350)。接觸球410之一子組之各者在與底側401相對之一頂側402上電耦合至積體電路451之一第一電壓輸入或一第二電壓輸入。積體電路封裝40A亦包含一電容器403，該電容器403具有與一第一接觸球(其與第一電壓輸入電耦合)耦合之一第一端子及與一第二接觸球(其與第二電壓輸入電耦合)耦合之一第二端子。4 shows a cross-sectional view of a system 400 according to some embodiments. The system 400 includes an integrated circuit package 40A and a memory circuit 40B mounted on a printed circuit board (PCB) 415. The system 400 includes a memory circuit package 40B that stores data and/or commands and an integrated circuit package 40A that includes an integrated circuit 451. The integrated circuit 451 is configured to execute commands or process storage in the memory circuit package. Information in 40B. The integrated circuit package 40A includes a ball grid array 450-1 formed on a bottom side 401 of a silicon substrate 405 in the integrated circuit package 40A. In some implementations, the ball grid array 450-1 includes a plurality of contact balls 410 (eg, ball grid arrays 150 and 350) arranged in a pattern. Each of a subgroup of contact balls 410 is electrically coupled to a first voltage input or a second voltage input of the integrated circuit 451 on a top side 402 opposite to the bottom side 401. The integrated circuit package 40A also includes a capacitor 403 having a first terminal coupled to a first contact ball (which is electrically coupled to the first voltage input) and a second contact ball (which is electrically coupled to the second voltage input) The input is electrically coupled) coupled to one of the second terminals.

在一些實施方案中，系統400係一電子設備(例如，一個人電腦、一膝上型電腦、一行動電腦、智慧型電話、掌上電腦或類似者)。在一些實施方案中，記憶體電路封裝40B亦在底側401上封裝有一球格陣列450-2，其中在矽基板405之頂側402上具有記憶體區塊453。球格陣列450-2可包含一電容器403，如本文中所揭示。記憶體電路封裝40B可包含可由積體電路封裝40A中之積體電路451存取之一隨機存取記憶體(RAM)，諸如一動態RAM (DRAM)或一同步RAM (SRAM)。In some embodiments, the system 400 is an electronic device (for example, a personal computer, a laptop computer, a mobile computer, a smart phone, a palmtop computer, or the like). In some embodiments, the memory circuit package 40B also houses a ball grid array 450-2 on the bottom side 401, wherein a memory block 453 is provided on the top side 402 of the silicon substrate 405. The ball grid array 450-2 may include a capacitor 403, as disclosed herein. The memory circuit package 40B may include a random access memory (RAM) that can be accessed by the integrated circuit 451 in the integrated circuit package 40A, such as a dynamic RAM (DRAM) or a synchronous RAM (SRAM).

在一些實施方案中，系統400亦可包含安裝於印刷電路板415上之一正電源端子421及一負電源端子422。例如，在一些實施方案中，正電源端子421可將VDD電壓提供至一CMOS電路 (例如，至記憶體區塊453或至積體電路451)。同樣地，在一些實施方案中，負電源端子422可將VSS電壓提供至CMOS電路。此外，在一些實施方案中，正電源端子421及負電源端子422可直接耦合至接觸球410，該等接觸球410繼而將電壓提供至電容器403、積體電路451及記憶體區塊453。此外，在一些實施例中，系統400包含安裝於印刷電路板415上之一板電容器425。板電容器425可針對低頻信號(例如，30 MHz或更小)向系統400提供一電容釋放。在一些實施方案中，板電容器425可具有直接耦合至正電源端子421之一第一端子及直接耦合至負電源端子422之一第二端子。In some implementations, the system 400 may also include a positive power terminal 421 and a negative power terminal 422 mounted on the printed circuit board 415. For example, in some implementations, the positive power terminal 421 can provide the VDD voltage to a CMOS circuit (for example, to the memory block 453 or to the integrated circuit 451). Likewise, in some implementations, the negative power terminal 422 can provide the VSS voltage to the CMOS circuit. In addition, in some implementations, the positive power terminal 421 and the negative power terminal 422 may be directly coupled to the contact balls 410, which in turn provide voltage to the capacitor 403, the integrated circuit 451, and the memory block 453. In addition, in some embodiments, the system 400 includes a board capacitor 425 mounted on the printed circuit board 415. The plate capacitor 425 can provide a capacitor release to the system 400 for low frequency signals (eg, 30 MHz or less). In some implementations, the plate capacitor 425 may have a first terminal directly coupled to the positive power supply terminal 421 and a second terminal directly coupled to the negative power supply terminal 422.

如本文使用，在一系列品項之前的片語「至少一者」(其中術語「及」或「或」用以分離任一品項)修飾整個清單，而非清單的每一成員(即，各品項)。片語「至少一者」不需要選擇至少一個品項；實情係，片語容許包含該等品項之任一者之至少一者及/或該等品項之任何組合之至少一者及/或該等品項之各者之至少一者之一含義。藉由實例，片語「A、B及C之至少一者」或「A、B或C之至少一者」各係指僅A、僅B或僅C；A、B及C之任何組合；及/或A、B及C之各者之至少一者。在術語「包含」、「具有」或類似者用於描述或發明申請專利範圍中的程度上，此術語旨在以類似於術語「包括」在「包括」用作一請求項中之一過渡字詞時所解釋之一方式係包含性的。As used herein, the phrase "at least one" before a series of items (where the term "and" or "or" is used to separate any item) modifies the entire list, rather than each member of the list (ie, each Food items). The phrase "at least one" does not need to select at least one item; the truth is, the phrase allows to include at least one of any of these items and/or at least one of any combination of these items and/ Or at least one of the meanings of each of these items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; any combination of A, B, and C; And/or at least one of each of A, B, and C. To the extent that the terms "include", "have" or the like are used in the description or the scope of the invention patent application, this term is intended to be used as a transition word in a claim similar to the term "include" in "include" One way of interpretation of words is inclusive.

除非明確陳述，否則對一單數元件之引用不旨在意謂「一個且僅一個」，而為「一或多個」。術語「一些」係指一或多個。一般技術者已知或稍後將知道之貫穿本發明描述之各種組態之元件之所有結構及功能等效物明確地以引用之形式併入本文中且旨在藉由本發明技術涵蓋。再者，本文揭示之任何事物皆不旨在專用於公眾，無關於本發明是否在以上描述中明確陳述。Unless expressly stated, reference to a singular element is not intended to mean "one and only one" but "one or more." The term "some" refers to one or more. All the structural and functional equivalents of the various configurations of the elements described in the present invention that are known or will be known later to those of ordinary skill are expressly incorporated herein by reference and are intended to be covered by the technology of the present invention. Furthermore, nothing disclosed in this article is intended to be exclusively used by the public, and it does not matter whether the present invention is explicitly stated in the above description.

儘管本說明書含有諸多細節，但此等不應被解釋為對所主張內容之範疇之限制，而應被解釋為標的物之特定實施方案之描述。亦可在一單一實施方案中組合地實施本說明書中在單獨實施方案之背景中所描述之某些特徵。相反地，在單個實施方案之背景中所描述之不同特徵亦可單獨或以任意適當子組合在多個實施方案中實施。再者，儘管上文可將特徵描述為以特定組合起作用且即使最初如此主張，但在一些情況中，來自所主張組合之一或多個特徵可自組合中刪去，且所主張組合可係關於一子組合或一子組合之變體。Although this specification contains many details, these should not be construed as limitations on the scope of the claimed content, but should be construed as descriptions of specific implementations of the subject matter. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, different features that are described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in a particular combination and even if initially claimed as such, in some cases, one or more of the features from the claimed combination may be omitted from the combination, and the claimed combination may It is about a sub-group or a variant of a sub-group.

本說明書之標的物已相對於特定態樣描述，但可實施其他態樣且其等在下列發明申請專利範圍之範疇內。例如，雖然在圖式中按一特定順序描繪操作，但此不應被理解為要求按所展示之特定順序或循序順序執行此等操作，或執行所有繪示之操作以達成所要結果。在發明申請專利範圍中敘述之動作可以一不同順序執行且仍達成所要結果。作為一個實例，在附圖中描繪之程序不必要求所展示之特定順序或連續順序來達成所要結果。在特定境況中，多任務處理及並行處理可為有利的。再者，在上文中描述之態樣中之各種系統組件之分離不應被理解為在所有態樣中皆需要此分離，且應理解所描述之程式組件及系統通常可一起整合於一單一軟體產品中或封裝至多個軟體產品中。其他變化係在下列發明申請專利範圍之範疇內。The subject matter of this specification has been described with respect to a specific aspect, but other aspects can be implemented and are within the scope of the following invention applications. For example, although the operations are depicted in a specific order in the drawing, this should not be understood as requiring that these operations be performed in the specific order or sequential order shown, or that all the operations shown are performed to achieve the desired result. The actions described in the scope of the invention application can be performed in a different order and still achieve the desired result. As an example, the procedures depicted in the figures do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various system components in the above described aspects should not be understood as requiring this separation in all aspects, and it should be understood that the described program components and systems can usually be integrated together in a single software In the product or packaged in multiple software products. Other changes are within the scope of the following invention patent applications.

10:積體電路封裝 20:積體電路封裝 30A:積體電路封裝 30B:積體電路封裝 30C:積體電路封裝 30D:積體電路封裝 40A:積體電路封裝 40B:記憶體電路 100:電容器 101:第一側 102:第二側 105:矽基板 110:接觸球 110-1:第一接觸球 110-2:第二鄰近接觸球 113:積體電路組件 121:第一電壓輸入 122:第二電壓輸入 150:球格陣列(BGA) 155:節距 200:電容器 201:底側 202:頂側 205:矽基板 210:接觸球 210a:接觸球 210b:接觸球 211a:端子 211b:端子 212:電容器主體 213:積體電路組件 220:接觸墊/BGA墊 220a:合併墊 220b:合併墊 230a:接觸區域 230b:接觸區域 241:間隙 243:寬度 245:總長度/寬度 247:間隙 249:長度 250:正方形BGA 251:間隙距離 252:間隙距離 253:寬度 255:節距 257:寬度 259:間距/間隙 260:寬度 270:絕緣層 280:高度 281:高度/輪廓 320:接觸墊 320a:合併墊 320b:合併墊 330a:正橋接器 330b:負橋接器 350:BGA 400:系統 401:底側 402:頂側 403:電容器 405:矽基板 410:接觸球 415:印刷電路板 421:正電源端子 422:負電源端子 425:板電容器 450-1:球格陣列 450-2:球格陣列 451:積體電路 453:記憶體區塊 10: Integrated circuit packaging 20: Integrated circuit packaging 30A: Integrated circuit package 30B: Integrated circuit package 30C: Integrated circuit package 30D: Integrated circuit package 40A: Integrated circuit package 40B: Memory circuit 100: capacitor 101: first side 102: second side 105: Silicon substrate 110: contact ball 110-1: First contact ball 110-2: Second adjacent contact ball 113: Integrated Circuit Components 121: first voltage input 122: second voltage input 150: Ball grid array (BGA) 155: Pitch 200: capacitor 201: bottom side 202: top side 205: Silicon substrate 210: contact ball 210a: Touch the ball 210b: Touch the ball 211a: Terminal 211b: Terminal 212: Capacitor body 213: Integrated Circuit Components 220: Contact pad/BGA pad 220a: merge pad 220b: merge pad 230a: contact area 230b: contact area 241: Gap 243: width 245: total length/width 247: gap 249: length 250: Square BGA 251: gap distance 252: gap distance 253: width 255: Pitch 257: width 259: pitch/gap 260: width 270: Insulation layer 280: height 281: height/profile 320: contact pad 320a: merge pad 320b: merge pad 330a: Positive bridge 330b: Negative bridge 350: BGA 400: System 401: bottom side 402: top side 403: Capacitor 405: Silicon substrate 410: contact ball 415: Printed Circuit Board 421: Positive power terminal 422: Negative power terminal 425: plate capacitor 450-1: Ball grid array 450-2: Ball grid array 451: Integrated Circuit 453: memory block

圖1繪示根據一些實施方案之一積體電路封裝之一底側。Figure 1 illustrates a bottom side of an integrated circuit package according to some embodiments.

圖2A繪示根據一些實施方案之在對角相鄰接觸球之間包含一電容器之一積體電路封裝之一底側之一平面視圖。2A shows a plan view of a bottom side of an integrated circuit package including a capacitor between diagonally adjacent contact balls according to some embodiments.

圖2B繪示根據一些實施方案之用於一積體電路封裝之底側上之一電容器之接觸墊之一平面視圖。Figure 2B shows a plan view of a contact pad for a capacitor on the bottom side of an integrated circuit package according to some implementations.

圖2C繪示根據一些實施方案之在相鄰接觸球之間包含一個電容器之一積體電路封裝中之一積體電路之一截面視圖。2C illustrates a cross-sectional view of an integrated circuit in an integrated circuit package including a capacitor between adjacent contact balls according to some embodiments.

圖3A繪示根據一些實施方案之包含用於呈一第一圖案之多個電容器之接觸球之一積體電路封裝之一底側之一部分視圖。3A shows a partial view of a bottom side of an integrated circuit package including contact balls for a plurality of capacitors in a first pattern according to some embodiments.

圖3B繪示根據一些實施方案之包含呈一第二圖案之多個電容器之一積體電路封裝之一底側之一部分視圖。3B shows a partial view of a bottom side of an integrated circuit package including a plurality of capacitors in a second pattern according to some implementations.

圖3C繪示根據一些實施方案之包含呈一第三圖案之多個電容器之一積體電路封裝之一底側之一部分視圖。3C shows a partial view of a bottom side of an integrated circuit package including a plurality of capacitors in a third pattern according to some embodiments.

圖3D繪示根據一些實施方案之包含呈一第四圖案之多個電容器之一積體電路封裝之一底側之一部分視圖。3D shows a partial view of a bottom side of an integrated circuit package including a plurality of capacitors in a fourth pattern according to some embodiments.

圖4繪示根據一些實施方案之包含安裝於一印刷電路板上之一積體電路封裝及一記憶體電路封裝之一系統之一截面視圖。4 shows a cross-sectional view of a system including an integrated circuit package and a memory circuit package mounted on a printed circuit board according to some implementations.

在圖中，除非另有指示，否則具有相同或類似元件符號之元件具有相同或類似功能或步驟。In the figures, unless otherwise indicated, elements with the same or similar element symbols have the same or similar functions or steps.

10:積體電路封裝 10: Integrated circuit packaging

100:電容器 100: capacitor

101:第一側 101: first side

102:第二側 102: second side

105:矽基板 105: Silicon substrate

110:接觸球 110: contact ball

110-1:第一接觸球 110-1: First contact ball

110-2:第二鄰近接觸球 110-2: Second adjacent contact ball

113:積體電路組件 113: Integrated Circuit Components

121:第一電壓輸入 121: first voltage input

122:第二電壓輸入 122: second voltage input

150:球格陣列(BGA) 150: Ball grid array (BGA)

155:節距 155: Pitch

Claims (18)

一種積體電路封裝，其包括：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；一球格陣列，其經形成於該基板之該第一側上，該球格陣列包括配置成一圖案之多個接觸球，其中該等接觸球之一第一子組之各者經電耦合至該積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入；及一電容器，其經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子，其中該第一電壓輸入係一互補金屬氧化物半導體電路之一汲極電壓輸入，且該第二電壓輸入係該互補金屬氧化物半導體電路之一汲電電壓輸入。 An integrated circuit package comprising: a substrate having a first side and a second side opposite to the first side; an integrated circuit component coupled to the second side of the substrate; A ball grid array formed on the first side of the substrate, the ball grid array including a plurality of contact balls arranged in a pattern, wherein each of a first subgroup of the contact balls is electrically coupled to the A first voltage input of an integrated circuit component, and each of a second subgroup of the contact balls is electrically coupled to a second voltage input of the integrated circuit component; and a capacitor mounted to the Of the first side and having a first terminal coupled to one of the first contact balls in the first subgroup of the contact balls and one of the second contact balls in the second subgroup coupled to the contact balls A second terminal, wherein the first voltage input is a drain voltage input of a complementary metal oxide semiconductor circuit, and the second voltage input is a drain voltage input of the complementary metal oxide semiconductor circuit. 如請求項1之積體電路封裝，其中該球格陣列具有1.27毫米或更小之一節距。 The integrated circuit package of claim 1, wherein the ball grid array has a pitch of 1.27 mm or less. 如請求項1之積體電路封裝，其中該第一接觸球及該第二接觸球係該球格陣列中之相鄰者。 Such as the integrated circuit package of claim 1, wherein the first contact ball and the second contact ball are adjacent ones in the ball grid array. 如請求項1之積體電路封裝，其中該第一接觸球及該第二接觸球在該 球格陣列中沿相對於該圖案之一對角方向彼此相鄰。 Such as the integrated circuit package of claim 1, wherein the first contact ball and the second contact ball are in the The ball grid array is adjacent to each other along a diagonal direction with respect to the pattern. 如請求項1之積體電路封裝，其進一步包括一橋接器，該橋接器電耦合一第三接觸球與該第一接觸球或該第二接觸球之至少一者。 Such as the integrated circuit package of claim 1, which further includes a bridge that electrically couples a third contact ball and at least one of the first contact ball or the second contact ball. 如請求項1之積體電路封裝，其中該電容器包括一電容器主體，該電容器主體經安置於該基板之該第一側上之一絕緣層上方。 The integrated circuit package of claim 1, wherein the capacitor includes a capacitor body, and the capacitor body is disposed above an insulating layer on the first side of the substrate. 如請求項1之積體電路封裝，其中各接觸球具有自該基板之該第一側延伸遠於該電容器之一高度之一高度。 The integrated circuit package of claim 1, wherein each contact ball has a height extending from the first side of the substrate farther than a height of the capacitor. 如請求項1之積體電路封裝，其中該電容器之各端子透過一接觸墊與該接觸球電接觸，其中該接觸墊經安置於沈積於該基板之該第一側上之一介電層上方且經安置於沈積於該介電層上方之一絕緣層下方。 The integrated circuit package of claim 1, wherein each terminal of the capacitor is in electrical contact with the contact ball through a contact pad, wherein the contact pad is disposed on a dielectric layer deposited on the first side of the substrate And it is arranged under an insulating layer deposited above the dielectric layer. 如請求項1之積體電路封裝，其中一第三接觸球與該第一端子之間的一間隙避免該接觸球與該第一端子之間的電弧效應。 Such as the integrated circuit package of claim 1, wherein a gap between a third contact ball and the first terminal prevents an arc effect between the contact ball and the first terminal. 一種電子系統，其包括：一印刷電路板；及一積體電路封裝，其經安裝於該印刷電路板上，其中該積體電路封裝包括：一基板，其具有一第一側及與該第一側相對之一第二側； 一積體電路組件，其經耦合至該基板之該第二側；一球格陣列，其經形成於該基板之該第一側上，該球格陣列包括配置成一圖案之多個接觸球，其中該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入；及一電容器，其經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子，其中在該積體電路封裝中，該第一電壓輸入係一互補金屬氧化物半導體電路之一汲極電壓輸入，且該第二電壓輸入係該互補金屬氧化物半導體電路之一汲電電壓輸入。 An electronic system includes: a printed circuit board; and an integrated circuit package mounted on the printed circuit board, wherein the integrated circuit package includes: a substrate having a first side and a first side One side opposite to a second side; An integrated circuit component coupled to the second side of the substrate; a ball grid array formed on the first side of the substrate, the ball grid array including a plurality of contact balls arranged in a pattern, Wherein each of the first subgroup of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of the second subgroup of the contact balls is electrically coupled to the product A second voltage input of the bulk circuit component; and a capacitor mounted to the first side and having a first terminal and a first terminal of a first contact ball in the first subgroup coupled to the contact balls To a second terminal of a second contact ball in the second subgroup of the contact balls, wherein in the integrated circuit package, the first voltage input is a drain of a complementary metal oxide semiconductor circuit Voltage input, and the second voltage input is a drain voltage input of the complementary metal oxide semiconductor circuit. 如請求項10之電子系統，其中在該積體電路封裝中，該球格陣列具有1.27毫米或更小之一節距。 The electronic system of claim 10, wherein in the integrated circuit package, the ball grid array has a pitch of 1.27 mm or less. 如請求項10之電子系統，其中在該積體電路封裝中，該第一接觸球及該第二接觸球係該球格陣列中之相鄰者。 The electronic system of claim 10, wherein in the integrated circuit package, the first contact ball and the second contact ball are adjacent ones in the ball grid array. 如請求項10之電子系統，其中該積體電路封裝進一步包括一橋接器，該橋接器電耦合一第三接觸球與該第一接觸球或該第二接觸球之至少一者。 The electronic system of claim 10, wherein the integrated circuit package further includes a bridge that electrically couples a third contact ball and at least one of the first contact ball or the second contact ball. 如請求項10之電子系統，其中在該積體電路封裝中，該電容器包括 一電容器主體，該電容器主體經安置於該基板之該第一側上之一絕緣層上方。 The electronic system of claim 10, wherein in the integrated circuit package, the capacitor includes A capacitor body which is arranged above an insulating layer on the first side of the substrate. 如請求項10之電子系統，其進一步包括一記憶體電路封裝，該記憶體電路封裝經安裝於該印刷電路板上，該記憶體電路封裝儲存指令或資料以供該積體電路封裝之該積體電路組件處理。 For example, the electronic system of claim 10, which further includes a memory circuit package mounted on the printed circuit board, and the memory circuit package stores commands or data for the product of the integrated circuit package Body circuit assembly processing. 一種電子系統，其包括：一印刷電路板；及一積體電路封裝，其經安裝於該印刷電路板上，其中該積體電路封裝包括：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；一球格陣列，其經形成於該基板之該第一側上，該球格陣列包括配置成一圖案之多個接觸球，其中該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入；一電容器，其經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子；及一板電容器，該板電容器經安裝於該印刷電路板上，該板電容器具有：一汲極電壓端子，其與將一汲極電壓提供至該積體電路組件之一第一電源端子耦合；及一汲電電壓端子，其與將一汲電電壓提供至該積體電路 組件之一第二電源端子耦合。 An electronic system includes: a printed circuit board; and an integrated circuit package mounted on the printed circuit board, wherein the integrated circuit package includes: a substrate having a first side and a first side One side opposite to a second side; an integrated circuit component coupled to the second side of the substrate; a ball grid array formed on the first side of the substrate, the ball grid array including A plurality of contact balls arranged in a pattern, wherein each of a first subgroup of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and a second subgroup of the contact balls Each of them is electrically coupled to a second voltage input of the integrated circuit component; a capacitor is mounted to the first side and has a first contact in the first subgroup coupled to the contact balls A first terminal of the ball and a second terminal of a second contact ball in the second subgroup coupled to the contact balls; and a plate capacitor mounted on the printed circuit board, the The plate capacitor has: a drain voltage terminal that is coupled to a first power terminal that provides a drain voltage to the integrated circuit assembly; and a drain voltage terminal that is connected to a drain voltage to the product. Body circuit One of the components is coupled to the second power terminal. 一種電子系統，其包括：一印刷電路板；及一積體電路封裝，其經安裝於該印刷電路板上，其中該積體電路封裝包括：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；一球格陣列，其經形成於該基板之該第一側上，該球格陣列包括配置成一圖案之多個接觸球，其中該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入；一電容器，其經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子；及一第一電源端子，其經安裝於該印刷電路板上且經耦合至該第一接觸球；及一第二電源端子，其經安裝於該印刷電路板上且經耦合至該第二接觸球，其中該第一電源端子將一汲極電壓提供至該積體電路組件且該第二電源端子將一汲電電壓提供至該積體電路組件。 An electronic system includes: a printed circuit board; and an integrated circuit package mounted on the printed circuit board, wherein the integrated circuit package includes: a substrate having a first side and a first side One side opposite to a second side; an integrated circuit component coupled to the second side of the substrate; a ball grid array formed on the first side of the substrate, the ball grid array including A plurality of contact balls arranged in a pattern, wherein each of a first subgroup of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and a second subgroup of the contact balls Each of them is electrically coupled to a second voltage input of the integrated circuit component; a capacitor is mounted to the first side and has a first contact in the first subgroup coupled to the contact balls A first terminal of the ball and a second terminal of a second contact ball in the second subgroup coupled to the contact balls; and a first power terminal mounted on the printed circuit board and Coupled to the first contact ball; and a second power terminal mounted on the printed circuit board and coupled to the second contact ball, wherein the first power terminal provides a drain voltage to the integrated body The circuit component and the second power terminal provide a drain voltage to the integrated circuit component. 一種電子系統，其包括：一印刷電路板；及一積體電路封裝，其經安裝於該印刷電路板上，其中該積體電路封 裝包括：一基板，其具有一第一側及與該第一側相對之一第二側；一積體電路組件，其經耦合至該基板之該第二側；一球格陣列，其經形成於該基板之該第一側上，該球格陣列包括配置成一圖案之多個接觸球，其中該等接觸球之一第一子組之各者經電耦合至一積體電路組件之一第一電壓輸入，且該等接觸球之一第二子組之各者經電耦合至該積體電路組件之一第二電壓輸入；一電容器，其經安裝至該第一側且具有耦合至該等接觸球之該第一子組中之一第一接觸球之一第一端子及耦合至該等接觸球之該第二子組中之一第二接觸球之一第二端子；及一記憶體電路封裝，該記憶體電路封裝經安裝於該印刷電路板上，該記憶體電路封裝儲存指令或資料以供該積體電路封裝之該積體電路組件處理，其中該記憶體電路封裝在一底側處包含一第二球格陣列，該第二球格陣列包括多個接觸球，其中該第二球格陣列包含一第二電容器，該第二電容器具有：一汲極電壓端子，其與一汲極電壓接觸球耦合；及一汲電電壓端子，其與一汲電電壓接觸球耦合，且其中該汲極電壓接觸球及該汲電電壓接觸球選自該第二球格陣列。 An electronic system includes: a printed circuit board; and an integrated circuit package mounted on the printed circuit board, wherein the integrated circuit package The package includes: a substrate having a first side and a second side opposite to the first side; an integrated circuit component coupled to the second side of the substrate; a ball grid array Formed on the first side of the substrate, the ball grid array includes a plurality of contact balls arranged in a pattern, wherein each of a first subgroup of the contact balls is electrically coupled to one of an integrated circuit component A first voltage input, and each of a second subgroup of the contact balls is electrically coupled to a second voltage input of the integrated circuit assembly; a capacitor mounted to the first side and having a coupling to A first terminal of a first contact ball in the first subgroup of the contact balls and a second terminal of a second contact ball in the second subgroup coupled to the contact balls; and a The memory circuit package is mounted on the printed circuit board, and the memory circuit package stores instructions or data for processing by the integrated circuit assembly of the integrated circuit package, wherein the memory circuit is packaged in A bottom side includes a second ball grid array, the second ball grid array includes a plurality of contact balls, wherein the second ball grid array includes a second capacitor, the second capacitor has: a drain voltage terminal, which Coupled with a drain voltage contact ball; and a drain voltage terminal coupled with a drain voltage contact ball, and wherein the drain voltage contact ball and the drain voltage contact ball are selected from the second ball grid array.
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