TWI734178B - Coding transform coefficients with throughput constraints - Google Patents

Abstract

A video coder that constrains the total number of regular bins used for entropy coding syntax elements of a current block is provided. The video coder entropy encodes or decodes the syntax elements selectively as either regular bins using context modeling or as bypass bins without context modeling. A constraint is specified to limit a total number of regular bins used for entropy coding the syntax elements of the current block. There may be no constraint limiting a number of regular bins specific to an individual syntax element of the current block.

Description

Coding conversion coefficient with output limitation

The present disclosure generally relates to video processing. In particular, the present disclosure relates to a method of encoding and decoding transform coefficients.

Unless otherwise indicated herein, the methods described in this section are not prior art within the scope of the patent application listed below, and are not included in this section but are recognized as prior art.

High Efficiency Video Codec (HEVC) is the latest international video codec standard developed by the Joint Video Codec Team (JCT-VC). The input video signal is predicted from the reconstructed signal, which is derived from the codec picture area. The prediction residual signal is processed by linear transformation. Quantize the transform coefficients and perform entropy coding and decoding together with other side information in the bit stream. After inversely transforming the dequantized transform coefficients, a reconstructed signal is generated from the prediction signal and the reconstructed residual signal. The reconstructed signal is further processed by loop filtering to remove codec artifacts. The decoded images are stored in the frame buffer to predict future images in the input video signal.

In HEVC, a codec picture is divided into non-overlapping square block regions represented by an associated coding tree unit (CTU). A codec picture can be represented by a set of slices, and each slice includes an integer number of CTUs. Each CTU in the slice is processed in raster scan order. Up to two motion vectors and reference indexes can be used to decode bi-predictive (bi-predictive, abbreviated as B) slices using intra prediction or inter prediction to predict the sample value of each block. Use intra prediction or inter prediction to decode prediction (P) slices using at most one motion vector and reference index to predict the sample value of each block. Only intra prediction is used to decode intra (I) slices.

A recursive quadtree (QT) structure can be used to divide the CTU into multiple non-overlapping codec units (CU) to adapt to various local motion and texture features. The CTU can also be divided into one or more smaller-sized CUs using a quadtree with a nested multi-type tree with binary and ternary splits. The resulting CU partition can be square or rectangular.

One or more prediction units (PUs) are designated for each CU. The prediction unit, together with the associated CU syntax, serves as the basic unit for transmitting predictor information. Use the specified prediction process to predict the value of the relevant pixel sample within the PU. The residual quadtree (RQT) structure can be used to further divide the CU to represent the associated prediction residual signal. The leaf nodes of RQT correspond to the transformation unit (TU). For 4:2:0 color format pictures, the transform unit consists of a transform block (TB) with a size of 8x8, 16x16, or 32x32 with a luminance sample (TB) or a transform block with four luminance samples with a size of 4x4 and two The corresponding chroma sampling transform block is composed. The integer transform is applied to the transform block, and the level value of the quantized coefficient is used together with other auxiliary information to perform entropy coding and decoding in the bit stream.

The terms Codec Tree Block (CTB), Codec Block (CB), Prediction Block (PB) and Transform Block (TB) are defined as 2-D specifying one color component associated with CTU, CU, PU, and TU, respectively Sampling array. Therefore, CTU is composed of one luminance CTB, two chrominance CTBs and related syntax elements. A similar relationship is valid for CU, PU, and TU. Tree division is usually applied to both luminance and chrominance, but exceptions are when certain minimum sizes of chrominance are reached.

The codec block flag (CBF) is used to signal whether there are any non-zero transform coefficients in the transform block. When CBF is equal to 0, no further coding or decoding is performed on the related transform block, and it is inferred that all coefficients in the current transform block are equal to zero. Otherwise, the relevant transform block contains at least one non-zero transform coefficient. The non-zero transform block is further divided into non-overlapping sub-blocks. The syntax element coded_sub_block_flag can be signaled to indicate whether the current sub-block contains any non-zero coefficients. When coded_sub_block_flag is equal to 0, no further coding or decoding is performed on the associated transform sub-block, and it is inferred that all coefficients in the current transform sub-block are equal to zero. Otherwise, the associated transform block contains at least one non-zero transform coefficient. Multiple subblock coding passes are used to perform entropy coding and decoding on the value of the transform coefficient level in the associated subblock. In each encoding and decoding process, each transform coefficient is accessed and processed once according to a predefined scan order.

In HEVC, the syntax element sig_coeff_flag is signaled during the encoding and decoding process of the first sub-block to indicate whether the absolute value of the current transform coefficient level is greater than zero. Further, in the second encoding and decoding process, the syntax element coeff_abs_level_greater1_flag is sent for the current coefficient with sig_coeff_flag equal to 1 to indicate whether the absolute value of the correlation transform coefficient level is greater than 1. For the current coefficient with coeff_abs_level_greater1_flag equal to 1, the syntax element coeff_abs_level_greater2_flag is further sent in the third codec process to indicate whether the absolute value of the associated transform coefficient level is greater than 2. In the fourth codec and the fifth sub-block codec, the sign information and the remaining level value are signaled through the syntax elements coeff_sign_flag and coeff_abs_level_remaining, respectively.

The following summary of the invention is only illustrative, and is not intended to be limiting in any way. That is, the following overview is provided to introduce the concepts, highlights, benefits, and advantages of the novel and non-obvious technologies described herein. In the following detailed description, the options are further described but not all implementations. Therefore, the following summary is not intended to identify necessary features of the claimed subject matter, nor is it intended to be used to determine the scope of the claimed subject matter.

Some embodiments of the present disclosure provide a video codec (for example, a video encoder or a video decoder) that limits the current use of entropy codec The total number of regular bins of the syntax element of the block. The video codec selectively entropy encodes or decodes syntax elements into regular bits using context modeling or bypass bits without context modeling. Specify a constraint to limit the total number of regular bits used for entropy encoding and decoding of syntax elements. There may be no constraints that limit the number of regular bits specific to a single syntax element.

In some embodiments, multiple syntax elements are encoded and decoded in multiple encoding and decoding processes. This constraint limits the total number of regular bits used for entropy encoding and decoding of syntax elements in the first encoding and decoding process. Multiple syntax elements specify multiple transform coefficients, where the absolute value of the transform coefficient is indicated by at least a first flag, a second flag, and a third flag that are entropy-coded and decoded in the first coding and decoding process.

In some embodiments, the constraint that limits the number of regular bits is greater for the larger first block than for the smaller second block. In some embodiments, the constraints that limit the number of regular bits are different for the first color component and for the second color component. In some embodiments, the constraint that limits the number of regular bits is calculated by multiplying the default constraint with a predefined factor. The predefined factor is calculated from the number of codec sub-blocks in the current block and all the sub-blocks in the current block. Calculated by the ratio of the number of sub-blocks.

In the following detailed description, many specific details are explained by way of examples to provide a thorough understanding of related teachings. Any changes, derivations and/or extensions based on the teachings described herein are within the protection scope of the present disclosure. In some cases, well-known methods, processes, components, and/or circuits related to one or more example implementations disclosed herein may be described at a relatively high level without detailed descriptions to avoid unnecessary Obfuscate all aspects of the teachings of this disclosure.

The Joint Video Expert Group (JVET) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 are currently establishing the next-generation video codec standard. ITU-T VCEG (Q6/16) and ISO/IEC MPEG (JTC 1/SC 29/WG 11) Joint Video Expert Group (JVET) in the Multi-Function Video Codec (VVC) Working Draft (WD) 2 (B.Brossey) Et al., "Versatile Video Coding (Draft 2)" specifies certain tasks (document JVE061001, 11th meeting: Ljubljana, SI, July 10-18, 2018)).

VVC WD2 specifies that the transform coefficients of the codec block can be quantized through scalar quantization. The choice of one of the two quantizers is specified by a state machine with four states. The state of the current transform coefficient is determined by the state and parity of the absolute level value of the previous transform coefficient in the scan order. The syntax elements sig_coeff_flag, par_level_flag and rem_abs_gt1_flag are sent during the coding and decoding process of the first sub-block. The absolute value of the transform coefficient level partially reconstructed from the decoding process of the first sub-block is given by

AbsLevelPass1 = sig_coeff_flag + par_level_flag + 2 * rem_abs_gt1_flag

The context selection for entropy coding and decoding sig_coeff_flag depends on the state of the current coefficient. Therefore, the par_level_flag is sent during the first encoding and decoding process to derive the state of the next coefficient. The syntax elements rem_abs_gt2_flag, abs_remainder, and coeff_sign_flag are sent in the second, third, and fourth encoding and decoding processes, respectively. The absolute value of the fully reconstructed transform coefficient level is given by

AbsLevel = AbsLevelPass1 + 2 * (rem_abs_gt2_flag + abs_remainder) The transformation coefficient level is given by the following formula

TransCoeffLevel = (2*AbsLevel−(QState>1?1:0))*(1−2*coeff_sign_flag),

Among them, QState indicates the current state of the transform coefficient. I. Coding and decoding transform coefficients

Some embodiments of the present disclosure provide a video codec that uses multiple codec processes to signal or analyze the absolute value of the transform coefficient level. In some embodiments, the absolute value of the complete reconstruction of the transform coefficient level can be expressed by the following formula:

AbsLevel = (AbsLevelRS1 >> 1) + ParityBit,

Among them, ParityBit represents the parity of the absolute value of the transform coefficient level, and AbsLevelRS1 represents the absolute value of the transform coefficient level shifted down by 1. The syntax elements sig_coeff_flag, coeff_abs_level_greater1_flag, and par_level_flag can be signaled in the first encoding and decoding process. When sig_coeff_flag is equal to 0, the associated transform coefficient level is equal to 0. Otherwise, the coeff_abs_level_greater1_flag is further sent to indicate whether the absolute value of the associated transform coefficient level is greater than 1. When coeff_abs_level_greater1_flag is equal to 0, AbsLevelRS1 is set to be equal to 0, and ParityBit is set to sig_coeff_flag for the correlation transform coefficient. Otherwise, the par_level_flag is further signaled to indicate the value of ParityBit for the associated transform coefficient level. One or more encoding and decoding processes can be used to further send more information about AbsLevelRS1 and information about the sign of the relevant transform coefficient level.

When the current coefficient, coeff_abs_level_greater1_flag is greater than 1, the video codec may further signal the syntax element coeff_abs_level_rs1_gt1_flag to indicate whether AbsLevelRS1 is greater than 1. When coeff_abs_level_rs1_gt1_flag is equal to 0, AbsLevelRS1 is set equal to 1 for the relevant transform coefficient level. Otherwise, it is concluded that AbsLevelRS1 is greater than 1, and the remaining value of AbsLevelRS1 is further sent. In some embodiments, the syntax element coeff_abs_level_rs1_gt1_flag is signaled in the same codec process as coeff_abs_level_greater1_flag. In some embodiments, after the coding and decoding process for signaling coeff_abs_level_greater1_flag, the coeff_abs_level_rs1_gt1_flag is sent in a separate coding and decoding process.

When for the current coefficient, coeff_abs_level_rs1_gt1_flag is greater than 1, the video codec may further signal the syntax element coeff_abs_level_rs1_gt2_flag to indicate whether AbsLevelRS1 is greater than 2. When coeff_abs_level_rs1_gt2_flag is equal to 0, AbsLevelRS1 is set equal to 2 for the coefficient level associated with it. Otherwise, it is concluded that AbsLevelRS1 is greater than 2, and the remaining value of AbsLevelRS1 is further sent. The coeff_abs_level_rs1_gt2_flag may be sent in the same codec process as the coeff_abs_level_rs1_gt1_flag, or the coeff_abs_level_rs1_gt2_flag may be sent in a separate codec process after the codec process of sending the coeff_abs_level_rs1_gt1_flag. In some embodiments, the syntax elements coeff_abs_level_greater1_flag, coeff_abs_level_rs1_gt1_flag, and coeff_abs_level_rs1_gt2_flag are all signaled in one encoding and decoding process.

In some embodiments, the video codec performs entropy codec on the residual block quantized by using dependent scalar quantization. The video codec uses the syntax elements sig_coeff_flag, coeff_abs_level_greater1_flag, par_level_flag, coeff_abs_levelsrs1_gt1_flag, coeff_abs_level_rs1_gt2_flag, and coeff_abs_level_rs1_rema to code and decode the absolute value of the transform coefficient level. Table 1 below provides a syntax table for decoding the residual transform block. When coeff_abs_level_rs1_gt2_flag is equal to 1, the syntax element coeff_abs_level_rs1_remainder is used to signal the remaining absolute value of the associated coefficient level. When not codec, the syntax elements sig_coeff_flag, coeff_abs_level_greater1_flag, coeff_abs_level_rs1_gt1_flag, coeff_abs_level_rs1_gt2_flag, and coeff_abs_level_rs1_remainder are inferred to be equal to zero. Table 1 : Residual codec syntax

Some embodiments of the present disclosure relate to reducing the complexity by reducing the number of encoding and decoding processes used for entropy encoding and decoding of transform blocks or sub-blocks. For example, in some embodiments, the syntax element rem_abs_gt2_flag may be coded and decoded in the same codec process as the syntax element rem_abs_gt1_flag. In some embodiments, the information about the sign and the remaining value of the transform coefficient uses CABAC for entropy encoding and decoding in the bypass mode, and can be signaled in one encoding and decoding process. In one embodiment, all syntax elements that use CABAC entropy encoding and decoding in the normal mode are signaled in one encoding and decoding process. In another encoding and decoding process, the entropy of all syntax elements that use the CABAC encoding and decoding in the bypass mode is sent. II. Restrict sub-blocks or regular bits in the encoding and decoding process

In order to achieve high compression efficiency, the context-based adaptive binary arithmetic coding and decoding (CABAC) mode, or regular mode, is used to encode and decode the values of syntax elements in HEVC. Since the arithmetic codec in the CABAC engine only encodes the binary symbol value, the CABAC operation first needs to convert the value of the syntax element into a binary string. This process is usually called binarization. In the encoding and decoding process, a probability model is gradually established according to the coded symbols of different contexts. The coding and decoding information can be used to determine the selection of the modeling context for coding and decoding the next binary symbol. The values of the syntax elements processed in the regular mode are called "regular bits", and context modeling is used to encode and decode them entropy. Symbols can also be coded and decoded without a context modeling stage, and an equal probability distribution (usually called bypass mode) is assumed to improve bit stream parsing throughput. The value of the syntax element processed in the bypass mode is called "bypass bit", and entropy coding and decoding is performed without context modeling. In HEVC, the values of syntax elements in the transform sub-block (for example, coded_sub_block_flag, sig_coeff_flag, coeff_abs_level_greater1_flag, and coeff_abs_level_greater2_flag) are coded and decoded into regular bits in the regular mode. The values of the syntax elements coeff_sign_flag and coeff_abs_level_remaining in the transform sub-block are coded and decoded into bypass bits in the bypass mode. In order to limit the total number of regular bits of the entropy coding transform coefficient level in a sub-block in the worst case, each sub-block can only code and decode eight coeff_abs_level_greater1_flag values and one coeff_abs_level_greater2_flag value at most. In this way, the maximum number of regular bits in each sub-block is limited to 26.

Some embodiments of the present disclosure involve constraints on the maximum allowable number of CABAC regular bits used for codec transform sub-blocks. Having the constraint on the regular bits of the sub-block is beneficial to control the bit stream parsing throughput rate of each sub-block (for example, in the worst case), because the entropy codec of CABAC is used in the regular mode than in the bypass mode The following involves higher complexity. In some embodiments, the video codec may impose constraints on the maximum allowable number of regular bits in a sub-block or a sub-block encoding and decoding process, but for the sub-block or the sub-block encoding and decoding process. There is no specific limit on the maximum allowable number of regular bits of each syntax element in the decoding process. The video codec can track the current sub-block or the cumulative number of regular bits consumed in the current codec process. When the specified maximum allowable number of regular bits is reached, the video codec may switch the CABAC engine to the bypass mode for the remaining codec processes in the current sub-block. Or the video codec can terminate the codec process in the regular CABAC mode. The remaining absolute value of the transform coefficient level is coded and decoded through the sub-block coding and decoding process in the bypass mode.

Figure 1 conceptually shows a video codec, which selectively entropy encodes and decodes the syntax of sub-blocks of a block in a regular mode or a bypass mode based on a constraint on the number of regular bits used for a sub-block element. The figure shows the current block 100 that is being coded (encoded or decoded). The current block 100 may be a transform block or a TU such as a pixel block of a codec unit (CU). The current block 100 includes 4×4 = 16 sub-blocks, including the sub-block 110.

The sub-block 110 includes a plurality of syntax elements. These syntax elements (SE) can represent several transform coefficients of the current block (for example, Coef1-Coef5). Each transform coefficient can be represented by several syntax elements (for example, SE1-SE6). The syntax element of the transform coefficient may include a flag indicating the absolute value and parity of the transform coefficient.

These syntax elements use CABAC for entropy encoding and decoding, as regular bits (encoding and decoding in conventional mode through context modeling) or bypass bits (encoding and decoding in bypass mode without context modeling) . The video codec imposes constraints 115. In some embodiments, the constraint limits the maximum allowable number of CABAC regular bits used to transform the block 100, for example, the maximum allowable number of CABAC regular bits used to encode and decode the sub-block 110. This constraint provides a budget for regular bits, which is shared by the syntax elements of the block or sub-block. Entropy coding and decoding of each syntax element into regular bits consumes budget until there is no remaining budget.

In the example in Figure 1, the constraint 115 of the sub-block 110 is 32. Some syntax elements are coded and decoded by using the regular mode (syntax elements are shown as shaded). These syntax elements include Coef1: SE1, Coef1: SE2, Ceof1: SE3, Coef1: SE4, Coef2: SE1, Coef2: SE2, Ceof2: SE3, Coef2: SE4, and Coef3: SE1. Entropy coding these syntax elements consumes 30 regular bits. To encode more syntax elements into regular bits, restrict the number of sub-blocks beyond 32. Therefore, all other syntax elements are coded and decoded as bypass bits (not shaded in the figure).

The example in Figure 1 also shows several encoding and decoding processes 121, 122, and 123. In the first coding and decoding process 121, the video codec entropy encodes the SE1-SE4 of each coefficient, especially according to Coef1: SE1, Coef1: SE2, Ceof1: SE3, Coef1: SE4, Coef2: SE1, Coef2 : SE2, Ceof2: SE3, etc. are coded and decoded in the order. In the second encoding and decoding process 122, the video codec performs entropy encoding on the SE5 of each coefficient, especially in the order of Coef1:SE5, Coef2:SE5, Coef3:SE5, Coef4:SE5, etc. In the third coding and decoding process 123, the video codec performs entropy coding on the SE6 of each coefficient, especially in the order of Coef1:SE6, Coef2:SE6, Coef3:SE6, Coef4:SE6, etc.

In some embodiments, the constraint 115 limits the total number of regular bits used by all syntax elements of the sub-block, regardless of which codec process they are coded or decoded in. In some embodiments, the constraint 115 limits the total number of regular bits used by the syntax elements of the codec during the first codec process 121 (or the leading coding pass), but is not limited to other codecs. The number of regular bits used during the decoding process.

In some embodiments, regardless of whether the constraint 115 applies to all the syntax elements of the sub-block 110 or only applies to the syntax elements coded and decoded in the first codec process 121, the video codec applies to the sub-block 110 or the first codec. There is no specific restriction on the maximum allowable number of regular bits of each syntax element existing in the process 121. In some embodiments, the video codec can apply constraints to the maximum allowable number of regular bits in a sub-block or a sub-block encoding and decoding process (for example, the first codec process 121), and also for the existence of Specific constraints are imposed on the maximum allowable number of regular bits of each syntax element in the sub-block or sub-block encoding and decoding process.

In some embodiments, the limitation of the HEVC on the specified maximum allowable number of regular bits of the syntax elements coeff_abs_level_greater1_flag and coeff_abs_level_greater2_flag is removed. Specifically, the syntax elements coeff_abs_level_greater1_flag and coeff_abs_level_greater2_flag are coded and decoded in the preamble sub-block coding and decoding process. Once the cumulative number of regular bits in the current sub-block reaches the specified maximum allowable number of 25 or 26, the coding and decoding process of the leading sub-block in the regular CABAC mode can be terminated. The syntax element coeff_abs_level_remaining is in the bypass mode to encode and decode the remaining absolute values of the remaining transform coefficient levels. In this way, the video codec can still meet the worst-case constraint on the number of regular bits per sub-block, while being able to use more regular bits than the maximum number originally specified for the syntax elements coeff_abs_level_greater1_flag and coeff_abs_level_greater2_flag son.

In some embodiments, the video codec may impose constraints on the maximum allowable number of regular bits in the encoding and decoding process of the first sub-block, so as to perform entropy encoding and decoding on the transform coefficient level generated by the dependent scalar quantization. The video codec can track the cumulative number of regular bits consumed in the current preamble codec to send sig_coeff_flag, par_level_flag, and rem_abs_gt1_flag, or send sig_coeff_flag, coeff_abs_level_greater1_flag, par_level_flag, and coeff_gt1_level.

When the cumulative number of regular bits is greater than the specified threshold, the video codec can switch its CABAC engine to bypass mode to encode and decode the remaining processes in the bypass bits. Or the video codec can terminate the current leading codec process. The remaining absolute value of the transform coefficient level is coded and decoded by the sub-block coding and decoding process in the bypass mode, and is used for sending abs_remainder or coeff_abs_level_rs1_remainder.

In some embodiments, the video codec may impose constraints on the maximum allowable number of regular bits for entropy coding and decoding of transform sub-blocks generated by subordinate scalar quantization. The video codec can track the sig_coeff_flag, par_level_flag, rem_abs_gt1_flag, and rem_abs_gt2_flag or the cumulative number of bits consumed for signaling sig_coeff_flag, coeff_abs_level_greater1_flag, par_level_flag_abrs_flag, par_level_flag, coeff_flag, par_level_flag, coeff_flag, par_level_flag, coeff_flag, and regular sub-level_coeff_g When the cumulative number of regular bits is greater than the specified threshold, the remaining absolute values of the transform coefficient levels are all coded and decoded through the sub-block coding and decoding process in the bypass mode for sending abs_remainder or coeff_abs_level_rs1_remainder.

In some embodiments, coeff_abs_level_rs1_gt1_flag can be integrated into the first codec process. Specifically, before sending par_flag (parity bit, par_level_flag), gt1_flag (coeff_abs_level_greater1_flag or rem_abs_gt1_flag) has been sent, and gt2_flag (coeff_abs_level_rs1_gt1_flag or rem_abs_flag is moved to the first encoding and decoding process). Table 2 lists some examples of codewords at different levels. Table 2 : Examples of codewords at different levels

Since the context modeling of sig_flag (sig_coeff_flag) is related to the subordinate quantization state determined by the parity bit of the previous coefficient, and the state transition depends on the parity bit of this level, the modified analysis process is described as follows. In the parsing stage of sig_flag, the even-numbered context model will be prepared and stored in the local buffer. If sig_flag is 0, the stored even level context model will be applied to the next sig_flag. If sig_flag is 1, then gt1_flag is parsed. In the parsing stage of gt1_flag, the odd-numbered context model is loaded and then stored in the local buffer. If gt1_flag is 0, the stored odd level context model can be applied to the next sig_flag. If gt1_flag is 1, both par_flag and gt2_flag are parsed. These two bits will be parsed in order, that is, the bits of par_flag will be parsed into bits of gt2_flag. If par_flag is 0, the even-numbered context model will be loaded during the parsing stage of gt2_flag. If par_flag is 1, the stored odd level context model can be used for the next sig_flag. In one embodiment, one bit is always parsed after the parity bit in the first encoding and decoding process. After moving the gt2_flag to the first encoding and decoding process, the context modeling can be modified accordingly.

In some embodiments, the value of the variable sumAbs1 becomes the sum of the absolute levels of partial reconstruction after the first encoding and decoding process, which is equal to the sum of coeff_partial (= sig_flag + gt1_flag + par_flag + (gt2_flag >> 1)) or Min(4+(x&1),x) in five adjacent positions, where x is the absolute level of the coefficient. In some embodiments, the value of sumAbs1 only considers sig_flag, par_flag, and gt1_flag. Specifically, sumAbs1 is equal to the sum of min (coeff_partial, 3) or (sig_flag + gt1_flag + par_flag) or min (2 + (x & 1), x) in five adjacent positions. In some embodiments, the video codec parses at least one bit after par_flag in the same process. Therefore, the time period spent on parsing other bits can be used to prepare the context model for the next sig_flag.

Figure 2 shows the encoding and decoding process, which includes a flag indicating the absolute value of the transform coefficient level when entropy encoding and decoding a sub-block of the transform block. This figure shows the coding and decoding process for entropy coding and decoding the transform coefficients of the sub-blocks of the transform block. Each transform coefficient includes syntax elements indicating absolute values (sig_flag, gt1_flag, gt2_flag), parity (par_flag), remainder (absr), and the sign of the transform coefficient.

The sig_flag may refer to sig_coeff_flag, or any other flag indicating whether the absolute value of the corresponding transform coefficient level (for example, the value of AbsLevelRS1) is greater than 0. The gt1_flag may refer to coeff_abs_level_greater1_flag or any other flag used to indicate whether the absolute value of the corresponding transform coefficient is greater than 1. The gt2_flag may refer to coeff_abs_level_rs1_gt1_flag or any other flag used to indicate whether the absolute value of the corresponding transform coefficient is greater than 3. par_flag may refer to par_level_flag or any other flag indicating the parity of the absolute value of the transform coefficient level (for example, the value of ParityBit). The remaining part can be indicated by a flag such as abs_remainder or coeff_abs_level_remaining. The sign may be indicated by a flag such as coeff_sign_flag.

Figure 2 shows two schemes 210 and 220 of the encoding and decoding process. In the first scheme 210 of the encoding and decoding process, the sig_flag, gt1_flag, and par_flag of each transform coefficient are encoded and decoded in the first encoding and decoding process, and gt2_flag is encoded and decoded in the second encoding and decoding process, and the remaining part is in the third encoding and decoding process. It is encoded and decoded during the encoding and decoding process, and the sign is encoded and decoded during the fourth encoding and decoding process. In other words, not all indicators of the absolute value of the transform coefficient are in the same encoding and decoding process. In the second scheme 220 of the coding and decoding process, the sig_flag, gt1_flag, par_flag, and gt2_flag of each transform coefficient are coded and decoded in the same first codec. The remaining parts and signs are coded and decoded in the second and third coding and decoding processes, respectively. In other words, at least three or all indicators of the absolute value of the transform coefficient are in the same encoding and decoding process. Regardless of whether the gt2_flag is coded or decoded in the first codec process or the subsequent codec process, in some embodiments, the regular bits used to perform entropy codec on the syntax elements of the first codec process or the sub-blocks of the transform block The total number of yuanzi is subject to constraints or budgets as described in Figure 1 above.

In some embodiments, the maximum number of regular bits for some syntax elements or the maximum number of regular bits for certain encoding and decoding processes may be further specified. For example, the video codec may specify the maximum number of regular bits for coeff_abs_level_rs1_gt2_flag or the maximum number of regular bits used for coding and decoding coeff_abs_level_rs1_gt2_flag during the encoding and decoding process. When encoding and decoding these syntax elements during the encoding and decoding process, when the cumulative number of regular bits is greater than the specified threshold, the video codec can switch its CABAC engine to bypass mode to remove the remainder of the encoding and decoding process. The bit sub-codec is to bypass the bit sub or terminate the current (leading) codec process. The remaining absolute value of the transform coefficient level is coded and decoded through the sub-block coding and decoding process in the bypass mode. In some embodiments, even if there is no regular bit quota allowed or no budget for regular bits, certain syntax elements are not counted as regular bit counts or can always be programmed in regular bits. decoding. For example, in some embodiments, sig_coeff_flag is coded and decoded in a regular bit, regardless of any regular bit constraints of its coding and decoding process. For another example, in some embodiments, sig_coeff_flag and par_level_flag are coded and decoded in regular bits (regardless of any regular bit constraints of the codec process). In some embodiments, if there is no quota or budget for using regular bits to encode and decode par_level_flag and rem_abs_gt1_flag during the encoding and decoding process, only sig_coeff_flag is encoded and decoded into regular bits during the encoding and decoding process. The context modeling state of sig_coeff_flag can be the same as the parsing result of sig_coeff_flag or converted.

In some embodiments, during the encoding and decoding process, if the remaining number of available regular bits is not greater than the required number of regular bits of the coefficients in the encoding and decoding process, that is, if the number of regular bits in the encoding and decoding process is If the remaining budget is insufficient to meet the number of regular bits required to encode and decode the coefficient, the video codec may switch its CABAC engine to bypass mode for the rest of the encoding and decoding process, or the video codec The current leading codec process may be terminated. The absolute values of the remaining transform coefficient levels are all coded and decoded through the sub-block coding and decoding process in the bypass mode. The remaining budget required for encoding and decoding coefficients into regular bits in the encoding and decoding process is also called the termination threshold of the coefficients. For example, if sig_coeff_flag, par_level_flag, and rem_abs_gt1_flag are coded and decoded in one codec process, the termination threshold (used to use regular bits) is 3. If sig_coeff_flag, par_level_flag, rem_abs_gt1_flag, and rem_abs_gt2_flag are encoded and decoded in one encoding and decoding process, the termination threshold is 4.

In some embodiments, one or more advanced syntax sets such as sequence set (SPS), picture parameter set (PPS), or slice header may be used, for example, to pre-defined or explicitly signal in the bit stream. Specify constraints on the maximum allowable number of regular bits used for codec transformation sub-blocks. The specified constraints may depend on the level indicated in the configuration file and codec bitstream. Different constraints can be used for different color components. For different transform sub-block sizes, different constraints can be adopted. In some embodiments, the video codec may limit the maximum allowable number of regular bits of a 2×2 sub-block to be equal to one-fourth of the maximum allowable number of regular bits of a 4×4 sub-block. In some embodiments, the video codec may limit the maximum allowable number of regular bits of the 4×4 chrominance sub-block to be equal to half of the maximum allowable number of regular bits of the 4×4 luma sub-block. The specified constraints for 4x4 transform sub-blocks can be signaled in SPS. In one example, the specified constraints for 4x4 luma sub-blocks, 4x4 chroma sub-blocks, and 2x2 chroma sub-blocks can be signaled in the SPS. In one embodiment, the maximum allowable number of regular bits for the 4×4 chroma sub-block is equal to or less than the maximum allowable number of regular bits for the 4×4 luma sub-block. In another embodiment, the maximum allowable number of regular bits for a 2×2 chroma sub-block is equal to or less than the maximum allowable number of regular bits for a 2×2 chroma sub-block.

In some embodiments, the largest regular bit of a 4x4 luma sub-block can be 25, 30 or 32, the largest regular bit of a 4x4 chroma sub-block can be 25, 16 or 15, and the largest regular bit of a 2x2 chroma sub-block Regular bits can be 2, 3, 4, 5, 6, 7, or 8. For example, {4x4 luma sub-block, one 4x4 chroma sub-block, one 2x2 chroma sub-block} can be {25, 25, 8}, {25, 25, 6}, {25, 25 , 7}, {32, 16, 4}, {32, 32, 8}, {30, 16, 4}, {30, 15, 4} or {30, 15, 3}.

In some embodiments, the largest regular bit of the codec coeff_abs_level_rs1_gt1_flag can also be specified. For example, the largest regular bit of coeff_abs_level_rs1_gt1_flag in a 4x4 luma sub-block can be 2, 3, 4, or 5, and the largest regular bit of coeff_abs_level_rs1_gt1_flag in a 4x4 chroma sub-block can be 0, 1, 2, 3, or 4. , Then the largest regular bit of coeff_abs_level_rs1_gt1_flag in the 2x2 chroma sub-block can be 0, 1, or 2. For example, {4x4 luma sub-block, coeff_abs_level_rs1_gt1_flag in 4x4 luma sub-block, 4x4 chroma sub-block, coeff_abs_level_rs1_gt1_flag in 4x4 chroma sub-block, 2x2 chroma sub-block, maximum coeff_abs_flag in 2x2 chroma sub-block}_gt1_level_g1 Bits can be {25, 4, 25, 4, 8, 2}, {25, 4, 25, 4, 6, 2}, {25, 4, 25, 4, 6, 1}, {25, 3, 25, 3, 6, 2}, {25, 3, 25, 3, 6, 1}, {25, 2, 25, 2, 6, 1}, {25, 2, 25, 2, 6, 0}, {25, 1, 25, 1, 6, 1}, {25, 1, 25, 1, 6, 0}, {25, 3, 25, 3, 7, 2}, {32, 4, 16, 2, 4, 1}, {32, 4, 16, 2, 4, 0}, {32, 4, 16, 4, 4, 1}, {32, 4, 16, 4, 4, 0} , {32, 3, 16, 2, 4, 1}, {32, 3, 16, 2, 4, 0}, {30, 4, 16, 2, 4, 1}, {30, 4, 16, 2, 4, 0}, {30, 3, 16, 2, 4, 1}, {30, 3, 16, 2, 4, 0}, {30, 4, 15, 2, 4, 1}, { 30, 4, 15, 2, 4, 0}, {30, 3, 15, 2, 4, 1}, {30, 3, 15, 2, 4, 0}, {30, 4, 15, 2, 3, 1}, {30, 4, 15, 2, 3, 0}, {30, 3, 15, 2, 3, 1}, {30, 3, 15, 2, 3, 0}, {32, 4, 32, 4, 8, 1).

In some embodiments, the video codec may have constraints on the maximum allowable number of regular bits specified for entropy coding and decoding of some sizes of transform units or transform blocks. The constraint on the maximum allowable number of regular bits in the current sub-block can be derived from the constraints specified for the relevant transform unit or transform block. For example, the constraints on the maximum allowable number of regular bits of the 4x4 transform block and the 2x2 transform block in the video codec can be derived from the constraints on the maximum allowable number of regular bits of the 4x4 transform block and the 2x2 transform block. .

In some embodiments, when rem_abs_gt2_flag is included in the preamble codec process (for example, the first codec process) and the regular bit number constraint value of rem_abs_gt2_flag is (from the regular bit number constraint value of sig_coeff_flag, par_level_flag, rem_abs_gt1_flag) ) Separately specified and send rem_abs_gt2_flag, if the parity bit is sent before rem_abs_gt1_flag, the partial sum of the coefficient (= sig_flag + gt1_flag + par_flag + (gt2_flag >> 1) or = sig_flag + par_flag +>> (gt1_flag ) + (gt2_flag >> 1)) is equal to or greater than 5, or if the parity bit is signaled after rem_abs_gt1_flag, and the partial sum of the coefficient is equal to or greater than 4, the remaining level of the coefficient is coded and decoded. Otherwise, the remaining levels of coefficients are not coded or decoded. If rem_abs_gt2_flag is not signaled because the available number of regular bits of rem_abs_gt2_flag is zero, if the parity bit is signaled before rem_abs_gt1_flag, when the partial sum of the coefficient is equal to or greater than 4, the remaining level of the coefficient is coded and decoded , And if the parity bit is signaled after rem_abs_gt1_flag, when the partial sum of the coefficient is equal to or greater than 2, the remaining level of the coefficient is coded and decoded. Otherwise, the remaining levels of coefficients are not coded or decoded. However, if the available number of regular bits is less than the threshold, in one embodiment, the preamble coding and decoding process is terminated, and if the coefficients are not coded and decoded by the preamble process, the Golomb-Rice code is directly used to code and decode the level. When the current guide codec process is terminated, the remaining level of codec process is executed. The remaining horizontal codec process starts from the last position of the current sub-block to the first position of the sub-block.

In some embodiments, the maximum allowable number of regular bits is specified for the TU. The threshold used to terminate the regular bit sub-coding and decoding of the TU (or the regular bit budget) can be derived from the threshold used to terminate the regular bit sub-coding and decoding of the 4x4 sub-block. For example, if the TU is a luminance 8x8 block, and the threshold of the luminance 4x4 block is 32, then the threshold of this 8x8 luminance TU is 32x4=128. For different color components or different TU sizes, the threshold can be different.

In some embodiments, a constraint on the maximum allowable number of regular bits is specified for the transform sub-block, but the number of constraints on the allowable number of regular bits may depend on the current TU size, TU type, and TU width. , TU height, total number of sub-blocks in the current TU, sub-block size, sub-block width, sub-block height, color component, position of the last significant coefficient, position of the last non-zero subblock, or Any combination of the above. For example, the number of constraints may depend on the total number of sub-blocks in the current TU, color components, sub-block size, and the last non-zero sub-block position.

In order to encode and decode the coefficients of the sub-blocks of the TU, the allowable number of regular bits can be shared between the sub-blocks. For example, in the first sub-block of the TU, the allowable number of regular bits is 128. When encoding and decoding the first sub-block, when using regular bits for coding and decoding coefficients, the allowable number of regular bits is reduced. The remaining allowable value is used for the next sub-block of the TU. In some embodiments, the required number of codec sub-blocks can be derived after (or based on) the last non-zero coefficient position or the last non-zero sub-block position of the coding/decoding. For example, a 16x16 TU has 16 4x4 sub-blocks. The total number of regular bits allowed by the TU can be 32x16 = 512. After decoding the last non-zero coefficient position, if the number of required codec sub-blocks is 8, each sub-block can use 64 regular bits (64x8 = 512).

In some embodiments, when determining the position of the last non-zero sub-block, the number of sub-blocks to be coded and decoded can be determined. If the number of sub-blocks to be coded and decoded is less than the total number of sub-blocks in the current TU, that is, some sub-blocks are skipped in the entropy coding and decoding, the maximum allowable number of regular bits per sub-block can be increased. .

Figure 3 shows that the allowed number of regular bits are shared among the sub-blocks of the current block. The figure shows a first block 310 and a second block 320, which are transform blocks or TUs. Each of the first block 310 and the second block 320 has 4×4 = 16 sub-blocks. Each of the first block 310 and the second block 320 has a total constraint or budget of 512 regular bits for that block.

All sub-blocks of the first block 310 are coded and decoded (shown as shaded in the figure), so that the position of the last coded and decoded sub-block is sub-block 319, which is the 16th sub-block in the first block 310. Each sub-block of the first block 310 is given a constraint or budget of 512÷16=32 regular bits.

On the other hand, only 8 sub-blocks of the second block 320 are coded and decoded, so that the position of the last coded and decoded sub-block is the sub-block 325, which is the 8th sub-block in the second block 320. Each codec sub-block of the first block 320 is given a constraint or budget of 512÷8=64 regular bits.

In some embodiments, the constraint on the regular bits of the sub-block is calculated by multiplying the default constraint value by a factor. (The default constraint in the example in Figure 3 is 32.) This factor is calculated as (the total number of sub-blocks in the current TU)/(the number of sub-blocks to be coded and decoded) or floor ((the sub-blocks in the current TU) Total)/(the number of sub-blocks to be coded and decoded)), where floor(x) means finding the largest integer value less than or equal to x. In some embodiments, some predefined factors are specified. Pre-defined factors can be selected from {4, 2, 1.5, 1.25, 1} or other values according to the power of the two denominators, and other values can be calculated by left and right shift and addition operations. Suppose the total number of sub-blocks in the current TU is A, and the number of sub-blocks to be coded and decoded is B. In an example, if B * 4 >= A, the factor can be 4. Otherwise, if B * 2 >= A, the factor can be 2. Otherwise, if B * 3 >= A * 2, the factor can be 1.5. Otherwise, if B * 5 >= A * 4, the factor can be 1.25. Otherwise, the factor can be 1. In another example, if B * 4 >= A, the factor can be 4. Otherwise, if B * 3 >= A, the factor can be 3. Otherwise, if B * 2 >= A, the factor can be 2. Otherwise, if B * 3 >= A * 2, the factor can be 1.5. Otherwise, if B * 5 >= A * 4, the factor can be 1.25. Otherwise, the factor can be 1. For different syntax types or different sub-block sizes or different color components, the factors can be different. III. Example video encoder

The video encoder 400 is an example of the fourth figure. As shown in the figure, the video encoder 400 receives the input video signal from the video source 405 and encodes the signal into a bit stream 495. The video encoder 400 has several components or modules for encoding the signal from the video source 405, including at least some components selected from the following: transform module 410, quantization module 411, inverse quantization module 414, inverse transform module 415, picture Intra estimation module 420, intra prediction module 425, motion compensation module 430, motion estimation module 435, loop filter 445, reconstructed picture buffer 450, MV buffer 465 and MV prediction module 475, and entropy codec 490. The motion compensation module 430 and the motion estimation module 435 are part of the inter prediction module 440.

In some embodiments, the modules 410 to 490 are modules of software instructions executed by one or more processing units (for example, processors) of a computing device or an electronic device. In some embodiments, the modules 410-490 are modules of hardware circuits implemented by one or more collective circuits (ICs) of the electronic device. Although the modules 410-490 are illustrated as separate modules, some modules may be combined into a single module.

The video source 405 provides an original video signal, and the original video signal can present the pixel data of each video frame without compression. The subtractor 408 calculates the difference between the original video pixel data of the video source 405 and the predicted pixel data 413 from the motion compensation module 430 or the intra prediction module (intra-picture prediction module shown in the figure) 425. The transform module 410 converts the difference (or residual pixel data or residual signal 409) into transform coefficients 416 (for example, by performing a discrete cosine transform (DCT)). The quantization module 411 quantizes the transform coefficients into quantized data (or quantized coefficients) 412, which is encoded into a bit stream 495 by the entropy codec 490.

The inverse quantization module 414 inversely quantizes the quantized data (or quantized coefficients) 412 to obtain transform coefficients, and the inverse transform module 415 performs inverse transform on the transform coefficients to generate a reconstruction residual 419. The reconstruction residual 419 is added to the predicted pixel data 413 to generate the reconstructed pixel data 417. In some embodiments, the reconstructed pixel data 417 is temporarily stored in a line buffer (not shown) for intra-picture prediction and spatial MV prediction. The reconstructed pixels are filtered by the loop filter 445 and stored in the reconstructed picture buffer 450. In some embodiments, the reconstructed picture buffer 450 is a memory external to the video encoder 400. In some embodiments, the reconstructed picture buffer 450 is the internal memory of the video encoder 400.

The intra-picture estimation module 420 performs intra-frame prediction based on the reconstructed pixel data 417 to generate intra-frame prediction data. The intra-frame prediction data is provided to the entropy codec 490 to be encoded as a bit stream 495. The intra prediction data is also used by the intra prediction module 425 to generate prediction pixel data 413.

The motion estimation module 435 performs inter prediction by generating MV, where MV is The reference pixel data of the previously decoded frame stored in the reconstructed picture buffer 450. These MVs are provided to the motion compensation module 430 to generate predicted pixel data.

Instead of encoding the complete actual MV in the bitstream, the video encoder 400 uses MV prediction to generate a predicted MV, and encodes the difference between the MV used for motion compensation and the predicted MV as residual motion data and Stored in bit stream 495.

The MV prediction module 475 generates a predicted MV based on a reference MV (ie, a motion compensation MV for performing motion compensation) generated for encoding a previous video frame. The MV prediction module 475 retrieves the reference MV from the previous video frame in the MV buffer 465. The video encoder 400 stores the MV generated for the current video frame in the MV buffer 465 as a reference MV for generating the predicted MV.

The MV prediction module 475 uses the reference MV to create a predicted MV. The predicted MV can be calculated by spatial MV prediction or temporal MV prediction. The entropy codec 490 encodes the difference (residual motion data) between the predicted MV and the motion compensation MV (MC MV) of the current frame into the bitstream 495.

The entropy codec 490 encodes various parameters and data into the bit stream 495 by using an entropy coding and decoding technique such as context adaptive binary arithmetic coding (CABAC) or Huffman coding. The entropy codec 490 encodes various header elements, flags, and quantized transform coefficients 412 and residual motion data into the bit stream 495 as syntax elements. The bit stream 495 is stored in a storage device or sent to the decoder via a communication medium, such as a network.

The loop filter 445 performs a filtering or smoothing operation on the reconstructed pixel data 417 to reduce encoding artifacts, especially at the boundaries of pixel blocks. In some embodiments, the filtering operation performed includes sample adaptive offset (SAO). In some embodiments, the filtering operation includes an adaptive loop filter (ALF).

Figure 5 illustrates the part of the video encoder 400, which is based on the conventional The syntax elements of the sub-blocks of the block are selectively entropy-encoded in the regular mode or the bypass mode under the constraint of the number of bits. The figure shows the components of the entropy encoder module 490.

The syntax element generator 502 generates syntax elements to be entropy coded and decoded, including syntax elements representing transform coefficients of the current sub-block based on the quantized coefficients 412. The syntax elements are generated according to a predetermined encoding pass (for example, sig_flag, gt1_flag, gt2_flag, and par_flag in the first encoding pass).

The selected syntax element is converted into a bin string 510 (for non-binary value syntax elements) by the binarizer 506 or directly used as a bin string (for binary Value syntax element). The normal/bypass mode switch 508 determines whether the syntax element bit substring 510 is entropy coded into a normal bit or a bypass bit. The context modeler 512 and the regular coding engine 514 use context modeling to process regular bits into code bits 518. The bypass bits are processed by the bypass coding engine 516 into coded bits 518 without using context modeling. The coded bits 518 are stored as part of the bit stream 495.

The normal/bypass mode switch 508 is controlled by the normal/bypass mode selection module 520. The normal/bypass mode selection module uses the normal bit sub-counter 522 to determine whether to select the normal mode or the bypass mode. The regular bit sub-counter 522 counts the number of regular bits encoded for the current sub-block, and the regular/bypass mode switch 508 allows bit substrings to be encoded as regular bits, as long as the regular bit sub-counter It is not greater than or equal to the constraint (shown as a regular bit sub-constraint in Figure 8) 524. Therefore, the constraint 524 limits the current sub-block or the number of regular bits in the current codec process of the current sub-block. The constraint 524 may be determined based on the size of the sub-block, the number of coded sub-blocks in the current block, the total number of sub-blocks in the current block, the color components of the current sub-block, or other attributes of the current block or sub-block.

Fig. 6 conceptually illustrates a process 600, which selectively entropy encodes the syntax elements of the current block in a regular mode or a bypass mode based on the constraint of limiting the number of regular bits used to transform a block. In some embodiments, one or more processing units (eg, processors) of a computing device that implements the video encoder 400 perform the process 600 by executing instructions stored in a computer-readable medium. exist In some embodiments, the electronic device implementing the video encoder 400 performs the process 600.

The video encoder receives (at step 610) input data associated with syntax elements representing transform coefficients of the current block. The transform coefficient may be the transform coefficient of the transform block of the current block, or the transform coefficient of the sub-block of the transform block. In some embodiments, the syntax elements will be entropy encoded in multiple encoding and decoding processes. For each transform coefficient, at least the first flag, the second flag, and the third flag representing the absolute value of the transform coefficient will be entropy-encoded in the first encoding and decoding process. The first flag may indicate whether the absolute value of the transform coefficient level is greater than 0 (for example, sig_flag). The second flag may indicate whether the absolute value of the transform coefficient level is greater than 1 (for example, gt1_flag). The third flag may indicate whether the absolute value of the transform coefficient level is greater than 2 or 3 (for example, gt2_flag). In some embodiments, the parity of the absolute value of the transform coefficient (for example, par_flag) is also entropy-coded and decoded in the first encoding and decoding process, and the remaining part of the transform coefficient is entropy-encoded and decoded in the second encoding and decoding process, And in the third coding and decoding process, the sign of the transform coefficient is entropy coding and decoding. Entropy encoding and decoding of regular bits of transform coefficients in the first encoding and decoding process using a context-based model, which is based on the parity determination of the first flag, the second flag, the third flag, and the absolute value of the transform coefficient .

The video encoder identifies (at step 620) constraints that limit the total number of regular bits used for entropy encoding and decoding of syntax elements. In some embodiments, the constraints on the first color component are different from the constraints on the second color component. In some embodiments, the constraints are determined based on the size of the transform block. In some embodiments, the constraint is calculated by multiplying the default constraint with a predefined factor derived from the ratio of the number of coded sub-blocks in the current block to the number of all sub-blocks in the current block. In some embodiments, the total number of regular bits used for entropy encoding and decoding of the syntax elements in the first encoding and decoding process is restricted by constraints. In some embodiments, there are no constraints that limit the number of regular bits specific to a single syntax element.

The video encoder selects or receives (at step 625) the syntax element as the current syntax element to be entropy encoded. The choice of syntax elements can be determined by the current encoding and decoding process. Video encoder It is then determined (at step 630) whether to use bypass mode or regular mode to encode the current syntax element. In some embodiments, the video decoder keeps track of the number or count of regular bits that have been used to encode syntax elements. The number of regular bits is compared with the constraint identified in step 620, which limits the maximum allowable number of CABAC regular bits of the transform block, for example, the maximum number of CABAC regular bits used to encode sub-blocks. Allowed quantity. If encoding the current syntax element as a regular bit would exceed the constraint, the process proceeds to 650. If encoding the current syntax element as a regular bit will not exceed the constraint, the process proceeds to 640. In some embodiments, the video codec can encode specific syntax elements into regular bits without restriction.

In step 640, the video encoder uses context modeling to encode and decode the current syntax element entropy into regular bits. The video encoder also updates (at step 645) the total number or count of regular bits used for entropy encoding and decoding of syntax elements. Then, the process 600 proceeds to 660.

In step 650, the video encoder entropy encodes the current syntax element into bypass bits without using context modeling. Then the process proceeds to 660.

In step 660, the video encoder determines whether there are more syntax elements to be entropy encoded for the current transform block, the current sub-block, or the current encoding and decoding process. If so, the process returns to step 625 to entropy encode more syntax elements. Otherwise, the process proceeds to 670 to store the entropy-coded syntax elements as coded bits in the bitstream.

IV. Example video decoder

Figure 7 shows an example video decoder 700. As shown in the figure, the video decoder 700 is a picture decoding or video decoding circuit, which receives a bit stream 795 and decodes the content of the bit stream into pixel data of a video frame for display. The video decoder 700 has several components or modules for decoding the bit stream 795, including an inverse quantization module 705, an inverse transform module 710, an intra prediction module 725, a motion compensation module 730, a loop filter 745, and decoded pictures. Some components in the buffer 750, the MV buffer 765, the MV prediction module 775, and the parser 790. The motion compensation module 730 is an inter prediction module 740 a part of.

In some embodiments, the modules 710-790 are modules of software instructions executed by one or more processing units (eg, processors) of the computing device. In some embodiments, the modules 710-790 are modules of hardware circuits implemented by one or more ICs of the electronic device. Although the modules 710-790 are illustrated as separate modules, certain modules may be combined into a single module.

The parser 790 (or entropy decoder) receives the bit stream 795 and performs initial parsing according to the syntax defined by the video coding or picture coding standard. The parsed syntax elements include various header elements, flags, and quantized data (or quantized coefficients) 712. The parser 790 parses various syntax elements by using an entropy coding technique such as context adaptive binary arithmetic coding (CABAC) or Huffman coding.

The inverse quantization module 705 dequantizes the quantized data (or quantized coefficients) 712 to obtain transform coefficients, and the inverse transform module 710 performs inverse transform on the transform coefficients 716 to generate a reconstructed residual signal 719. The predicted pixel data 713 from the intra prediction module 725 or the motion compensation module 730 is added to the reconstructed residual signal 719 to generate decoded pixel data 717. The decoded pixel data is filtered by the loop filter 745 and stored in the decoded picture buffer 750. In some embodiments, the decoded picture buffer 750 is a memory external to the video decoder 700. In some embodiments, the decoded picture buffer 750 is the internal memory of the video decoder 700.

The intra-frame prediction module (shown as the intra-picture prediction module in the figure) 725 receives intra-frame prediction data from the bitstream 795 and generates predicted pixel data 713 from the decoded pixel data 717 stored in the decoded picture buffer 750 accordingly. In some embodiments, the decoded pixel data 717 is also stored in a line buffer (not shown) used for intra-picture prediction and spatial MV prediction.

In some embodiments, the contents of the decoded picture buffer 750 are used for display. The display device 755 either captures the content of the decoded picture buffer 750 for direct display, or captures the content of the decoded picture buffer to the display buffer. In some embodiments, the display device transfers pixels from the decoding The picture buffer 750 receives pixel values.

The motion compensation module 730 generates predicted pixel data 713 from the decoded pixel data 717 stored in the decoded picture buffer 750 according to the motion compensation MV (MC MV). These motion-compensated MVs are decoded by adding the residual motion data received from the bitstream 795 and the predicted MVs received from the MV prediction module 775.

The MV prediction module 775 generates a predicted MV based on a reference MV (for example, a motion compensation MV for performing motion compensation) generated for decoding a previous video frame. The MV prediction module 775 retrieves the reference MV of the previous video frame from the MV buffer 765. The video decoder 700 stores the motion compensation MV generated for decoding the current video frame in the MV buffer 765 as a reference MV for generating the predicted MV.

The loop filter 745 performs a filtering or smoothing operation on the decoded pixel data 717 to reduce coding artifacts, especially at the boundaries of pixel blocks. In some embodiments, the filtering operation performed includes sample adaptive offset (SAO). In some embodiments, the filtering operation includes adaptive loop filtering (ALF).

Figure 8 illustrates the part of the video decoder 700 that selectively entropy decodes the syntax elements of the sub-blocks of the block in the regular mode or the bypass mode based on the constraint of limiting the number of regular bits used for the sub-block. The figure shows the components of the entropy decoder module 790.

The entropy decoder 790 receives coded bits 818 from the bit stream 795. The normal/bypass mode switch 808 determines whether the coded bits will be decoded as normal bits or bypass bits. The context modeler 812 and the regular decoding engine 814 use context modeling to process the coded bits to be decoded into regular bits into a bit substring 810. The coded bits to be decoded as bypass bits are processed by the bypass encoding engine 816 as bit substrings 810 without using context modeling.

The bit substring 810 is converted into a syntax element (for non-binary value syntax elements) by the debinarizer 806, or directly used as a syntax element (for binary value syntax elements). The syntax element converter 802 converts syntax elements into signals or values to be used by various parts of the video decoder 700, including converting syntax elements of transform coefficients (for example, sig_flag, gt1_flag, gt2_flag, and par_flag) into quantized coefficients 712 to use于inverse quantizer 705. The syntax elements are converted according to the order specified by the predetermined codec process.

The normal/bypass mode switch 808 is controlled by the normal/bypass mode selection module 820. The normal/bypass mode selection module uses the normal bit sub-counter 822 to make a decision on whether to select the normal mode or the bypass mode. The regular bit sub-counter 822 counts the number of regular bits decoded for the current sub-block, and the regular/bypass mode switch 808 allows the coded bits to be decoded into regular bits, as long as the regular bit sub-counter is not greater than or equal to Constraints (shown as regular bit sub-constraints in the figure) 824. Therefore, the constraint 824 limits the current sub-block or the number of regular bits in the current codec process of the current sub-block. The constraint 824 may be determined based on the size of the sub-block, the number of coded sub-blocks in the current block, the total number of sub-blocks in the current block, the color components of the current sub-block, or other attributes of the current block and the sub-block.

Figure 9 conceptually illustrates a process 900 that selectively entropy-decodes syntax elements of sub-blocks of a block in a regular mode or a bypass mode based on a constraint that limits the number of regular bits used to transform a block. In some embodiments, one or more processing units (eg, processors) of a computing device that implements the video decoder 700 perform the process 900 by executing instructions stored in a computer-readable medium. In some embodiments, the electronic device implementing the video decoder 700 performs the process 900.

The video decoder receives (at step 910) encoded bits corresponding to a plurality of syntax elements representing transform coefficients of the current block from the bit stream. The transform coefficient may be the transform coefficient of the transform block of the current block, or the transform coefficient of the sub-block of the transform block. In some embodiments, the syntax elements will be entropy decoded in multiple encoding and decoding processes. For each transform coefficient, at least the first flag, the second flag, and the third flag indicating the absolute value of the transform coefficient will be entropy-decoded in the first encoding and decoding process. The first flag may indicate whether the absolute value of the transform coefficient level is greater than 0 (for example, sig_flag). The second flag may indicate whether the absolute value of the transform coefficient level is greater than 1 (for example, gt1_flag). The third mark can Indicates whether the absolute value of the transform coefficient level is greater than 2 or 3 (for example, gt2_flag). In some embodiments, the parity of the absolute value of the transform coefficient (for example, par_flag) is also entropy-coded and decoded in the first encoding and decoding process, and the remaining part of the transform coefficient is entropy-encoded and decoded in the second encoding and decoding process, And in the third coding and decoding process, the sign of the transform coefficient is entropy coding and decoding. Entropy encoding and decoding of regular bits of transform coefficients in the first encoding and decoding process using a context-based model, which is based on the parity determination of the first flag, the second flag, the third flag, and the absolute value of the transform coefficient .

The video decoder identifies (at step 920) constraints that limit the total number of regular bits used for entropy decoding of syntax elements. In some embodiments, the constraints on the first color component are different from the constraints on the second color component. In some embodiments, the constraints are determined based on the size of the transform block. In some embodiments, the constraint is calculated by multiplying the default constraint with a predefined factor derived from the ratio of the number of coded sub-blocks in the current block to the number of all sub-blocks in the current block. In some embodiments, the total number of regular bits used for entropy decoding of syntax elements in the first encoding and decoding process is restricted by constraints. In some embodiments, there are no constraints that limit the number of regular bits specific to a single syntax element.

The video decoder selects or receives (at step 925) a syntax element from the coded bits of the bitstream as the current syntax element to be entropy decoded. The choice of syntax elements can be determined by the current encoding and decoding process. Then, the video decoder determines (at step 930) whether to use the bypass mode or the regular mode to decode the current syntax element. In some embodiments, the video decoder tracks the number or count of regular bits that have been used to decode syntax elements. The number of regular bits is compared with the constraint identified in step 920, which limits the maximum allowable number of CABAC regular bits used to transform the block, for example, the CABAC regular bits used to encode sub-blocks The maximum allowable number of.

If decoding the current syntax element into regular bits would exceed the constraint, the process proceeds to 950. If decoding the current syntax element into regular bits will not exceed the constraint, the process proceeds to 940. In some embodiments, the video codec can decode certain syntax elements as Regular seat.

In step 940, the video decoder uses context modeling to entropy decode the current syntax element into regular bits. The video decoder also updates (at step 945) the total number or count of regular bits used for entropy decoding of syntax elements. Then, the process 900 proceeds to 960.

In step 950, the video decoder entropy decodes the current syntax element into bypass bits without using context modeling. Then the process proceeds to 960.

In step 960, the video decoder determines whether there are more syntax elements to be entropy-decoded for the current sub-block or the current codec process of the current sub-block. If so, the process returns to step 925 to entropy decode more syntax elements. Otherwise, the process proceeds to 970 to reconstruct the current block using entropy decoded syntax elements such as transform coefficients.

V. Example electronic system

Many of the aforementioned features and applications are implemented as software processes designated as a set of instructions recorded on a computer-readable storage medium (also referred to as computer-readable medium). When these instructions are executed by one or more computing or processing units (for example, one or more processors, processor cores, or other processing units), they cause the processing units to perform the actions indicated in the instructions. Examples of computer readable media include, but are not limited to, CD-ROMs, flash drives, random access memory (RAM) chips, hard disk drives, erasable programmable read-only memory (EPROM), electrically erasable Programmable read-only memory (EEPROM), etc. Computer-readable media does not include carrier waves and electronic signals that are transmitted wirelessly or through wired connections.

In this specification, the term "software" is intended to include firmware residing in read-only memory or applications stored in magnetic memory, which can be read into memory for processing by a processor. Similarly, in some embodiments, multiple software inventions can be implemented as sub-parts of a larger program, while retaining different software inventions. In some embodiments, multiple software inventions can also be implemented as separate programs. Finally, any combination of individual programs that together implement the software invention described herein is within the scope of the present disclosure. In some embodiments, when a software program is installed to run on one or more electronic systems, it defines one or more specific machine implementations that execute and implement the operations of the software program. In some embodiments, the encoding operation refers to an encoding operation or a decoding operation.

Figure 10 conceptually illustrates an electronic system 1000 implementing some embodiments of the present disclosure. The electronic system 1000 may be a computer (for example, a desktop computer, a personal computer, a tablet computer, etc.), a telephone, a PDA, or any other kind of electronic equipment. Such electronic systems include various types of computer readable media and interfaces for various other types of computer readable media. The electronic system 1000 includes a bus 1005, a processing unit(s) 1010, a graphics processing unit (GPU) 1015, a system memory 1020, a network 1025, a read-only memory 1030, a permanent storage device 1035, and an input device 1040, And output device 1045.

The bus 1005 collectively represents all systems, peripheral devices, and chipset buses that communicatively connect many internal devices of the electronic system 1000. For example, the bus 1005 communicatively connects the processing unit 1010 with the GPU 1015, the read-only memory 1030, the system memory 1020, and the permanent storage device 1035.

The processing unit 1010 retrieves the instructions to be executed and the data to be processed from these various storage units in order to execute the processing of the present disclosure. In different embodiments, one or more processing units may be a single processor or a multi-core processor. Some instructions are passed to and executed by GPU 1015. The GPU 1015 can offload various calculations or supplement the image processing provided by the processing unit 1010.

A read-only memory (ROM) 1030 stores static data and static data and instructions used by the processing unit 1010 and other modules of the electronic system. On the other hand, the permanent storage device 1035 is a read-write storage device. This device is a non-volatile storage unit that stores instructions and data even when the electronic system 1000 is turned off. Some embodiments of the present disclosure use mass storage devices (such as magnetic disks or optical disks and their corresponding disk drives) as permanent storage devices 1035.

Other embodiments use removable storage devices (such as floppy disks, flash memory devices, etc., and Corresponding disk drive) as a permanent storage device. Like the permanent storage device 1035, the system memory 1020 is a read-write storage device. However, unlike the storage device 1035, the system memory 1020 is a volatile read-write memory, such as a random access memory. The system memory 1020 stores some instructions and data used by the processor when it is running. In some embodiments, the processing according to the present disclosure is stored in the system memory 1020, the permanent storage device 1035, and/or the read-only memory 1030. For example, according to some embodiments, various storage units include instructions for processing multimedia clips. The processing unit 1010 retrieves the instructions to be executed and the data to be processed from these various storage units, so as to perform the processing of some embodiments.

The busbar 1005 is also connected to input and output devices 1040 and 1045. The input device 1040 enables the user to convey information to the electronic system and select commands. The input device 1040 includes an alphanumeric keyboard and pointing device (also called a "mouse control device"), a camera (for example, a webcam), a microphone or similar device for receiving voice commands, and the like. The output device 1045 displays pictures generated by the electronic system or output materials. The output device 1045 includes a printer and a display device, such as a cathode ray tube (CRT) or a liquid crystal display (LCD), and a speaker or similar audio output device. Some embodiments include devices that act as both input devices and output devices, such as touch screens.

Finally, as shown in Figure 10, the bus 1005 also couples the electronic system 1000 to the network 1025 through a network adapter (not shown). In this manner, the computer may be part of a computer network, such as a local area network ("LAN"), a wide area network ("WAN"), or an intranet or a network of networks, such as the Internet. Any or all components of the electronic system 1000 can be used in conjunction with the present disclosure.

Some embodiments include an electronic component, such as a microprocessor, a memory storing computer program instructions in a machine-readable or computer-readable medium (or referred to as a computer-readable storage medium, a machine-readable medium, or a machine-readable storage medium) And memory. Some examples of such computer-readable media include RAM, ROM, compact disc read only (CD-ROM), compact disc recordable (CD-R), rewritable Optical discs (CD-RW), read-only digital versatile discs (for example, DVD-ROM, double-layer DVD-ROM), various recordable/rewritable DVDs (for example, DVD-RAM, DVD-RW, DVD+RW, etc.) , Flash memory (such as SD card, mini-SD card, micro-SD card, etc.), magnetic and/or solid-state hard drive, read-only and recordable Blu-Ray® disc, ultra-density optical disc, any other optical or magnetic media And floppy disks. The computer-readable medium may store a computer program that can be executed by at least one processing unit, and the computer program includes an instruction set for performing various operations. Examples of computer programs or computer codes include machine codes such as generated by a compiler, and files including high-level codes executed by computers, electronic components, or microprocessors using an interpreter.

Although the above discussion mainly refers to microprocessors or multi-core processors that execute software, many of the above features and applications are executed by one or more collective circuits, such as dedicated collective circuits (ASICs) or field programmable controller gate arrays. (FPGA). In some embodiments, such collective circuits execute instructions stored on the circuit itself. In addition, some embodiments execute software stored in a programmable logic device (PLD), ROM, or RAM device.

As used in this specification and any patent application in this application, the terms "computer", "server", "processor" and "memory" all refer to electronic or other technical devices. These terms do not include individuals or groups of people. For the purpose of description, the term "display" or "displaying" refers to displaying on an electronic device. As used in this specification and the scope of any patent application of this application, the terms "computer readable medium", "computer readable medium" and "machine readable medium" are completely limited to storing information in a form that can be read by a computer. Of tangible physical objects. These terms do not include any wireless signals, wired download signals, and any other temporary signals.

Although the present disclosure has been described with reference to many specific details, those skilled in the art will recognize that the present disclosure may be embodied in other specific forms without departing from the spirit of the present disclosure. In addition, many drawings (including Figures 6 and 9) conceptually illustrate the process. The specific operations of these procedures may not be performed in the exact order shown and described. Can be different A specific operation is performed in a continuous series of operations, and different specific operations may be performed in different embodiments. In addition, the process can be implemented using several sub-processes, or as part of a larger macro process. Therefore, those with ordinary knowledge in the field will understand that the present disclosure is not limited to the foregoing illustrative details, but is limited by the scope of the appended application.

Additional statement

The subject matter described in the text sometimes shows different components contained within or connected to other different components. It should be understood that the architecture depicted in this way is only exemplary, and in fact, many other architectures that achieve the same function can be implemented. In a conceptual sense, any arrangement of components that achieve the same function is effectively "associated" so that the desired function is achieved. Therefore, any two components combined to obtain a specific function in the text can be regarded as "associated" with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be regarded as being "operably connected" or "operably coupled" to each other to achieve the desired function, and any two components that can be so associated Components can also be considered "operably coupleable" to each other to achieve desired functions. Specific examples of "operably coupleable" include, but are not limited to: physically connectable and/or physically interacting components, and/or wirelessly interactable and/or wirelessly interacting components, and /Or logically interacting and/or logically interactable components.

In addition, with regard to the use of basically any plural and/or singular term in the text, as long as it is appropriate for the context and/or application, a person with ordinary knowledge in the relevant technical field can convert the plural to the singular and/or convert the singular to the plural.

Those with ordinary knowledge in the technical field will understand that, generally, the terms used in the text, especially the terms used in the scope of the attached application (for example, the subject of the scope of the attached application), are usually intended as "open Terminology (for example, the term "includes" should be interpreted as "including but not limited to", the term "having" should be interpreted as "at least having", and the term "including" should be interpreted as "including but not limited to" Wait). Those with general knowledge in the technical field will also understand that if they intend to apply for a patent as described The scope states the specific number of objects, then such an intention will be clearly stated in the scope of the patent application. In the absence of such a statement, there is no such intention. For example, to help understanding, the scope of the appended patent application may include the use of the introductory phrases "at least one" and "one or more" to introduce the object of the statement of the patent scope. However, the use of such phrases should not be construed as: the introduction of the object of the patent application with the indefinite article "a (a or an)" shall limit the scope of any application that contains the object of the statement of the patent application so introduced to Contains only one invention that is the subject of such a statement, even if the introductory phrase "one or more" or "at least one" and such as "one (a)" or "one (an)" are included in the same patent application In the case of indefinite articles (for example, "a" and/or "a" should usually be interpreted as meaning "at least one" or "one or more"); The definite article to introduce the object of the statement of the scope of the patent application is also applicable. In addition, even if the specific number of objects of the stated scope of the patent application is clearly stated, those with ordinary knowledge in the technical field will recognize that such a statement should usually be interpreted as meaning at least the stated number (for example, only A statement with "two statement objects" without other modifiers usually means at least two statement objects, or two or more statement objects). In addition, in the case of using an idiom similar to "at least one of A, B, and C, etc.", usually such a structure is intended to have the meaning of the idiom understood by ordinary knowledgeable persons in the technical field (for example, " A system having at least one of A, B, and C" will include, but is not limited to, having a single A, a single B, a single C, A and B together, A and C together, B and C together, and/or A, B and C together system, etc.). In the case of using an idiom similar to "at least one of A, B, or C, etc.", usually such a structure is intended to have the meaning of the idiom understood by those skilled in the art (for example, "has A A system with at least one of, B, or C" will include but is not limited to having a single A, a single B, a single C, A and B together, A and C together, B and C together, and/or A, B and C together with the system, etc.). Those with ordinary knowledge in the technical field will further understand that, whether in the specification, the scope of the patent application or in the drawings, almost any abstract words and/or phrases representing two or more replaceable terms should be understood as Consider including one of the terms, any of the terms, or all There are two possibilities for terms. For example, the phrase "A or B" should be understood to include the possibilities of "A", "B", or "A and B."

Although different methods, devices, and systems have been used in the text to describe and show some exemplary technologies, those with ordinary knowledge in the technical field should understand that it can be carried out without departing from the claimed subject matter. Various other modifications and equivalent replacements. In addition, without departing from the central idea described in the text, many modifications can be made to adapt a particular situation to the teaching of the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific examples disclosed, and such claimed subject matter may also include all implementations and their equivalents falling within the scope of the appended application patent.

100: current block

110, 319, 325: sub-block

115, 524, 824: constraints

121, 122, 123: encoding and decoding process

210, 220: plan

310, 320: block

400: Video encoder

405: Video Source

495, 795: bit stream

410: Transformation module

411: Quantization Module

412, 712: quantization coefficient

413: Predict pixel data

414, 705: Inverse quantization module

415, 710: Inverse transform module

417: Reconstruct pixel data

419: reconstruction residual

420: In-picture estimation module

425, 725: intra prediction module

430, 730: Motion compensation module

435: Motion estimation module

440, 740: Inter-frame prediction module

445, 745: loop filter

450: Reconstruct the picture buffer

465, 765: MV buffer

475, 775: MV prediction module

490: Entropy Codec

502, 802: Syntax element generator

506: Binary

508, 808: conventional/bypass mode switch

510, 810: bit substring

512, 812: Context Modeler

514, 814: conventional encoding engine

518, 818: coding bits

516, 816: Bypass encoding engine

520, 820: conventional/bypass mode selection module

522, 822: conventional bit counters

600, 900: process

610~670, 910~970: steps

700: Video decoder

750: decode picture buffer

790: parser

716: transform coefficient

713: Pixel Data

719: Reconstruct residual signal

717: decode pixel data

755: display device

806: Go to Binary

1000: Electronic system

1005: bus

1010: processing unit

1015: graphics processing unit

1020: System memory

1025: Internet

1030: Read only memory

1035: Permanent storage device

1040: input device

1045: output device

The accompanying drawings are included to provide a further understanding of the present disclosure, and the accompanying drawings are incorporated and constitute a part of the present disclosure. The drawings illustrate the embodiments of the present disclosure, and together with the text description are used to explain the principle of the present disclosure. It can be understood that the drawings are not necessarily drawn to scale, because in order to clearly illustrate the concept of the present disclosure, some components may be displayed as out of proportion to the size in actual implementation. Figure 1 conceptually shows a video codec, which selectively entropy encodes and decodes the syntax of sub-blocks of a block in a regular mode or a bypass mode based on a constraint on the number of regular bits used for a sub-block element. Figure 2 shows the encoding and decoding process, which includes a flag indicating the absolute value of the transform coefficient level when entropy encoding and decoding a sub-block of the transform block. Figure 3 shows that the allowed number of regular bits are shared among the sub-blocks of the current block.

Figure 4 shows an example of a video encoder.

Figure 5 shows a part of the video codec, which selectively entropy encodes and decodes the syntax elements of the sub-blocks of the block in the regular mode or the bypass mode based on the constraint of limiting the number of regular bits used for the sub-block .

Fig. 6 conceptually shows a process of selectively entropy-encoding the syntax elements of sub-blocks of a block in a regular mode or a bypass mode based on the constraint of limiting the number of regular bits used for the sub-block.

Figure 7 shows an example of a video decoder.

Figure 8 illustrates the part of a video decoder that selectively entropy decodes the syntax elements of the sub-blocks of the block in the normal mode or the bypass mode based on the constraint of limiting the number of regular bits used for the sub-block.

Fig. 9 conceptually shows a process of selectively entropy decoding the syntax elements of sub-blocks of a block in a regular mode or a bypass mode based on the constraint of limiting the number of regular bits used for the sub-block.

Figure 10 conceptually illustrates an electronic system for implementing some embodiments of the present disclosure.

900: process

910~970: steps

Claims (12)

A method for encoding and decoding includes: receiving input data associated with multiple syntax elements representing multiple transformation coefficients of a current block; and selectively entropy encoding and decoding the multiple syntax elements into context modeling Multiple regular bits or multiple bypass bits without context modeling, wherein the number of the multiple regular bits used for entropy coding and decoding of the multiple syntax elements is restricted by constraints, The multiple syntax elements represent multiple transformation coefficients of the transformation block, and the constraint that limits the number of the multiple regular bits is determined based on the size of the transformation block. The method described in item 1 of the scope of the patent application, wherein the multiple syntax elements are encoded and decoded in multiple encoding and decoding processes, and wherein the restriction is used to restrict the use of the syntax elements in the first encoding and decoding process. The total number of multiple regular bits for which multiple syntax elements perform entropy coding and decoding. The method described in item 2 of the scope of the patent application, wherein one or more of the first flag, the second flag, and the third flag that are entropy-coded and decoded in the first coding and decoding process indicate the absolute value of the transform coefficient, And: the first flag indicates whether the absolute value of the transform coefficient is greater than 0, the second flag indicates whether the absolute value of the transform coefficient is greater than 1, and the third flag indicates whether the absolute value of the transform coefficient is greater than 3 . The method described in item 3 of the scope of patent application, wherein: the parity of the absolute value of the transform coefficient is entropy-encoded and decoded in the first encoding and decoding process, and the remaining part of the transform coefficient is entropy-encoded in the second encoding and decoding process Perform entropy coding and decoding, and perform entropy coding and decoding on the sign of the transform coefficient in the third coding and decoding process. The method described in item 4 of the scope of patent application, wherein one or more context models that rely on one or more indicators of the absolute value of one or more adjacent transform coefficients are used to Entropy coding and decoding is performed on the multiple regular bits of the first coding and decoding process. The method described in item 5 of the scope of patent application, wherein at least one context model is selected based on the value of the third flag. The method described in item 1 of the scope of the patent application, wherein the constraint that limits the number of the plurality of regular bits is different for the first color component and for the second color component. The method described in item 1 of the scope of patent application, wherein the constraint that limits the number of the plurality of regular bits is calculated by multiplying the default constraint by a predefined factor, and the predefined factor is derived from the current block It is derived from the ratio of the number of coded sub-blocks in the current block to the number of all sub-blocks in the current block. For the method described in item 1 of the scope of the patent application, there is no restriction to limit the number of the plurality of regular bits specific to a single syntax element. The method described in item 1 of the scope of the patent application, wherein the restriction of limiting the number of the plurality of regular bits limits the number of the plurality of regular bits used for the sub-block of the current block. A decoder circuit capable of: receiving bit stream coded bits associated with multiple syntax elements representing multiple transform coefficients of a current block; selectively entropy-encoding and decoding the coded bits into the multiple syntax elements, Multiple regular bits modeled for the use of context or multiple bypass bits without context modeling, wherein the number of the multiple regular bits used for entropy decoding the multiple syntax elements Subject to constraints, the multiple syntax elements represent multiple transformation coefficients of the transformation block, and the restriction that limits the number of the multiple regular bits is determined based on the size of the transformation block; and the multiple syntax elements that use entropy decoding Each syntax element reconstructs the current block. An electronic device for encoding and decoding, including: an encoder circuit with the following functions: Receive multiple syntax elements representing multiple transform coefficients of the current block; selectively entropy encode the multiple syntax elements into multiple regular bits using context modeling or multiple bypass bits without context modeling Element, wherein the number of regular bits used for entropy encoding the multiple syntax elements is restricted by constraints, the multiple syntax elements represent multiple transformation coefficients of the transformation block, and based on the transformation block To determine the constraint that limits the number of the regular bits; and store the entropy-coded syntax elements in the bit stream.

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