TWI732335B - Integrated circuit device and fabricating method thereof - Google Patents

Abstract

A integrated circuit device fabricating method includes receiving a semiconductor structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the semiconductor structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

Description

Integrated circuit device and manufacturing method thereof

The present disclosure relates to an integrated circuit device, particularly an integrated circuit device with well isolation characteristics.

The semiconductor integrated circuit (IC) industry is growing rapidly. In the IC development process, when the geometric size (for example: the smallest part that can be made by the process) decreases, the functional density (for example: the number of connected components per chip area) usually increases. This miniaturization process provides advantages by increasing production efficiency and reducing related costs. However, this scaling is also accompanied by increased complexity in the design and manufacture of devices including these integrated circuits. Parallel developments in manufacturing have allowed increasingly complex designs to be manufactured accurately and reliably.

For example, advancements in manufacturing have achieved three-dimensional designs, such as Fin-like Field Effect Transistor (FinFET). Compared with planar FETs, FinFETs provide reduced short-channel effects, reduced leakage, and higher current. Because of these advantages, FinFETs have been used to further scale down ICs. However, some areas of the existing FinFET manufacturing process can be further improved. For example, in the FinFET Complementary Metal-Oxide-Semiconductor (CMOS) design, latch-up may occur due to the leakage between adjacent N-wells and P-wells.

The present disclosure provides a method for manufacturing an integrated circuit device. The manufacturing method of an integrated circuit device includes receiving a semiconductor structure. The semiconductor structure includes a substrate. The substrate includes a first well region with a first dopant type and a second well region with a second dopant type. The second dopant The type is opposite to the first dopant type; and a plurality of fins extending above the substrate. The manufacturing method of the integrated circuit device further includes forming a patterned etching mask on the semiconductor structure, wherein the patterned etching mask provides an opening directly above the first fin of the fin, wherein the first fin is in the first well region Directly above; the semiconductor structure is etched through the patterned etching mask, wherein the etching step removes the first fin and forms a recess in the substrate that spans from the first well region to the second well region; and in the plural remaining fins A dielectric material is formed between the parts and in the recess.

The present disclosure provides a method for manufacturing an integrated circuit device. The manufacturing method of the integrated circuit device includes receiving a semiconductor structure. The semiconductor structure includes: a substrate including an N-well region and a P-well region adjacent to the N-well region; and a plurality of fin structures extending above the substrate. The manufacturing method of the integrated circuit device further includes forming a dielectric liner above the upper surface of the substrate, the top of the fin structure and the plurality of side walls; forming a patterned etching mask above the semiconductor structure, and the patterned etching mask has openings, The first fin structure of the fin structure is erected in the opening, wherein the first fin structure is directly above the N-well region; the first fin structure and the substrate are etched through the opening, and the etching step forms the cross-N-well region in the substrate And the depression of the boundary between the P-well region and the P-well region; and the formation of a dielectric material between and within the plurality of remaining parts of the fin structure.

The present disclosure provides an integrated circuit device. The integrated circuit device includes a substrate, including a first well region with a first doping type and a second well region with a second doping type, the second dopant type is different from the first dopant type; a plurality of fins , Extending from the substrate; a dielectric material disposed between the fins so that the fins extend above the top surface of the dielectric material; and a well isolation feature, including a portion of the dielectric material extending into the substrate, wherein the well isolation feature The bottom surface of the fin is below the top surface of the substrate extending between the well isolation feature and the first fin of the fin.

This disclosure provides many different embodiments or examples to implement different features of the case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not meant to be limiting. For example, if this disclosure describes that a first feature is formed on or above a second feature, it means that it may include an embodiment in which the first feature is in direct contact with the second feature, or it may include There are embodiments in which additional features are formed between the first feature and the second feature, and the first feature and the second feature may not be in direct contact. In addition, forming a feature connected to another feature and/or forming a feature coupled with another feature in the subsequent disclosure may include embodiments in which the feature is formed in direct contact, and may also include an insertion feature that can form additional features The embodiment, so that the feature can not be in direct contact.

In addition, space-related terms, such as "below", "above", "horizontal", "vertical", "above", "above", "below", "below", "above", "Down", "top", "bottom", etc. and their derivatives (for example: "horizontally", "downward", "upward", etc.) are used to change the relationship between one feature of the present disclosure and another feature Easy. These spatially related terms are intended to encompass the different orientations of characteristic devices. In addition, the same reference symbols or signs may be used repeatedly in different embodiments of the present disclosure below. These repetitions are for the purpose of simplification and clarity, and are not used to limit the specific relationship between the different embodiments and/or structures discussed. In addition, when a number or a range of numbers is described in terms of "about", "approximately", etc., the term is intended to encompass quantities within a reasonable range that include the stated quantity, such as a value within +/-10% or those in the art Other values usually understood by knowledgeable persons. For example, the term "about 5 nm" includes the size range of 4.5 nm to 5.5 nm.

As devices continue to shrink, leakage current between oppositely doped wells on the IC becomes a problem because it can trigger a latch-up in the circuit. Place N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) transistors (including NMOS FinFET and PMOS FinFET) closely This is especially worthy of attention in terms of today’s SRAM design. Figure 12 illustrates an example of a latch. Figure 12 shows the layout of a semiconductor device 100 including a 1-bit Static Random Access Memory (SRAM) cell with a CMOS circuit on the right, and shows the layout of a 1-bit SRAM cell on the left. The circuit diagram of the intrinsic bipolar transistor of the CMOS circuit. When one of the two bipolar transistors becomes forward biased (due to the leakage current flowing through the well or the substrate, as shown by "N+/NWà" and "P+/PWà"), it is the other transistor The base is powered. This positive feedback increases the current until the circuit fails or burns out. This is called "latch". The purpose of the present disclosure is to prevent latch-up by providing well isolation features that separate well regions of different dopant types. For example, a well isolation feature can be provided between the N-type doped well region and the P-type doped well region to greatly reduce the leakage current between the two well regions.

Some embodiments of the present disclosure are described with reference to FIGS. 1-12. FIG. 1 is a flowchart of a method 10 for manufacturing a semiconductor device with well isolation characteristics according to an embodiment of the disclosure. Method 10 is only an example, and is not intended to limit the content specifically recorded in the patent application scope of this disclosure. Additional operations may be provided before, during, and after method 10, and for additional embodiments of the method, some of the operations described may be replaced, removed, or moved. The method 10 is described below with reference to FIGS. 2 to 11, which shows various schematic diagrams and cross-sectional views of the semiconductor device 100 during the manufacturing process according to the method 10. In addition, FIG. 12 shows a schematic diagram and layout diagram of an example IC manufactured according to the present disclosure.

Referring to Figure 1, in operation 12, the method 10 receives a semiconductor structure (or workpiece) 100 having a substrate, the semiconductor structure having a well region and semiconductor fins extending from the substrate. An example of the semiconductor structure 100 is shown in FIG. 2.

Referring to FIG. 2, the semiconductor structure 100 includes a substrate 102, which represents any structure on which a circuit device can be formed. In various embodiments, the substrate 102 includes elemental (single element) semiconductors, such as silicon or germanium with a crystal structure; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or antimony Indium; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphorous (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide ( GaInP) and/or gallium indium arsenide (GaInAsP); non-semiconductor materials, such as soda lime glass, fused silica, fused silica, and/or calcium fluoride (CaF ₂ ); and/or combinations thereof.

The substrate 102 may be uniform in composition or may include various material layers. These material layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to cause device strain and thereby adjust device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrates. In some embodiments, one material layer of the substrate 102 may include an insulator, such as semiconductor oxide, semiconductor nitride, semiconductor oxynitride, semiconductor carbide, and/or other suitable insulator materials; and another material layer of the substrate 102 includes Semiconductor material. In some embodiments, the substrate 102 is a bulk semiconductor substrate, such as a bulk silicon wafer.

A doped region (for example, a well) may be formed on the substrate 102. In this regard, some parts of the substrate 102 may be doped with P-type dopants, such as boron, boron difluoride (BF ₂ ) or indium, and other parts of the substrate 102 may be doped with N-type dopants. , Such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. In the illustrated embodiment, the well region 104A has a first dopant type (for example: N-type), and the well region 104B has a second dopant type (for example: P-type) that is opposite to the first dopant type. , And the well region 104C has the first dopant type. Therefore, a pn junction (pn junction) can be formed at the interface between these well regions 104. The inventors of the present disclosure have observed that these PN junctions can cause leakage current and latch-up problems, especially in SRAM designs with very small device geometry. Likewise, the three well areas 104A to 104C are only examples. In various embodiments, the semiconductor structure 100 may include two or more oppositely doped well regions.

In some embodiments, the device to be formed on the substrate 102 extends out of the substrate 102. For example, FinFETs and/or other non-planar devices can be formed on fins (or fin structures) 106 disposed on the substrate 102. The fin 106 represents any raised feature on the substrate 102 used to form FinFET devices and other raised active and passive devices. The composition of the fin 106 may be similar to or different from that of the substrate 102. For example, in some embodiments, the substrate 102 may mainly include silicon, and the fin 106 includes one or more material layers mainly of germanium or silicon germanium (SiGe) semiconductor. In some embodiments, the substrate 102 includes a silicon germanium semiconductor, and the fin 106 includes a silicon germanium semiconductor having a different silicon germanium ratio than the substrate 102. In some embodiments, both the fin 106 and the substrate 102 mainly comprise silicon. Figure 2 shows only six fins 106a, 106b, 106c, 106d, 106e, and 106f. In various embodiments, the semiconductor structure 100 may include any number of fins 106. In the following discussion, "fin 106" refers to any one of the fins 106a to 106f or another fin not shown in the drawings, and "a plurality of fins 106" refers to one of the fins 106a to 106f Any two or more of the fins or other fins not shown in the diagram. The fins 106 are oriented lengthwise along the "Y" direction and are spaced apart from each other along the "X" direction. The well area 104 is also oriented longitudinally along the "Y" direction.

The portions of the fins 106 may be doped differently from the portions of the substrate 102 from which they extend. In some embodiments, each fin 106 has a semiconductor region 108 (also referred to as a bottom 108), which contains the same dopant type as the well region 104 extending therefrom, and has an opposite dopant type. The semiconductor region 110 (also referred to as the top 110). In a specific embodiment, the well regions 104A and 104C are N-type doped (ie, N-well), the semiconductor regions 108 of the fins 106a, 106b, 106e, and 106f are also N-type doped, and the fins 106a, The semiconductor regions 110 of 106b, 106e, and 106f are P-type doped; the well region 104B is P-type doped (ie, P-well), the semiconductor regions 108 of the fins 106c and 106d are also P-type doped, and The semiconductor regions 110 of the fins 106c and 106d are n-type doped.

The fin 106 may be formed by etching a portion of the substrate 102, by depositing various material layers on the substrate 102 and etching these material layers, and/or by other suitable techniques. For example, one or more lithography processes may be used to pattern the fins 106, and the lithography processes include double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine lithography and self-alignment processes to allow the production of patterns with pitches that are smaller than those obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate 102 and one or more hard mask layers (ie, the material layer formed by the fin top hard mask patterns 112 and 114). The sacrificial layer is patterned using a photolithography process. A self-aligned process is used to form spacers beside the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers are used to pattern the substrate 102 and the hard mask layer by removing the material not covered by the spacers. The remaining material becomes the fin 106 including the hard mask patterns 112 and 114 on the top of the fin in this embodiment.

The fin top hard mask patterns 112 and 114 can be used to control the etching process that defines the fin 106, and can protect the fin 106 during subsequent processes. Therefore, the fin top hard mask patterns 112 and 114 can be selected to have different etch selectivities from the material(s) of other parts of the fin 106 and each other. The fin top hard mask patterns 112 and 114 may include dielectric materials, such as semiconductor oxide, semiconductor nitride, semiconductor oxynitride, semiconductor carbide, semiconductor carbonitride, semiconductor oxycarbonitride, and/or metal oxide .

In some embodiments, the fins 106 are arranged in a repeating pattern to simplify the patterning process, and those fins 106 that are not part of the final circuit design can be subsequently removed, which will be discussed later.

Referring to FIG. 1, in operation 14, method 10 forms a dielectric liner layer 116 on the semiconductor structure. Referring to FIG. 3, a dielectric liner layer 116 is formed above the top surface 102U of the substrate 102 and on the top and sidewalls of the fin 106. In this embodiment, the dielectric liner layer 116 is formed in a substantially conformal manner (that is, its thickness is substantially uniform). The dielectric liner layer 116 may include silicon nitride (e.g., Si3N4), and may use chemical vapor deposition (CVD) (e.g., low-pressure CVD (LPCVD) or plasma-assisted CVD). The dielectric liner layer 116 is deposited by plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable methods. In various embodiments, the dielectric liner layer 116 may have a thickness of about 1 nm to about 5 nm. Operation 14 is optional, and may be omitted in some embodiments.

Operations 16, 18, and 20 in FIG. 1 describe the process of removing some fins 106. In brief, operation 16 forms a patterned hard mask over the semiconductor structure 100, wherein the patterned hard mask has openings directly above one of the fins 106 and the two well regions 104; The opening in the mask is used to etch the semiconductor structure 100 to form a recess extending into the substrate 102; and operation 20 is to remove the patterned hard mask. Operations 16, 18, and 20 are further described below.

1, in operation 16, the method 10 forms a patterned hard mask over the semiconductor structure 100, and the patterned hard mask provides an opening 206 directly above a portion of the fin 106 to be removed, as shown in Step 4. As shown in the figure. In this embodiment, operation 16 involves multiple process steps, including depositing a hard mask layer (or filling layer) 202 on the substrate 102 and filling the gaps between the fins 106, and spinning light on the hard mask layer 202. The resist layer 204 and performing a photolithography process to pattern the photoresist layer 204 to form the opening 206. The patterned hard mask can also be formed by other methods.

Referring to FIG. 4, the hard mask layer 202 surrounds the fin 106 and may be disposed on top of the hard masks 112 and 114 on top of the fins. Suitable materials for the hard mask layer 202 include dielectric, polysilicon, and/or other suitable materials, and the material of the hard mask layer 202 can be selected to have a hard mask (fin The hard mask pattern on the top of the sheet) 112 and 114 of the fins 106 have different etchant sensitivity. In some embodiments, the hard mask layer 202 includes a spin-on dielectric material. The hard mask layer 202 can be formed by chemical vapor deposition (CVD), plasma assisted CVD (PECVD), high-density plasma CVD (High-Density Plasma CVD; HDP-CVD), atomic layer deposition (ALD), electrical Plasma-assisted ALD (Plasma Enhanced ALD; PEALD), flow CVD (; FCVD), spin coating and/or other suitable deposition techniques are formed.

A photoresist layer 204 is formed on the hard mask layer 202 (for example, by spin coating), and is patterned to provide an opening 206 therein. Any suitable lithography process (such as immersion lithography, electron beam lithography, and extreme ultraviolet (EUV) lithography) can be used to pattern the photoresist layer 204. In one embodiment, the lithography system exposes the photoresist layer 204 to radiation in a specific pattern determined by the mask. The light passing through or reflecting off the mask hits the photoresist layer 204, thereby transferring the pattern formed on the mask to the photoresist layer 204. In another embodiment, direct writing or maskless lithography techniques (such as laser patterning, electron beam patterning, and/or ion beam patterning) are used to expose the photoresist layer 204. Once exposed, the photoresist layer 204 is developed, leaving the exposed portions of the photoresist, or in alternative embodiments, the unexposed portions of the photoresist. An exemplary patterning process includes soft baking of the photoresist layer 204, mask alignment, exposure, post-exposure baking, developing the photoresist layer 204, rinsing, and drying (for example, hard baking). The patterned photoresist layer 204 exposes the portion of the hard mask layer 202 that will be etched through the opening 206.

In this embodiment, the opening 206 (the one shown in Figure 4) is directly above the portion of the fin 106 to be removed (in this embodiment, a part of the fin 106b). In order to form the well isolation feature according to the present embodiment, the opening 206 is wide enough to extend on the interface (or boundary) between two well regions (eg, well region 104A and well region 104B) having opposite dopant types. In the embodiment shown in Figure 4, along the X direction from the boundary of the well regions 104A and 104B to the sidewall of the fin 106c (the fin on the well region 104B that is closest to the well region 104A) The distance in the width direction of the fin is W1, the opening 206 extends along the X direction from the boundary of the well regions 104A and 104B toward the fin 106c by a distance W2, and the distance W2 is smaller than the distance W1. In some embodiments, the distance W2 is controlled to be about half of the distance W1, for example, 40% to 60% of the distance W1. This is to resolve process changes and still provide sufficient isolation between the well regions 104A and 104B (as will be described later with reference to the well isolation feature 404 in FIGS. 8 to 11). If the distance W2 is too large (that is, the edge of the opening 206 is very close to the fin 106c), the subsequent etching process may damage the fin 106c. If the distance W2 is too small (ie, the edge of the opening 206 is very close to the boundary of the well regions 104A and 104B, or the opening 206 does not even reach the well region 104B), the isolation effect of the isolation feature 404 will be lost. In addition, the opening 206 is directly above the fin 106b and has sufficient margin on both sides thereof to ensure that part of the fin 106b is completely removed. In this embodiment, the opening 206 extends along the X direction from the boundary of the well regions 104A and 104B toward the fin 106b and passes through the fin 106b (which is the fin closest to the well region 104B among the fins on the well region 104A). The distance W3, and the distance W3 is greater than the distance W2. Although one opening 206 is shown in FIG. 4, any number of openings 206 can be formed based on the circuit design operation 16. In the embodiment shown in Figure 12, two openings 206 are provided to remove part of the fins 106a and 106b.

1, in operation 18, the method 10 performs one or more etching processes to remove the exposed portion of the hard mask layer 202 and the underlying hard mask 112 and 114 (if any) including the top of the fins. Fins 106. In some embodiments, this includes a first etching process to remove exposed portions of the hard mask layer 202, followed by a second etching process performed on these portions of the fin 106. The first etching process may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching (RIE), ashing, and/or other etching techniques. In some embodiments, the etchant is selected to etch the hard mask layer 202 without significantly etching the substrate 102 and fins 106. As a result, as shown in FIG. 5, a part of the fin 106b is exposed in the opening 206. If the semiconductor structure includes the optional dielectric liner layer 116, a portion of the dielectric liner layer 116 on the top and sidewalls of the fin 106b and on the upper surface of the substrate 102 becomes exposed in the opening 206, as in the first As shown in Figure 5. After the hard mask layer 202 is etched, the photoresist layer 204 may be removed.

Subsequently, a second etching process is performed on the portions of the fin 106 in the opening 206 (which may be covered by the optional dielectric liner layer 116). In some embodiments, the second etching process includes an RIE etching process, in which fluorine ions and/or other ion species (ion specie) are directed to the optional dielectric liner layer 116 to be etched, the hard cover on the top of the fin Curtains 112 and 114, and semiconductor regions 108 and 110. Ions can remove material from these features from the impact force (sputter etching) and/or react with the material of the feature to produce compounds that are sensitive to subsequent wet or dry etchants. In one embodiment, the second etching process uses a fluorine-containing etchant, which includes carbon difluoride (CF ₂ ), difluoromethane (CH ₂ F ₂ ), fluorine gas (F ₂ ), sulfur hexafluoride (SF ₆ ) One or more of fluoromethane (CH _{3 F).} Exemplary etching conditions include an etching power of about 300W to 600W and an etching bias of about 400V to 600V. Additionally or alternatively, the etching process may include the use of oxygen-based etchant, fluorine-based etchant, chlorine-based etchant, bromine-based etchant, iodine-based etchant, other suitable etchant gases or plasma And/or a combination of wet etching, dry etching, other RIE processes, and/or other suitable etching techniques.

In addition to removing part of the fin 106 (for example: the fin 106b), the etching also cuts into the substrate 102 and creates depressions 302 therein (in some cases, this is called "heavier etching" because it is more Only the fins are removed and the etching is deeper), as shown in Figure 6 where a recess 302 is shown. The recess 302 is subsequently filled with dielectric material(s) to produce well isolation features (such as feature 404 in Figures 9 to 11), which reduces leakage between well regions (such as well regions 104A and 104B). Current. This provides many advantages. For example, reducing leakage current itself may be beneficial because reduced leakage improves efficiency and reduces heat. As another example, the well isolation feature 404 can prevent latch-up, where a conductive transistor causes the other transistor to conduct regardless of the gate voltage. As device spacing shrinks, latching may become more common. However, by reducing the current flow between the well regions, the well isolation feature 404 allows for tighter device spacing and reduces the occurrence of latch-up.

The depression 302 crosses the boundary of the well regions 104A and 104B. As shown in FIG. 6, the depression 302 extends from the boundary of the well regions 104A and 104B into the well region 104B at a distance W2', and extends from the boundary of the well regions 104A and 104B into the well region 104A at a distance W3'. In this embodiment, the distance W3' is greater than the distance W2'. In addition, the distance W2' is about 40% to 60% of the distance W1. Taking into account any differences caused by the etching process, the distance W2' and the distance W3' are approximately the same as the distance W2 and the distance W3, respectively.

The recess 302 may be etched to any suitable depth 304, and in an embodiment where the fin 106 extends between about 100 nm to about 500 nm above the top surface 102U of the substrate 102, the recess 302 may be below the top surface 102U of the substrate 102 Extending at least 25 nm, the top surface 102U is between the fins 106a and 106c and immediately adjacent to the recess 302. In some embodiments, the depth 304 is between about 25 nm and about 75 nm below the top surface 102U of the substrate 102. The depth 304 is designed so that the relatively heavily doped portions of the well regions 104A and 104B are removed from the recesses to greatly reduce leakage current through the well regions. As observed from real samples and simulated data, the dopants in the well region 104 (such as the well region 104A and the well region 104B) tend to be concentrated in the upper part of the well region, for example, from 25 nm to the top surface of the substrate 102. Within a thickness of 75nm. By removing this part of the well region and replacing it with a dielectric material (shown as feature 404 in Figures 8-11), the leakage current through the well region is greatly reduced. The portion of the well 104 below the recess 302 is lighterly doped and has a relatively higher resistance than the removed portion. Therefore, it will not cause any meaningful leakage current. In one embodiment, the recess 302 extends at least 40 nm below the top surface of the substrate 102 (ie, the depth 304 is 40 nm or greater) to ensure that the more heavily doped portions of the well regions 104A and 104B are removed. In various embodiments, the thickness of the substrate 102 is at least a few hundred nanometers or a few microns.

In various embodiments, operation 18 may use a timer and/or other methods to control the depth 304 of the etching. For example, operation 18 may monitor the etching residue to determine when the second etching process starts to etch the well region 104, and then control the etching depth 304 based on the etching time and the etching rate. The etching rate is affected by the type, density and/or flow rate of the etchant, etching power, etching bias, the material of the well region 104, and other factors. The etching rate can be determined based on experiments and/or past process data. In some embodiments, the above-mentioned first etching process and second etching process may be performed continuously or as one etching process (for example, performed in the same etching chamber).

The recess 302 may be etched to have a different profile. In the embodiment shown in Figure 6, the recess 302 has a substantially rectangular profile. This may be caused by a highly directional etching process. In another embodiment, the recess 302 may be etched to have a tapered profile, such as having a top opening that is wider than the bottom opening. Such an embodiment is shown in Figure 11, where the tapered profile of the well isolation feature 404 represents the profile of the depression 302. In this embodiment, the recess 302 (and the well isolation feature 404) have rounded corners (dome corners and/or rounded corners) produced by the etching process. In addition, in this embodiment, the top opening of the recess 302 is wider than the bottom opening. The tapered profile in the recess 302 makes it easier to fill the dielectric material without any voids, thereby increasing the reliability of the circuit.

1, in operation 20, the method 10 removes the hard mask layer 202 after etching the fin 106 and the well region 104. Operation 20 may use any suitable etching technique that is selective to the material in the hard mask layer 202 (for example, wet etching, dry etching, and RIE). The resulting semiconductor structure 100 is shown in FIG. 7, which is substantially the same as the semiconductor structure 100 shown in FIG. 3, but with the fin 106 and part of the well region 104 removed.

1, in operation 22, the method 10 forms isolation features 402 that specifically fill the recesses 302 over the semiconductor structure 100. Referring to FIG. 8, by depositing one or more dielectric materials (such as semiconductor oxide, semiconductor nitride, semiconductor carbide, fluorosilicate glass; FSG) between the fins 106 included in the recess 302 ), low-K dielectric materials and/or other suitable dielectric materials), forming isolation features 402 (such as Shallow Trench Isolation (STI) features) on the semiconductor structure 100. The portion of the isolation feature 402 within the recess 302 becomes the well isolation feature 404. The material of the isolation feature 402 may be formed by including CVD, PECVD, HDP-CVD, ALD, PEALD, FCVD, spin coating, and/or other suitable deposition techniques. In some embodiments, operation 22 may include a chemical mechanical polishing (CMP) process to planarize the top surface of the isolation feature 402. The hard mask 114 on the top of the fin can be used as an etch stop layer for the CMP process.

Referring to Figure 1, in operation 24, the method 10 recesses the isolation feature 402 (or etches back the isolation feature 402). In one embodiment, the isolation feature 402 is recessed to a level that is flush with the interface between the semiconductor region 110 and the semiconductor region 108, as shown in FIG. 9. Referring to FIG. 9, the fin 106 extends above the top surface of the isolation feature 402, and the well isolation feature 404 (which is a part of the isolation feature 402) extends into the substrate 102. The bottom surface of the well isolation feature 404 is below the top surface 102U of the substrate 102. Specifically, the well isolation feature 404 spans the boundary between the well regions 104A and 104B. The well isolation feature 404 extends from the boundary of the well regions 104A and 104B into the well region 104B at a distance W2', and extends from the boundary of the well regions 104A and 104B into the well region 104A at a distance W3'. In this embodiment, the distance W3' is greater than the distance W2'. In addition, the distance W2' is about 40% to 60% of the distance W1. The contour of the well isolation feature 404 substantially matches the contour of the depression 302. When the recess 302 has a substantially rectangular outline (for example, as shown in FIG. 6), the well isolation feature 404 also has a substantially rectangular outline (for example, as shown in FIG. 9). When the depression 302 has a tapered profile, the well isolation feature 404 also has a tapered profile, as shown in FIG. 11, where the top of the well isolation feature 404 is wider than the bottom of the well isolation feature 404. Furthermore, in some embodiments, the well isolation feature 404 may have rounded corners (dome corners and/or rounded bottom corners).

Figure 10 shows some of the benefits of the well isolation feature 404. Referring to FIG. 10, there is shown a PNPN structure having an example with a dotted line between the fins 106a and 106c. More specifically, the semiconductor region 110 of the fin 106a is P-type doped, the semiconductor region 108 and the well region 104A of the fin 106a are N-type doped, and the semiconductor region 108 and the well region 104B of the fin 106c are P Type doped and the semiconductor region 110 of the fin 106c are N type doped. If there is sufficient leakage between the well regions 104A and 104B (for example, as shown in the circuit diagram of FIG. 12), the PNPN structure can trigger the latch in the circuit. In this embodiment, since the tops of the well regions 104A and 104B are removed and replaced by the well isolation feature 404, the leakage current between the well regions 104A and 104B is greatly reduced, and the possibility of this PNPN structure triggering latch is also Significantly reduced. The inventors have observed that the leakage current is reduced by up to 2 orders of magnitude (ie, 100 times), and the latch trigger voltage (ie, the supply voltage at which latching occurs) is improved by up to 10%. In another embodiment, the types of dopants in the semiconductor region 110, the semiconductor region, and the well region 104 can be reversed to produce an NPNP structure. For example, the semiconductor region 110 of the fin 106a is N-type doped, the semiconductor region 108 and the well region 104A of the fin 106a are P-type doped, and the semiconductor region 108 and the well region 104B of the fin 106c are N-type. The doped and semiconductor regions 110 of the fin 106c are P-type doped. In this embodiment, the well isolation feature 404 also reduces the possibility of the NPNP structure triggering any latch-up in the circuit.

Referring to FIG. 1, in operation 26, the method 10 performs further processing on the semiconductor structure 100. For example, the semiconductor structure 100 may be processed to form active devices and passive devices thereon. In some embodiments, a transistor (for example, FinFET) is formed on the fin 106 by forming a pair of source/drain features separated by a channel. The source/drain features may include semiconductors (eg, silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.) and one or more dopants, such as P-type dopants or N-type dopants. Similarly, the channel region may include semiconductors and one or more dopants of the opposite type to those of the source/drain characteristics, or be undoped at all. In some embodiments, gate stacks are formed adjacent to and surrounding the channel region to control the flow of charge carriers through the channel region (electrons for N-channel FinFETs and holes for P-channel FinFETs). An Inter-Level Dielectric (ILD) layer may be formed on the semiconductor structure 100. The ILD layer serves as a conductive trace that supports and isolates an electrical multi-level interconnect structure that is electrically interconnected with elements of the semiconductor structure 100 (e.g., source/drain features and gate stacks). traces) insulator. The ILD layer may include dielectric materials (for example: semiconductor oxide, semiconductor nitride, semiconductor oxynitride, semiconductor carbide, etc.), spin on glass (SOG), FSG, phosphosilicate glass (phosphosilicate glass, etc.). ; PSG), borophosphosilicate glass (BPSG), BlackDiamond® (applied materials in Santa Clara, California), Xerogel, Aerogel, Amorphous Carbon Fluoride , Parylene (parylene), benzocyclobutene (Benzocyclobutene; BCB), SiLK® (The Dow Chemical Company of Midland, Michigan) and/or combinations thereof. The ILD layer can be formed by any suitable process including CVD, PVD, spin-on deposition, and/or other suitable processes.

FIG. 12 shows a layout diagram of a semiconductor device 100 including a 1-bit SRAM cell on the right, and a circuit diagram showing a part of the 1-bit SRAM cell on the left. Referring to FIG. 12, the semiconductor device (semiconductor structure) 100 includes fins 106 (including fins 106a to 106d, 106e' and 106f') oriented lengthwise along the "Y" direction, and the gate stack 500 is perpendicular to The "X" direction of the "Y" direction is longitudinally oriented. The line A-A in Figure 12 is the same as the line A-A in Figure 3. The cutting pattern 206 marks the area of the fin 106 and the well 104 to be etched (corresponding to the opening 206 in Figure 4). In this embodiment, the cutting pattern 206 extends from the edge of one gate stack 500 to the edge of the other gate stack 500. It is worth noting that the “cutting” process (ie, etching of the fin 106 and the well 104) is performed before forming the gate stack 500. Therefore, the “cutting” process will not damage the gate stack 500 formed later. In addition, since there is no source or drain on one side of the gate, the gate stack 500 on both sides of the cut pattern 206 in the PMOS region is not used as a gate, but can be used as a mutual gate in some embodiments. even. The fins 106e' and 106f' are individually equivalent to the fins 106e and 106f of FIGS. 2 to 11, but are placed on the left side of the fin 106a. The fins 106e and 106f in FIGS. 2 to 11 are part of the right side of the SRAM cell shown in FIG. 12, and are not shown in this drawing. The well isolation feature 404 occupies a space corresponding to the cut pattern 206 in the well region 104.

Although not limiting, one or more embodiments of the present disclosure provide many benefits for semiconductor devices and their formation. For example, the disclosed embodiments provide well isolation features in FinFET circuits, particularly FinFET SRAM cells. The well isolation feature reduces the leakage between two adjacent and oppositely doped well regions, thereby reducing the possibility of PNPN or NPNP structure triggering latch-up in the circuit.

In one embodiment, the present disclosure provides a method of manufacturing an integrated circuit device. The manufacturing method of an integrated circuit device includes receiving a semiconductor structure including a substrate. The substrate includes a first well region having a first dopant type and a second well region having a second dopant type, the second dopant type being opposite In the first dopant type; and a plurality of fins extending above the substrate. The manufacturing method of the integrated circuit device further includes forming a patterned etching mask on the semiconductor structure, wherein the patterned etching mask provides an opening directly above the first fin of the fin, wherein the first fin is in the first well region Directly above. The manufacturing method of the integrated circuit device further includes etching the semiconductor structure through the patterned etching mask, wherein the etching step removes the first fin and forms a recess in the substrate that spans from the first well region to the second well region; and A dielectric material is formed between the remaining portions of the fins and in the recesses.

In one embodiment, before the step of forming the patterned etching mask, the manufacturing method of the integrated circuit device further includes forming a dielectric liner above the substrate, the top of the fin and the plurality of sidewalls, wherein the opening is exposed and disposed in the first A dielectric liner on the top of the fin and above the sidewalls.

In the embodiment of the manufacturing method of the integrated circuit device, the second fin of the fin is directly above the second well region and is adjacent to the first fin along the width direction of the fin, and the opening is in the first fin The first part of the second well region between and the second fin is directly above. In another embodiment, the width of the first portion is 40% to 60% of the width of the second well region between the first fin and the second fin along the fin width direction.

In the embodiment of the method of manufacturing an integrated circuit device, the recesses extend from the upper surface of the substrate to at least 40 nm into the substrate. In another embodiment, during the step of etching the semiconductor structure, a timer is used to control the depth of the recess. In another embodiment, the first portion of the first well region and the second well region removed by the etching step is more heavily doped than the second portion of the first well region and the second well region remaining under the recess. miscellaneous.

In the embodiment of the method of manufacturing an integrated circuit device, the top of the recess is wider than the bottom of the recess. In another embodiment, the first dopant type is N-type, and the second dopant type is P-type. In another embodiment, the manufacturing method of the integrated circuit device further includes removing the patterned etching mask after the step of etching the semiconductor structure and before the step of forming the dielectric material.

In one embodiment, the present disclosure provides a method of manufacturing an integrated circuit device. The manufacturing method of the integrated circuit device includes receiving a semiconductor structure including a substrate, the substrate including an N-well region and a P-well region adjacent to the N-well region; and a plurality of fin structures extending above the substrate. The manufacturing method of the integrated circuit device further includes forming a dielectric liner above the upper surface of the substrate, the top of the fin structure and the plurality of sidewalls. The manufacturing method of the integrated circuit device further includes forming a patterned etching mask over the semiconductor structure, the patterned etching mask has an opening, wherein the first fin structure of the fin structure is erected in the opening, and the first fin structure is Right above the N well area. The manufacturing method of the integrated circuit device further includes etching the first fin structure and the substrate through the opening, wherein the etching step forms a recess in the substrate that crosses the boundary between the N-well region and the P-well region; and in the plurality of remaining fin structures A dielectric material is formed between the parts and in the recess.

In the embodiment of the manufacturing method of the integrated circuit device, the step of forming a patterned etching mask includes forming a filling layer above the dielectric liner and surrounding the fin structure; forming a photoresist layer on the filling layer; The resist layer is patterned to obtain a patterned photoresist layer; and the filling layer is etched through the patterned photoresist layer to provide openings.

In another embodiment of the method of manufacturing an integrated circuit device, each of the fin structures includes a semiconductor fin connected to the substrate and a hard mask on the top of the fin disposed above the semiconductor fin. In yet another embodiment, the opening is exposed at a portion of the dielectric liner directly above the P-well region.

In an embodiment of the method of manufacturing an integrated circuit device, the distance from the upper surface of the substrate to the bottom surface of the recess is at least 25 nm. In another embodiment, the recess has a tapered profile with the top of the recess wider than the bottom of the recess.

In one embodiment, the present disclosure provides an integrated circuit device. The integrated circuit device includes a substrate, including a first well region with a first doping type and a second well region with a second doping type, the second dopant type is different from the first dopant type; a plurality of fins , Extending from the substrate; a dielectric material disposed between the fins so that the fins extend above the top surface of the dielectric material; and a well isolation feature, including a portion of the dielectric material extending into the substrate, wherein the well isolation feature The bottom surface of the fin is below the top surface of the substrate extending between the well isolation feature and the first fin of the fin.

In an integrated circuit device embodiment, the bottom surface of the well isolation feature is at least 40 nm below the top surface of the substrate. In another embodiment, the well isolation feature has plural rounded bottom corners. In yet another embodiment, the well isolation feature is disposed above both the first well zone and the second well zone, and a larger portion of the well isolation feature is disposed above the first well zone instead of the second well zone.

The foregoing text outlines the features of many embodiments, so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the present disclosure, and achieve the same purpose and/or the same as the embodiments introduced herein. The advantages. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Without departing from the spirit and scope of the present disclosure, various changes, substitutions or modifications can be made to the present disclosure.

10: method 12~26: Operation 100: Semiconductor structure/semiconductor device 102: substrate 104A, 104B, 104C: Well area 106a, 106b, 106c, 106d, 106e, 106f: fins 108, 110: semiconductor area 112,114: Hard cover pattern on top of fins / Hard cover on top of fins 102U: upper surface 116: Dielectric liner 202: hard mask layer 204: photoresist layer 206: open W1, W2, W3: distance 302: Depression 304: Depth W2’,W3’: distance 402: Isolation Features 404: Well Isolation Features 500: gate stack 106e’,106f’: fins

This disclosure can be better understood from the subsequent embodiments and the accompanying drawings. Note that the schematic diagram is an example, and the different features are not shown here. The size of different features may be increased or decreased arbitrarily for clear discussion. FIG. 1 is a flowchart of the manufacturing method of the integrated circuit device according to the embodiment of the disclosure. Figures 2 and 3 are schematic diagrams of a workpiece according to an embodiment of the present disclosure. Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 are cross-sectional views of the workpiece according to an embodiment of the present disclosure, wherein the cross-sectional view is along the first 3 The AA line segment in the figure is intercepted. FIG. 12 is a schematic diagram and layout diagram of an integrated circuit according to an embodiment of the disclosure.

no

100: Semiconductor structure/semiconductor device

102: substrate

104A, 104B, 104C: Well area

106a, 106c, 106d, 106e, 106f: fins

108, 110: semiconductor area

112,114: Hard cover pattern on top of fins / Hard cover on top of fins

102U: upper surface

116: Dielectric liner

W1: distance

304: Depth

W2’,W3’: distance

402: Isolation Features

404: Well Isolation Features

Claims (9)

A method for manufacturing an integrated circuit device includes: receiving a semiconductor structure, the semiconductor structure includes: a substrate, including a first well region having a first dopant type and a second dopant type In the second well region, the second dopant type is opposite to the first dopant type; and a plurality of fins extending above the substrate; a patterned etching mask is formed on the semiconductor structure, wherein the patterning The etching mask provides an opening directly above a first fin of the fin, wherein the first fin is directly above the first well region; the semiconductor structure is etched through the patterned etching mask, wherein the etching Removing the first fin, and forming a depression in the substrate that spans from the first well region to the second well region, wherein a larger portion of the depression is disposed above the first well region, Instead of above the second well region; and forming a dielectric material between the plurality of remaining parts of the fins and in the recesses. The method for manufacturing an integrated circuit device according to claim 1, wherein a second fin of the fin is directly above the second well region and is adjacent to the first fin along a fin width direction, and The opening is directly above a first portion of the second well region between the first fin and the second fin. The method for manufacturing an integrated circuit device of claim 2, wherein the width of the first portion is the width of the second well region between the first fin and the second fin along the width direction of the fin 40% to 60%. The method of manufacturing an integrated circuit device of claim 1, wherein by the above-mentioned etching A first portion of the first well region and the second well region removed by the step is more heavily doped than a second portion of the first well region and the second well region remaining under the recess. The method for manufacturing an integrated circuit device according to claim 1, wherein a top of the recess is wider than a bottom of the recess. A method for manufacturing an integrated circuit device includes: receiving a semiconductor structure, the semiconductor structure comprising: a substrate including an N-well region and a P-well region adjacent to the N-well region; and a plurality of fin structures, in the above-mentioned Extending above the substrate; forming a dielectric spacer above the upper surface of the substrate and a top of the fin structure and above the plurality of side walls; forming a patterned etching mask above the semiconductor structure, the patterned etching mask having An opening, wherein a first fin structure of the fin structure stands in the opening, wherein the first fin structure is directly above the N-well region; the first fin structure and the substrate are etched through the opening, Wherein, the etching step forms a recess in the substrate that crosses a boundary between the N-well region and the P-well region, wherein a larger portion of the recess is disposed above the N-well region instead of the P-well region Above; and a dielectric material is formed between the plurality of remaining parts of the fin structure and the recess. The method for manufacturing an integrated circuit device according to claim 6, wherein the step of forming the patterned etching mask includes: forming a filling layer above the dielectric spacer, and the filling layer surrounds the fin structure; Forming a photoresist layer on the filling layer; patterning the photoresist layer to obtain a patterned photoresist layer; and The filling layer is etched through the patterned photoresist layer to provide the opening. The method for manufacturing an integrated circuit device according to claim 6, wherein each of the fin structures includes a semiconductor fin connected to the substrate and a fin top hard mask disposed above the semiconductor fin. An integrated circuit device includes: a substrate, including a first well region with a first doping type and a second well region with a second doping type, the second dopant type and the first well region A different type of dopant; a plurality of fins extending from the substrate; a dielectric material disposed between the fins such that the fins extend above a top surface of the dielectric material; and a well isolation feature , Including a portion of the dielectric material extending into the substrate, wherein a bottom surface of the well isolation feature is below a top surface of the substrate extending between the well isolation feature and a first fin of the fin , Wherein the well isolation feature is arranged above both the first well zone and the second well zone, and a larger part of the well isolation feature is arranged above the first well zone instead of the second well zone Above.

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