TWI728556B - 神經元電路及類神經網路晶片 - Google Patents
神經元電路及類神經網路晶片 Download PDFInfo
- Publication number
- TWI728556B TWI728556B TW108141732A TW108141732A TWI728556B TW I728556 B TWI728556 B TW I728556B TW 108141732 A TW108141732 A TW 108141732A TW 108141732 A TW108141732 A TW 108141732A TW I728556 B TWI728556 B TW I728556B
- Authority
- TW
- Taiwan
- Prior art keywords
- memristor
- input
- pulse train
- neuron
- neuron circuit
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0061—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0045—Read using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0078—Write using current through the cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
- G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Molecular Biology (AREA)
- General Health & Medical Sciences (AREA)
- Biophysics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Neurology (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
Abstract
一種神經元電路及類神經網路晶片。神經元電路包括憶阻器與積分器。其中,憶阻器在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。積分器並聯於憶阻器,用以接收並累積由前層網路在不同時間發送的輸入脈衝,並在所累積的輸入脈衝的電壓超過預定閾值時,驅動憶阻器發送脈衝串至下一層網路。
Description
本揭露是有關於一種人工智慧技術,且特別是有關於一種神經元電路及類神經網路晶片。
深度學習的硬體加速被視為未來泛人工智慧(Artificial Intelligence,AI)的基礎,涵括多域、多模及分散式人工智慧。超越當代的各種數位AI加速器,使用大量平行交叉(parallel crossbar)架構的非揮發性記憶體來加速深度學習演算法中的矩陣乘法運算的類神經網路(Artificial Neural Network,ANN),因為能夠克服范鈕曼(von Neumann)的資料傳輸效能瓶頸,而受到高度重視。
大部分的類神經網路研究專注在運算用高密度突觸(synapses)的實現,但近年的研究發現,用來支持類神經網路運算的必要週邊輸入/輸出(I/O)電路,對比於生物學的整合與發送(Integrate-and-Fire,I&F),事實上比交叉陣列花費更多的面積及能量。整合與發送神經元通常是使用複雜的數位類比轉換器/類比數位轉換器(DAC/ADC)電路來實現,近年來提出許多基於相變化隨機存取記憶體/相變化記憶體(PRAM/PCM)、閾值開關(Threshold-switch,TS)裝置、自旋軌道矩(spin-orbit-torque,SOT)磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory,MRAM)等架構的高密度神經元電路。然而,其優點因為需要額外的重置電路及/或大尺寸電容器而受限。
本揭露提供一種神經元電路,其包括憶阻器與積分器。其中,憶阻器在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。積分器並聯於憶阻器,用以接收並累積由前層網路在不同時間發送的輸入脈衝,並在所累積的輸入脈衝的電壓超過預定閾值時,驅動憶阻器發送脈衝串至下一層網路。
本揭露提供一種神經元電路,其包括憶阻器與電流電壓轉換器。其中,憶阻器在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。電流電壓轉換器,並聯於憶阻器,用以接收由前層網路發送的輸入脈衝,並在輸入脈衝的電壓超過預定閾值時,驅動憶阻器發送脈衝串至下一層網路。
本揭露提供一種類神經網路晶片,其包括突觸陣列、多個神經元電路及控制電路。其中,突觸陣列包括分別連接多個輸入端與多個輸出端的n*m個突觸元件,其中位於同一列的突觸元件連接相同的輸入端,位於同一行的突觸元件連接相同的輸出端,n與m為正整數。各個神經元電路的輸入端連接所述輸出端其中之一。控制電路分別連接輸入端與神經元電路的輸出端,調整各個突觸元件的權重值,並監測各個神經元電路所發送的脈衝串。各個神經元電路包括憶阻器及積分器。其中,憶阻器在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。積分器並聯於憶阻器,用以接收並累積由前層網路經由輸入端輸入並經過突觸元件的輸入脈衝,並在所累積的輸入脈衝的電壓超過預定閾值時,驅動憶阻器發送脈衝串至下一層網路。
為讓本揭露的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
本揭露實施例提出一種類神經網路晶片內神經元電路的設計方式,其運用憶阻器在特定操作條件下,會隨著操作能量發射出不同頻率脈衝波的特性,來製作神經元電路,可大幅減少傳統以互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor,CMOS)設計的神經元電路的面積,進而提升神經元的密度,再搭配運用憶阻器的突觸架構,可完成高密度運算核心的類神經網路晶片。
圖1是依據本揭露的一神經系統的架構。請參照圖1,神經系統10提供動物能夠對刺激產生動作或反應,其仰賴多個神經元傳遞訊號。神經元和神經元的相接處稱為突觸,神經訊號的流向是從突觸前神經元 (presynaptic neuron)12到突觸後神經元(postsynaptic neuron)14,突觸142通常形成在突觸前神經元12的軸突(axon)122和突觸後神經元14的樹突(dendrite)144之間,而用以作為突觸後神經元14接收神經信號的輸入渠道。
仿生晶片(即,後述的類神經網路晶片)即依據上述神經系統10的架構來設計,其通常包括突觸電路與神經元電路兩部分。圖2是依據本揭露一實施例所繪示的類神經網路晶片的訊號傳遞的示意圖。如圖2所示,突觸電路主要用來調節兩層網路間訊息傳遞的強度,其架構通常為憶阻器的交叉陣列結構,而神經元電路則是用來收集前層網路的訊息並決定是否傳送訊息至下一層網路。在一實施例中,神經元電路可利用積分電路來累積來自前層網路在不同時序下的脈衝電壓
V
1 ~
V
3 ,當累積電壓
V
mem 超過預定閾值
V
th 時,神經元電路可激發並產生輸出的脈衝串
V
spike ,該脈衝串
V
spike 將被傳遞到下一層網路。
圖3是依據本揭露一實施例所繪示的類神經網路晶片的架構圖。請參照圖3,本實施例的類神經網路晶片30包括突觸陣列32、多個神經元電路34及控制電路36。
突觸陣列32包括分別連接多個輸入端與多個輸出端的n*m個突觸元件(memory cell)322,其中位於同一列的突觸元件322連接相同的輸入端,位於同一行的突觸元件322連接相同的輸出端,n與m為正整數。
各個神經元電路34的輸入端連接突觸陣列32的輸出端其中之一,控制電路36則分別連接突觸陣列32的輸入端與神經元電路34的輸出端。其中,控制電路36例如是中央處理單元(Central Processing Unit,CPU),或是其他可程式化之一般用途或特殊用途的微處理器(Microprocessor)、數位訊號處理器(Digital Signal Processor,DSP)、可程式化控制器、特殊應用積體電路(Application Specific Integrated Circuits,ASIC)或其他類似裝置或這些裝置的組合,而可用以調整各個突觸元件322的權重值,並監測各個神經元電路34所發送的脈衝串。
各個神經元電路34包括憶阻器342及積分器344。其中,憶阻器342在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。積分器344並聯於憶阻器342,用以接收並累積由前層網路經由突觸陣列32的輸入端輸入並經過突觸元件322的輸入脈衝,並在所累積的輸入脈衝的電壓超過預定閾值時,驅動憶阻器342發送脈衝串至下一層網路。
在本實施例中,突觸陣列32中的突觸元件322是使用磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory,MRAM)的憶阻器為例,但並不限於此。任何可產生類似特性的憶阻器,包括可變電阻式記憶體(Resistive random-access memory,RRAM)、相變化記憶體(Phase-change memory,PCM)等憶阻器,皆為本揭露包含之範圍。
以磁阻式記憶體為例,圖4A及圖4B是依據本揭露一實施例所繪示的磁阻式記憶體的穿透式電子顯微鏡(Transmission electron microscope,TEM)影像及結構圖。由磁阻式記憶體40的結構圖40a可知,本實施例的磁阻式記憶體40為具有雙氧化鎂/鈷鐵硼(MgO/CoFeB)界面及鈷/鉑(Co/Pt)多層合成反鐵磁(synthetic antiferromagnetic,SAF)固定層(pinned layer)及自由層(free layer)的垂直式磁性穿隧接面(pMTJ)。
需說明的是,磁阻式記憶體在反向跳躍(Back Hopping,BH)的狀態下,由於類場轉矩(Field-like torque)與自旋轉移矩(Spin-transfer torque,STT)相互競爭,所以會發生電阻轉換振盪的情況。
詳言之,本揭露一實施例提出一種基於自旋轉移矩磁阻式隨機存取記憶體(STT-MRAM)技術的新型高密度類比整合與發送(Integrate-and-Fire,I&F)神經元。所述神經元利用磁性穿隧接面(magnetic tunnel junctions,MTJ)的反向跳躍(BH)振盪機制來實施單一裝置的當前整合、電壓突波(spike)產生、狀態重置,可顯露令人印象深刻的4位元解析度。此不需要額外重置電路的無電容器設計可確保密度的最大化。此外,相同的元件也可用以作為不同偏壓(bias regimes)下的隨機二元突觸。本揭露一實施例提出的全旋轉式類神經網路可以內嵌的STT-MRAM的標準整合流程來實現。
反向跳躍是描述STT-MRAM程式化(特別是高偏壓)時的異常轉回(switching back)現象,此現象因為會阻止確定性的STT切換,而使得程式化效益下降,通常不樂見於記憶體操作。然而,反向跳躍振盪卻是實現整合與發送(I&F)神經元的有用機制。儘管切換主要是由自旋轉移矩(STT)決定,研究顯示類場轉矩(Field-like torque)對能量障壁(energy barrier,EB)的重要性及對非對稱MTJ的切換動力學的重要性。
圖5是依據本揭露一實施例所繪示之磁阻式記憶體在反向跳躍狀況下的電阻振盪的示意圖。請參照圖5,(a)-(c)分別繪示不具有反向跳躍特性的標準MJI(S1)在相同偏壓下的二元電導變化,(d)-(f)分別繪示具有反向跳躍特性的定制MJI(S2)在相同偏壓下的二元電導變化。對比於S1在固定偏壓施加下始終顯示穩定的反平行(antiparallel,AP)到平行(parallel,P)切換,S2則在AP和P狀態之間隨機振盪,且在某個閾值電流之上顯示出興趣突波(spike)。其中,S2的振盪頻率與操作能量有關,且隨著能量變高,振盪頻率變大,突波數目也增加,如圖6所示。
本揭露實施例即運用磁阻式記憶體在反向跳躍下的操作特性,在需累積與時間相關的前層網路的輸入脈衝電壓的仿生晶片裡,採用如圖7A所示的神經元電路架構,來取代傳統神經元電路的重置與閥值判斷電路,或是在僅需累積當下前層網路的輸入脈衝電壓的類神經網路晶片中,採用如圖7B所示的神經元電路架構,用以做為啟動(activation)功能使用。
詳言之,圖7A及圖7B是依據本揭露一實施例所繪示之神經元電路的電路圖。圖7A的神經元電路72包括憶阻器722與積分器724。其中,憶阻器722例如是磁阻式隨機存取記憶體、可變電阻式記憶體或相變化記憶體,積分器724例如是以運算放大器OP結合電容C及電阻(未繪示)來實現,但不限於此。憶阻器722在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。積分器724並聯於憶阻器722,用以接收並累積由前層網路在不同時間發送的輸入脈衝,並在所累積的輸入脈衝的電壓超過預定閾值時,驅動憶阻器722發送脈衝串至下一層網路。
圖7B的神經元電路74包括憶阻器742與電流電壓轉換器744。其中,憶阻器742例如是磁阻式隨機存取記憶體、可變電阻式記憶體或相變化記憶體,電流電壓轉換器744例如是由運算放大器結合電阻(未繪示)來實現,但不限於此。憶阻器742在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串。電流電壓轉換器744則並聯於憶阻器742,用以接收由前層網路發送的輸入脈衝,並在輸入脈衝的電壓超過預定閾值時,驅動憶阻器742發送脈衝串至下一層網路。
綜上所述,本揭露的神經元電路及類神經網路晶片,藉由憶阻器獨特的電流驅動反向跳躍(BH)振盪,無需額外配置電容器或重置電路,可確保神經元密度的最大化。且藉由自旋轉移矩磁阻式隨機存取記憶體(STT- MRAM)技術,可證明基於高密度全旋轉類神經網路(ANN)、類比整合與發送(I&F)神經元及隨機二進制突觸進行深度學習加速的可行性。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10:神經系統
12:突觸前神經元
122:軸突
14:突觸後神經元
142:突觸
144:樹突
30:類神經網路晶片
32:突觸陣列
322:突觸元件
34、72、74:神經元電路
342、722、742:憶阻器
344、724:積分器
36:控制電路
40:磁阻式記憶體
40a:結構圖
744:電流電壓轉換器
C:電容
OP:運算放大器
V
1 ~
V
3 :脈衝電壓
V
mem :累積電壓
V
spike :脈衝串
圖1是依據本揭露一神經系統的架構。
圖2是依據本揭露一實施例所繪示的類神經網路晶片的訊號傳遞的示意圖。
圖3是依據本揭露一實施例所繪示的類神經網路晶片的架構圖。
圖4A及圖4B是依據本揭露一實施例所繪示的磁阻式記憶體的穿透式電子顯微鏡影像及結構圖。
圖5是依據本揭露一實施例所繪示之磁阻式記憶體在反向跳躍狀況下的電阻振盪的示意圖。
圖6是依據本揭露一實施例所繪示之磁阻式記憶體的振盪頻率與操作能量的關係圖。
圖7A及圖7B是依據本揭露一實施例所繪示之神經元電路的電路圖。
30:類神經網路晶片
32:突觸陣列
322:突觸元件
34:神經元電路
342:憶阻器
344:積分器
36:控制電路
Claims (7)
- 一種神經元電路,包括:憶阻器,在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串;以及積分器,並聯於所述憶阻器,接收並累積由前層網路在不同時間發送的輸入脈衝,並在所累積的所述輸入脈衝的電壓超過所述預定閾值時,驅動所述憶阻器發送所述脈衝串至下一層網路。
- 如申請專利範圍第1項所述的神經元電路,其中所述脈衝串的頻率與所述憶阻器的操作能量有關。
- 如申請專利範圍第1項所述的神經元電路,其中所述憶阻器包括磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory,MRAM)、可變電阻式記憶體(Resistive random-access memory,RRAM)或相變化記憶體(Phase-change memory,PCM)。
- 一種類神經網路晶片,包括:突觸陣列,包括分別連接多個輸入端與多個輸出端的n*m個突觸元件,其中位於同一列的所述突觸元件連接相同的所述輸入端,位於同一行的所述突觸元件連接相同的所述輸出端,n與m為正整數;多個神經元電路,各所述神經元電路的輸入端連接所述輸出端其中之一;以及 控制電路,分別連接所述輸入端與所述神經元電路的輸出端,調整各所述突觸元件的權重值,並監測各所述神經元電路所發送的脈衝串,其中各所述神經元電路包括:憶阻器,在施加的電壓超過預定閾值時,產生具有一振盪頻率的脈衝串;以及積分器,並聯於所述憶阻器,接收並累積由前層網路經由所述輸入端輸入並經過所述突觸元件的輸入脈衝,並在所累積的所述輸入脈衝的電壓超過所述預定閾值時,驅動所述憶阻器發送所述脈衝串至下一層網路。
- 如申請專利範圍第4項所述的類神經網路晶片,其中所述積分器包括以電流電壓轉換器實現,並在由所述前層網路經由所述輸入端輸入並經過所述突觸元件的輸入脈衝的電壓超過所述預定閾值時,驅動所述憶阻器發送所述脈衝串至所述下一層網路。
- 如申請專利範圍第4項所述的類神經網路晶片,其中所述突觸元件是以憶阻器實現。
- 如申請專利範圍第4項所述的類神經網路晶片,其中所述憶阻器包括磁阻式隨機存取記憶體、可變電阻式記憶體或相變化記憶體。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108141732A TWI728556B (zh) | 2019-11-18 | 2019-11-18 | 神經元電路及類神經網路晶片 |
US16/809,522 US11625588B2 (en) | 2019-11-18 | 2020-03-04 | Neuron circuit and artificial neural network chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW108141732A TWI728556B (zh) | 2019-11-18 | 2019-11-18 | 神經元電路及類神經網路晶片 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI728556B true TWI728556B (zh) | 2021-05-21 |
TW202121258A TW202121258A (zh) | 2021-06-01 |
Family
ID=75908224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108141732A TWI728556B (zh) | 2019-11-18 | 2019-11-18 | 神經元電路及類神經網路晶片 |
Country Status (2)
Country | Link |
---|---|
US (1) | US11625588B2 (zh) |
TW (1) | TWI728556B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI803234B (zh) * | 2022-03-09 | 2023-05-21 | 國立清華大學 | 類神經網路系統、高效率內嵌式人工突觸元件及其操作方法 |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11361215B2 (en) * | 2017-11-29 | 2022-06-14 | Anaflash Inc. | Neural network circuits having non-volatile synapse arrays |
US20210097379A1 (en) * | 2019-09-26 | 2021-04-01 | Qatar Foundation For Education, Science And Community Development | Circuit for calculating weight adjustments of an artificial neural network, and a module implementing a long short-term artificial neural network |
US11887647B2 (en) | 2020-04-09 | 2024-01-30 | Micron Technology, Inc. | Deep learning accelerator and random access memory with separate memory access connections |
US11726784B2 (en) | 2020-04-09 | 2023-08-15 | Micron Technology, Inc. | Patient monitoring using edge servers having deep learning accelerator and random access memory |
US11461651B2 (en) * | 2020-04-09 | 2022-10-04 | Micron Technology, Inc. | System on a chip with deep learning accelerator and random access memory |
US11355175B2 (en) | 2020-04-09 | 2022-06-07 | Micron Technology, Inc. | Deep learning accelerator and random access memory with a camera interface |
US11874897B2 (en) | 2020-04-09 | 2024-01-16 | Micron Technology, Inc. | Integrated circuit device with deep learning accelerator and random access memory |
US11200948B1 (en) * | 2020-08-27 | 2021-12-14 | Hewlett Packard Enterprise Development Lp | System for a flexible conductance crossbar |
US11715517B2 (en) * | 2021-08-06 | 2023-08-01 | International Business Machines Corporation | Linear phase change memory |
US11894029B1 (en) | 2022-10-27 | 2024-02-06 | Globalfoundries Singapore Pte. Ltd. | Spiking neural network hardware based on magnetic-tunnel-junction layer stacks |
CN116523011B (zh) * | 2023-07-03 | 2023-09-15 | 中国人民解放军国防科技大学 | 基于忆阻的二值神经网络层电路及二值神经网络训练方法 |
CN117692003B (zh) * | 2023-12-11 | 2024-05-28 | 广东工业大学 | 一种基于神经元的模数转换器 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8332340B2 (en) * | 2007-12-05 | 2012-12-11 | Hewlett-Packard Development Company, L.P. | Hybrid microscale-nanoscale neuromorphic integrated circuit |
CN104916312A (zh) * | 2015-06-03 | 2015-09-16 | 华中科技大学 | 一种基于运算放大器的忆阻器编程电路及其操作方法 |
TWI584207B (zh) * | 2012-11-20 | 2017-05-21 | 高通公司 | 用於分段線性神經元建模的方法、裝置與電腦程式產品 |
CN107615307A (zh) * | 2015-06-29 | 2018-01-19 | 国际商业机器公司 | 神经形态处理设备 |
CN110383301A (zh) * | 2017-03-08 | 2019-10-25 | 阿姆有限公司 | 尖峰神经网络 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6501146B2 (ja) | 2014-03-18 | 2019-04-17 | パナソニックIpマネジメント株式会社 | ニューラルネットワーク回路およびその学習方法 |
US20150372805A1 (en) | 2014-06-23 | 2015-12-24 | Qualcomm Incorporated | Asynchronous pulse modulation for threshold-based signal coding |
US9990580B2 (en) | 2015-03-13 | 2018-06-05 | International Business Machines Corporation | Neuromorphic synapses |
US10268949B2 (en) * | 2016-03-21 | 2019-04-23 | International Business Machines Corporation | Artificial neuron apparatus |
CN109063833B (zh) | 2018-10-29 | 2023-09-08 | 南京邮电大学 | 一种基于忆阻器阵列的神经网络突触觉结构 |
-
2019
- 2019-11-18 TW TW108141732A patent/TWI728556B/zh active
-
2020
- 2020-03-04 US US16/809,522 patent/US11625588B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8332340B2 (en) * | 2007-12-05 | 2012-12-11 | Hewlett-Packard Development Company, L.P. | Hybrid microscale-nanoscale neuromorphic integrated circuit |
TWI584207B (zh) * | 2012-11-20 | 2017-05-21 | 高通公司 | 用於分段線性神經元建模的方法、裝置與電腦程式產品 |
CN104916312A (zh) * | 2015-06-03 | 2015-09-16 | 华中科技大学 | 一种基于运算放大器的忆阻器编程电路及其操作方法 |
CN107615307A (zh) * | 2015-06-29 | 2018-01-19 | 国际商业机器公司 | 神经形态处理设备 |
CN110383301A (zh) * | 2017-03-08 | 2019-10-25 | 阿姆有限公司 | 尖峰神经网络 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI803234B (zh) * | 2022-03-09 | 2023-05-21 | 國立清華大學 | 類神經網路系統、高效率內嵌式人工突觸元件及其操作方法 |
Also Published As
Publication number | Publication date |
---|---|
US20210150317A1 (en) | 2021-05-20 |
US11625588B2 (en) | 2023-04-11 |
TW202121258A (zh) | 2021-06-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI728556B (zh) | 神經元電路及類神經網路晶片 | |
Burr et al. | Neuromorphic computing using non-volatile memory | |
Rajendran et al. | Neuromorphic computing based on emerging memory technologies | |
Kuzum et al. | Low-energy robust neuromorphic computation using synaptic devices | |
Yu et al. | An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation | |
US11157803B2 (en) | Neuromorphic device including a synapse having a variable resistor and a transistor connected in parallel with each other | |
Chen et al. | Essential characteristics of memristors for neuromorphic computing | |
US10790016B2 (en) | Probabilistic neuron circuits | |
CN107194462A (zh) | 三值神经网络突触阵列及利用其的神经形态计算网络 | |
US10679121B2 (en) | Synapse and a neuromorphic device including the same | |
US10332000B2 (en) | Synapse and neuromorphic device including the same | |
Yu et al. | Design considerations of synaptic device for neuromorphic computing | |
Kim et al. | Double MgO-based perpendicular magnetic tunnel junction for artificial neuron | |
Zhang et al. | Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning | |
Wang et al. | Memristor‐Based Biologically Plausible Memory Based on Discrete and Continuous Attractor Networks for Neuromorphic Systems | |
US11210581B2 (en) | Synapse and a synapse array | |
Zhou et al. | The characteristics of binary spike-time-dependent plasticity in HfO 2-based RRAM and applications for pattern recognition | |
Garbin et al. | Probabilistic neuromorphic system using binary phase-change memory (PCM) synapses: Detailed power consumption analysis | |
Suri et al. | Addition of HfO2 interface layer for improved synaptic performance of phase change memory (PCM) devices | |
Yu | Orientation classification by a winner-take-all network with oxide RRAM based synaptic devices | |
Milo et al. | Resistive switching synapses for unsupervised learning in feed-forward and recurrent neural networks | |
Ismael Salinas et al. | Spintronic materials and devices towards an artificial neural network: accomplishments and the last mile | |
Kavehei et al. | Highly scalable neuromorphic hardware with 1-bit stochastic nano-synapses | |
Zhang et al. | Configurable neural phase shifter with spike-timing-dependent plasticity | |
Ielmini et al. | Neuromorphic computing with hybrid memristive/CMOS synapses for real-time learning |