TWI728318B - System in package structure - Google Patents
System in package structure Download PDFInfo
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- TWI728318B TWI728318B TW108106828A TW108106828A TWI728318B TW I728318 B TWI728318 B TW I728318B TW 108106828 A TW108106828 A TW 108106828A TW 108106828 A TW108106828 A TW 108106828A TW I728318 B TWI728318 B TW I728318B
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Abstract
Description
本發明係關於一種封裝結構,尤指一種系統級封裝結構。 The present invention relates to a packaging structure, in particular to a system-in-a-package structure.
系統級封裝,係透過將多個晶片及電子元件整合於單一封裝結構中,而使該單一封裝結構可提供一系統的功能,以因應目前對於高效能元件的需求。請參閱圖6所示,在現有技術的系統級封裝結構50,針對其內部體積較大的電子元件51(例如電感),連接墊52與導線架53之間需要較大量的內部錫膏54,才能透過回焊(reflow)製程而將體積較大的電子元件51加以固定。
The system-in-package is to integrate multiple chips and electronic components into a single package structure, so that the single package structure can provide a system function to meet the current demand for high-performance components. As shown in FIG. 6, in the prior art system-in-
當欲將現有技術的系統級封裝結構50設置於相應的電路結構上時,需於導線架53外露的接點55處塗布外部錫膏後再進行回焊製程,其中在進行回焊製程時,係透過控制加溫來熔融外部錫膏以達到接合效果。然而,當進行回焊製程時,加溫不只使得外部錫膏熔融,也同樣會使得內部錫膏54熔融。由於內部錫膏54的量較多,熔融後容易由封裝材56與導線架53之間溢出,而導致現有技術的系統級封裝結構50失效。
When the prior art system-in-
有鑑於此,本發明係改良現有技術的系統級封裝結構,以避免內部錫膏在後續的回焊製程中溢出封裝材外。 In view of this, the present invention improves the prior art system-in-package structure to prevent the internal solder paste from overflowing out of the packaging material during the subsequent reflow process.
為達到上述之發明目的,本發明係提供一種系統級封裝結構,其中包括:至少一功能晶片及數個電子元件,各電子元件包含有一本體及數個連接墊,該連接墊設置於該本體之底側;一導線架,所述之功能晶片及電子元件設置於該導線架之第一表面並與導線架形成電連接,所述電子元件之連接墊透過錫膏設置於該導線架之第一表面而與導線架形成電連接,該導線架之第二表面設有數個外部接點,該導線架之第一表面設有至少一阻隔單元,各阻隔單元包含有至少一子阻隔單元,所述子阻隔單元圍繞於相對應之電子元件的至少其中一連接墊之周圍,以將所述連接墊圍繞於其中;以及一封裝材,其覆蓋於所述功能晶片、電子元件、及導線架之第一表面上。 In order to achieve the above-mentioned object of the invention, the present invention provides a system-in-package structure, which includes: at least one functional chip and a plurality of electronic components, each electronic component includes a body and a plurality of connection pads, the connection pads are arranged on the body Bottom side; a lead frame, the functional chip and electronic components are arranged on the first surface of the lead frame and form an electrical connection with the lead frame, and the connection pads of the electronic components are arranged on the first of the lead frame through solder paste The second surface of the lead frame is provided with a plurality of external contacts, the first surface of the lead frame is provided with at least one blocking unit, and each blocking unit includes at least one sub-blocking unit. The sub-blocking unit surrounds at least one of the connection pads of the corresponding electronic component, so as to surround the connection pad therein; and a packaging material which covers the functional chip, the electronic component, and the first part of the lead frame On the surface.
本發明的優點在於,當封裝後的系統級封裝結構在後續的回焊製程中遭遇溫度升高,而使得內部的錫膏熔融時,藉由阻隔單元的設置而抵擋熔融的錫膏溢出封裝材外,以維持系統級封裝結構的完整性,進而避免其失效。 The advantage of the present invention is that when the packaged system-in-package structure encounters an increase in temperature during the subsequent reflow process, which causes the internal solder paste to melt, the arrangement of the barrier unit prevents the molten solder paste from overflowing the packaging material. In addition, in order to maintain the integrity of the system-in-package structure, thereby avoiding its failure.
10:系統級封裝結構 10: System-in-package structure
20:電子元件 20: Electronic components
21:本體 21: body
22:連接墊 22: Connection pad
23:錫膏 23: Solder paste
30:導線架 30: Lead frame
31、31A、31B:阻隔單元 31, 31A, 31B: barrier unit
311、311A、311B:子阻隔單元 311, 311A, 311B: Sub-blocking unit
32:外部接點 32: External contact
40:封裝材 40: Packaging material
50:系統級封裝結構 50: System-in-package structure
51:電子元件 51: electronic components
52:連接墊 52: connection pad
53:導線架 53: Lead frame
54:內部錫膏 54: Internal solder paste
55:接點 55: Contact
56:封裝材 56: Packaging material
圖1為本發明之第一實施例的部份結構側視剖面示意圖。 FIG. 1 is a schematic side sectional view of a part of the structure of the first embodiment of the present invention.
圖2為本發明之第一實施例的導線架部份結構上視圖。 Fig. 2 is a top view of a part of the structure of the lead frame of the first embodiment of the present invention.
圖3為本發明之第二實施例的導線架部份結構上視圖。 3 is a top view of a part of the structure of the lead frame of the second embodiment of the present invention.
圖4為本發明之第三實施例的部份結構側視剖面示意圖。 4 is a schematic side sectional view of part of the structure of the third embodiment of the present invention.
圖5為本發明之第三實施例的導線架部份結構上視圖。 Fig. 5 is a top view of a part of the structure of the lead frame of the third embodiment of the present invention.
圖6為現有技術的部份結構側視剖面示意圖。 Fig. 6 is a schematic side sectional view of a part of the structure of the prior art.
以下配合圖式及本發明之實施例,進一步闡述本發明為達成預定發明目的所採取的技術手段,其中圖式僅為了說明目的而已被簡化,並通過描述本發明的元件和組件之間的關係來說明本發明的結構或方法發明,因此,圖中所示的元件不以實際數量、實際形狀、實際尺寸以及實際比例呈現,尺寸或尺寸比例已被放大或簡化,藉此提供更好的說明,已選擇性地設計和配置實際數量、實際形狀或實際尺寸比例,而詳細的元件佈局可能更複雜。 The following figures and embodiments of the present invention are used to further explain the technical means adopted by the present invention to achieve the intended purpose of the invention. The figures are simplified for illustrative purposes only and describe the relationship between the elements and components of the present invention. To illustrate the structure or method of the present invention, therefore, the elements shown in the figure are not presented in actual numbers, actual shapes, actual sizes, and actual ratios. The sizes or size ratios have been enlarged or simplified to provide a better description. , The actual number, actual shape or actual size ratio has been selectively designed and configured, and the detailed component layout may be more complicated.
請參閱圖1所示,本發明之系統級封裝結構10包含有至少一功能晶片(圖中未示)、數個電子元件20、一導線架30及一封裝材40。
Please refer to FIG. 1, the system-in-
前述之功能晶片及電子元件20係設置於導線架30之第一表面上並與導線架30形成電連接,各電子元件20包含有一本體21及數個連接墊22,連接墊22設置於本體21之底側。各電子元件20之連接墊22透過錫膏23設置於導線架30之第一表面上並與導線架30形成電連接。一般而言,功能晶片及電子元件20可依照系統級封裝結構10所欲提供的功能而加以設置,例如數位處理晶片、記憶體晶片、天線、被動元件等,但不以此為限。
The aforementioned functional chip and
前述之導線架30之第一表面設有至少一阻隔單元31,各阻隔單元31設置於其中一電子元件20的連接墊22之側,導線架30之第二表面設有數個外部接點32,用以與外部電路形成電連接。前述之封裝材40覆蓋於所述功能晶片、電子元件20、及導線架30之第一表面上,以保護所述功能晶片、電子元件20及導線架30之第一表面不受外部的侵襲而損壞。
The first surface of the
因此,當本發明之系統級封裝結構10設置於相應的電路結構上時,於導線架30的外部接點32處塗布外部錫膏後再進行回焊製程時,倘若加溫而使得系統級封裝結構10內的錫膏23熔融,溢出的錫膏23受到阻隔單元31的阻
擋而不由導線架30與封裝材40之間溢出,以維持系統級封裝結構10的完整性,進而避免其失效。
Therefore, when the system-in-
在一實施例中(如圖2所示),各阻隔單元31包含有數個子阻隔單元311,各子阻隔單元311間隔設置於相對應之電子元件20的其中一連接墊22之周圍,以將該連接墊22圍繞於其中,則當該連接墊22相對應的錫膏23熔融而溢出時,將受到該子阻隔單元311的阻擋而防止進一步溢出封裝材40外。在另一實施例中(如圖3所示),各阻隔單元31A包含有一子阻隔單元311A,該子阻隔單元311A呈連續封閉狀圍繞於相對應電子元件20的其中一連接墊22之周圍,以將該連接墊22圍繞於其中,則當該連接墊22相對應的錫膏23熔融而溢出時,將受到該子阻隔單元311A的阻擋而防止進一步溢出封裝材40外。阻隔單元之設置並不限於前述之實施例,各阻隔單元亦可間隔圍繞設置、或呈連續封閉狀圍繞設置於相對應之電子元件周圍,以將該電子元件之各連接墊一併圍繞於其中,亦同樣可達到防止熔融的錫膏溢出的封裝材40外的效果。
In one embodiment (as shown in FIG. 2), each
進一步而言,在一實施例中(如圖1及圖2所示),各阻隔單元31之各子阻隔單元311內凹設置於導線架30之表面,則當錫膏23熔融而溢出時,會先流入內凹的子阻隔單元311而被收集於其中,以防止進一步溢出封裝材40外。在另一實施例中(如圖4及圖5所示),各阻隔單元31B之各子阻隔單元311B突出設置於導線架30B之表面,則當錫膏23熔融而溢出時,會受到子阻隔單元311B的抵擋,以防止進一步溢出封裝材40外。
Furthermore, in one embodiment (as shown in FIGS. 1 and 2), each
以上所述僅是本發明的實施例而已,並非對本發明做任何形式上的限制,雖然本發明已以實施例揭露如上,然而並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明技術方案的範圍內,當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例,但凡是 未脫離本發明技術方案的內容,依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾,均仍屬於本發明技術方案的範圍內。 The above are only the embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field, Without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make slight changes or modification into equivalent embodiments with equivalent changes, but generally Without departing from the content of the technical solution of the present invention, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.
10:系統級封裝結構 10: System-in-package structure
20:電子元件 20: Electronic components
21:本體 21: body
22:連接墊 22: Connection pad
23:錫膏 23: Solder paste
30:導線架 30: Lead frame
31:阻隔單元 31: Barrier unit
311:子阻隔單元 311: Sub-blocking unit
32:外部接點 32: External contact
40:封裝材 40: Packaging material
Claims (9)
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TW108106828A TWI728318B (en) | 2019-02-27 | 2019-02-27 | System in package structure |
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TW108106828A TWI728318B (en) | 2019-02-27 | 2019-02-27 | System in package structure |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002069400A1 (en) | 2001-02-27 | 2002-09-06 | Chippac, Inc. | Plastic semiconductor package |
US20090236714A1 (en) * | 2002-04-16 | 2009-09-24 | Elsie Agdon Cabahug | Robust leaded molded packages and methods for forming the same |
TW200947629A (en) * | 2008-01-09 | 2009-11-16 | Yamaha Corp | Microphone package, lead frame, mold substrate, and mounting structure therefor |
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- 2019-02-27 TW TW108106828A patent/TWI728318B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002069400A1 (en) | 2001-02-27 | 2002-09-06 | Chippac, Inc. | Plastic semiconductor package |
US20090236714A1 (en) * | 2002-04-16 | 2009-09-24 | Elsie Agdon Cabahug | Robust leaded molded packages and methods for forming the same |
TW200947629A (en) * | 2008-01-09 | 2009-11-16 | Yamaha Corp | Microphone package, lead frame, mold substrate, and mounting structure therefor |
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