TWI727706B - Display device - Google Patents

Abstract

A display device includes a plurality of data lines, a pixel circuit, and a multiplexer circuit. The pixel circuit is disposed in the active area, and the pixel circuit includes a plurality of pixel units. The multiplexer circuit is electrically connected to the pixel circuit and the data lines. The multiplexer circuit includes a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer. The first multiplexer and the second multiplexer are turned on in different time period. The third multiplexer and the fourth multiplexer are turned on in different time period.

Description

Display device

This disclosure relates to a display device, especially a display device with a multiplexer design.

In the display panel technology, the interference source of the panel mainly comes from the switching of signals. For example, the electromagnetic interference (EMI) generated by the switching between the enable level and the disable level of the multiplexer affects the display panel. Display quality. Therefore, in order to reduce the interference of the noise, the spread spectrum method (Spread Spectrum) can be used to spread the enable signal of the multiplexer to reduce the peak level of the noise and improve the anti-interference ability of the display panel.

The first implementation aspect of this case is to provide a display device, which includes a plurality of data lines, a pixel circuit, and a multiplexer circuit. The pixel circuit is arranged in the display area and is electrically connected to the data line. The pixel circuit includes a plurality of sub-pixel units. The multiplexer circuit is arranged in the peripheral area and is electrically connected to the pixel circuit and the data line. The multiplexer circuit includes: a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer. The first multiplexer is arranged on one side of the peripheral area and is electrically connected to a plurality of odd data lines. The second multiplexer is arranged on the side and is electrically connected to a plurality of even data lines. The third multiplexer is arranged on an opposite side of the first multiplexer and the second multiplexer, and is electrically connected to an odd number of data lines. The fourth multiplexer is arranged on the opposite side and is electrically connected to an even number of data lines. The first multiplexer and the third multiplexer are not enabled at the same time, and the second multiplexer and the fourth multiplexer are not enabled at the same time.

The display device of the present invention mainly uses multiple sets of multiplexers to enable different sets of multiplexers in different time periods to achieve the effect of spreading or reducing the frequency of the enabling signal. Furthermore, the gate signal is used to control the charging time of some sub-pixel units, so the number of switches in the multiplexer can be further reduced.

The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the display device 100 includes a pixel circuit 110, a gate driving circuit 120, a source driving circuit 130 and a multiplexer circuit 140. The pixel circuit 110 is disposed in the display area AA. The pixel circuit 110 is electrically connected to a plurality of data lines DL and a plurality of gate lines GL. The pixel circuit 110 includes a plurality of sub-pixel units 111. The gate driving circuit 120, the source driving circuit 130, and the multiplexer circuit 140 are disposed in the peripheral area PA. The multiplexer circuit 140 is electrically connected to the pixel circuit 110 and the data line DL.

In accordance with the above, in one embodiment, the multiplexer circuit 140 includes multiplexers 141, 142, 143, and 144. The multiplexer 141 is disposed on one side of the peripheral area PA, and the multiplexer 141 is electrically connected to an odd number of Data lines DL1, DL3 and DL5. The multiplexer 142 is disposed in the peripheral area PA and on the same side as the multiplexer 141, and the multiplexer 142 is electrically connected to an even number of data lines DL2, DL4, and DL6. The multiplexer 143 is disposed on the side of the peripheral area PA and opposite to the multiplexers 141 and 142, and the multiplexer 143 is electrically connected to an odd number of data lines DL1, DL3, and DL5. The multiplexer 144 is disposed on the same side as the multiplexer 143 in the peripheral area PA, and the multiplexer 144 is electrically connected to an even number of data lines DL2, DL4, and DL6.

It is worth noting that when the multiplexer 141 is enabled, the multiplexer 143 is at the disabled level; when the multiplexer 142 is enabled, the multiplexer 144 is at the disabled level. That is, the multiplexers 141 and 143 are not enabled at the same time, and the multiplexers 142 and 144 are not enabled at the same time.

In view of the above, the multiplexer 141 includes switches T1 and T2. The first terminal of the switch T1 is electrically connected to the odd number of data lines DL1, the second terminal of the switch T1 is used for receiving the data voltage, and the control terminal of the switch T1 is used for receiving the control signal CTLa1. The first terminal of the switch T2 is electrically connected to the odd number of data lines DL5, the second terminal of the switch T5 is used for receiving the data voltage, and the control terminal of the switch T1 is used for receiving the control signal CTLa1.

In view of the above, the multiplexer 142 includes switches T3 and T4. The first terminal of the switch T3 is electrically connected to an even number of data lines DL2, the second terminal of the switch T3 is used for receiving the data voltage, and the control terminal of the switch T3 is used for receiving the control signal CTLa2. The first terminal of the switch T4 is electrically connected to the odd number of data lines DL4, the second terminal of the switch T4 is used for receiving the data voltage, and the control terminal of the switch T4 is used for receiving the control signal CTLa2.

In view of the above, the multiplexer 143 includes switches T5 and T6. The first terminal of the switch T5 is electrically connected to the odd number of data lines DL1, the second terminal of the switch T5 is used for receiving the data voltage, and the control terminal of the switch T5 is used for receiving the control signal CTLb1. The first end of the switch T6 is electrically connected to the odd number of data lines DL5, the second end of the switch T6 is used to receive the data voltage, and the control end of the switch T6 is used to receive the control signal CTLb1.

In view of the above, the multiplexer 144 includes switches T7 and T8. The first terminal of the switch T7 is electrically connected to an even number of data lines DL2, the second terminal of the switch T7 is used for receiving the data voltage, and the control terminal of the switch T7 is used for receiving the control signal CTLb2. The first terminal of the switch T8 is electrically connected to the odd number of data lines DL4, the second terminal of the switch T8 is used to receive the data voltage, and the control terminal of the switch T8 is used to receive the control signal CTLb2.

Please refer to FIGS. 2 and 3. FIG. 2 is a partially enlarged schematic diagram of the multiplexer circuit 140 and part of the pixel circuit 110 according to an embodiment of the present disclosure, and FIG. 3 is based on the present disclosure A timing diagram of the operation of the multiplexer circuit 140 in an embodiment of the document. As shown in the embodiment shown in Figure 2, only one gate line GL(n), six data lines DL1 to DL6 and part of the sub-pixel units are shown. The operations of the rest of the components are similar. Go into details again.

As shown in FIG. 3, during the period TP1, the multiplexer 141 is enabled according to the control signal CTLa, and then the multiplexer 142 is enabled according to the control signal CTLa2. When the control signal CTLa1 enables the multiplexer 141, the switch T1 and the switch T2 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLa2 enables the multiplexer 142, the switch T3 and the switch T4 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f. It is worth noting that the sub-pixel units 111a and 111d can be implemented as red sub-pixels, the sub-pixel units 111b and 111e can be implemented as green sub-pixels, and the sub-pixel units 111c and 111f can be implemented as blue sub-pixels. Vegetarian.

Please continue to refer to FIGS. 2 and 3, during the time period TP2, the multiplexer 143 is enabled according to the control signal CTLb1, and then the multiplexer 144 is enabled according to the control signal CTLb2. When the control signal CTLb1 enables the multiplexer 143, the switch T5 and the switch T6 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLb2 enables the multiplexer 144, the switch T7 and the switch T8 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

In view of the above, in the time period TP3, the multiplexer 141 is enabled according to the control signal CTLa1, and then the multiplexer 144 is enabled according to the control signal CTLb2. When the control signal CTLa1 enables the multiplexer 141, the switch T1 and the switch T2 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLb2 enables the multiplexer 144, the switch T7 and the switch T8 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

In view of the above, in the time period TP4, the multiplexer 143 is enabled according to the control signal CTLb1, and then the multiplexer 142 is enabled according to the control signal CTLa2. When the control signal CTLb1 enables the multiplexer 143, the switch T5 and the switch T6 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLa2 enables the multiplexer 142, the switch T3 and the switch T4 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

It is worth noting that there is no sequence for the time periods TP1 to TP4, and the operation sequence of each time period can be adjusted arbitrarily. Furthermore, the time period shown in Figure 3 is the enable time of a gate signal, which means a line time. As shown in Figure 3, in this operation, the enabling time interval of the control signal CTLb2 is interval X1, the enabling time interval of the control signals CTLa1 and CTLb1 is interval X2, and the enabling time interval of the control signal CTLa2 is interval X3. However, the sequence of the time periods TP1 to TP4 can be adjusted arbitrarily, so the enabling time interval of each control signal is not fixed.

For example, the operating frequency of the multiplexer circuit 140 is 55 KHz. In the embodiment shown in Figure 3, the interval X1 is 55 KHz, so the operating frequency of the multiplexer 144 is 55 KHz; the interval X2 is 27.5 KHz. Therefore, the operating frequency of the multiplexers 141 and 143 is 27.5 KHz; the interval X3 is 18.3 KHz, so the operating frequency of the multiplexer 142 is 18.3 KHz. In other words, the operating frequency of the multiplexer circuit 140 will not be fixed at 55 KHz, but will be distributed to different operating frequencies to achieve the effect of spreading the enable signal of the multiplexer.

Next, in another embodiment, please refer to FIG. 2 and FIG. 4 together. FIG. 4 is an operation timing diagram of the multiplexer circuit 140 according to an embodiment of the present disclosure. As shown in FIG. 4, during the period TP1, the multiplexer 141 is enabled according to the control signal CTLa1, and then the multiplexer 142 is enabled according to the control signal CTLa2. In the time period TP2, the multiplexer 143 is enabled according to the control signal CTLb1, and then the multiplexer 144 is enabled according to the control signal CTLb2.

In view of the above, in the period TP1, when the control signal CTLa1 enables the multiplexer 141, the switch T1 and the switch T2 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLa2 enables the multiplexer 142, the switch T3 and the switch T4 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

In view of the above, in the period TP2, when the control signal CTLb1 enables the multiplexer 143, the switch T5 and the switch T6 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLb2 enables the multiplexer 144, the switch T7 and the switch T8 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

Next, the operation of the time period TP3 is the same as that of the time period TP1, and the operation of the time period TP4 is the same as that of the time period TP2, which will not be repeated here. It should be noted that there is no sequence for the time periods TP1 and TP2, and the time period TP2 can also be executed first and then the time period TP1. Similarly, as shown in FIG. 4, in this operation, the enabling time interval of the control signals CTLa1, CTLa2, CTLb1, and CTLb2 is the interval X2. For example, the operating frequency of the multiplexer circuit 140 is 55 KHz. In the embodiment shown in Figure 4, the interval X2 is 27.5 KHz, so the operating frequency of the multiplexers 141 to 144 is 27.5 KHz, in other words , The operating frequency of the multiplexer circuit 140 is reduced from 55 KHz to 27.5 KHz. Therefore, the embodiment shown in FIG. 4 can achieve the effect of downscaling the enable signal of the multiplexer.

Next, in another embodiment, please refer to FIG. 2 and FIG. 5 together. FIG. 5 is an operation timing diagram of the multiplexer circuit 140 according to an embodiment of the present disclosure. As shown in FIG. 5, during the period TP1, the multiplexer 141 is enabled according to the control signal CTLa1, and then the multiplexer 144 is enabled according to the control signal CTLb2. In the time period TP2, the multiplexer 143 is enabled according to the control signal CTLb1, and then the multiplexer 142 is enabled according to the control signal CTLa2.

In view of the above, in the period TP1, when the control signal CTLa1 enables the multiplexer 141, the switch T1 and the switch T2 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLb2 enables the multiplexer 142, the switch T7 and the switch T8 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

In view of the above, in the period TP2, when the control signal CTLb1 enables the multiplexer 143, the switch T5 and the switch T6 are turned on, and the data voltage Vdata is written to the odd-numbered sub-pixel units 111a, 111c, and 111e. Then, when the control signal CTLa2 enables the multiplexer 142, the switch T3 and the switch T4 are turned on, and the data voltage Vdata is written to the even-numbered sub-pixel units 111b, 111d, and 111f.

Next, the operation of the time period TP3 is the same as that of the time period TP1, and the operation of the time period TP4 is the same as that of the time period TP2, which will not be repeated here. It is worth noting that there is no sequence for the time periods TP1 to TP2, and the time period TP2 can also be executed first and then the time period TP1. Similarly, as shown in FIG. 5, in this operation, the enabling time interval of the control signals CTLa1, CTLa2, CTLb1, and CTLb2 is the interval X2. For example, the operating frequency of the multiplexer circuit 140 is 55 KHz. In the embodiment shown in Figure 5, the interval X2 is 27.5 KHz, so the operating frequency of the multiplexers 141 to 144 is 27.5 KHz, in other words , The operating frequency of the multiplexer circuit 140 is reduced from 55 KHz to 27.5 KHz. Therefore, the embodiment shown in FIG. 5 can achieve the effect of downscaling the enable signal of the multiplexer.

In another embodiment, please refer to FIG. 6. FIG. 6 is a schematic diagram of a display device 600 according to an embodiment of the present disclosure. As shown in FIG. 6, the display device 600 includes a pixel circuit 110, gate driving circuits 120a and 120b, a source driving circuit 130, and a multiplexer circuit 140. The pixel circuit 110 is disposed in the display area AA. The pixel circuit 110 is electrically connected to a plurality of data lines DL and a plurality of gate lines GLa and GLb. The pixel circuit 110 includes a plurality of sub-pixel units 111. The gate driving circuits 120a and 120b, the source driving circuit 130, and the multiplexer circuit 140 are disposed in the peripheral area PA. The multiplexer circuit 140 is electrically connected to the pixel circuit 110 and the data line DL.

In accordance with the above, in one embodiment, the multiplexer circuit 140 includes multiplexers 141, 142, 143, and 144. The multiplexer 141 is disposed on one side of the peripheral area PA, and the multiplexer 141 is electrically connected to an odd number of Data lines DL1, DL3 and DL5. The multiplexer 142 is disposed in the peripheral area PA and on the same side as the multiplexer 141, and the multiplexer 142 is electrically connected to an even number of data lines DL2, DL4, and DL6. The multiplexer 143 is disposed on the side of the peripheral area PA and opposite to the multiplexers 141 and 142, and the multiplexer 143 is electrically connected to an odd number of data lines DL1, DL3, and DL5. The multiplexer 144 is disposed on the same side as the multiplexer 143 in the peripheral area PA, and the multiplexer 144 is electrically connected to an even number of data lines DL2, DL4, and DL6.

It is worth noting that when the multiplexer 141 is enabled, the multiplexer 143 is at the disabled level; when the multiplexer 142 is enabled, the multiplexer 144 is at the disabled level. That is, the multiplexers 141 and 143 are not enabled at the same time, and the multiplexers 142 and 144 are not enabled at the same time.

In view of the above, the multiplexer 141 includes the switch T9. The first terminal of the switch T9 is electrically connected to the odd number of data lines DL1, the second terminal of the switch T9 is used for receiving the data voltage, and the control terminal of the switch T9 is used for receiving the control signal CTLa1. The multiplexer 142 includes a switch T10. The first terminal of the switch T10 is electrically connected to an even number of data lines DL4, the second terminal of the switch T10 is used for receiving the data voltage, and the control terminal of the switch T10 is used for receiving the control signal CTLa2.

In view of the above, the multiplexer 143 includes the switch T11. The first terminal of the switch T11 is electrically connected to the odd number of data lines DL1, the second terminal of the switch T11 is used for receiving the data voltage, and the control terminal of the switch T11 is used for receiving the control signal CTLb1. The multiplexer 144 includes a switch T12. The first terminal of the switch T12 is electrically connected to an even number of data lines DL4, the second terminal of the switch T12 is used for receiving the data voltage, and the control terminal of the switch T12 is used for receiving the control signal CTLb2.

Please refer to Figure 7 and Figure 8 together. FIG. 7 is a partially enlarged schematic diagram of the multiplexer circuit 140 and part of the pixel circuit 110 according to an embodiment of the present disclosure, and FIG. 8 is the operation of the multiplexer circuit 140 according to an embodiment of the present disclosure Timing diagram. As in the embodiment shown in Figure 7, only the gate lines GLa(n) and GLb(n), 6 data lines DL1 to DL6, and part of the sub-pixel units are shown. The operations of the remaining components are similar. I won't repeat them here.

As shown in FIG. 8, in the period TP1, the multiplexers 141 and 142 are enabled according to the control signal CTLa. When the control signal CTLa enables the multiplexers 141 and 142, the switch T9 and the switch T10 are turned on, and the data voltage Vdatar is transmitted to the plurality of sub-pixel units 111r, 111g, and 111b. Then, when the control signal CTLa is switched to the disable level, the switch T9 and the switch T10 are turned off, and the sub-data voltage Vdatar is written to the pixel unit 111r, and no other data voltages are written. Then, the data voltage Vdatag is transmitted to the sub-pixel units 111g and 111b. When the gate signal Ga(n) is switched to the disable level, the data voltage Vdatag is written to the sub-pixel unit 111g, and no other data is written into it. Voltage. Then, the data voltage Vdatab is transmitted to the sub-pixel unit 111b, and when the gate signal Gb(n) is switched to the disable level, the data voltage Vdatab is written to the sub-pixel unit 111b.

In the time period TP2, the multiplexers 143 and 144 are enabled according to the control signal CTLb. When the control signal CTLb enables the multiplexers 143 and 144, the switch T11 and the switch T12 are turned on, and the data voltage Vdatar is transmitted to the plurality of sub-pixel units 111r, 111g, and 111b. Then, when the control signal CTLb is switched to the disable level, the switch T11 and the switch T12 are turned off, and the sub-data voltage Vdatar is written into the pixel unit 111r, and no other data voltage is written into it. Then, the data voltage Vdatag is transmitted to the sub-pixel units 111g and 111b. When the gate signal Ga(n+1) is switched to the disable level, the data voltage Vdatag is written to the sub-pixel unit 111g and is no longer written Other information voltage. Then, the data voltage Vdatab is transmitted to the sub-pixel unit 111b, and when the gate signal Gb(n+1) is switched to the disable level, the data voltage Vdatab is written to the sub-pixel unit 111b.

In view of the above, the operation of the time period TP3 is similar to the time period TP1, and the operation of the time period TP4 is similar to the time period TP2, which will not be repeated here. It should be noted that there is no sequence for the time periods TP1 and TP2, and the time period TP2 can also be executed first and then the time period TP1. Furthermore, the time period shown in Figure 3 is the enable time of a gate signal, which means a line time. As shown in Fig. 7, in this operation, the enable time interval of the control signals CTLa and CTLb is the interval X2. For example, the operating frequency of the multiplexer circuit 140 is 55 KHz. In the embodiment shown in Figure 7, the interval X2 is 27.5 KHz, so the operating frequency of the multiplexers 141 to 144 is 27.5 KHz, in other words , The operating frequency of the multiplexer circuit 140 is reduced from 55 KHz to 27.5 KHz. Therefore, the embodiment shown in FIG. 7 can achieve the effect of downscaling the enable signal of the multiplexer.

To sum up, the display device of the present disclosure mainly uses multiple sets of multiplexers to enable different sets of multiplexers in different time periods to achieve the effect of spreading or reducing the frequency of the enabling signal. Furthermore, the gate signal is used to control the charging time of some sub-pixel units, so the number of switches in the multiplexer can be further reduced.

In the specification and the scope of the patent application, certain words are used to refer to specific elements. However, a person with ordinary knowledge in the relevant technical field should understand that the same element may be called by different terms. The specification and the scope of patent application do not use differences in names as a way to distinguish components, but use differences in functions of components as a basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.

In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.

100: display device

110: pixel circuit

111,111a,111b,111c,111d,111de,111f,111r,111g: sub-pixel unit

120, 120a, 120b: gate drive circuit

130: Source drive circuit

140: Multiplexer circuit

141, 142, 143, 144: multiplexer

GL, GLa, GLb, GL(n), GLa(n), GLb(n): gate line

DL, DL1~DL6: data line

AA: Display area

PA: Peripheral area

Vdata, Vdatar, Vdatag, Vdatab: data voltage

T1~T12: switch

CTLa, CTLa1, CTLa2, CTLb, CTLb1, CTLb2: control signal

TP1~TP4: time period

X1~X3: interval

Ga(n),Gb(n),Ga(n+1),Gb(n+1),Ga(n+2),Gb(n+2),Ga(n+3),Gb(n+3 ): Gate signal

In order to make the above and other purposes, features, advantages and embodiments of the disclosure document more obvious and understandable, the description of the accompanying drawings is as follows: Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure; FIG. 2 is a partially enlarged schematic diagram of the multiplexer circuit and part of the pixel circuit 110 according to an embodiment of the present disclosure; FIG. 3 is an operation timing diagram of the multiplexer circuit according to an embodiment of the present disclosure; FIG. 4 is an operation timing diagram of a multiplexer circuit according to an embodiment of the present disclosure; FIG. 5 is an operation timing diagram of the multiplexer circuit according to an embodiment of the present disclosure; FIG. 6 is a schematic diagram of a display device according to an embodiment of the present disclosure; FIG. 7 is a partially enlarged schematic diagram of a multiplexer circuit and part of a pixel circuit according to an embodiment of the present disclosure; and FIG. 8 is an operation timing diagram of the multiplexer circuit according to an embodiment of the present disclosure.

100: display device

110: pixel circuit

111: Sub-pixel unit

120: Gate drive circuit

130: Source drive circuit

140: Multiplexer circuit

141, 142, 143, 144: multiplexer

GL: Gate line

DL, DL1~DL6: data line

AA: Display area

PA: Peripheral area

T1~T8: switch

CTLa1, CTLa2, CTLb1, CTLb2: control signal

Claims (20)

A display device comprising: a plurality of data lines; a pixel circuit arranged in a display area and electrically connected to the data lines, wherein the pixel circuit includes a plurality of sub-pixel units; and a multiplexer circuit, Is arranged in a peripheral area and is electrically connected to the pixel circuit and the data lines, wherein the multiplexer circuit includes: a first multiplexer arranged on one side of the peripheral area and electrically connected to a plurality of An odd number of data lines; a second multiplexer, arranged on the side, electrically connected to a plurality of even number of data lines; a third multiplexer, arranged on the first multiplexer and the second multiplexer An opposite side of the device is electrically connected to the odd-numbered data lines; and a fourth multiplexer is disposed on the opposite side and is electrically connected to the even-numbered data lines; wherein the first multiplexer The second multiplexer and the fourth multiplexer are not enabled at the same time, and the second multiplexer and the fourth multiplexer are not enabled at the same time. The display device according to claim 1, wherein the first multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected to One of the odd-numbered data lines, the second end is used to receive a data voltage, the first control end is used to receive a first control signal; and a second switch has a third end and a first control signal. Four terminals and a second control The control terminal, the third terminal is electrically connected to the other of the odd data lines, the fourth terminal is electrically connected to the second terminal, and the second control terminal is used for receiving the first control signal. The display device according to claim 1, wherein the second multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the even-numbered data lines, the second terminal is used to receive a data voltage, the first control terminal is used to receive a second control signal; and a second switch has a third terminal, a A fourth terminal and a second control terminal. The third terminal is electrically connected to the other of the even-numbered data lines, the fourth terminal is electrically connected to the second terminal, and the second control terminal is used for Receive the second control signal. The display device according to claim 1, wherein the third multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the odd-numbered data lines, the second terminal is used to receive a data voltage, the first control terminal is used to receive a third control signal; and a second switch has a third terminal, a A fourth terminal and a second control terminal, the third terminal is electrically connected to the other of the odd data lines, the fourth terminal is electrically connected to the second terminal, and the second control terminal is used for Pick up Receive the third control signal. The display device according to claim 1, wherein the fourth multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the even-numbered data lines, the second terminal is used to receive a data voltage, the first control terminal is used to receive a fourth control signal; and a second switch has a third terminal, a A fourth terminal and a second control terminal. The third terminal is electrically connected to the other of the even-numbered data lines, the fourth terminal is electrically connected to the second terminal, and the second control terminal is used for Receive the fourth control signal. The display device according to claim 1, wherein, in a first time period, the first multiplexer is enabled according to a first control signal, and then the second multiplexer is enabled according to a second control signal; In a second time period, the third multiplexer is enabled according to a third control signal, and then the fourth multiplexer is enabled according to a fourth control signal; in a third time period, the third multiplexer is enabled according to the first control signal The signal enables the first multiplexer, and then the fourth multiplexer is enabled according to the fourth control signal; in a fourth time period, the third multiplexer is enabled according to the third control signal, and then according to The second control signal enables the second multiplexer. The display device according to claim 6, wherein, when the first When a control signal enables the first multiplexer, a first data voltage is written to a plurality of odd-numbered sub-pixel units connected to the odd-numbered data lines; then when the second control signal enables the In the second multiplexer, a second data voltage is written to a plurality of even-numbered sub-pixel units connected to the even-numbered data lines. The display device according to claim 6, wherein, when the third control signal enables the third multiplexer, a first data voltage is written to a plurality of odd-numbered items connected to the odd-numbered data lines Sub-pixel unit; then when the fourth control signal enables the fourth multiplexer, a second data voltage is written to a plurality of even-numbered sub-pixel units connected to the even-numbered data lines. The display device according to claim 6, wherein when the first control signal enables the first multiplexer, a first data voltage is written to a plurality of odd-numbered items connected to the odd-numbered data lines Sub-pixel unit; then when the fourth control signal enables the fourth multiplexer, a second data voltage is written to a plurality of even-numbered sub-pixel units connected to the even-numbered data lines. The display device according to claim 6, wherein, when the third control signal enables the third multiplexer, a first data voltage is written to a plurality of odd-numbered items connected to the odd-numbered data lines Sub-pixel unit; then when the second control signal enables the second multiplexer, a second data The voltage is written to a plurality of even-numbered sub-pixel units connected to the even-numbered data lines. The display device according to claim 1, wherein, within a period of time, the first multiplexer is enabled according to a first control signal, and then the second multiplexer is enabled according to a second control signal; In another time period, the third multiplexer is enabled according to a third control signal, and then the fourth multiplexer is enabled according to a fourth control signal. The display device according to claim 1, wherein, within a period of time, the first multiplexer is enabled according to a first control signal, and then the fourth multiplexer is enabled according to a fourth control signal; In another time period, the third multiplexer is enabled according to a third control signal, and then the second multiplexer is enabled according to a second control signal. The display device according to claim 1, further comprising: a first gate driving circuit disposed in the peripheral area and electrically connected to the plurality of first sub-pixel units and the plurality of third sub-pixel units; and A second gate driving circuit is arranged in the peripheral area and is electrically connected to a plurality of second sub-pixel units. The display device according to claim 1, wherein the first multiplexer further comprises: a first switch having a first end, a second end, and a first control The control terminal, the first terminal is electrically connected to one of the odd data lines, the second terminal is used for receiving a data voltage, and the first control terminal is used for receiving a first control signal. The display device according to claim 1, wherein the second multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the even-numbered data lines, the second terminal is used for receiving a data voltage, and the first control terminal is used for receiving a second control signal. The display device according to claim 1, wherein the third multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the odd data lines, the second terminal is used for receiving a data voltage, and the first control terminal is used for receiving a third control signal. The display device according to claim 1, wherein the fourth multiplexer further comprises: a first switch having a first terminal, a second terminal and a first control terminal, the first terminal is electrically connected To one of the even-numbered data lines, the second terminal is used for receiving a data voltage, and the first control terminal is used for receiving a fourth control signal. The display device according to claim 13, wherein the first multiplexer and the second multiplexer are enabled according to a first control signal in a period of time; in another period of time, the first multiplexer and the second multiplexer are enabled according to a second The control signal enables the third multiplexer and the fourth multiplexer. The display device according to claim 18, wherein, during the period, when the first control signal enables the first multiplexer and the second multiplexer, a first data voltage is written to the The first sub-pixel units, the second sub-pixel units, and the third sub-pixel units; then when the first control signal disables the first multiplexer and the second multiplexer, A second data voltage is written to the second sub-pixel units and the third sub-pixel units; then a third data voltage is written to the third sub-pixel units. The display device according to claim 18, wherein, in the other time period, when the second control signal enables the third multiplexer and the fourth multiplexer, a first data voltage is written To the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units; then when the second control signal disables the third multiplexer and the fourth multiplexer At this time, a second data voltage is written to the second sub-pixel units and the third sub-pixel units; then a third data voltage is written to the third sub-pixel units.

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