TWI727706B - Display device - Google Patents
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本揭示文件有關一種顯示裝置,尤指一種具有多工器設計的顯示裝置。This disclosure relates to a display device, especially a display device with a multiplexer design.
在顯示面板的技術中,面板的干擾源主要是來自訊號的切換,例如多工器在致能準位及禁能準位之間切換產生的電磁干擾(Electromagnetic Interference,EMI),影響顯示面板的顯示品質。因此,為了降低雜訊的干擾可以利用擴展頻譜法(Spread Spectrum)來對多工器的致能訊號展頻,以降低雜訊的峰值位準,提高顯示面板抗干擾的能力。In the display panel technology, the interference source of the panel mainly comes from the switching of signals. For example, the electromagnetic interference (EMI) generated by the switching between the enable level and the disable level of the multiplexer affects the display panel. Display quality. Therefore, in order to reduce the interference of the noise, the spread spectrum method (Spread Spectrum) can be used to spread the enable signal of the multiplexer to reduce the peak level of the noise and improve the anti-interference ability of the display panel.
本案之第一實施態樣是在提供一種顯示裝置,包含:複數條資料線、畫素電路以及多工器電路。畫素電路設置於顯示區,電性連接至資料線,其中畫素電路包含複數個子畫素單元。多工器電路設置於周邊區,電性連接至畫素電路以及資料線。多工器電路包含:第一多工器、第二多工器、第三多工器以及第四多工器。第一多工器設置於周邊區的一側邊,電性連接至複數個奇數條資料線。第二多工器設置於側邊,電性連接至複數個偶數條資料線。第三多工器設置於第一多工器及第二多工器的一相對側邊,電性連接至奇數條資料線。第四多工器設置於相對側邊,電性連接至偶數條資料線。其中第一多工器及第三多工器不同時致能,第二多工器及第四多工器不同時致能。The first implementation aspect of this case is to provide a display device, which includes a plurality of data lines, a pixel circuit, and a multiplexer circuit. The pixel circuit is arranged in the display area and is electrically connected to the data line. The pixel circuit includes a plurality of sub-pixel units. The multiplexer circuit is arranged in the peripheral area and is electrically connected to the pixel circuit and the data line. The multiplexer circuit includes: a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer. The first multiplexer is arranged on one side of the peripheral area and is electrically connected to a plurality of odd data lines. The second multiplexer is arranged on the side and is electrically connected to a plurality of even data lines. The third multiplexer is arranged on an opposite side of the first multiplexer and the second multiplexer, and is electrically connected to an odd number of data lines. The fourth multiplexer is arranged on the opposite side and is electrically connected to an even number of data lines. The first multiplexer and the third multiplexer are not enabled at the same time, and the second multiplexer and the fourth multiplexer are not enabled at the same time.
本發明之顯示裝置主要係利用多組多工器,在不同時段中致能不同組的多工器,來達到將致能訊號展頻或降頻的效果。再者,利用閘極訊號來控制部份子畫素單元的充電時間,因此可以進一步減少多工器中開關的數量。The display device of the present invention mainly uses multiple sets of multiplexers to enable different sets of multiplexers in different time periods to achieve the effect of spreading or reducing the frequency of the enabling signal. Furthermore, the gate signal is used to control the charging time of some sub-pixel units, so the number of switches in the multiplexer can be further reduced.
以下將配合相關圖式來說明本發明的實施例。在圖式中,相同的標號表示相同或類似的元件或方法流程。The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.
請參閱第1圖。第1圖為根據本揭示文件一實施例的顯示裝置100的示意圖。如第1圖所繪示,顯示裝置100包含畫素電路110、閘極驅動電路120、源極驅動電路130以及多工器電路140。畫素電路110設置於顯示區AA,畫素電路110電性連接至多條資料線DL及多條閘極線GL,畫素電路110包含複數個子畫素單元111。閘極驅動電路120、源極驅動電路130以及多工器電路140設置於周邊區PA。多工器電路140電性連接至畫素電路110以及資料線DL。Please refer to Figure 1. FIG. 1 is a schematic diagram of a
承上述,於一實施例中,多工器電路140包含多工器141、142、143以及144,多工器141設置於周邊區PA的一側邊,多工器141電性連接至奇數條資料線DL1、DL3及DL5。多工器142設置於周邊區PA並且與多工器141相同的側邊,多工器142電性連接至偶數條資料線DL2、DL4及DL6。多工器143設置於周邊區PA並且與多工器141及142相對的側邊,多工器143電性連接至奇數條資料線DL1、DL3及DL5。多工器144設置於周邊區PA並且與多工器143相同的側邊,多工器144電性連接至偶數條資料線DL2、DL4及DL6。In accordance with the above, in one embodiment, the
值得注意的是,當多工器141致能時,多工器143為禁能位準;當多工器142致能時,多工器144為禁能位準。也就是說,多工器141和143不同時致能,多工器142和144不同時致能。It is worth noting that when the
承上述,多工器141包含開關T1及T2。開關T1的第一端電性連接至奇數條資料線DL1,開關T1的第二端用以接收資料電壓,開關T1的控制端用以接收控制訊號CTLa1。開關T2的第一端電性連接至奇數條資料線DL5,開關T5的第二端用以接收資料電壓,開關T1的控制端用以接收控制訊號CTLa1。In view of the above, the
承上述,多工器142包含開關T3及T4。開關T3的第一端電性連接至偶數條資料線DL2,開關T3的第二端用以接收資料電壓,開關T3的控制端用以接收控制訊號CTLa2。開關T4的第一端電性連接至奇數條資料線DL4,開關T4的第二端用以接收資料電壓,開關T4的控制端用以接收控制訊號CTLa2。In view of the above, the
承上述,多工器143包含開關T5及T6。開關T5的第一端電性連接至奇數條資料線DL1,開關T5的第二端用以接收資料電壓,開關T5的控制端用以接收控制訊號CTLb1。開關T6的第一端電性連接至奇數條資料線DL5,開關T6的第二端用以接收資料電壓,開關T6的控制端用以接收控制訊號CTLb1。In view of the above, the
承上述,多工器144包含開關T7及T8。開關T7的第一端電性連接至偶數條資料線DL2,開關T7的第二端用以接收資料電壓,開關T7的控制端用以接收控制訊號CTLb2。開關T8的第一端電性連接至奇數條資料線DL4,開關T8的第二端用以接收資料電壓,開關T8的控制端用以接收控制訊號CTLb2。In view of the above, the
請一併參考第2圖及第3圖,第2圖為根據本揭示文件一實施例的多工器電路140以及部份的畫素電路110的部分放大示意圖,以及第3圖為根據本揭示文件一實施例的多工器電路140的操作時序圖。如第2圖所示的實施例中,僅繪示出一條閘極線GL(n)、6條資料線DL1~DL6以及部份的子畫素單元,其餘的元件操作均類似,在此不再贅述。Please refer to FIGS. 2 and 3. FIG. 2 is a partially enlarged schematic diagram of the
如第3圖所示,於時段TP1內,根據控制訊號CTLa致能多工器141,接著根據控制訊號CTLa2致能多工器142。當控制訊號CTLa1致能多工器141時,開關T1及開關T2導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLa2致能多工器142時,開關T3及開關T4導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。值得注意的是,子畫素單元111a及111d可以實施為紅色子畫素,子畫素單元111b及111e可以實施為綠色子畫素,以及子畫素單元111c及111f可以實施為藍色子畫素。As shown in FIG. 3, during the period TP1, the
請繼續參考第2圖及第3圖,於時段TP2內,根據控制訊號CTLb1致能多工器143,接著根據控制訊號CTLb2致能多工器144。當控制訊號CTLb1致能多工器143時,開關T5及開關T6導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLb2致能多工器144時,開關T7及開關T8導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。Please continue to refer to FIGS. 2 and 3, during the time period TP2, the
承上述,於時段TP3內,根據控制訊號CTLa1致能多工器141,接著根據控制訊號CTLb2致能多工器144。當控制訊號CTLa1致能多工器141時,開關T1及開關T2導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLb2致能多工器144時,開關T7及開關T8導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the time period TP3, the
承上述,於時段TP4內,根據控制訊號CTLb1致能多工器143,接著根據控制訊號CTLa2致能多工器142。當控制訊號CTLb1致能多工器143時,開關T5及開關T6導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLa2致能多工器142時,開關T3及開關T4導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the time period TP4, the
值得注意的是,時段TP1~TP4並沒有先後順序,可以任意調整各時段的操作順序。再者,第3圖所示的時段為一個閘極訊號的致能時間,意即一個列時間(line time)。如第3圖所示,在此操作中,控制訊號CTLb2的致能時間間隔為區間X1,控制訊號CTLa1及CTLb1的致能時間間隔為區間X2,控制訊號CTLa2的致能時間間隔為區間X3。然而,時段TP1~TP4的順序可以任意調整,因此每個控制訊號的致能時間間隔並不固定。It is worth noting that there is no sequence for the time periods TP1 to TP4, and the operation sequence of each time period can be adjusted arbitrarily. Furthermore, the time period shown in Figure 3 is the enable time of a gate signal, which means a line time. As shown in Figure 3, in this operation, the enabling time interval of the control signal CTLb2 is interval X1, the enabling time interval of the control signals CTLa1 and CTLb1 is interval X2, and the enabling time interval of the control signal CTLa2 is interval X3. However, the sequence of the time periods TP1 to TP4 can be adjusted arbitrarily, so the enabling time interval of each control signal is not fixed.
舉例而言,多工器電路140的操作頻率為55KHz,於第3圖所示的實施例中,區間X1即為55KHz,因此多工器144的操作頻率為55 KHz;區間X2即為27.5 KHz,因此多工器141及143的操作頻率為27.5 KHz;區間X3即為18.3 KHz,因此多工器142的操作頻率為18.3 KHz。換句話說,多工器電路140的操作頻率不會固定於55 KHz,而是會被分散至不同的操作頻率,以達到將多工器的致能訊號展頻的效果。For example, the operating frequency of the
接著,於另一實施例中,請一併參考第2圖及第4圖,第4圖為根據本揭示文件一實施例的多工器電路140的操作時序圖。如第4圖所示,於時段TP1內,根據控制訊號CTLa1致能該多工器141,接著根據控制訊號CTLa2致能多工器142。於時段TP2內,根據控制訊號CTLb1致能該多工器143,接著根據控制訊號CTLb2致能多工器144。Next, in another embodiment, please refer to FIG. 2 and FIG. 4 together. FIG. 4 is an operation timing diagram of the
承上述,於時段TP1內,當控制訊號CTLa1致能多工器141時,開關T1及開關T2導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLa2致能多工器142時,開關T3及開關T4導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the period TP1, when the control signal CTLa1 enables the
承上述,於時段TP2內,當控制訊號CTLb1致能多工器143時,開關T5及開關T6導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLb2致能多工器144時,開關T7及開關T8導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the period TP2, when the control signal CTLb1 enables the
接著,時段TP3的操作與時段TP1相同,時段TP4的操作與時段TP2相同,在此不再贅述。值得注意的是,時段TP1及TP2並沒有先後順序,也可以先執行時段TP2在執行時段TP1。同樣地,如第4圖所示,在此操作中,控制訊號CTLa1、CTLa2、CTLb1及CTLb2的致能時間間隔為區間X2。舉例而言,多工器電路140的操作頻率為55KHz,於第4圖所示的實施例中,區間X2即為27.5 KHz,因此多工器141~144的操作頻率為27.5 KHz,換句話說,多工器電路140的操作頻率由55 KHz降低至27.5 KHz。因此第4圖所示的實施例可以達到將多工器的致能訊號降頻的效果。Next, the operation of the time period TP3 is the same as that of the time period TP1, and the operation of the time period TP4 is the same as that of the time period TP2, which will not be repeated here. It should be noted that there is no sequence for the time periods TP1 and TP2, and the time period TP2 can also be executed first and then the time period TP1. Similarly, as shown in FIG. 4, in this operation, the enabling time interval of the control signals CTLa1, CTLa2, CTLb1, and CTLb2 is the interval X2. For example, the operating frequency of the
接著,於另一實施例中,請一併參考第2圖及第5圖,第5圖為根據本揭示文件一實施例的多工器電路140的操作時序圖。如第5圖所示,於時段TP1內,根據控制訊號CTLa1致能該多工器141,接著根據控制訊號CTLb2致能多工器144。於時段TP2內,根據控制訊號CTLb1致能該多工器143,接著根據控制訊號CTLa2致能多工器142。Next, in another embodiment, please refer to FIG. 2 and FIG. 5 together. FIG. 5 is an operation timing diagram of the
承上述,於時段TP1內,當控制訊號CTLa1致能多工器141時,開關T1及開關T2導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLb2致能多工器142時,開關T7及開關T8導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the period TP1, when the control signal CTLa1 enables the
承上述,於時段TP2內,當控制訊號CTLb1致能多工器143時,開關T5及開關T6導通,資料電壓Vdata被寫入至奇數項子畫素單元111a、111c及111e。接著,當控制訊號CTLa2致能多工器142時,開關T3及開關T4導通,資料電壓Vdata被寫入至偶數項子畫素單元111b、111d及111f。In view of the above, in the period TP2, when the control signal CTLb1 enables the
接著,時段TP3的操作與時段TP1相同,時段TP4的操作與時段TP2相同,在此不再贅述。值得注意的是,時段TP1~TP2並沒有先後順序,也可以先執行時段TP2在執行時段TP1。同樣地,如第5圖所示,在此操作中,控制訊號CTLa1、CTLa2、CTLb1及CTLb2的致能時間間隔為區間X2。舉例而言,多工器電路140的操作頻率為55KHz,於第5圖所示的實施例中,區間X2即為27.5 KHz,因此多工器141~144的操作頻率為27.5 KHz,換句話說,多工器電路140的操作頻率由55 KHz降低至27.5 KHz。因此第5圖所示的實施例可以達到將多工器的致能訊號降頻的效果。Next, the operation of the time period TP3 is the same as that of the time period TP1, and the operation of the time period TP4 is the same as that of the time period TP2, which will not be repeated here. It is worth noting that there is no sequence for the time periods TP1 to TP2, and the time period TP2 can also be executed first and then the time period TP1. Similarly, as shown in FIG. 5, in this operation, the enabling time interval of the control signals CTLa1, CTLa2, CTLb1, and CTLb2 is the interval X2. For example, the operating frequency of the
於另一實施例中,請參閱第6圖。第6圖為根據本揭示文件一實施例的顯示裝置600的示意圖。如第6圖所繪示,顯示裝置600包含畫素電路110、閘極驅動電路120a及120b、源極驅動電路130以及多工器電路140。畫素電路110設置於顯示區AA,畫素電路110電性連接至多條資料線DL及多條閘極線GLa及GLb,畫素電路110包含複數個子畫素單元111。閘極驅動電路120a及120b、源極驅動電路130以及多工器電路140設置於周邊區PA。多工器電路140電性連接至畫素電路110以及資料線DL。In another embodiment, please refer to FIG. 6. FIG. 6 is a schematic diagram of a display device 600 according to an embodiment of the present disclosure. As shown in FIG. 6, the display device 600 includes a
承上述,於一實施例中,多工器電路140包含多工器141、142、143以及144,多工器141設置於周邊區PA的一側邊,多工器141電性連接至奇數條資料線DL1、DL3及DL5。多工器142設置於周邊區PA並且與多工器141相同的側邊,多工器142電性連接至偶數條資料線DL2、DL4及DL6。多工器143設置於周邊區PA並且與多工器141及142相對的側邊,多工器143電性連接至奇數條資料線DL1、DL3及DL5。多工器144設置於周邊區PA並且與多工器143相同的側邊,多工器144電性連接至偶數條資料線DL2、DL4及DL6。In accordance with the above, in one embodiment, the
值得注意的是,當多工器141致能時,多工器143為禁能位準;當多工器142致能時,多工器144為禁能位準。也就是說,多工器141和143不同時致能,多工器142和144不同時致能。It is worth noting that when the
承上述,多工器141包含開關T9。開關T9的第一端電性連接至奇數條資料線DL1,開關T9的第二端用以接收資料電壓,開關T9的控制端用以接收控制訊號CTLa1。多工器142包含開關T10。開關T10的第一端電性連接至偶數條資料線DL4,開關T10的第二端用以接收資料電壓,開關T10的控制端用以接收控制訊號CTLa2。In view of the above, the
承上述,多工器143包含開關T11。開關T11的第一端電性連接至奇數條資料線DL1,開關T11的第二端用以接收資料電壓,開關T11的控制端用以接收控制訊號CTLb1。多工器144包含開關T12。開關T12的第一端電性連接至偶數條資料線DL4,開關T12的第二端用以接收資料電壓,開關T12的控制端用以接收控制訊號CTLb2。In view of the above, the
請一併參考第7圖及第8圖。第7圖為根據本揭示文件一實施例的多工器電路140以及部份的畫素電路110的部分放大示意圖,以及第8圖為根據本揭示文件一實施例的多工器電路140的操作時序圖。如第7圖所的實施例中,僅繪示出閘極線GLa(n)及GLb(n)、6條資料線DL1~DL6以及部份的子畫素單元,其餘的元件操作均類似,在此不再贅述。Please refer to Figure 7 and Figure 8 together. FIG. 7 is a partially enlarged schematic diagram of the
如第8圖所示,於時段TP1內,根據控制訊號CTLa致能多工器141及142。當控制訊號CTLa致能多工器141及142時,開關T9及開關T10導通,資料電壓Vdatar被傳送至多個子畫素單元111r、111g及111b。接著,當控制訊CTLa號切換至禁能位準時,開關T9及開關T10關斷,子資料電壓Vdatar寫入至畫素單元111r,不再被寫入其他資料電壓。接著,資料電壓Vdatag被傳送至子畫素單元111g及111b,當閘極訊號Ga(n)切換至禁能位準時,資料電壓Vdatag寫入至子畫素單元111g,不再被寫入其他資料電壓。接著,資料電壓Vdatab被傳送至子畫素單元111b,當閘極訊號Gb(n)切換至禁能位準時,資料電壓Vdatab寫入至子畫素單元111b。As shown in FIG. 8, in the period TP1, the
於時段TP2內,根據控制訊號CTLb致能多工器143及144。當控制訊號CTLb致能多工器143及144時,開關T11及開關T12導通,資料電壓Vdatar被傳送至多個子畫素單元111r、111g及111b。接著,當控制訊CTLb號切換至禁能位準時,開關T11及開關T12關斷,子資料電壓Vdatar寫入至畫素單元111r,不再被寫入其他資料電壓。接著,資料電壓Vdatag被傳送至子畫素單元111g及111b,當閘極訊號Ga(n+1)切換至禁能位準時,資料電壓Vdatag寫入至子畫素單元111g,不再被寫入其他資料電壓。接著,資料電壓Vdatab被傳送至子畫素單元111b,當閘極訊號Gb(n+1)切換至禁能位準時,資料電壓Vdatab寫入至子畫素單元111b。In the time period TP2, the
承上述,時段TP3的操作與時段TP1類似,時段TP4的操作與時段TP2類似,在此不再贅述。值得注意的是,時段TP1及TP2並沒有先後順序,也可以先執行時段TP2在執行時段TP1。再者,第3圖所示的時段為一個閘極訊號的致能時間,意即一個列時間(line time)。如第7圖所示,在此操作中,控制訊號CTLa及CTLb的致能時間間隔為區間X2。舉例而言,多工器電路140的操作頻率為55KHz,於第7圖所示的實施例中,區間X2即為27.5 KHz,因此多工器141~144的操作頻率為27.5 KHz,換句話說,多工器電路140的操作頻率由55 KHz降低至27.5 KHz。因此第7圖所示的實施例可以達到將多工器的致能訊號降頻的效果。In view of the above, the operation of the time period TP3 is similar to the time period TP1, and the operation of the time period TP4 is similar to the time period TP2, which will not be repeated here. It should be noted that there is no sequence for the time periods TP1 and TP2, and the time period TP2 can also be executed first and then the time period TP1. Furthermore, the time period shown in Figure 3 is the enable time of a gate signal, which means a line time. As shown in Fig. 7, in this operation, the enable time interval of the control signals CTLa and CTLb is the interval X2. For example, the operating frequency of the
綜上所述,本揭露之顯示裝置主要係利用多組多工器,在不同時段中致能不同組的多工器,來達到將致能訊號展頻或降頻的效果。再者,利用閘極訊號來控制部份子畫素單元的充電時間,因此可以進一步減少多工器中開關的數量。To sum up, the display device of the present disclosure mainly uses multiple sets of multiplexers to enable different sets of multiplexers in different time periods to achieve the effect of spreading or reducing the frequency of the enabling signal. Furthermore, the gate signal is used to control the charging time of some sub-pixel units, so the number of switches in the multiplexer can be further reduced.
在說明書及申請專利範圍中使用了某些詞彙來指稱特定的元件。然而,所屬技術領域中具有通常知識者應可理解,同樣的元件可能會用不同的名詞來稱呼。說明書及申請專利範圍並不以名稱的差異做為區分元件的方式,而是以元件在功能上的差異來做為區分的基準。在說明書及申請專利範圍所提及的「包含」為開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」在此包含任何直接及間接的連接手段。因此,若文中描述第一元件耦接於第二元件,則代表第一元件可通過電性連接或無線傳輸、光學傳輸等信號連接方式而直接地連接於第二元件,或者通過其他元件或連接手段間接地電性或信號連接至該第二元件。In the specification and the scope of the patent application, certain words are used to refer to specific elements. However, a person with ordinary knowledge in the relevant technical field should understand that the same element may be called by different terms. The specification and the scope of patent application do not use differences in names as a way to distinguish components, but use differences in functions of components as a basis for distinction. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or through other elements or connections. The means is indirectly connected to the second element electrically or signally.
另外,除非說明書中特別指明,否則任何單數格的用語都同時包含複數格的涵義。In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.
以上僅為本發明的較佳實施例,凡依本發明請求項所做的均等變化與修飾,皆應屬本發明的涵蓋範圍。The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.
100:顯示裝置100: display device
110:畫素電路110: pixel circuit
111,111a,111b,111c,111d,111de,111f,111r,111g:子畫素單元111,111a,111b,111c,111d,111de,111f,111r,111g: sub-pixel unit
120,120a,120b:閘極驅動電路120, 120a, 120b: gate drive circuit
130:源極驅動電路130: Source drive circuit
140:多工器電路140: Multiplexer circuit
141,142,143,144:多工器141, 142, 143, 144: multiplexer
GL,GLa,GLb,GL(n),GLa(n),GLb(n):閘極線GL, GLa, GLb, GL(n), GLa(n), GLb(n): gate line
DL,DL1~DL6:資料線DL, DL1~DL6: data line
AA:顯示區AA: Display area
PA:周邊區PA: Peripheral area
Vdata,Vdatar,Vdatag,Vdatab:資料電壓Vdata, Vdatar, Vdatag, Vdatab: data voltage
T1~T12:開關T1~T12: switch
CTLa,CTLa1,CTLa2,CTLb,CTLb1,CTLb2:控制訊號CTLa, CTLa1, CTLa2, CTLb, CTLb1, CTLb2: control signal
TP1~TP4:時段TP1~TP4: time period
X1~X3:區間X1~X3: interval
Ga(n),Gb(n),Ga(n+1),Gb(n+1),Ga(n+2),Gb(n+2),Ga(n+3),Gb(n+3):閘極訊號Ga(n),Gb(n),Ga(n+1),Gb(n+1),Ga(n+2),Gb(n+2),Ga(n+3),Gb(n+3 ): Gate signal
為讓揭示文件之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:
第1圖為根據本揭示文件一實施例的顯示裝置的示意圖;
第2圖為根據本揭示文件一實施例的多工器電路以及部份的畫素電路110的部分放大示意圖;
第3圖為根據本揭示文件一實施例的多工器電路的操作時序圖;
第4圖為根據本揭示文件一實施例的多工器電路的操作時序圖;
第5圖為根據本揭示文件一實施例的多工器電路的操作時序圖;
第6圖為根據本揭示文件一實施例的顯示裝置的示意圖;
第7圖為根據本揭示文件一實施例的多工器電路以及部份的畫素電路的部分放大示意圖;以及
第8圖為根據本揭示文件一實施例的多工器電路的操作時序圖。
In order to make the above and other purposes, features, advantages and embodiments of the disclosure document more obvious and understandable, the description of the accompanying drawings is as follows:
Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure;
FIG. 2 is a partially enlarged schematic diagram of the multiplexer circuit and part of the
100:顯示裝置 100: display device
110:畫素電路 110: pixel circuit
111:子畫素單元 111: Sub-pixel unit
120:閘極驅動電路 120: Gate drive circuit
130:源極驅動電路 130: Source drive circuit
140:多工器電路 140: Multiplexer circuit
141,142,143,144:多工器 141, 142, 143, 144: multiplexer
GL:閘極線 GL: Gate line
DL,DL1~DL6:資料線 DL, DL1~DL6: data line
AA:顯示區 AA: Display area
PA:周邊區 PA: Peripheral area
T1~T8:開關 T1~T8: switch
CTLa1,CTLa2,CTLb1,CTLb2:控制訊號 CTLa1, CTLa2, CTLb1, CTLb2: control signal
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TW201322227A (en) * | 2011-11-18 | 2013-06-01 | Au Optronics Corp | Display panel and source driving structure thereof |
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