TWI724979B - Class-d amplifier which can suppress differential mode power noise - Google Patents

Abstract

A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

Description

Class D amplifier capable of suppressing differential mode power supply noise

The present invention relates to a class D amplifier, and particularly relates to a class D amplifier that can suppress the noise of a differential mode power supply.

Traditionally, Class D amplifiers may have differential mode power noise and common mode power noise. In some cases, common-mode power supply noise may cause differential-mode power supply noise due to mismatched feedback paths.

However, to improve the matching of the feedback path requires additional silicon area. Therefore, high-performance Class D amplifiers require a design with high Power Supply Rejection Ratio (PSRR).

An object of the present invention is to provide a class D amplifier that can reduce the noise of the differential mode power supply without adjusting the matching of the feedback path.

An embodiment of the present invention discloses a class D amplifier for adjusting at least one input signal to at least one output signal, including: a loop filter for receiving the input signal; a pulse width modulation (PWM) circuit for adjusting at least one output signal To generate at least one PWM signal; an addition circuit coupled to an output of the loop filter and an input of the PWM circuit; an output circuit to generate the output signal in response to the PWM signal, wherein the output circuit operates On a supply voltage; and a supply voltage filter for monitoring the supply voltage to generate a filtered signal to the addition circuit. The addition circuit is used for adding the output of the loop filter to the filter signal to adjust a common mode level of the input of the PWM circuit.

Another embodiment of the present invention discloses a class D amplifier used to adjust at least one input signal to at least one output signal, including: a loop filter for receiving the input signal; and a PWM circuit coupled to the loop A filter for generating at least one PWM signal in response to a triangular wave signal; an output circuit operating under a supply voltage for generating the output signal in response to the PWM signal; and a supply voltage filter for monitoring the supply Voltage to generate a filtered signal; and a triangle wave adjustment circuit for adjusting a common mode level of the triangle wave signal corresponding to the filtered signal.

FIG. 1 shows a block diagram of a class D amplifier 100 according to an embodiment of the invention. As shown in Figure 1, the class D amplifier 100 is used to adjust (for example, amplify) the input signals V_ip, V_in to generate output signals V_op, V_on, and includes a loop filter 101, an addition circuit 103, and PWM (Pulse Width Modulation) Width modulation) circuit 105, output circuit 107 and supply voltage filter 109. In addition, the class D amplifier 100 further includes feedback paths P_1 and P_2 between the input of the loop filter 101 and the output of the output circuit 107.

The loop filter 101 is used to receive and filter the input signals V_ip, V_in. The addition circuit 103 is coupled to the output of the loop filter 101 and the input of the PWM circuit 105 to add the output of the loop filter 101 and the filtered signal FS from the supply voltage filter 109 to adjust the input signal of the PWM circuit 105 Common mode level (ie, the average voltage of the voltage swing of the input signal). The PWM circuit 105 is used for modulating the output from the adding circuit 103 into PWM signals PW_p and PW_n in response to the triangular wave signal Tr. The output circuit 107 operating under the supply voltage PVDD is used to generate output signals V_op and V_on according to the PWM signals PW_p and PW_n. The supply voltage filter 109 is used to monitor the supply voltage PVDD to generate a filtered signal FS to the adding circuit 103. Please also note that the output circuit 107 and/or the PWM circuit 105 can also operate under the supply voltage PVDD.

。也就是說，高通截止頻率f_H可以是

，N是正整數。 The supply voltage filter 109 may be a band pass filter, as shown in FIG. 2. In an embodiment, the low-pass cutoff frequency f_L of the supply voltage filter 109 is lower than or equal to the audio signal frequency (for example, 20 Hz). In addition, in an embodiment, the high-pass cutoff frequency f_H of the supply voltage filter 109 depends on the modulation frequency of the PWM circuit 107. For example, the PWM circuit 107 modulates the output of the addition circuit 103 into PWM signals PW_p and PW_n in response to the clock signal with the adjusted frequency fc, and the high-pass cutoff frequency f_H is less than or equal to

. In other words, the high-pass cutoff frequency f_H can be

, N is a positive integer.

Figures 3 and 4 show detailed circuit diagrams of the class D amplifier in Figure 1 according to different embodiments of the present invention. Please note that the circuits in FIGS. 3 and 4 are only examples, and are not intended to limit the scope of the present invention. Any circuit that can achieve the same function should also fall within the scope of the present invention.

In the embodiment of FIG. 3, the PWM circuit 105 includes a first PWM input and a second PWM input. Furthermore, the addition circuit 103 includes amplifiers a_p1, a_p2, a_n1, a_n2, a first adder A_1 and a second adder A_2. The gains of the amplifiers a_p1, a_p2, a_n1, and a_n2 may be equal to or greater than 1. In addition, the amplifiers a_p1 and a_n2 amplify the filtered signal FS, and the amplifiers a_p2 and a_n1 amplify the output signal of the loop filter 101. The first adder A_1 adds the amplified signal of the amplifier a_P1 and the amplified signal of the amplifier a_P2 to generate the common mode level of the first input signal of the PWM circuit 105. The second adder A_2 adds the amplified signal of the amplifier a_n1 and the amplified signal A_n2 of the amplifier a_n2 to generate the common mode level of the second input signal of the PWM circuit 105. Therefore, the output of the adders A_1 and A_2 can reflect the change from the filtered signal FS.

FIG. 4 is a more detailed circuit of the circuit of the class D amplifier 100 shown in FIG. 3 according to an embodiment of the present invention. As shown in FIG. 4, the loop filter 101 includes resistors R_1i, R_2i, R_1z, R_2z, capacitors C_1a, C_1b, C_2a, C_2b, and an operational amplifier OP_1. Furthermore, the addition circuit 103 includes resistors R_1a, R_1b, R_2a, and R_2b. The PWM circuit 105 includes comparators CM_1 and CM_2. The comparators CM_1 and CM_2 respectively include a negative input terminal for receiving the triangular wave signal Tr and a positive input terminal for receiving the output from the addition circuit 103. The output circuit 107 may have various conventional circuit structures well known to those skilled in the art, which will not be repeated here for the sake of brevity. In addition, the supply voltage filter 109 includes an operational amplifier OP_2, resistors R_c1, R_c2, and capacitors C_LP, C_HP. Furthermore, in the embodiment of FIG. 4, the feedback paths P_1 and P_2 include resistors R_1f and R_2f, respectively.

Fig. 5 shows a waveform diagram of the class D amplifier in Fig. 4 according to an embodiment of the present invention. In this embodiment, the supply voltage PVDD represents the supply voltage received by the supply voltage filter 109 and the output circuit 107. The voltage V_opx1 represents the voltage on the connection end of the capacitor C_1b and the resistor R_1a, and the voltage V_onx1 represents the voltage on the connection end of the capacitor C_2b and the resistor R_2a. In addition, the voltage V_opx2 refers to the voltage on the connection end of the resistors R_1a and R_1b, and the voltage V_onx2 refers to the voltage on the connection end of the resistors R_2a and R_2b. In addition, the signals V_opi and V_oni represent output signals that will be generated by the output circuit 107 without being processed (for example, filtered) by the supply voltage filter 109. In addition, the output signals V_op and V_on represent output signals generated by the output circuit 107 after being processed by the addition circuit 103 and the supply voltage filter 109.

As shown in Figure 5, the supply voltage PVDD may have ripples, and part or all of the phase of the filtered signal FS is opposite to the supply voltage PVDD. Moreover, the amplitude of the filtered signal FS is proportional to the supply voltage PVDD. In addition, the PWM signals PW_p and PW_n are generated by processing the signals V_opx2 and V_onx2 with the triangular wave signal TR. Since the signals V_opx2 and V_onx2 change corresponding to the filtered signal FS, the duty cycles of the PWM signals PW_p and PW_n also change corresponding to the filtered signal FS. In other words, the duty ratios of the PWM signals PW_p and PW_n can vary in accordance with the ripple of the supply voltage PVDD. Therefore, since the duty cycle of the PWM signals PW_p and PW_n can be changed corresponding to the ripple of the supply voltage PVDD, the interference caused by the ripple of the supply voltage PVDD to the output signals V_op and V_on can be eliminated.

In addition to adjusting the common mode level of the input signal of the PWM circuit 105, the common mode level of the triangular wave signal can also be adjusted to compensate for the influence caused by the ripple of the supply voltage PVDD, so as to achieve the same effect. Fig. 6 shows a block diagram of a class D amplifier according to another embodiment of the present invention. As shown in FIG. 6, the class D amplifier 600 includes a loop filter 601, a PWM circuit 603, an output circuit 605, a supply voltage filter 607, and a triangle wave adjustment circuit 609. Moreover, the class D amplifier 600 also includes feedback paths P_1 and P_2 between the loop filter 601 and the output circuit 605. The loop filter 601, the PWM circuit 603, and the output circuit 605 may include the same circuit configuration as the loop filter 101, the PWM circuit 105, and the output circuit 107 shown in FIG. 1.

The loop filter 601 is used to receive input signals V_ip, V_in. The PWM circuit 603 is coupled to the output of the loop filter 601 and used to generate a PWM signal in response to the triangular wave signal Tr. The output circuit 605 operating under the supply voltage PVDD is used to generate output signals V_op and V_on in response to the PWM signals PW_p and PW_n. The supply voltage filter 607 is used to monitor the supply voltage PVDD to generate the filtered signal FS. In addition, the triangle wave adjustment circuit 609 is used to adjust the common mode level of the triangle wave signal Tr corresponding to the filter signal FS. The triangle wave generating circuit 611 is used to generate a triangle wave signal Tr.

。即，高通截止頻率f_H可以是

，N是正整數。 The supply voltage filter 607 may be a band pass filter, as shown in FIG. 2. In an embodiment, the low-pass cutoff frequency f_L of the supply voltage filter 607 is lower than or equal to the audio signal frequency (for example, 20 Hz). Similarly, in one embodiment, the high-pass cutoff frequency f_H of the supply voltage filter 607 depends on the modulation frequency of the PWM circuit 603. For example, the PWM circuit 603 modulates the output of the loop filter 601 into a PWM signal PW_p and a PWM signal PW_n in response to a clock signal with a modulation frequency fc, and the high-pass cutoff frequency f_H is less than or equal to

. That is, the high-pass cutoff frequency f_H can be

, N is a positive integer.

In addition, in another embodiment, the supply voltage filter 607 is a low-pass filter, as shown in FIG. 7. The high-pass cutoff frequency f_H of the supply voltage filter 607 is less than or equal to the modulation frequency of the PWM circuit. In this case, the circuit of the supply voltage filter 607 can be designed to ensure that the operational amplifier in the supply voltage filter 607 can receive an appropriate voltage. The details of the supply voltage filter 607 as a low-pass filter will be described later.

Figures 8 and 9 show detailed circuit diagrams of the class D amplifier in Figure 6 according to different embodiments of the present invention. Please also note that the circuits in Figs. 8 and 9 are only examples and are not meant to limit the scope of the present invention. Any circuit that can achieve the same function should also fall within the scope of the present invention. The supply voltage filter 607 is a band-pass filter in the embodiment of FIG. 8 and a low-pass filter in the embodiment of FIG. 9.

In the embodiment of FIG. 8, the loop filter 601 includes resistors R_1i, R_2i, R_1z, R_2z, capacitors C_1a, C_1b, C_2a, C_2b, and an operational amplifier OP_1. The PWM circuit 603 includes comparators CM_1 and CM_2. The comparators CM_1 and CM_2 respectively include a negative input terminal for receiving the triangular wave signal Tr and a positive input terminal for receiving the output from the loop filter 601. The output circuit 605 may have various conventional circuit structures well known to those skilled in the art, and will not be repeated here for the sake of brevity. In addition, the supply voltage filter 607 includes an operational amplifier OP_2, resistors R_c1, R_c2, R_c3, R_c4, and capacitors C_LP1, C_LP2, C_HP. In addition, in this case, the amplitude of the filter signal FS is proportional to the amplitude of the supply voltage PVDD, and the phase of the filter signal FS is proportional to the phase of the supply voltage instead of being opposite.

In addition, in the embodiment of FIG. 8, the triangle wave adjustment circuit 609 includes an adder AD, which adds the initial common mode level of the triangle wave signal Tr to the filtered signal FS to generate the current common mode level of the triangle wave signal Tr. PWM circuit 603. In this embodiment, the initial common mode level (V_cmi) of the triangular wave signal is set to 1/2 VP, and the signal V_cm is the sum of the initial common mode level V_cmi and the filtered signal FS. Therefore, the phase of the signal V_cm is proportional to the phase of the supply voltage PVDD. If the positive ripple of the supply voltage PVDD increases, the signal V_cm also increases, so that the triangular wave signal Tr moves upward. In this way, the duty ratios of the PWM signals PW_p, PW_n are correspondingly reduced to offset the influence caused by the positive ripple of the supply voltage PVDD.

。在本實施例中，運算放大器OP_2的輸出電壓作為三角波信號Tr的當前共模位準。因此，如果三角波信號Tr的電壓擺幅為Vp，則可以透過比例R_c1/R_c2來產生電壓Vp / 2。即，低通濾波器607的輸出電壓用於設定三角波信號Tr的共模位準。此外，在某些情況下，從供應電壓PVDD到PWM電路603的電源雜訊消除增益可能小於比例R_c1/R_c2，因此三角波調整電路609還包含電阻R_a2，該電阻R_a2接收另一個電壓V_opcm（設定電壓）。如此，藉由電壓V_opcm，可以提高三角波信號Tr的共模位準。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 In the embodiment of Fig. 9, the supply voltage filter 607 does not include the capacitor C_HP shown in Fig. 7. Therefore, the supply voltage filter 607 is a low-pass filter instead of a band-pass filter. In this case, the output voltage of the operational amplifier OP_2 is equal to

. In this embodiment, the output voltage of the operational amplifier OP_2 is used as the current common mode level of the triangular wave signal Tr. Therefore, if the voltage swing of the triangular wave signal Tr is Vp, the voltage Vp/2 can be generated through the ratio R_c1/R_c2. That is, the output voltage of the low-pass filter 607 is used to set the common mode level of the triangular wave signal Tr. In addition, in some cases, the power noise cancellation gain from the supply voltage PVDD to the PWM circuit 603 may be less than the ratio R_c1/R_c2, so the triangle wave adjustment circuit 609 also includes a resistor R_a2, which receives another voltage V_opcm (set voltage ). In this way, with the voltage V_opcm, the common mode level of the triangular wave signal Tr can be increased. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

100, 600: Class D amplifier 101, 601: Loop filter 103: addition circuit 105: PWM circuit 107, 605: output circuit 109, 607: Supply voltage filter 603: PWM circuit 609: Triangle wave adjustment circuit 611: Triangle wave generating circuit AD: adder a_p1, a_p2, a_n1, a_n2: amplifier A_1: first adder A_2: Second adder P_1, P_2: feedback path R_1i, R_2i, R_1z, R_2z, R_c1, R_c2, R_1a, R_1b, R_2a: resistance R_2b, R_1f, R_2f, R_c3, R_c4, R_a1, R_a2: resistance C_1a, C_1b, C_2a, C_2b, C_LP, C_LP1, C_LP2, C_HP: capacitance OP_1, OP_2: operational amplifier CM_1, CM_2: comparator

Figure 1 shows a block diagram of a class D amplifier according to an embodiment of the invention. FIG. 2 shows a schematic diagram of the operation of the supply voltage filter in FIG. 1 according to an embodiment of the present invention. Figures 3 and 4 show detailed circuit diagrams of the class D amplifier in Figure 1 according to different embodiments of the present invention. Fig. 5 shows a waveform diagram of the class D amplifier in Fig. 4 according to an embodiment of the present invention. Fig. 6 shows a block diagram of a class D amplifier according to another embodiment of the present invention. FIG. 7 is a schematic diagram of the operation of the supply voltage filter in FIG. 6 according to an embodiment of the present invention. Figures 8 and 9 show detailed circuit diagrams of the class D amplifier in Figure 6 according to different embodiments of the present invention.

100: Class D amplifier

101: Loop filter

103: addition circuit

105: PWM circuit

107: output circuit

109: Supply voltage filter

P_1 and P_2: feedback path

Claims (14)

A class D amplifier for adjusting at least one input signal to at least one output signal, including: A loop filter to receive the input signal; A pulse width modulation (PWM) circuit for generating at least one PWM signal; An addition circuit, coupled to an output of the loop filter and an input of the PWM circuit; An output circuit for generating the output signal in response to the PWM signal, wherein the output circuit operates on a supply voltage; and A supply voltage filter for monitoring the supply voltage to generate a filtered signal to the addition circuit; The addition circuit is used for adding the output of the loop filter to the filter signal to adjust a common mode level of the input of the PWM circuit. The class D amplifier according to claim 1, wherein the supply voltage filter is a band pass filter. The class D amplifier according to claim 2, wherein a low-pass cutoff frequency of the supply voltage filter is lower than or equal to an audio signal frequency. The class D amplifier according to claim 2, wherein a high-pass cut-off frequency of the supply voltage filter depends on a modulation frequency of the PWM circuit. The class D amplifier of claim 2, wherein part or all of the phase of the filtered signal is opposite to the supply voltage, and the amplitude of the filtered signal is proportional to the supply voltage. The class D amplifier according to claim 1, wherein the PWM circuit includes a first PWM input and a second PWM input, and the addition circuit includes: A first amplifier for receiving the filtered signal; A second amplifier for receiving the filtered signal; A third amplifier for receiving a first output signal of the loop filter; A fourth amplifier for receiving a second output signal of the loop filter; A first adder for adding an amplified signal of the first amplifier and an amplified signal of the third amplifier to generate the common mode level of the first PWM input of the PWM circuit; and A second adder is used for adding an amplified signal of the fourth amplifier and an amplified signal of the second amplifier to generate the common mode level of the second PWM input of the PWM circuit. A class D amplifier is used to adjust at least one input signal to at least one output signal, including: A loop filter to receive the input signal; A PWM circuit, coupled to the loop filter, for generating at least one PWM signal in response to a triangular wave signal; An output circuit operating under a supply voltage for generating the output signal in response to the PWM signal; A supply voltage filter for monitoring the supply voltage to generate a filtered signal; and A triangle wave adjustment circuit is used to adjust a common mode level of the triangle wave signal corresponding to the filtered signal. The class D amplifier according to claim 7, wherein the supply voltage filter is a band pass filter. The class D amplifier according to claim 8, wherein a low-pass cutoff frequency of the supply voltage filter is lower than or equal to an audio signal frequency. The class D amplifier according to claim 8, wherein a high-pass cutoff frequency of the supply voltage filter depends on a modulation frequency of the PWM circuit. The class D amplifier according to claim 8, wherein the amplitude of the filtered signal is proportional to the supply voltage. The class D amplifier according to claim 7, wherein the supply voltage filter is a low-pass filter. The class D amplifier according to claim 12, wherein a high-pass cutoff frequency of the supply voltage filter is less than or equal to a modulation frequency of the PWM circuit. The class D amplifier according to claim 12, wherein the triangle wave adjustment circuit includes: A first resistor for receiving the filtered signal to adjust the common mode level of the triangular wave signal; and A second resistor is used for receiving a setting voltage to adjust the common mode level of the triangular wave signal.

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