TWI722343B - Computer and central processing unit for mining of virtual currencies - Google Patents

Abstract

The present application provides a computer for mining of virtual currencies. The computer comprises a central processing unit including a computing core, which is configured to retrieve a first input data and a second input data from a first server and a second server with regard to a first mining algorithm and a second mining algorithm, respectively; have a first auxiliary computing logic execute the first mining algorithm according to the first input data; and have a second auxiliary computing logic execute the second mining algorithm according to the second input data. The first auxiliary computing logic and the central processing unit are installed on one board. After the assigned first mining algorithm is done, the first auxiliary computing logic sends an interrupt signal to the computing core.

Description

Computer and central processing unit for multiple virtual currency mining

The present invention relates to a computer structure, and particularly relates to a computer structure of virtual currency mining.

Virtual currencies such as Bitcoin and Ethereum have entered the lives of modern people in recent years, using the shared public ledger accounting method of the blockchain to achieve transactions. Taking Bitcoin as an example, all transactions will be announced between users and confirmed by mining programs on the network within a period of time. Mining is a decentralized consensus system used to confirm transactions and add them to the blockchain. Mining can ensure the time sequence of the blockchain, protect the neutrality of the network, and allow different computers to reach a consensus on the state of the system.

Mining is deliberately designed to consume computational resources very much in order to ensure that the blocks found by miners every day are stable. Each block must contain a proof of work, and the proof of work will be verified by other nodes when they receive the block. The main purpose of mining is to ensure that the transaction history cannot be modified by any single node. By downloading and verifying the blockchain, nodes can reach a consensus on the sequence of transaction history events. Mining is also used to increase the virtual currency in the system. When there is any new virtual currency, miners will get transaction fees as dividends. The above two can send new virtual currency in a decentralized situation, and can also motivate people to provide security for the system.

As mining consumes computing resources, the computing resources of mining computers have shifted from a general-purpose central processing unit to a graphics processor for drawing. In addition, there are field programmable logic gate arrays (FPGA) and application-specific integrated circuits (ASIC) specially designed for a certain type of virtual currency mining program. These methods are to improve the mining resources of a single mining computer for a single virtual currency.

However, for some virtual currencies, due to the limited output of new blocks and a large number of competitors, the benefits of mining are gradually decreasing. If the mining computer only mines for a certain type of virtual currency, it may not conform to the economic effect. If the mining computer can simultaneously mine two or more virtual currencies at the same time, it can reduce purchase costs and increase mining revenue.

According to an embodiment of the present invention, a computer for multiple virtual currency mining is provided, including: a network interface for connecting a first server and a second server on the network; and a first auxiliary calculation logic The circuit is used to execute the first mining algorithm; a second auxiliary calculation logic circuit is used to execute the second mining algorithm; and a central processing unit. The central processing unit includes: a first communication interface for connecting to the first auxiliary calculation logic circuit; a second communication interface for connecting to the second auxiliary calculation logic circuit; and a network communication port for connecting to the A network interface; and a computing core connected to the above-mentioned first communication interface, second communication interface and network communication port. The computing core is used to obtain the first input data and the second input of the first mining algorithm and the second mining algorithm from the first server and the second server through the network communication port. Data; using the first auxiliary calculation logic circuit to execute the first mining algorithm according to the first input data; and using the second auxiliary calculation logic circuit to execute the second mining algorithm according to the second input data. Wherein, the first auxiliary calculation logic circuit and the central office The processor is installed on the same circuit board, and the first auxiliary calculation logic circuit sends an interrupt signal to the calculation core when the allocated first mining algorithm is completed.

In this embodiment, in order to connect the first auxiliary calculation logic circuit or the second auxiliary calculation logic circuit, the first communication interface or the second communication interface includes one of the following hardware interfaces: a plurality of general-purpose I/O ports ( GPIO); Peripheral interface in the form of serial transmission; Peripheral interface in the form of parallel transmission; Universal Asynchronous Transceiver (UART); and Serial Peripheral Interface (SPI).

In this embodiment, in order to use the first auxiliary calculation logic circuit and the second auxiliary calculation logic circuit of different interfaces, the first communication interface and the second communication interface include different hardware interfaces.

In this embodiment, in order to shorten the physical distance between the two to increase the anti-interference ability, the first auxiliary calculation logic circuit is an independent package, and the central processing unit and the first auxiliary calculation logic circuit are installed On the same circuit board.

In this embodiment, in order to further shorten the physical distance between the two so as to increase the anti-interference ability and reduce the assembly problems of the system manufacturer, the central processing unit and the first auxiliary computing logic circuit are respectively located on different chips , But belong to the same package.

In this embodiment, in order to send a hardware interrupt signal to the computing core, the interrupt signal is sent to the computing core by the first auxiliary computing logic circuit through at least one port of the first communication interface including a plurality of universal I/O ports. .

In this embodiment, in order to present an interrupt signal to the computing core, the interrupt signal includes at least one of the following: a hardware interrupt signal; and a software specified in the software communication protocol transmitted through the plurality of general-purpose I/O ports Interrupt signal.

In this embodiment, in order to increase the spatial density of calculation, the central processing unit and the second auxiliary calculation logic circuit are respectively located on different circuit boards.

According to the present invention, a central processing unit as in the above-mentioned various embodiments is provided.

According to the computer and the central processing unit provided by the present invention, the computer can simultaneously mine two or more virtual currencies at the same time, thereby reducing the purchase cost and increasing the mining income.

100‧‧‧Computer

110‧‧‧Central Processing Unit

111‧‧‧Compute Core

112‧‧‧First communication interface

113‧‧‧Second communication interface

114‧‧‧Memory Controller

115‧‧‧Network communication port

120‧‧‧The first auxiliary calculation logic circuit

130‧‧‧Second auxiliary calculation logic circuit

140‧‧‧Memory chip

150‧‧‧Network Interface

200‧‧‧Calculation method

210~260‧‧‧Step

300‧‧‧Calculation method

310~390‧‧‧Step

FIG. 1 is a block diagram of a computer according to an embodiment of the invention.

FIG. 2 is a schematic flowchart of a calculation method according to an embodiment of the present invention.

FIG. 3 is a schematic flowchart of a calculation method according to another embodiment of the present invention.

Some embodiments of the present invention will be described in detail as follows. However, in addition to the disclosed embodiments, the present invention can also be widely used in other embodiments. The scope of the present invention is not limited by these embodiments, but the scope of subsequent patent applications shall prevail. In order to provide a clearer description and enable those familiar with the art to understand the content of the present invention, the various parts in the figure are not drawn according to their relative dimensions, and the ratios of certain dimensions to other relevant dimensions will be highlighted. It seems exaggerated, and the irrelevant details are not completely drawn in order to keep the diagram concise. In addition, among the steps shown in the flowcharts of the present invention, other steps that are not related to the present invention can be inserted. Unless there is a causal dependence, the present invention does not limit the execution order of each step.

Please refer to FIG. 1, which is a block diagram of a computer 100 according to an embodiment of the present invention. The computer 100 includes a central processing unit 110, one or more first auxiliary computers The calculation logic circuit 120, one or more second auxiliary calculation logic circuits 130, one or more memory chips 140, and a network interface 150.

In an embodiment, the first auxiliary calculation logic circuit 120 may be a logic circuit particularly suitable for calculating the first type of mining algorithm, and the second auxiliary calculation logic circuit 130 may be particularly suitable for calculating the second type of mining algorithm. The logic circuit of the algorithm. In another embodiment, the first auxiliary calculation logic circuit 120 may be a general-purpose auxiliary calculation logic circuit, which is set to be suitable for calculating the first mining algorithm through software or firmware. Similarly, the second auxiliary calculation logic circuit 130 can also be a general-purpose auxiliary calculation logic circuit, which is set to be suitable for calculating the second mining algorithm through software or firmware. The first type of mining algorithm corresponds to the first type of virtual currency, and the second type of mining algorithm corresponds to the second type of virtual currency.

The first auxiliary calculation logic circuit 120 or the second auxiliary calculation logic circuit 130 may be a field programmable logic gate array (FPGA), or may be an application-specific integrated circuit (ASIC). It can have an internal state-machine, as well as a program counter and related registers, which are used to autonomously execute the first or second mining algorithm after receiving mining input data , And get the result corresponding to the mining input data.

The network interface 150 is used to connect to external servers. The network interface 150 may be a wired or wireless interface that complies with industry standards, such as IEEE 802.3, IEEE 802.11, 3GPP 3G/4G/5G UTRAN, Bluetooth, USB, Wireless USB, Zigbee, etc. The network interface 150 can be connected to the nodes corresponding to each virtual currency through the network to obtain mining input data. The central processing unit 110 may include a network communication port 115 to connect to the network interface 150.

The memory chip 140 may include dynamic memory (DRAM) and programmable erasable read-only memory (EEPROM). The dynamic memory system is used as the system memory of the central processing unit 110 The body is used to support the central processing unit 110 to execute the operating system and application programs. Programmable erasing read-only memory is used to store the above-mentioned operating system and applications, as well as other settings.

The central processing unit 110 may include one or more computing cores 111 (core) for executing the above-mentioned operating system and application programs. The present invention does not limit the form of the instruction set supported by the computing core 111, which may be a reduced instruction set computer (RISC) or a complex instruction set computer (CISC). The former includes the ARM instruction set of Amou, while the latter includes the x86 and x64 instruction sets of Intel Corporation. The central processing unit 110 may include various levels of cache memory. For example, it may include L1 cache, L2 cache, and L3 cache. The present invention does not limit the form and level of cache memory.

The computing core 111 can be used to execute the third mining algorithm, which corresponds to the third virtual currency. In addition, the computing core 111 can also be used to execute the first mining algorithm and/or the second mining algorithm. In an embodiment, when the central processing unit 110 includes a plurality of computing cores 111, each computing core 111 can be made to execute a different mining algorithm. In another embodiment, when the central processing unit 110 includes only one computing core 111, the only computing core 111 can also be used to execute different mining algorithms in a time division multiplexing manner.

The central processing unit 110) includes a first communication interface 112 for connecting the one or more first auxiliary calculation logic circuits 120. The central processing unit 110 includes a second communication interface 113 for connecting to the one or more second auxiliary calculation logic circuits 130. Since the mining algorithm is an algorithm that requires a large amount of computing resources but does not require a large amount of input and output data, the first communication interface 112 and the second communication interface 113 may be low-speed connection interfaces. For example, their transmission rate can be millions of Hertz per second (MHz) or lower, that is, they can support various mining algorithms.

In the present invention, the first communication interface 112 and the second communication interface 113 It can be an interface composed of multiple general-purpose output ports (GPIO), a peripheral interface in the form of serial transmission, and various peripheral interfaces or buses in the form of parallel transmission, such as DB-25. It includes a universal asynchronous transceiver (UART), such as RS-232, RS-422, RS-423, RS-449, RS-485, etc., and it can also include a serial peripheral interface (SPI) bus.

In one embodiment, when the second communication interface 113 is the master of the serial peripheral interface bus, a plurality of second auxiliary calculation logic circuits 130 may be connected to the same bus at the same time, as a plurality of slaves. Slave. The master can select one of the multiple controlled terminals through multiple selection signals (Slave Selected).

The first communication interface 112 and the second communication interface 113 may be interfaces of the same form, or may be interfaces of different forms. The aforementioned first communication interface 112 and second communication interface 113 refer to standard hardware-level interfaces. On the standard interface of the hardware level, the computing core 111 and the first auxiliary computing logic circuit 120 can communicate through a dedicated software communication protocol. The so-called proprietary software communication protocol is a communication protocol between the computing core 111 and the first auxiliary computing logic circuit 120. The software communication protocol can include but is not limited to the following functions: transmitting the input data required by the first mining algorithm; receiving the output data calculated by the first mining algorithm; starting the calculation of the first mining algorithm; closing Operation of the first mining algorithm; and query whether the first auxiliary calculation logic circuit 120 has completed the operation of the first mining algorithm.

On some forms of communication interface 112, the computing core 111 must periodically query whether the first auxiliary calculation logic circuit 120 has completed the calculation after starting the calculation of the first mining algorithm of the first auxiliary calculation logic circuit 120. When the calculation has not been completed, the computing core 111 must query again in the next query cycle. In other words, the computing core 111 wastes precious time on queries. When the calculation is completed, but before the calculation core 111 has not inquired, the first auxiliary calculation logic The computing resources of the circuit 120 are left unused, and the calculation of the first mining algorithm in the next round cannot be performed. For example, when the aforementioned universal asynchronous transceiver or serial peripheral interface is used as the first communication interface 112, a regular query mechanism must be adopted.

On some other forms of communication interface 112, the first auxiliary computing logic circuit 120 can issue an interrupt request to the computing core through one or more ports of the hardware, so as to indicate the status of the first auxiliary computing logic circuit 120. The calculation has been completed, or other matters that need to be reported to the computing core 111. The interrupt request may be a pure hardware interrupt, for example, an interrupt may be issued through at least one port of a universal I/O port, or an interrupt may be issued through more than two ports. The interrupt request can also be a more complicated hardware and software interrupt. For example, the first auxiliary calculation logic circuit 120 first sends a hardware interrupt notification to the calculation core, and then through the software communication protocol between the calculation core 111 and the first auxiliary calculation logic circuit 120, the calculation core 111 knows that the calculation has been completed. The first auxiliary calculation logic circuit 120 receives output data and prepares for the next round of calculations. When the interrupt request is used to notify the computing core 111, the idle time of the aforementioned periodic query can be reduced.

The interrupt signal can have a priority order. When the computer 100 has multiple first auxiliary calculation logic circuits 120 and/or second auxiliary calculation logic circuits 130, different priority orders can be set for these first auxiliary calculation logic circuits 120 and/or second auxiliary calculation logic circuits 130 Interrupt request. When the computing core 111 is processing a lower priority interrupt request, it can be interrupted by a higher priority interrupt request. When the computing core 111 is processing an interrupt request with a higher priority, it cannot be interrupted by an interrupt request with a lower priority or the same priority. In an embodiment, the interrupt request priority order of the first auxiliary calculation logic circuit 120 is higher than that of the second auxiliary calculation logic circuit 130 or vice versa. In one embodiment, all the first auxiliary calculation logic circuits The priority order of 120 interrupt requests is the same. In another embodiment, the interrupt request priority order of all the second auxiliary calculation logic circuits 130 is the same.

Since the first communication interface 112 may be interfered by the computer 100 itself or various signals around it, if the line length of the first communication interface 112 can be shortened, interference can be more effectively resisted. In an embodiment, one or more of the first auxiliary calculation logic circuit 120 and the central processing unit 110 may be mounted on the same circuit substrate, so as to shorten the line length of the first communication interface 112 and improve the anti-interference ability. In another embodiment, one or more of the first auxiliary calculation logic circuit 120 may be implemented on a chip and packaged in the same package as another chip of the central processing unit 110. Both can be distributed and connected through the same circuit board.

In an embodiment, the first communication interface 112 may also include the aforementioned universal asynchronous transceiver or serial peripheral interface, and a connection line for raising a hardware interrupt signal, so as to implement the aforementioned software and hardware interrupt. In another embodiment, the second communication interface 113 and the second auxiliary calculation logic circuit can also be applied to the aforementioned first communication interface 112 embodiment.

In an embodiment, in order to achieve high-density calculations, the plurality of second auxiliary calculation logic circuits 130 may be mounted on another circuit board different from the central processing unit 110. Each arithmetic sub-board may include a plurality of auxiliary calculation logic circuits 130, and the computer 100 may include a plurality of arithmetic sub-boards. In this way, as many second auxiliary calculation logic circuits 130 as possible can be placed in a small space, so as to save space resources.

The central processing unit 110 may include a memory controller 114 for connecting to the aforementioned one or more memory chips 140. The two can follow the existing industry standard interfaces, such as the double data rate synchronous dynamic random access memory (DDR) defined by the JEDEC Solid State Technology Association. SDRAM) specifications. Since a mining algorithm may require a large amount of memory resources, the computing core 111 that executes one or more mining algorithms can use multiple memory chips 140 to support the calculation of one or more mining algorithms. The more types of mining algorithms are calculated, the more memory chips 140 are needed. Or when the number of computing cores 111 is greater, the number of mining algorithms that can be executed simultaneously is greater.

Due to the electrical specifications of the memory interface, when the physical distance between the memory controller 114 and the memory chip 140 is shorter, the signal will not be distorted. The transmission distance between multiple signals will not differ too much, and the transmission clock needs to be reduced to compensate for the difference. And the anti-interference ability is also better. Therefore, in one embodiment, although the aforementioned one or more memory chips 140 and the CPU 110 belong to different packages, they can be mounted on the same circuit substrate to increase the transmission bandwidth. In another embodiment, the central processing unit 110, the first auxiliary computing logic circuit 120 and the memory chip 140, which belong to different packages, are all mounted on the same circuit substrate. In another embodiment, the central processing unit 110, the first auxiliary calculation logic circuit 120 and the memory chip 140 are all mounted on the same circuit substrate and packaged in the same package.

Please refer to FIG. 2, which is a schematic flowchart of a calculation method 200 for mining multiple virtual currencies according to an embodiment of the present invention. The computing method 200 can be implemented by an application program, and at least one computing core 111 shown in FIG. 1 is responsible for executing the application program. In addition, the application can also be a multi-threaded application. That is, there can be multiple program counters, which can be executed on multiple computing cores 111 at the same time or on one computing core 111 in a time division multiplexing manner. Unless otherwise specified, the present invention does not limit the execution order of each step.

Step 210: Separately from the first server and the second server through the network communication port The server obtains first input data and second input data of the first mining algorithm and the second mining algorithm.

Optional step 215: Obtain the third input data of the third mining algorithm from the third server through the network communication port.

Step 220: Use the first auxiliary calculation logic circuit to execute the first mining algorithm according to the first input data.

Step 230: Use the second auxiliary calculation logic circuit to execute the second mining algorithm according to the second input data.

Optional step 240: the computing core executes the third mining algorithm according to the third input data to obtain the corresponding third output data.

Step 250: Accept an interrupt signal sent by the first auxiliary calculation logic circuit. The step 250 may also include receiving first output data corresponding to the first input data from the first auxiliary calculation logic circuit.

Step 260: Periodically inquire whether the second auxiliary calculation logic circuit has completed the work of the second mining algorithm. If completed, step 260 may also include receiving second output data corresponding to the second input data from the second auxiliary calculation logic circuit.

Please refer to FIG. 3, which is a schematic flowchart of a calculation method 300 for mining multiple virtual currencies according to an embodiment of the present invention. The computing method 300 can be implemented by an application program, and at least one computing core 111 shown in FIG. 1 is responsible for executing the application program. In addition, the application can also be a multi-threaded application. That is, there can be multiple program counters, which can be executed on multiple computing cores 111 at the same time or on one computing core 111 in a time division multiplexing manner. Unless otherwise specified, the present invention does not limit each step The order of execution of the steps.

In an embodiment, the calculation method 300 may be performed by three threads, which are respectively responsible for the sub-processes of steps 310, 320, and 330. In another embodiment, the calculation method 300 can be performed by three applications, which are respectively responsible for the sub-processes of steps 310, 320, and 330, and the operating system is responsible for scheduling these three applications.

Step 310: Obtain the first input data of the first mining algorithm from the first server through the network communication port.

Step 320: Obtain the second input data of the second mining algorithm from the second server through the network communication port.

Optional step 330: Obtain the third input data of the third mining algorithm from the third server through the network communication port.

Step 340: Use the first auxiliary calculation logic circuit to execute the first mining algorithm according to the first input data.

Step 350: Accept an interrupt signal sent by the first auxiliary calculation logic circuit. The step 350 may also include receiving first output data corresponding to the first input data from the first auxiliary calculation logic circuit. Then, the process returns to step 310 to continue to download the first input data of the next round.

Step 360: Inquire whether the second auxiliary calculation logic circuit has completed the work of the second mining algorithm. When it has not been completed, the flow continues to step 370. When the work has been completed, the flow continues to step 380.

Step 370: Wait for a period of time, and then the process returns to step 360.

Step 380: Receive from the second auxiliary calculation logic circuit corresponding to the second input The second output data of the data. Then, the process returns to step 320 to continue to download the second input data of the next round.

Optional step 390: the computing core executes the third mining algorithm according to the third input data to obtain the corresponding third output data. Then, the process returns to step 330 to continue to download the third input data of the next round.

In the variation of the embodiment of FIG. 2 and FIG. 3, it is possible to download multiple pieces of input data at a time so as to provide multiple rounds of mining algorithms for calculation work, instead of downloading only one piece of input data for work. In addition, the downloading step can also be executed at the same time as the algorithmic operation step, that is, the input data can be downloaded in advance when the previous round of algorithmic operation is not completed.

According to an embodiment of the present invention, a computer for multiple virtual currency mining is provided, including: a network interface for connecting a first server and a second server on the network; and a first auxiliary calculation logic The circuit is used to execute the first mining algorithm; a second auxiliary calculation logic circuit is used to execute the second mining algorithm; and a central processing unit. The central processing unit includes: a first communication interface for connecting to the first auxiliary calculation logic circuit; a second communication interface for connecting to the second auxiliary calculation logic circuit; and a network communication port for connecting to the A network interface; and a computing core connected to the above-mentioned first communication interface, second communication interface and network communication port. The computing core is used to obtain the first input data and the second input of the first mining algorithm and the second mining algorithm from the first server and the second server through the network communication port. Data; using the first auxiliary calculation logic circuit to execute the first mining algorithm according to the first input data; and using the second auxiliary calculation logic circuit to execute the second mining algorithm according to the second input data. Wherein, the first auxiliary calculation logic circuit and the central processing unit are installed on the same circuit board, and the first auxiliary calculation logic circuit is assigned to the first mining When the algorithm is completed, an interrupt signal is presented to the computing core.

In this embodiment, in order to connect the first auxiliary calculation logic circuit or the second auxiliary calculation logic circuit, the first communication interface or the second communication interface includes one of the following hardware interfaces: a plurality of general-purpose I/O ports ( GPIO); Peripheral interface in the form of serial transmission; Peripheral interface in the form of parallel transmission; Universal Asynchronous Transceiver (UART); and Serial Peripheral Interface (SPI).

In this embodiment, in order to use the first auxiliary calculation logic circuit and the second auxiliary calculation logic circuit of different interfaces, the first communication interface and the second communication interface include different hardware interfaces.

In this embodiment, in order to shorten the physical distance between the two to increase the anti-interference ability, the first auxiliary calculation logic circuit is an independent package, and the central processing unit and the first auxiliary calculation logic circuit are installed On the same circuit board.

In this embodiment, in order to further shorten the physical distance between the two so as to increase the anti-interference ability and reduce the assembly problems of the system manufacturer, the central processing unit and the first auxiliary computing logic circuit are respectively located on different chips , But belong to the same package.

In this embodiment, in order to send a hardware interrupt signal to the computing core, the interrupt signal is sent to the computing core by the first auxiliary computing logic circuit through at least one port of the first communication interface including a plurality of universal I/O ports. .

In this embodiment, in order to present an interrupt signal to the computing core, the interrupt signal includes at least one of the following: a hardware interrupt signal; and a software specified in the software communication protocol transmitted through the plurality of general-purpose I/O ports Interrupt signal.

In this embodiment, in order to increase the spatial density of calculations, the central processing unit and The second auxiliary calculation logic circuits are respectively located on different circuit boards.

According to the present invention, a central processing unit as in the above-mentioned various embodiments is provided.

According to the computer and the central processing unit provided by the present invention, the computer can simultaneously mine two or more virtual currencies at the same time, thereby reducing the purchase cost and increasing the mining income.

100‧‧‧Computer

110‧‧‧Central Processing Unit

111‧‧‧Compute Core

112‧‧‧First communication interface

113‧‧‧Second communication interface

114‧‧‧Memory Controller

115‧‧‧Network communication port

120‧‧‧The first auxiliary calculation logic circuit

130‧‧‧Second auxiliary calculation logic circuit

140‧‧‧Memory chip

150‧‧‧Network Interface

Claims (10)

A computer for multiple virtual currency mining, including: a network interface for connecting a first server and a second server on the network; a first auxiliary calculation logic circuit for executing the first mining Mining algorithm; a second auxiliary calculation logic circuit for executing the second mining algorithm while the first mining algorithm is being executed, wherein the first auxiliary calculation logic circuit and the second auxiliary calculation logic circuit Is an application-specific integrated circuit; and a central processing unit, including: a first communication interface for connecting to the first auxiliary calculation logic circuit; a second communication interface for connecting to the second auxiliary calculation logic circuit; The network communication port is used to connect to the network interface; and a computing core is connected to the first communication interface, the second communication interface and the network communication port mentioned above, and is used to: from the first communication interface through the network communication port The server obtains the first input data of the first mining algorithm; obtains the second input data of the second mining algorithm from the second server through the network communication port; utilizes the first auxiliary calculation logic circuit Execute the first mining algorithm according to the first input data; and execute the second mining algorithm according to the second input data by using the second auxiliary calculation logic circuit, wherein the first auxiliary calculation logic circuit and the The central processing unit is installed on the same circuit board, the The first auxiliary calculation logic circuit sends an interrupt signal to the calculation core when the allocated first mining algorithm is completed. For example, the first computer in the scope of the patent application, wherein the first communication interface or the second communication interface includes one of the following hardware interfaces: a plurality of general-purpose input and output ports (GPIO); a peripheral interface in the form of serial transmission; a parallel transmission form Peripheral interface; Universal Asynchronous Transceiver (UART); and Serial Peripheral Interface (SPI). For example, the first computer in the scope of the patent application, wherein the first communication interface and the second communication interface include different hardware interfaces. For example, the first computer in the scope of the patent application, wherein the first auxiliary calculation logic circuit is an independent package. For example, the first computer in the scope of the patent application, wherein the central processing unit and the first auxiliary calculation logic circuit are located on different chips, but belong to the same package. For example, in the computer of the first item of the patent application, the interrupt signal is transmitted from the first auxiliary calculation logic circuit to the computer through at least one port of the first communication interface including a plurality of general-purpose I/O ports. Calculated core proposed. For example, in the computer of the first item of the patent application, the interrupt signal includes at least one of the following: a hardware interrupt signal; and a software interrupt signal specified in the software communication protocol transmitted through the plurality of general-purpose I/O ports. For example, the computer of the first item in the scope of patent application, wherein the computing core asks the second auxiliary computing logic circuit whether to complete the assigned second mining algorithm work through the second communication interface. For example, the computer of the first item in the scope of the patent application, wherein the central processing unit and the second auxiliary calculation logic circuit are respectively located on different circuit boards. Such as the central processing unit of any one of items 1 to 9 in the scope of patent application.

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