TWI722331B - Semiconductor lamination structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor lamination structure and a manufacturing method thereof are provided. The semiconductor lamination structure includes, in a lamination direction, a substrate, a first lamination layer and a second lamination layer. The first lamination layer is disposed on the substrate and includes at least one first pattern layer. The first pattern layer includes a first upper surface, a first bottom surface and a first tapered wall. The first tapered wall tapers off in a direction from the first bottom surface to the first upper surface, wherein the direction from the first bottom surface to the first upper surface is the same as the lamination direction. The second lamination layer is disposed on the first lamination layer and includes at least one second pattern layer. The second pattern layer includes a second upper surface, a second bottom surface and a second tapered wall. The second tapered wall tapers off in a direction from the second bottom surface to the second upper surface, wherein the direction from the second bottom surface to the second upper surface is opposite to the lamination direction.

Description

Semiconductor laminated structure and manufacturing method thereof

The present invention relates to a semiconductor laminated structure and a manufacturing method thereof, and more particularly to a semiconductor laminated structure with good alignment accuracy and a manufacturing method thereof.

The multi-layer semiconductor laminate structure is usually in the form of reposting, in which one laminate pair on the temporary carrier is pasted to another laminate, and then the temporary carrier is removed. However, this temporary carrier board is usually flexible and easy to warp, which makes it impossible to accurately align the laminate to another laminate, thereby destroying the electrical connection between the two laminates.

The present invention relates to a semiconductor laminated structure and a manufacturing method thereof. During the bonding process of the two laminated layers, the two laminated layers are respectively carried by a rigid temporary carrier and a rigid substrate, so that a laminated layer is inverted The method faces the other laminated layers to align each other, thereby improving the alignment accuracy of the two laminated layers.

According to one aspect of the present invention, a semiconductor laminated structure is provided. The semiconductor stack structure includes a substrate, a first stack, and a second stack in a stacking direction in sequence. The first stack is located on the substrate. The first stack includes at least one first patterned layer. The first patterned layer includes a first upper surface, a first lower surface, and a first inclined wall. The first inclined wall is connected to The first upper surface and the first lower surface are tapered from the first lower surface to the first upper surface, wherein the direction from the first lower surface to the first upper surface is the same as the stacking direction. The second laminate layer is located on the first laminate layer. The second laminate layer includes at least one second patterned layer. The second patterned layer includes a second upper surface, a second lower surface and a second inclined wall. The inclined wall connects the second upper surface and the second lower surface, and is tapered from the second lower surface to the second upper surface, wherein the direction from the second lower surface to the second upper surface is opposite to the lamination direction.

According to another aspect of the present invention, a method for manufacturing a semiconductor laminated structure is provided. The manufacturing method includes the following steps. A hard substrate is provided, and a first laminated layer is formed on the hard substrate. A first hard carrier is provided, and a second laminated layer is formed on the first hard carrier. The second stack faces the first stack and is paired on the first stack so that the second stack is located on the first stack along a stacking direction. Separate the first rigid carrier from the second laminate.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

1, 2: Semiconductor laminated structure

10: Hard substrate

10’: The first rigid carrier board

10": The second hard carrier board

11: First stack

12: Second stack

13: third stack

14, 16: Joining procedure

15, 17: Stripping procedure

100, 200: substrate

110, 210: first stack

111, 211c: scan line

113a, 113b, 113c, 213a, 213b, 213c: data lines

120, 220: second stack

120c, 220b: the first thin film transistor

121, 221: first gate

121c, 123c, 131b, 221b, 133b, 223b, 141a, 231a, 143a, 233a: patterned connection part

122, 222: the first semiconductor layer

123, 223: first source

124, 224: The first drain

130, 230: third stack

130b, 210c: second thin film transistor

131, 211: second gate

132, 212: second semiconductor layer

133, 213: second source

134, 214: second drain

140, 240: fourth stack

140a, 230a: the third thin film transistor

141, 231: third gate

142, 232: third semiconductor layer

143, 233: third source

144, 234: Third Drain

150: fifth stack

150a, 240a: third organic light emitting unit

150b, 240b: second organic light emitting unit

150c, 240c: third organic light emitting unit

151, 241: Interval layer

160, 250: thin film encapsulation layer

AN: First electrode

CA: second electrode

CP: connection pad

D1: stacking direction

EM: Emitting layer

L1: The first inclined wall

L2: second inclined wall

L3: The third inclined wall

P1: the first patterned layer

P2: second patterned layer

P3: third patterned layer

S11: First upper surface

S12: First bottom surface

S21: The second upper surface

S22: Second lower surface

S31: The third upper surface

S32: Third bottom surface

VC1, VC2: vertical channel

1A is a cross-sectional view of a rigid substrate and a first laminate formed on the rigid substrate according to an embodiment of the present invention, and a partial enlarged view of the first laminate.

1B is a cross-sectional view of a first rigid carrier and a second laminate formed on the first rigid carrier according to an embodiment of the present invention, and a partial enlarged view of the second laminate.

2A and 2D are cross-sectional views and partially enlarged views of a manufacturing process of a semiconductor laminated structure according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor laminated structure according to another embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor laminated structure according to still another embodiment of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can mean that there are other elements between the two elements.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, these elements, components, regions, and/or Or part should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the “first element”, “component”, “region”, “layer” or “portion” discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used here is only for the purpose of describing specific embodiments and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one." It should also be understood that when used in this specification, the terms "including" and/or "including" designate the presence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more The existence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe the relationship between one element and another element, as shown in the figure. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, elements described as being on the "lower" side of other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" may include an orientation of "lower" and "upper," depending on the specific orientation of the drawing. Similarly, if the device in one figure is turned over, elements described as "below" or "below" other elements will be oriented as Other components are "above". Thus, the exemplary terms "below" or "below" can include an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or excessive The formal meaning, unless explicitly defined as such in this article.

The exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, a change in the shape of the diagram as a result of, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shape of the area as shown herein, but include, for example, shape deviations caused by manufacturing. For example, regions shown or described as flat may generally have rough and/or non-linear characteristics. In addition, the acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shape of the regions.

1A is a cross-sectional view of a rigid substrate 10 and a first laminate 11 formed on the rigid substrate 10 according to an embodiment of the present invention, and a partial enlarged view of the first laminate 11. 1B is a cross-sectional view of a first rigid carrier 10' and a second laminate 12 formed on the first rigid carrier 10' according to an embodiment of the present invention, and a partial enlarged view of the second laminate 12 .

First, referring to FIG. 1A, a rigid substrate 10 is provided, and a first laminate 11 is formed on the rigid substrate 10. The hard substrate 10 is, for example, a glass substrate, or is, for example, quartz, wafer, or other suitable materials.

The first stack 11 may include at least one first patterned layer P1, and the first patterned layer P1 includes a first upper surface S11 and a first lower surface S12. The first patterned layer P1 is formed by patterning, for example, by etching. Generally speaking, the film formed by etching tends to have a taper angle. Therefore, the first patterned layer P1 includes sidewalls with tapered angles from the first upper surface S11 toward the first lower surface S12. In other words, as shown in the enlarged view of FIG. 1A, the first patterned layer P1 includes a first inclined wall L1. The first inclined wall L1 connects the first upper surface S11 and the first lower surface S12 and extends from the first lower surface. The direction from S12 to the first upper surface S11 is tapered.

Next, referring to FIG. 1B, a first rigid carrier 10' is provided, and a second laminate 12 is formed on the first rigid carrier 10'. The first rigid carrier 10' is, for example, a glass substrate, or, for example, quartz, wafer, or other applicable materials.

The second laminate 12 may include at least one second patterned layer P2, and the second patterned layer P2 includes a second upper surface S21 and a second lower surface S22. Similarly, the second patterned layer P2 is formed by patterning, for example, by etching. Therefore, the second patterned layer P2 includes sidewalls with tapered angles from the second upper surface S21 toward the second lower surface S22. In other words, as shown in the enlarged view of FIG. 1B, the second patterned layer P2 includes a second inclined wall L2. The second inclined wall L2 connects the second upper surface S21 and the second lower surface S22 and extends from the second lower surface. The direction from S22 to the second upper surface S21 is tapered.

Please refer to the descriptions of FIGS. 2A to 2D below, which are a cross-sectional view and a partially enlarged view of a manufacturing process of a semiconductor laminated structure according to an embodiment of the present invention.

As shown in FIG. 2A, after the rigid substrate 10 and the first laminate 11 of FIG. 1A and the first rigid carrier 10' and the second laminate 12 of FIG. 1B are provided, a bonding process 14 is performed to connect The second laminated layer 12 and the first laminated layer 11 are joined together in a joined pair. In detail, the second laminate 12 faces the first laminate 11 and is attached to the first laminate 11, so that the second laminate 12 is located on the first laminate 11 along a laminate direction D1.

Next, as shown in FIG. 2B, a peeling process 15 is performed to separate the first rigid carrier 10' from the second laminate 12. In one embodiment, the peeling process 15 is performed by, for example, laser lift-off (laser lift-off), but the invention is not limited thereto. For example, in another embodiment, a release layer may be provided between the first rigid carrier 10' and the second laminate 12 to facilitate the separation of the first rigid carrier 10' from the second laminate 12 .

Since in this embodiment, the substrate 10 and the temporary carrier 10' are both rigid substrates, during the bonding process 14, the rigid temporary carrier 10' and the rigid substrate 10 are used to respectively carry the second laminate 12 and the first laminate 11 are aligned to each other, so that the carrier board 10' and the substrate 10 will not be deformed during the bonding process, so as to improve the accuracy of the second laminate 12 and the first laminate 11 to avoid both The electrical connection between the laminated layers is damaged due to careless attachment.

In addition, in Figure 2A, the second laminate 12 is facing the first laminate 11 and the first laminate 11 in an upside-down manner. Therefore, after the bonding process 14 is completed, the second laminate The direction from the second lower surface S22 to the second upper surface S21 of the patterned layer P2 is opposite to the stacking direction D1, and the direction from the first lower surface S12 to the first upper surface S11 of the first patterned layer P1 is the same as the stacking direction D1. The layer direction D1 is the same.

If you want to make the semiconductor stack structure have more stacks, please refer to Figure 2C and Figure 2D, you can provide a second rigid carrier 10", and form a third stack 13 on the second rigid carrier 10" on. Wherein, the material of the second hard carrier 10" is similar to that of the first hard carrier 10'. Then, as described in FIG. 2A, a bonding process 16 is performed to connect the third laminate 13 and the second laminate 12 is joined together. In detail, the third laminate 13 faces the second laminate 12 and is attached to the second laminate 12, so that the third laminate 13 is located in the second laminate along the laminate direction D1. 12 on. Next, as described in Figure 2B, a peeling process 17 is performed to separate the second rigid carrier 10" from the third laminate 13.

Similarly, the third stack 13 may also include at least one third patterned layer P3, and the third patterned layer P3 includes a third upper surface S31 and a third lower surface S32. Similar to the first patterned layer P1 and the second patterned layer P2, the third patterned layer P3 also includes a third inclined wall L3. The third inclined wall L3 connects the third upper surface S31 and the third lower surface S32, and The direction from the third lower surface S32 to the third upper surface S31 is tapered. Moreover, after the third laminate 13 and the second laminate 12 are aligned, the direction from the third lower surface S32 to the third upper surface S31 of the third patterned layer P3 is opposite to the laminate direction D1.

Of course, the semiconductor laminated structure can have more than three laminated layers, and relevant personnel can make more laminated layers according to the aforementioned stacking method, and these laminated layers have better alignment accuracy.

In addition, in practical applications, after the required semiconductor stack structure is fabricated as described above, the hard substrate 10 and the first stack 11 can be further separated (for example, the hard substrate 10 and the first stack 11 There can be a release layer between them, and then replaced with a soft substrate to expand the possibilities of other applications. The flexible substrate is, for example, a flexible material, including but not limited to polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether Ether ketone (PEEK), polymethyl methacrylate (PMMA), other suitable flexible materials or combinations thereof.

In other words, as long as a rigid substrate and a rigid temporary carrier are used to align each other during the bonding process of these laminations, the alignment accuracy of these laminations can be ensured.

Please refer to FIG. 3, which is a cross-sectional view of a semiconductor stacked structure 1 according to another embodiment of the present invention. The semiconductor stacked structure 1 includes a substrate 100. In this embodiment, the semiconductor laminated structure 1 can be used in an organic electro luminescence display (OLED), such as a flat organic electro luminescence display or a curved organic electro luminescence display. For example, when the semiconductor laminated structure 1 is a flat organic electroluminescence display, the substrate 100 may be a rigid substrate. When the semiconductor laminated structure 1 is a curved organic electroluminescence display, the substrate 100 can be replaced by a flexible substrate.

The semiconductor laminated structure 1 further includes a first laminated layer 110, a second laminated layer 120, a third laminated layer 130, a fourth laminated layer 140, a fifth laminated layer 150, and a膜包层160。 Thin film packaging layer 160. The first stack 110 can be a bus line layer; the second stack 120 can be a first thin film transistor device layer, the third stack 130 can be a second thin film transistor device layer, and the fourth stack 140 It can be a third thin film transistor device layer; the fifth stack 150 can be an organic light emitting device layer. The second stack 120, the third stack 130, and the fourth stack 140 respectively serve as pixel driving circuits, and the thin film transistor elements therein are used to drive the organic light emitting elements of the fifth stack 150, respectively.

In this embodiment, the first stack 110, the second stack 120, the third stack 130, the fourth stack 140, and the fifth stack 150 can be fabricated using the aforementioned stacking method. That is, as shown in Figures 2A and 2B, the second stack 120 faces the first stack 110 and is paired on the first stack 110, so that the first stack 110 and the second stack 120 The connection pads CP are connected to each other to be electrically connected to each other; as shown in Figures 2C and 2D, the third stack 130 faces the second stack 120 and is paired on the second stack 120 to make the second stack The connection pads CP of the stack 120 and the third stack 130 are connected to each other to be electrically connected to each other; as the third stack 130 is made as described above, the fourth stack 140 faces the third stack 130 and is opposite to each other. On the third stack 130, the connection pads CP of the third stack 130 and the fourth stack 140 are connected to each other to be electrically connected to each other; as the third stack 130 is made, the fifth stack 150 Facing the fourth stack 140 and facing the fourth stack 140, the connection pads CP of the fourth stack 140 and the fifth stack 150 are connected to each other to be electrically connected to each other.

The first stack 110 is formed on the substrate 100. The first stack 110 includes scan lines 111 and data lines 113a, 113b, and 113c. The first laminate 110 is similar to the first laminate 11 in the aforementioned 2A to 2D drawings, and has a first patterned layer P1 similar to the first laminate 11. That is, the first patterned layer P1 is at least one of the scan line 111 and the data lines 113a, 113b, and 113c. In this embodiment, the scan lines 111 and the data lines 113a, 113b, and 113c all have structural features similar to the first patterned layer P1 of the first stack 11. Furthermore, as shown in FIG. 3, the scanning line 111 and the data lines 113a, 113b, and 113c formed by etching the inclined walls (not labeled) are tapered along the stacking direction D1.

The second stack 120 is located on the first stack 110. The second stack 120 includes a first thin film transistor 120c, and the first thin film transistor 120c includes a first gate 121, a first semiconductor layer 122, a first source 123, and a first drain 124. The second laminate 120 is similar to the second laminate 12 in the aforementioned 2A to 2D drawings, and has a second patterned layer P2 similar to the second laminate 12. That is, the second patterned layer P2 is at least one of the first gate 121, the first semiconductor layer 122, the first source 123, and the first drain 124. In this embodiment, the first gate 121, the first semiconductor layer 122, the first source 123, and the first drain 124 all have structural features similar to the second patterned layer P2 of the second stack 12. Furthermore, as shown in Figure 3, the first gate electrode 121, the first semiconductor layer 122, the first source electrode 123 and the first drain electrode 124 are etched to form inclined walls (not labeled) along the stack The direction opposite to the direction D1 tapers.

In this embodiment, the first thin film transistor 120c is a top gate type thin film transistor. As shown in Figure 3, the first gate 121 and the first semiconductor layer 122 are stacked The sequence in the layer direction D1 is: the first gate 121 and the first semiconductor layer 122. That is to say, after the second stack 120 and the first stack 110 are aligned, the order of the first thin film transistor 120c in the stacking direction D1 is reversed.

In another embodiment, the first thin film transistor 120c may be a bottom gate type thin film transistor. Therefore, after the second stack 120 and the first stack 110 are mated, the order of the first gate 121 and the first semiconductor layer 122 in the stacking direction D1 is: the first semiconductor layer 122 and the first gate 121 That is, in another embodiment, the positions of the first semiconductor layer 122 and the first gate electrode 121 are reversed from the positions of the first semiconductor layer 122 and the first gate electrode 121 in FIG. 3.

The first thin film transistor 120c is electrically connected to the scan line 111 and the data line 113c. In detail, the first gate 121 of the first thin film transistor 120c is connected to the patterned connection portion 121c located in the second stack 120, and the patterned connection portion 121c may have a third similar to the first thin film transistor 120c. The structural feature of a gate 121. The patterned connection portion 121c is electrically connected to the scan line 111 through the vertical channel VC1 passing through the first stack 110 and the second stack 120.

The first source electrode 123 of the first thin film transistor 120c is connected to the patterned connection portion 123c in the second stack 120, and the patterned connection portion 123c may have a first source electrode 123 similar to the first thin film transistor 120c The structural characteristics. The patterned connection portion 123c is electrically connected to the scan line data line 113c through the vertical channel VC1 passing through the first stack 110 and the second stack 120.

The third stack 130 is located on the second stack 120. The third stack 130 includes a second thin film transistor 130 b. The second thin film transistor 130 b includes a second gate electrode 131, a second semiconductor layer 132, a second source electrode 133 and a second drain electrode 134.

The fourth stack 140 is located on the third stack 130. The fourth stack 140 includes a third thin film transistor 140a, and the third thin film transistor 140a includes a third gate 141, a third semiconductor layer 142, a third source 143, and a third drain 144.

Here, the second gate 131, the second semiconductor layer 132, the second source 133 and the second drain 134 of the second thin film transistor 130b, the third gate 141 and the third semiconductor of the third thin film transistor 140a The layer 142, the third source electrode 143 and the third drain electrode 144 respectively have the first gate electrode 121, the first semiconductor layer 122, the first source electrode 123 and the first drain electrode 124 similar to the first thin film transistor 120c. Structure. Furthermore, as shown in FIG. 3, the second gate 131 of the second thin film transistor 130b, the second semiconductor layer 132, the second source 133 and the second drain 134, and the third thin film transistor 140a Inclined walls (not labeled) formed by etching of the triple gate electrode 141, the third semiconductor layer 142, the third source electrode 143 and the third drain electrode 144 are tapered in the opposite direction of the stacking direction D1.

In this embodiment, the second thin film transistor 130b and/or the third thin film transistor 140a are top gate type thin film transistors. As shown in FIG. 3, the order of the second gate 131 and the second semiconductor layer 132 in the stacking direction D1 is: the second gate 131 and the second semiconductor layer 132. The order of the third gate 141 and the third semiconductor layer 142 in the stacking direction D1 is: the third gate 141 and the third semiconductor layer 142. That is, when the third stack 130 and the second stack 120 are mated, and the fourth stack 140 and the third stack 130 After the alignment, the structural sequence of the second thin film transistor 130b and the third thin film transistor 140a in the stacking direction D1 is in an inverted state.

In another embodiment, the second thin film transistor 130b and/or the third thin film transistor 140a may be a bottom gate type thin film transistor. Therefore, after the third stack 130 and the second stack 120 are mated, the order of the second gate 131 and the second semiconductor layer 132 in the stacking direction D1 is: the second semiconductor layer 132 and the second gate 131 . After the fourth stack 140 and the third stack 130 are mated, the order of the third gate 141 and the third semiconductor layer 142 in the stacking direction D1 is: the third semiconductor layer 142 and the third gate 141, namely In another embodiment, the positions of the third semiconductor layer 142 and the third gate 141 and the positions of the third semiconductor layer 142 and the third gate 141 in FIG. 3 are reversed.

The second thin film transistor 130b is electrically connected to the scan line 111 and the data line 113b. In detail, the second gate 131 of the second thin film transistor 130b is connected to the patterned connection portion 131b located in the third stack 130, and the patterned connection portion 131b may have a second gate similar to that of the second thin film transistor 130b. The structural feature of two gates 131. The patterned connection portion 131b is electrically connected to the scan line 111 through the vertical channel VC1 passing through the first stack 110, the second stack 120, and the third stack 130.

The second source 133 of the second thin film transistor 130b is connected to the patterned connection portion 133b in the third stack 130, and the patterned connection portion 133b may have a second source 133 similar to the second thin film transistor 130b The structural characteristics. The patterned connection portion 133b is electrically connected to the scan line data line 113b through the vertical channel VC1 passing through the first stack 110, the second stack 120, and the third stack 130.

The third thin film transistor 140a is electrically connected to the scan line 111 and the data line 113a. In detail, the third gate 141 of the third thin film transistor 140a is connected to the patterned connection portion 141a in the fourth stack 140, and the patterned connection portion 141a may have a third similar to the third thin film transistor 140a. The structural features of the triple gate 141. The patterned connection portion 141a is electrically connected to the scan line 111 through a vertical channel VC1 passing through the first stack 110, the second stack 120, the third stack 130, and the fourth stack 140.

The third source 143 of the third thin film transistor 140a is connected to the patterned connection portion 143a located in the fourth stack 140, and the patterned connection portion 143a may have a third source 143 similar to the third thin film transistor 140a The structural characteristics. The patterned connection portion 143a is electrically connected to the scan line data line 113a through the vertical channel VC1 passing through the first stack 110, the second stack 120, the third stack 130, and the fourth stack 140.

The fifth stack 150 is located on the fourth stack 140. The fifth stack 150 includes a first organic light emitting unit 150c, a second organic light emitting unit 150b, and a third organic light emitting unit 150a. A spacer layer 151 is provided between the first organic light emitting unit 150c, the second organic light emitting unit 150b, and the third organic light emitting unit 150a. Each organic light emitting unit 150a, 150b, 150c includes a first electrode AN, a second electrode CA, and a light emitting layer EM. In this embodiment, the first electrode AN serves as the anode of the organic light-emitting units 150a, 150b, and 150c, and the second electrode CA serves as the cathode of the organic light-emitting units 150a, 150b, and 150c, but the invention is not limited thereto.

In this embodiment, the first thin film transistor 120c located in the second stack 120 is electrically connected to the first organic light emitting unit 150c, and the second thin film transistor 130b located in the third stack 130 is electrically connected to the second organic light emitting unit 150c. The light-emitting unit 150b is located on the fourth The third thin film transistor 140a in the stack 140 is electrically connected to the third organic light emitting unit 150a.

In detail, the first drain 124 of the first thin film transistor 120c is electrically connected through the vertical channel VC2 passing through the second stack 120, the third stack 130, the fourth stack 140, and the fifth stack 150 The first electrode AN of the first organic light emitting unit 150c. The second drain electrode 134 of the second thin film transistor 130b is electrically connected to the first electrode of the second organic light emitting unit 150b through the vertical channel VC2 passing through the third stack 130, the fourth stack 140 and the fifth stack 150 AN. The third drain electrode 144 of the third thin film transistor 140a is electrically connected to the first electrode AN of the third organic light emitting unit 150a through the vertical channel VC2 passing through the fourth stack 140 and the fifth stack 150. Thereby, the light emitting layer EM of each organic light emitting unit 150a, 150b, 150c can receive excitation light between the corresponding first electrode AN and the second electrode CA.

In the embodiment of FIG. 3, the fifth laminate 150 is a pair facing the fourth laminate 140, so that the connection pads CP of the fourth laminate 140 and the fifth laminate 150 are joined to each other, but the present invention Not limited to this. In another embodiment, after the laminate structure of the first laminate 110 to the fourth laminate 140 is completed, the laminate structure can be transferred to an OLED evaporation chamber to perform the evaporation of the fifth laminate 150 Plating procedure.

Please refer to FIG. 4, which is a cross-sectional view of a semiconductor stacked structure 2 according to still another embodiment of the present invention. The semiconductor stack structure 2 includes a substrate 200, a first stack 210, a second stack 220, a third stack 230, a fourth stack 240, and a thin film encapsulation layer 250 in the stacking direction D1 in sequence. . The first stack 210 may be a second thin film transistor element layer, and the second stack 220 may be a first thin film transistor element layer. The triple stack 230 can be a third thin film transistor device layer; the fourth stack 240 can be an organic light emitting device layer. The manufacturing method of these laminates may include the following steps: forming a first laminate 210 on the substrate 200; placing the second laminate 220 facing the first laminate 210 and pairing the first laminate 210 on the first laminate 210 to make the first laminate 210 The connection pads CP of 210 and the second stack 220 are joined to each other to be electrically connected to each other; the third stack 230 faces the second stack 220 and is paired on the second stack 220, so that the second stack 220 The connection pads CP of the third stack 230 are connected to each other to be electrically connected to each other. The fourth laminate 240 may be assembled on the third laminate 230 in a manner facing the third laminate 230; or, the fourth laminate 240 may be formed on the third laminate 230 by evaporation.

The main difference between the semiconductor stack structure 2 in this embodiment and the semiconductor stack structure 1 in FIG. 3 is that the bus line layer of the semiconductor stack structure 2 is integrated with the first stack 210, the second stack 220, and Within the third stack 230. For example, the scan line 211c and the data lines 213a, 213b, and 213c of the bus line layer can be located in the first stack 210, but it is not limited thereto.

As shown in FIG. 4, the first stack 210 is formed on the substrate 200. The first stack 210 includes a second thin film transistor 210c, and the second thin film transistor 210c includes a second gate 211, a second semiconductor layer 212, a second source 213, and a second drain 214. The first laminate 210 is similar to the first laminate 11 in the aforementioned 2A to 2D drawings, and has a first patterned layer P1 similar to the first laminate 11. That is, the first patterned layer P1 is at least one of the second gate electrode 211, the second semiconductor layer 212, the second source electrode 213, and the second drain electrode 214. In this embodiment, the second gate electrode 211, the second semiconductor layer 212, the second source electrode 213, and the second drain electrode 214 all have a shape similar to that of the first stack. 11 is the structural feature of the first patterned layer P1. Furthermore, as shown in FIG. 4, the second gate electrode 211, the second semiconductor layer 212, the second source electrode 213, and the second drain electrode 214 are etched to form inclined walls (not labeled) along the stack The direction D1 is tapered.

In this embodiment, the second thin film transistor 210c is a top gate type thin film transistor. As shown in FIG. 4, the order of the second gate electrode 211 and the second semiconductor layer 212 in the stacking direction D1 is: the second semiconductor layer 212 and the second gate electrode 211. In another embodiment, the second thin film transistor 210c may be a bottom gate type thin film transistor. In this case, the order of the second gate 211 and the second semiconductor layer 212 in the stacking direction D1 is: the second gate 211 and the second semiconductor layer 212, that is, in another embodiment, the second gate The positions of 211 and the second semiconductor layer 212 are reversed from the positions of the second gate 211 and the second semiconductor layer 212 in FIG. 4.

The second thin film transistor 210c is electrically connected to the scan line 211c and the data line 213c. In detail, the second gate 211 of the second thin film transistor 210c is connected to the scan line 211c, and the scan line 211c may have structural features similar to the second gate 211 of the second thin film transistor 210c.

The second source electrode 213 of the second thin film transistor 210c is connected to the data line 213c, and the data line 213c may have structural features similar to the second source electrode 213 of the second thin film transistor 210c.

The second stack 220 is located on the first stack 210. The second stack 220 includes a first thin film transistor 220b, and the first thin film transistor 220b includes a first gate 221, a first semiconductor layer 222, a first source 223, and a first drain 224. The second laminated layer 220 is similar to the second laminated layer 12 in the aforementioned 2A~2D diagrams, and has a similar The second patterned layer P2 of the second stack 12. That is, the second patterned layer P2 is at least one of the first gate 221, the first semiconductor layer 222, the first source 223, and the first drain 224. In this embodiment, the first gate electrode 221, the first semiconductor layer 222, the first source electrode 223, and the first drain electrode 224 all have structural features similar to the second patterned layer P2 of the second stack 12. Furthermore, as shown in Figure 4, the first gate electrode 221, the first semiconductor layer 222, the first source electrode 223 and the first drain electrode 224 are etched to form inclined walls (not labeled) along the stack The direction opposite to the direction D1 tapers.

In this embodiment, the first thin film transistor 220b is a top gate type thin film transistor. As shown in FIG. 4, the order of the first gate electrode 221 and the first semiconductor layer 222 in the stacking direction D1 is: the first gate electrode 221 and the first semiconductor layer 222. In other words, after the second stack 220 and the first stack 210 are aligned, the order of the structure of the first thin film transistor 220b in the stacking direction D1 is reversed.

In another embodiment, the first thin film transistor 220b may be a bottom gate type thin film transistor. Therefore, after the second stack 220 and the first stack 210 are mated, the order of the first gate 221 and the first semiconductor layer 222 in the stacking direction D1 is: the first semiconductor layer 222 and the first gate 221 That is, in another embodiment, the positions of the first semiconductor layer 222 and the first gate electrode 221 and the positions of the first semiconductor layer 222 and the first gate electrode 221 in FIG. 4 are reversed.

The first thin film transistor 220b is electrically connected to the scan line 211c and the data line 213b. In detail, the first gate electrode 221 of the first thin film transistor 220b is connected to the patterned connection portion 221b located in the second stack 220, and the patterned connection portion 221b may have a second similar to the first thin film transistor 220b. The structural feature of a gate 221. The patterned connection portion 221b is electrically connected to the scan line 211c through the vertical channel VC1 passing through the first stack 210 and the second stack 220.

The first source electrode 223 of the first thin film transistor 220b is connected to the patterned connection portion 223b in the second stack 220, and the patterned connection portion 223b may have a first source electrode 223 similar to the first thin film transistor 220b The structural characteristics. The patterned connection portion 223b is electrically connected to the scan line data line 213b through the vertical channel VC1 passing through the first stack 210 and the second stack 220.

The third stack 230 is located on the second stack 220. The third stack 230 includes a third thin film transistor 230a, and the third thin film transistor 230a includes a third gate 231, a third semiconductor layer 232, a third source 233, and a third drain 234. The third gate 231, the third semiconductor layer 232, the third source 233, and the third drain 234 of the third thin film transistor 230a respectively have a first gate 221 and a first semiconductor similar to the first thin film transistor 220b. The structural features of the layer 222, the first source electrode 223, and the first drain electrode 224. Furthermore, as shown in Figure 4, the third gate 231, the third semiconductor layer 232, the third source 233, and the third drain 234 of the third thin film transistor 230a are etched to form inclined walls (not Mark), which is tapered in the opposite direction of the stacking direction D1.

In this embodiment, the third thin film transistor 230a is a top gate type thin film transistor. As shown in FIG. 4, the order of the third gate 231 and the third semiconductor layer 232 in the stacking direction D1 is: the third gate 231 and the third semiconductor layer 232. That is, after the third stack 230 and the second stack 220 are aligned, the order of the structure of the third thin film transistor 230a in the stacking direction D1 is reversed.

In another embodiment, the third thin film transistor 230a may be a bottom gate type thin film transistor. Therefore, after the third stack 230 and the second stack 220 are mated, the order of the third gate 231 and the third semiconductor layer 232 in the stacking direction D1 is: the third semiconductor layer 232 and the third gate 231 That is, in another embodiment, the positions of the third gate 231 and the third semiconductor layer 232 and the positions of the third gate 231 and the third semiconductor layer 232 in FIG. 4 are reversed.

The third thin film transistor 230a is electrically connected to the scan line 211c and the data line 213a. In detail, the third gate 231 of the third thin film transistor 230a is connected to the patterned connection portion 231a located in the third stack 230, and the patterned connection portion 231a may have a third similar to the third thin film transistor 230a. The structural characteristics of the triple gate 231. The patterned connection portion 231a is electrically connected to the scan line 211c through the vertical channel VC1 passing through the first stack 210, the second stack 220, and the third stack 230.

The third source 233 of the third thin film transistor 230a is connected to the patterned connection part 233a in the third stack 230, and the patterned connection part 233a may have a third source 233 similar to the third thin film transistor 230a The structural characteristics. The patterned connection portion 233a is electrically connected to the scan line data line 213a through the vertical channel VC1 passing through the first stack 210, the second stack 220, and the third stack 230.

The fourth stack 240 is located on the third stack 230. The fourth stack 240 includes a first organic light emitting unit 240c, a second organic light emitting unit 240b, and a third organic light emitting unit 240a. A spacer layer 241 is provided between the first organic light emitting unit 240c, the second organic light emitting unit 240b, and the third organic light emitting unit 240a. Each organic light emitting unit 240a, 240b, 240c includes a first electrode AN and a second electrode CA And a light-emitting layer EM. In this embodiment, the first electrode AN serves as the anode of the organic light-emitting units 240a, 240b, 240c, and the second electrode CA serves as the cathode of the organic light-emitting units 240a, 240b, 240c, but the invention is not limited thereto.

In this embodiment, the second thin film transistor 210c located in the first stack 210 is electrically connected to the first organic light emitting unit 240c, and the first thin film transistor 220b located in the second stack 220 is electrically connected to the second organic light emitting unit 240c. The light emitting unit 240b, and the third thin film transistor 230a located in the third stack 230 are electrically connected to the third organic light emitting unit 240a.

In detail, the second drain 214 of the second thin film transistor 210c is electrically connected through the vertical channel VC2 passing through the first stack 210, the second stack 220, the third stack 230, and the fourth stack 240 The first electrode AN of the first organic light emitting unit 240c. The first drain electrode 224 of the first thin film transistor 220b is electrically connected to the first electrode of the second organic light emitting unit 240b through the vertical channel VC2 passing through the second stack 220, the third stack 230 and the fourth stack 240 AN. The third drain electrode 234 of the third thin film transistor 230a is electrically connected to the first electrode AN of the third organic light emitting unit 240a through the vertical channel VC2 passing through the third stack 230 and the fourth stack 240. Thereby, the light-emitting layer EM of each organic light-emitting unit 240a, 240b, 240c can receive excitation light between the corresponding first electrode AN and the second electrode CA.

To sum up, although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

10: Hard substrate

10’: The first rigid carrier board

11: First stack

12: Second stack

15: Stripping procedure

D1: stacking direction

L1: The first inclined wall

L2: second inclined wall

P1: the first patterned layer

P2: second patterned layer

S11: First upper surface

S12: First bottom surface

S21: The second upper surface

S22: Second lower surface

Claims (20)

A semiconductor stack structure, in a stacking direction, sequentially includes: a substrate; a first stack located on the substrate, the first stack includes at least one first patterned layer, the first patterned layer It includes a first upper surface, a first lower surface and a first inclined wall. The first inclined wall connects the first upper surface and the first lower surface and extends from the first lower surface to the first upper surface , The direction from the first lower surface to the first upper surface is the same as the direction of the stack; and a second stack is located on the first stack, the second stack includes: at least A second patterned layer including a second upper surface, a second lower surface and a second inclined wall, the second inclined wall connecting the second upper surface and the second lower surface, And tapered from the second lower surface to the second upper surface, wherein the direction from the second lower surface to the second upper surface is opposite to the stacking direction; and a first thin film transistor, the first A thin film transistor includes a first gate, a first semiconductor layer, a first source, and a first drain. The second patterned layer is the first gate, the first semiconductor layer, and the At least one of the first source and the first drain. According to the semiconductor laminated structure described in claim 1, wherein the first laminated layer includes a second thin film transistor, and the second thin film transistor includes a second gate, a second semiconductor layer, and a first Two sources and a second drain, the first The patterned layer is at least one of the second gate, the second semiconductor layer, the second source, and the second drain. According to the semiconductor laminated structure described in item 2 of the scope of patent application, the second thin film transistor system is a top gate type thin film transistor or a bottom gate type thin film transistor. The semiconductor laminated structure described in claim 1, wherein the first thin-film transistor is a top-gate thin-film transistor in a direction opposite to the laminated direction, and the first gate and the second The order of a semiconductor layer in the stacking direction is: the first gate and the first semiconductor layer. The semiconductor laminated structure described in claim 1, wherein the first thin film transistor is a bottom gate type thin film transistor in a direction opposite to the stacking direction, and the first gate and the second The order of a semiconductor layer in the stacking direction is: the first semiconductor layer and the first gate. The semiconductor laminated structure described in item 2 of the scope of patent application further includes: A third stack is located on the second stack, the third stack includes a third thin film transistor, the third thin film transistor includes a third gate, a third semiconductor layer, and a third source And a third drain; wherein the third thin film transistor is a top gate thin film transistor in the direction opposite to the stacking direction, and the third gate and the third semiconductor layer are in the stack The order in the layer direction is: the third gate and the third semiconductor layer. The semiconductor laminated structure described in the second item of the patent application further includes: a third laminated layer located on the second laminated layer, the third laminated layer including a third thin film transistor, the third thin film transistor The crystal includes a third gate, a third semiconductor layer, a third source, and a third drain; wherein the third thin film transistor is a bottom gate type in a direction opposite to the stacking direction For the thin film transistor, the order of the third gate electrode and the third semiconductor layer in the stacking direction is: the third semiconductor layer and the third gate electrode. The semiconductor laminate structure described in item 6 or item 7 of the scope of the patent application further includes: a fourth laminate layer located on the third laminate layer, the fourth laminate layer including a first organic light emitting unit, a A second organic light emitting unit and a third organic light emitting unit; Wherein, the second thin film transistor is electrically connected to the first organic light emitting unit, the first thin film transistor is electrically connected to the second organic light emitting unit, and the third thin film transistor is electrically connected to the third organic light emitting unit. The semiconductor laminated structure described in claim 1, wherein the first laminated layer includes a data line and a scan line, and the first patterned layer is at least one of the data line and the scan line . According to the semiconductor laminated structure described in claim 9, wherein the first thin film transistor is electrically connected to the data line and the scan line. In the semiconductor laminated structure described in claim 10, the first thin film transistor is a top-gate thin film transistor in a direction opposite to the laminated direction, and the first gate and the second The order of a semiconductor layer in the stacking direction is: the first gate and the first semiconductor layer. In the semiconductor laminated structure described in claim 10, the first thin film transistor is a bottom gate type thin film transistor in a direction opposite to the stacking direction, and the first gate and the second The order of a semiconductor layer in the stacking direction is: the first semiconductor layer and the first gate. The semiconductor laminate structure described in item 10 of the scope of patent application further includes: a third laminate layer on the second laminate layer, the third laminate layer including a second thin film transistor, the second thin film transistor The crystal is electrically connected to the data line and the scan line, and includes a second gate, a second semiconductor layer, a second source and a second drain; and a fourth stack located on the third stack Layer, the fourth stack includes a third thin film transistor electrically connected to the data line and the scan line, and includes a third gate, a third semiconductor layer, and a third Source and a third drain; wherein the second thin film transistor and the third thin film transistor are top gate type thin film transistors or bottom gate type thin film transistors in the direction opposite to the stacking direction Crystal. As for the semiconductor laminated structure described in claim 13, wherein the second thin film transistor is a top gate type thin film transistor in a direction opposite to the stacking direction, and the second gate and the first The order of the two semiconductor layers in the stacking direction is: the second gate and the second semiconductor layer. As for the semiconductor laminated structure described in claim 13, wherein the second thin film transistor is a bottom gate type thin film transistor in a direction opposite to the stacking direction, and the second gate and the first The order of the two semiconductor layers in the stacking direction is: the second semiconductor layer and the second gate. As for the semiconductor laminated structure described in claim 13, wherein the third thin film transistor is a top gate type thin film transistor in a direction opposite to the laminated direction, and the third gate and the second The order of the three semiconductor layers in the stacking direction is: the third gate and the third semiconductor layer. As for the semiconductor laminated structure described in claim 13, wherein the third thin film transistor is a bottom gate type thin film transistor in a direction opposite to the stacking direction, and the third gate and the second The order of the three semiconductor layers in the stacking direction is: the third semiconductor layer and the third gate. The semiconductor laminate structure described in item 13 of the scope of the patent application further includes: a fifth laminate layer located on the fourth laminate layer, the fifth laminate layer including a first organic light emitting unit and a second organic light emitting unit Unit and a third organic light emitting unit; wherein the first thin film transistor is electrically connected to the first organic light emitting unit, the second thin film transistor is electrically connected to the second organic light emitting unit, and the third thin film transistor is electrically connected The third organic light-emitting unit is sexually connected. A method for manufacturing a semiconductor laminated structure includes: providing a hard substrate, forming a first laminated layer on the hard substrate, the first laminated layer having at least one first patterned layer; A first rigid carrier is provided, a second laminate is formed on the first rigid carrier, and the second laminate has at least one second patterned layer; the second laminate faces the first laminate Set on the first laminate so that the second laminate is located on the first laminate along a laminate direction; separate the first rigid carrier board from the second laminate; provide a second rigid A carrier, forming a third laminate on the second rigid carrier, the third laminate having at least one third patterned layer, wherein the tapering direction of the at least one first patterned layer is the same as the at least one The tapering directions of a second patterned layer and the at least one third patterned layer are opposite; the third laminated layer faces the second laminated layer pair on the second laminated layer so that the third laminated layer is along The stacking direction is located on the second stack; and the second rigid carrier is separated from the third stack. The manufacturing method described in item 19 of the scope of patent application further includes: separating the rigid substrate from the first laminate.

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