TWI721383B - Package structure with plural integrated circuit units and manufacturing method thereof - Google Patents

Abstract

A package structure and a manufacturing method thereof are provided, in which the package structure includes a circuit substrate, a die and an encapsulation. The die is disposed on the circuit substrate, and the die includes at least two integrated circuit units and a dummy part, in which the dummy part separates the integrated circuit units and doesn’t electrically connect the integrated circuit units to each other, and the integrated circuit units are electrically connected to each other through the circuit substrate. The encapsulation covers the die and the circuit substrate.

Description

Packaging structure with multiple integrated circuit units and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, in particular to a packaging structure with a plurality of integrated circuit units and a manufacturing method thereof.

With the miniaturization and multi-functionalization of electronic products, multi-die packaging structures are becoming more and more common in many electronic products. Two or more dies are packaged in a single packaging structure to reduce the overall volume. In terms of flip chip packaging, the common multi-die packaging structure is to arrange more than two dies side by side on the same substrate, but the process error of the die bonding machine and the subsequent filling of the gap between the dies with the packaging glue are considered. There is a design limit between the dies arranged side by side, which limits the area of the package structure and cannot be further reduced, and the area of the package structure will increase with the increase in the number of chips. In view of this, reducing the size of the package structure is indeed the goal of the industry's efforts.

The purpose of the present invention is to provide a packaging structure and a manufacturing method thereof to reduce the volume of the packaging structure.

To achieve the above objective, the present invention provides a package structure, which includes a circuit carrier, a first die, and an encapsulant. The first die is disposed on the circuit carrier, and the first die includes at least two integrated circuit units and a dummy part, wherein the dummy part separates the integrated circuit unit, and the dummy part does not divide the integrated circuit unit. The circuit units are electrically connected to each other, and the integrated circuit units are electrically connected to each other through the circuit carrier board. The molding compound covers the first die and the circuit carrier.

In order to achieve the above objective, the present invention also provides a method for manufacturing a package structure, including providing a wafer wafer, wherein the wafer wafer includes a plurality of integrated circuit units; cutting the wafer wafer to form a plurality of first dies, Each first die includes at least two adjacent integrated circuit units and a dummy part, the dummy part separates the integrated circuit units, and the dummy part does not electrically connect the integrated circuit units to each other One of the first die is set on a circuit carrier, where the integrated circuit units are electrically connected to each other through the circuit carrier; and a sealant is formed on the first die and the circuit carrier.

In the package structure and manufacturing method disclosed in the present invention, through the design of the first die having at least two integrated circuit units, the spacing between the integrated circuit units can be reduced, so that the volume of the package structure can be effectively reduced . Moreover, through this design, the manufacturing cost and manufacturing process of the package structure can be effectively reduced, thereby saving costs.

Please refer to Fig. 1 to Fig. 6 for a schematic diagram of a method for manufacturing a package structure according to the first embodiment of the present invention. Fig. 1 to Fig. 3 are structural diagrams of the package structure in different steps. Fig. 4 is a schematic cross-sectional view taken along the line A-A' of the figure, Fig. 4 is a schematic top view of the package structure of the first embodiment of the present invention, Fig. 5 and Fig. 6 are respectively the package structure along the section line of Fig. A schematic cross-sectional view of B-B' and C-C'. The method for manufacturing a package structure provided in this embodiment includes the following steps. As shown in FIG. 1, first, a chip wafer 102 is provided, where the chip wafer 102 includes a plurality of integrated circuit units 104. Specifically, the chip wafer 102 may be an integrated circuit unit 104 having a specific function formed thereon. In this embodiment, each integrated circuit unit 104 may have the same structure, that is, each integrated circuit unit 104 is a functional unit with the same function and the same structure. For example, each integrated circuit unit 104 may be a memory device, such as dynamic random access memory (DRAM), flash memory (Flash) or other suitable memory.

In this embodiment, the wafer 102 may have a plurality of scribe lines 106, which are respectively located between two adjacent integrated circuit units 104 to separate the integrated circuit units 104 from each other. After the chip wafer 102 is formed, each integrated circuit unit 104 in the chip wafer 102 can be inspected, and each integrated circuit unit 104 can be recorded as a good product or a bad product in the inspection machine to indicate each function The normal position of the integrated circuit unit 104 helps to subsequently cut out the first die 108.

Next, a dicing process is performed on the wafer 102 to cut the wafer 102 along a part of the dicing line 106 to form a plurality of first dies 108. Specifically, since each integrated circuit unit 104 can know whether it is a good product during the inspection process, the position of the integrated circuit unit 104 that is judged to be a good product can be recorded through the machine, so that the cutting program in the machine can be judged as At least two adjacent integrated circuit units 104 of a good product are regarded as the same first die 108, and the first die 108 is separated from other parts of the wafer 102 along the dicing path 106 around the first die 108 . For example, the cutting lane 106 may include a plurality of first cutting lanes 106a extending along the first direction D1, a plurality of second cutting lanes 106b extending along the second direction D2, and a plurality of third cutting lanes 106c, where The first scribe lane 106 a and the second scribe lane 106 b can surround the range of the first die 108, and the third scribe lane 106 c is located between the integrated circuit units 104 of the first die 108. During the cutting process, cutting is not performed along the third scribe lane 106c, so the first die 108 may include a dummy portion 108P corresponding to the position of the third scribe lane 106c, and the dummy portion 108P may be connected to the first die The adjacent integrated circuit unit 104 in 108. To clearly illustrate the first die 108, the first die 108 of this embodiment includes two adjacent integrated circuit units 104, so the third cutting lane 106c located between the integrated circuit units 104 will not be cut. , But not limited to this. Since the third cutting lane 106c of this embodiment does not need to be cut, compared to the method of cutting each cutting lane, the cutting process of this embodiment can save cutting time, thereby improving cutting efficiency. In this embodiment, the integrated circuit unit 104 of the first die 108 can be arranged along the narrower side of the integrated circuit unit (such as the second direction D2), so the third cutting lane 106c can be arranged along the first The direction D1 extends, but is not limited to this. In some embodiments, the third scribe lane 106c may be defined according to the identified range of the first die 108, so the third scribe lane 106c may also extend along the second direction D2, or a different third scribe lane 106c It can extend along the first direction D1 and the second direction D2, respectively. In some embodiments, as shown in FIG. 2, the dummy portion 108P of the first die 108 may include a test pad TP, an alignment mark AM, or other components that do not affect the final package structure 100. In some embodiments, the test pad TP can be used to test different integrated circuit units 104, but it is not limited to this.

In this embodiment, the dicing process may include, for example, a laser grooving process and a wafer dicing process. The laser grooving process may first place the wafer 102 on the first dicing lane 106a. Cut off from a part of the film in the second dicing channel 106b, such as low-k films, metal layers, or materials that are difficult to cut with a cutting blade, such as aluminum nitride, gallium nitride, and alumina ceramics Or silicon carbide, the wafer dicing process may include full dicing of the wafer 102 using a dicing blade. In some embodiments, the cutting process can also be one or more laser cutting processes. The cutting process of the present invention is not limited to the above, and may also be other suitable cutting processes.

In some embodiments, the first die 108 may also include three or more integrated circuit units 104 according to actual requirements. In some embodiments, the integrated circuit unit 104 in the first die 108 may also have a different structure and be a different functional unit, for example, different memory devices or integrated circuits with different functions.

It is worth noting that the dummy part 108P of this embodiment does not electrically connect adjacent integrated circuit units 104 to each other, that is to say, the dummy part 108P does not have any wiring to connect the integrated circuit unit in the first die 108. The circuit units 104 are electrically connected to each other, so the integrated circuit units 104 in the first die 108 are still insulated from each other when the subsequent process is not performed. In some embodiments, the dummy portion 108P may also electrically connect the integrated circuit units 104 in the first die 108 to each other.

As shown in FIGS. 2 and 3, after the first die 108 is formed, a die bonding process is performed, and a first die 108 is disposed on a circuit carrier 110 to attach the first die 108 The die 108 is electrically connected to the circuit carrier 110, and the integrated circuit units 104 in the first die 108 can be electrically connected to each other through the circuit carrier 110. In this embodiment, the circuit carrier 110 may include a plurality of upper solder pads 110a, a plurality of interconnections 110b, and a plurality of lower solder pads 110c. The upper solder pads 110a are located on the circuit carrier 110 facing the first die 108. On the surface 110S1, the lower solder pad 110c is located on the other surface 110S2 of the circuit carrier 110 opposite to the surface 110S1, and the interconnection 110b is arranged between the upper solder pad 110a and the lower solder pad 110c, so that the upper solder pad 110a can be connected through the inner The wire 110b is electrically connected to the lower bonding pad 110c. A corresponding bump 112 may be formed on each upper pad 110a of the circuit carrier 110 of this embodiment, and during the die bonding process, the pad of the first die 108 is disposed facing the bump 112, so that the first The pads (not shown) of a die 108 can be bonded to the corresponding bumps 112 by flip chip bonding, so as to be fixed on the circuit carrier 110. The bonding method of the first die 108 and the circuit carrier 110 of the present invention is not limited to flip chip bonding, and other suitable bonding methods may also be used. In some embodiments, the upper solder pad 110a may be electrically connected to the lower solder pad 110c in a one-to-one or not in a one-to-one manner, that is, the number of upper solder pads 110a, the number of interconnections 110b, and the lower solder pads 110a The number of pads 110c and their connection method can be determined according to actual needs. In some embodiments, the bumps 112 may also be formed on the pads of the first die 108 first, and then in the die bonding process, the bumps 112 may be respectively bonded to the corresponding upper pads 110c.

It is worth noting that since the first die 108 of this embodiment includes at least two integrated circuit units 104, it is compared with the method of arranging at least two die each having an integrated circuit unit on the circuit carrier. In other words, the design of the first die 108 of the present embodiment can effectively reduce the number and frequency of setting the die, thereby improving the production efficiency of the die bonding process.

In this embodiment, the circuit carrier 110 may have a vent hole 110h, for example, arranged in the center of the circuit carrier 110 to facilitate the placement of the first die 108 and the circuit carrier 110 during the subsequent molding process. The air in between is discharged through the exhaust hole 110h, thereby reducing the generation of air bubbles.

As shown in FIGS. 4 to 6, after the first die 108 is fixed to the circuit carrier 110, a molding process is performed to form a molding compound 114 on the first die 108 and the circuit carrier 110 to The first die 108 is sealed on the circuit carrier 110. Subsequently, solder balls 116 are disposed under each of the lower bonding pads 110c to help the package structure 100 to be adhered to other components or circuit boards in the subsequent manufacturing process. So far, the package structure 100 of this embodiment can be formed. The molding compound 114 may include, for example, a molding compound or other suitable molding materials. In this embodiment, the molding compound 114 can cover the first die 108, but it is not limited thereto. In some embodiments, after the molding compound 114 is formed, the molding compound 114 on the first die 108 may be further removed to expose the upper surface of the first die 108 to reduce the thickness of the package structure 100. In this embodiment, since the circuit carrier 110 has the exhaust hole 110 a, the sealing compound 114 can be filled into the exhaust hole 110 a, and a part of the sealing compound 114 can overflow under the circuit carrier 110. In some embodiments, between the formation of the molding compound 114 and the placement of the solder balls 116, other rewiring layers, other packaging structures, or other dies can be optionally provided on the molding compound 114, but it is not limited thereto. In some embodiments, the circuit carrier 110 may also be a rewiring layer formed on a temporary carrier. In this case, the temporary carrier may be removed between the formation of the sealing body 114 and the placement of the solder balls 116.

It is worth mentioning that since only a single first die 108 is provided on the circuit carrier 110 of this embodiment (that is, there is no gap between the integrated circuit units 104), when the molding compound 114 is formed, the first die 108 The design of the particles 108 can avoid the existence of small gaps, which helps the molding compound to fill the gaps between the first die 108 and the circuit carrier 110 more quickly, thereby avoiding the generation of bubbles between the integrated circuit unit 104 to improve The reliability of the package structure 100. In addition, since the design of the first die can increase the filling of the gap between the first die 108 and the circuit carrier 110 by the molding compound, the number of vent holes designed for the circuit carrier can be reduced to reduce the manufacturing cost.

In this embodiment, the package structure 100 may be, for example, a molded under fill (MUF) type, but it is not limited thereto. In some embodiments, the package structure 100 may also be of a capillary under fill (capillary under fill, CUF) type, which may be filled between the first die 108 and the circuit carrier 110 before the molding compound 114 is formed A liquid encapsulant is used to reduce the probability of voids generated between the first die 108 and the circuit carrier 110.

It is worth noting that in the package structure 100 of this embodiment, since the integrated circuit units 104 in the first die 108 are not separated during the cutting process, the gap G1 between the integrated circuit units 104 can be close to The width of the scribe lane 106 makes the gap G1 smaller than the design limit of the die pitch of the die bonding process, for example, less than 300 microns. For example, the pitch G1 may be less than or equal to 65.6 microns. In this way, compared to a package structure in which two dies each having an integrated circuit unit are packaged, the area of the package structure 100 of this embodiment can be effectively reduced. Moreover, since the spacing G1 between the integrated circuit units 104 can be smaller than the design limit of the die spacing, the connection path of the integrated circuit units 104 can be shortened, thereby improving the electrical performance of the package structure 100 and reducing power consumption .

In this embodiment, since the gap G1 of the integrated circuit unit 104 of this embodiment can be reduced, the minimum distance between the upper pads 110a of the circuit carrier 110 that are electrically connected to different integrated circuit units 104 can also be reduced. Specifically, the upper soldering pad 110a of the circuit carrier 110 can be divided into at least two upper soldering pad groups 110a1, 110a2, wherein the upper soldering pad groups 110a1, 110a2 are electrically connected to different integrated circuit units 104, and the upper soldering The spacing G2 between the pad groups 110a1 and 110a2 may be smaller than the design limit of the grain spacing. For example, the gap G2 may be less than 300 microns, or even further less than or equal to 65.6 microns.

The packaging structure and manufacturing method of the present invention are not limited to the above-mentioned embodiments, and other embodiments of the present disclosure will be further described below. In order to facilitate the comparison of the various embodiments and simplify the description, the same reference numerals will be used to label the same elements below, and the differences between the different embodiments will be described in detail below, and the same parts will not be repeated.

Please refer to FIG. 7, which is a schematic cross-sectional view of the package structure of the second embodiment of the present invention. As shown in FIG. 7, the difference between the package structure 200 provided by this embodiment and the first embodiment is that the circuit carrier board 210 of this embodiment may not have vent holes. In this embodiment, the packaging structure 200 may optionally include a liquid encapsulant 218 to fill the gap between the first die 108 and the circuit carrier 210. Specifically, the liquid encapsulant 218 may have a filling capacity compared with the molding material, so as to reduce the probability of bubbles generated between the first die 108 and the circuit carrier 210. The liquid molding compound 218 can be filled into the gap between the first die 108 and the circuit carrier 210 before the molding compound 114 is formed. The liquid molding compound 218 may include epoxy resin, for example.

Please refer to FIG. 8, which shows a schematic cross-sectional view of the package structure of the third embodiment of the present invention. As shown in FIG. 8, the difference between the package structure 300 provided by this embodiment and the first embodiment is that the package structure 300 of this embodiment may further include a second die 320 disposed on the dummy of the first die 108 Between the portion 108P and the sealing glue layer 114. Specifically, as shown in FIGS. 3 and 8, the difference between the manufacturing method of the package structure 300 of this embodiment and the first embodiment is that before the molding compound 114 is formed, a second crystal is additionally provided on the dummy portion 108P.粒320. The second die 320 may be the same as or different from the first die 108 according to actual requirements. For example, it is worth noting that since there are no gaps between the integrated circuit units 104 of the first die 108, even if the second die 320 is provided on the dummy portion 108P, the molding material can still be filled quickly. The gap between the first die 108 and the circuit carrier 110 is filled without being affected by the arrangement of the second die 320. In summary, in the package structure disclosed in the present invention, through the design of the first die having at least two integrated circuit units, the spacing between the integrated circuit units can be reduced, so that the volume of the package structure can be effectively reduced. To shrink. Moreover, through this design, the manufacturing cost and manufacturing process of the package structure can be effectively reduced, thereby saving costs. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

100, 200, 300: package structure 102: Wafer 104: Integrated Circuit Unit 106: Cutting Road 106a: The first cutting pass 106b: second cutting pass 106c: third cutting lane 108: The first grain 108P: Dummy part 110, 210: Circuit carrier board 110a: Upper pad 110a1, 110a2: Upper pad group 110b: internal connection 110c: lower pad 110h: vent 110S1, 110S2: surface 112: bump 114: Sealant 116: Solder Ball 218: Liquid sealant 320: second grain D1: First direction D2: second direction TP: Test pad AM: Alignment mark G1, G2: spacing

Fig. 1 to Fig. 6 are schematic diagrams illustrating a method of manufacturing a package structure according to the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of the package structure according to the second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of the package structure of the third embodiment of the present invention.

104: Integrated Circuit Unit

108: The first grain

108P: Dummy part

110: circuit carrier board

110a: Upper pad

110a1, 110a2: Upper pad group

110b: internal connection

110c: lower pad

110S1, 110S2: surface

112: bump

114: Sealant

116: Solder Ball

G1, G2: spacing

Claims (10)

A packaging structure, including: A circuit carrier board; A first die arranged on the circuit carrier, and the first die includes at least two integrated circuit units and a dummy part, wherein the dummy part separates the integrated circuit units, The dummy part does not electrically connect the integrated circuit units to each other, and the integrated circuit units are electrically connected to each other through the circuit carrier; and A sealant covering the first die and the circuit carrier. The package structure according to claim 1, wherein the spacing between the integrated circuit units is smaller than the design limit of the die spacing. The package structure according to claim 1, wherein each of the integrated circuit units has the same structure. The package structure according to claim 1, wherein each of the integrated circuit units is a memory device. The package structure according to claim 1, wherein the distance between the integrated circuit units is less than 300 microns. The package structure according to claim 1, wherein the circuit carrier has two upper bonding pad groups, which are located on the surface of the circuit carrier facing the first die, and are respectively electrically connected to the different integrated circuit units And the minimum spacing between the upper bonding pad groups is smaller than the design limit of the grain spacing. The package structure according to claim 1, further comprising a second die disposed between the dummy part and the molding compound. A manufacturing method of an encapsulation structure, including: Provide a chip wafer, wherein the chip wafer includes a plurality of integrated circuit units; The chip wafer is diced to form a plurality of first dies, wherein each of the first dies includes at least two adjacent ones of the integrated circuit units and a dummy part, and the dummy part causes the at least two The integrated circuit units are separated, and the dummy part does not electrically connect the integrated circuit units to each other; Disposing one of the first dies on a circuit carrier, wherein the integrated circuit units are electrically connected to each other through the circuit carrier; and A sealant is formed on the one of the first dies and the circuit carrier. The manufacturing method of the package structure according to claim 8, further comprising disposing a second die on the dummy part before forming the molding compound. The manufacturing method of the package structure according to claim 8, wherein the spacing between the integrated circuit units is smaller than the chip spacing design limit of the die bonding process.

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