TWI721002B - Selective die transfer using controlled de-bonding from a carrier wafer - Google Patents

Abstract

Selective die transfer is described using controlled de-bonding from a carrier wafer. In one example, small dies are formed on a wafer and attached to a temporary carrier. Larger host dies are formed on a host wafer. Raised mesas are formed on the host dies at locations of the host dies that are to receive a small die. The small dies are aligned over the host dies using the temporary carrier and the small dies are applied to the host dies using the temporary carrier so that a subset of the small dies physically contact the raised mesas of the respective host dies while the small dies that are not of the subset do not contact the host dies. The temporary carrier and the remaining small dies are separated from the host dies. The host dies are singulated and packaged.

Description

Selective die transfer using controlled debonding from the carrier wafer

The present invention relates to assembling semiconductor dies for packaging, and particularly relates to an assembly of dies having different sizes connected together.

In order to increase the speed and power efficiency and reduce the size of electronic devices, integrated circuit die is made smaller and smaller. These dies are mounted closer together, so that the connections between these dies are also made shorter. The shortest connection is the connection made in the integrated circuit package. In some cases, the dies are mounted side by side on the package substrate and connected together through the package substrate or directly by wires. In other cases, one die is mounted on another die for direct connection without any centered wires or package substrate. This is sometimes referred to as stacked die packaging. One die can be placed on another die using a pick and place machine or various other types of equipment. The combination can be packaged as a single die with twice the height.

Combining multiple dies into a single package allows two or more different types of dies to be placed in a single package. This can be called grain-to-crystal Heterogeneous integration of granular connections. As an example, the crystal grains can be made of different materials, such as silicon, germanium, III-V group, silicon carbide, and so on. As another example, the die can be made using different technology nodes, such as 22nm, 14nm, 10nm, and so on. These differences can be combined and combined with other types of differences, so that different types of dies from different processes and different manufacturers can be placed in a single compact package.

2‧‧‧System Board

4‧‧‧Processor

6‧‧‧Communication chip

9‧‧‧Non-volatile memory

10‧‧‧Mass storage device

11‧‧‧Calculating device

12‧‧‧Graphics processor

14‧‧‧Chipset

16‧‧‧antenna

18‧‧‧Display

20‧‧‧Touch Screen Controller

22‧‧‧Battery

24‧‧‧Power Amplifier

26‧‧‧Global Positioning System (GPS) Device

28‧‧‧Compass

30‧‧‧Speaker

32‧‧‧Camera

102‧‧‧Donor Wafer

104‧‧‧Small grains

105‧‧‧Small grains

106‧‧‧Groove

108‧‧‧Temporary Adhesive

109‧‧‧Weakening

110‧‧‧Carrier wafer

114‧‧‧Vertical Conductive Post

116‧‧‧Last Floor

118‧‧‧Countertop

120‧‧‧Main device wafer

122‧‧‧Main grain

124‧‧‧Conductive wire or trace

130‧‧‧Conductive post or through hole

130‧‧‧Vertical through hole

132‧‧‧Conductive contact pad or wire

134‧‧‧Dielectric

202‧‧‧Donor Wafer

204‧‧‧Island

205‧‧‧Selected island

206‧‧‧Scribing grooves

208‧‧‧Adhesive

209‧‧‧Weakened Adhesive

210‧‧‧Temporary Carrier

214‧‧‧Vertical Conductive Post

216‧‧‧Last Floor

218‧‧‧Countertop

220‧‧‧Master Wafer

222‧‧‧Main grain

224‧‧‧Conductive wire or trace

230‧‧‧Conductive post or through hole

232‧‧‧Conductive contact pad or wire

234‧‧‧Additional dielectric

240‧‧‧Resistive heater element

242‧‧‧Through hole

244‧‧‧Dielectric layer

250‧‧‧External power supply

The embodiments of the present invention are illustrated by way of example rather than by way of limitation. In the drawings of the drawings, the same component symbols refer to similar components.

Figure 1 is a cross-sectional side view of a portion of a donor wafer carrying a plurality of small dies according to an embodiment.

2 is a cross-sectional side view of the donor wafer with a temporary carrier attached to the front side of the small die using a temporary adhesive according to an embodiment.

3 is a cross-sectional side view of the donor wafer and the temporary carrier after the donor wafer is thinned according to an embodiment.

4 is a cross-sectional side view of the donor wafer and the temporary carrier after the die is singulated through the donor wafer on the backside of the die according to an embodiment.

5 is a cross-sectional side view of the donor wafer and temporary carrier after the die is singulated through the donor wafer on the back side of the die according to an embodiment.

FIG. 6 is a cross-sectional side view of a master wafer with a raised mesa at a position of one of the small dies to be received according to an embodiment.

FIG. 7 is a cross-sectional side view of a donor wafer and a temporary carrier that are aligned on a portion of the main wafer and applied to the raised mesa according to an embodiment.

8 is a cross-sectional side view of the temporary carrier and other small dies that have not been applied to the mesa of the main die away from the main wafer according to an embodiment.

FIG. 9 is a cross-sectional side view of adding a dielectric and a metal wiring layer on the small die to complete the package according to an embodiment.

10 is a cross-sectional side view of a portion of a donor wafer carrying a plurality of small dies aligned on a temporary carrier having an array of heating elements according to an embodiment.

11 is a cross-sectional side view of the donor wafer with a temporary adhesive used to attach a temporary carrier to the front side of the small die according to an embodiment.

12 is a cross-sectional side view of the donor wafer and the temporary carrier after the donor wafer is thinned according to an embodiment.

Figure 13 is a cross-sectional side view of the donor wafer and the temporary carrier after the die is singulated through the donor wafer on the backside of the die according to an embodiment.

Figure 14 is a cross-sectional side view of the donor wafer and temporary carrier aligned on a portion of the master wafer and applied to the optional raised mesa according to an embodiment.

15 is a cross-sectional side view of a donor wafer and a temporary carrier applied to the master wafer and heating an adhesive for one of the small dies in accordance with an embodiment to debond the small die from the temporary carrier .

16 is a cross-sectional side view of the temporary carrier and other small dies removed according to an embodiment, in which the adhesive used for debonding away from the main wafer is not heated.

FIG. 17 is a cross-sectional side view of adding a dielectric and a metal wiring layer on the small die to complete the package according to an embodiment.

FIG. 18 is a block diagram of a computing device incorporating a hybrid semiconductor die package according to an embodiment.

[Content and Implementation of the Invention]

The functional small dies or islands as described herein can be integrated into existing positions on the die constructed on the master wafer. Very small and thin dies can be processed in large numbers by using wafer-level processing. Instead of manipulating a single small die into a small location, the entire wafer can be processed at once, but the die is only transferred to the selected area of the large die on the master wafer.

Two or more different integrated circuit die manufacturing technologies can be integrated on the same die. Different technologies can include different program nodes, different cores or blocks, different area sizes, or different (heterogeneous) materials. The islands of one or more technologies as described herein can be transferred to the die of another technology.

The device wafer as described in this article is manufactured to have a mesa that protrudes thicker than the rest of the device wafer at the mesa layer degree. The carrier wafer and the device wafer are aligned and contacted. This creates a bond between the island to be transferred and the table. The wafer is debonded, and the transferred island is debonded from the carrier wafer at the weakened interface. The carrier wafer can then be aligned and combined with the same or another device wafer, for example (albeit offset from the original position) to transfer different islands. A material can be used to bond the two substrates together to have a strong bond. The bond is then weakened to allow layer transfer.

For island transfer procedures, selective heating can be used to improve bonding, bonding strengthening, bonding weakening, or debonding. Small areas of the wafer can be heated as a mechanism for bonding, bonding strengthening, bonding weakening, or debonding. The local heating can be used to heat only the sub-collection of the island in the domain of the island, so that only the sub-collection of the island is transferred to the device wafer.

As described, the carrier wafer is manufactured with micro heaters for bonding, bonding strengthening, bonding weakening, and debonding purposes. Certain bonding mechanisms are strongly temperature dependent, so local heating of an island can be used to provide selective layer transfer. After the carrier wafer and the islands and the device wafer are in physical contact with each other, the integrated heaters in one or more areas of the carrier are selectively activated to bond or decouple only the islands to be transferred . After transferring islands or island collections, the carrier can be brought into contact with another device wafer to selectively transfer another island group. The heater-integrated carrier wafer described can be manufactured with each donor wafer, or it can be manufactured once and reused.

As described, the small dies are processed in groups on the wafer. When held on a carrier wafer, very small and thin die can be transferred. The die can be much smaller and thinner than can be simply manipulated by the die pick and place assembly. By forming interconnects on both the top and bottom of the island, more routing resources can be obtained.

Figures 1 to 9 show an example program for arranging the small island part crystal grain in a position so that it can be a small island part crystal grain that is completely buried inside the main crystal grain. FIG. 1 is a cross-sectional side view of a group of small dies 104 and 105 formed on a donor wafer 102. The island may have a different area size than the die 122 on the main device wafer 120 of FIG. 6, and the carrier wafer 110 of FIG. 2 may be reused to transfer the island to many device wafers. The donor wafer shown in Figure 1 is a substrate on which small dies or islands have been formed, and which safely carry the dies in a precisely aligned position. The die can be partially cut by sawing or scribing at this time or later, so as to have a scribing groove or saw cut through the die and deep into the wafer.

In this example, the die is called small only means that it is smaller than the main die to which it will be attached. The small crystal grain can be half the size of the main crystal grain, one-tenth the size, or any other relative size. The donor wafer contains many small dies to be transferred to the main die that has been formed on the device wafer. The small crystal grains can be beneficial to functional materials integrated with the main crystal grains. Examples of such functional materials may include silicon, germanium, silicon carbide, group III-V and group III-nitride compound semiconductors. Because the small die is independently formed on a separate wafer, it can be formed using a different technology, different material, or different process node from the main die. The small die can be a power supply, radio frequency, optical, memory or preferably with the main crystal Other types of devices formed by dividing the circle.

2 is a cross-sectional side view of the donor wafer 102 of FIG. 1 inverted and attached to the temporary carrier 110 using a temporary adhesive 108. As shown in FIG. This adhesive can be applied to the donor wafer, the carrier wafer, or both before the donor wafer and the carrier wafer are attached to each other. The front side of the die 104, 105 is covered by the carrier and the back side of the wafer 102 is exposed. The donor wafer is combined with the temporary carrier wafer so that the wafer can be handled by the carrier. Examples of temporary carrier materials are silicon and glass. However, other suitable materials can also be used. The temporary adhesive is selected to withstand any mechanical forces that may be caused during the polishing of the wafer and any thermal or mechanical overload during the thinning of the wafer. These forces can include shear, compression, tension, and so on.

The temporary adhesive is also selected so that the die can be simply unbonded from the carrier when needed. One such type of adhesive is a polymer adhesive. The polymer adhesive may include polymethacrylate, polyacrylate, polystyrene, polysilsesquioxane, polysiloxane, polynorbornene, polyimide, polybenzoxazole, epoxy Resin, novolac, benzocyclobutene, polycarbonate. The inorganic adhesive may include silicon implanted with hydrogen (H) (or silicon implanted with other volatile species) or amorphous silicon: hydrogen (Si:H).

The carrier wafer can be in physical contact with the die on the donor wafer to bond it. The wafer with the die can be annealed at an elevated temperature to increase the bonding strength. Heating the polymer adhesive to a temperature higher than its glass transformation temperature will allow it to flow and form a good relationship with the two substrates. contact. Once cooled, the polymer regains its rigidity and results in a strong, mechanically stable bond.

3 is a cross-sectional side view of the carrier wafer 110 and the dies 104 and 105 of FIG. 2 after the donor wafer is thinned. This can be done by grinding or in any other way. A large number of micromachining techniques can be used, such as grinding, wet etching, dry etching, chemical mechanical polishing, and so on. The number of thinning or thinning targets varies according to the degree of integration. If the die is to be embedded in the interconnect stack as shown in FIG. 8, the die does not require any structural stability and the wafer can be made very thin, for example, less than 1 micron thick . As another example, if the small die is to be embedded as part of C4 (Controlled Collapse Chip Connection) or package as shown in Figure 18, the die needs some mechanical reinforcement and stability But it may still be only tens of microns thick.

Figure 4 is a cross-sectional side view of the wafer of Figure 3 with singulated island die. The singulation can be achieved by masking and etching the trench 106 between the islands until the adhesive or carrier wafer is exposed. Other singulation techniques can be used depending on the size of the island, composition, and other procedures and structural features. If the size permits, laser scribing etching can also be used. Wet or dry etching methods can also be used for this singularization. It is also possible to use blade singulation.

The singulation can be performed before or after combining with the temporary carrier. The island can be mechanically singulated using a scribe trench or another structure to be deep enough in the donor wafer so that the spacing between the dies is within the It is exposed during grinding. In other words, the grinding can be performed to the depth of the trench, so that the donor wafer no longer extends between the dies. In this case, only the carrier wafer holds the die in position. The result is similar to that shown in Figure 4 after singulation.

At this stage, through holes and other attachment features can be added as needed. "Through die vias" can be manufactured in a similar way to through silicon vias (TSV). These can be drilled, etched or perforated through the backside substrate or wafer to make contact with the front-end circuit of the die. The drill hole is then filled with metal (such as copper, titanium, tantalum) to form the connection. The hole can be overfilled so that the metal surface at the top of the through hole is exposed. Depending on the embodiment, the through-die via may be formed before singulation or after the island is transferred and combined with the respective main die.

5 is a cross-sectional side view of the singulated die and donor wafer of FIG. 4 after the adhesive bond 108 has been weakened 109. After singulation, the temporary adhesive is weakened, so that the bonding strength of the interface is reduced, but the position of the side surface of the island remains unchanged. For polymer adhesives, this can be done by heat. Heating the polymer above its decomposition temperature or upper limit temperature causes the polymer to decompose or depolymerize. This leads to the loss of entangled polymer structure and strong bonds. The islands 104 and 105 maintain the bonding with the carrier wafer by weak bonding force. An example is the Van der Waals force between the island and the carrier or between polymer residues at the two interfaces. The solid bond 108 of FIG. 3 is no longer needed after the donor wafer has been thinned.

FIG. 6 is the width of the larger main die 122 formed on the main wafer 120 Sectional side view. The main wafer also has a stack underneath. There are vertical conductive pillars 114 that are used to connect to the pads or the through-die vias of the small die 105. The large die 122 has a conductive redistribution layer or other metal or conductive layer with conductive lines or traces 124 on the die.

The mesa 118 has been fabricated on the device wafer. The mesa protrudes some thickness above the last layer 116. The raised mesa is higher or farther from the die substrate than the surrounding surface or layer of the main die. The small die will be connected by the raised mesa or will be connected with the pad on the raised mesa or in the raised mesa. The countertop can be made of various materials. An example material is silicon dioxide (SiO ₂ ). Another example is carbon doped oxide (CDO). The mesa can be made by vacuum deposition or spin coating of the mesa material, masking the layer with a photoresist material, and then wet or dry etching on site. The mesa can be deposited on the finished last layer 116 or the last layer can be formed so that it is higher in some locations than in others.

Fig. 7 is a cross-sectional side view of the small die and the temporary carrier which are turned upside down again so that the back side of the die is facing downward. As shown in the two wafers, the main device wafer 120 and the carrier wafer 110 are aligned. For example, by moving the carrier wafer 110 and the two dies 104 and 105, the sub-assembly of the small die 105 is in physical contact with the table 118. The elevated table surface is only allowed to contact the island 105 to be transferred. For the other islands 104, there is a small gap corresponding to the height of the mesa 118 above the surrounding layer 116. The bond formed at the island-mesa interface is stronger than the weakened bond at the island-carrier interface.

The combination between the island and the countertop can be selected in various ways The ground is strengthened. Heat, pressure, metal bonding or any other technique can be used. This condition can be adjusted to form a stronger bond with the island. In this example, the rest of the area of the master wafer mainly made of ILD (Interlayer Dielectric) has little or no physical contact with other islands, so there is little or no physical contact with other islands. Any combination. These areas will be separated later.

In one embodiment, the temporary carrier presses the small crystal grains on each individual table surface to combine the small crystal grains with the main crystal grains by metal compression. Heat can be used to further strengthen the bond. In this case, the raised mesa includes pads, electrodes or other connectors to be electrically connected and physically bonded to the contact pads on the small die. Alternatively, the electrical connection may be formed on the opposite side of the small die and the small die may be attached to the main die in another manner.

Fig. 8 is a cross-sectional side view of separating the carrier wafer from the main wafer. This causes the two dies 104, 105 to be separated. The bond on the weakened temporary adhesive is weaker than the island-mesa bond, so the island remains on the device wafer. In some embodiments, some external stimuli (such as heat) may be applied to weaken the bond between the island die and the temporary carrier wafer. After separation, the carrier wafer can be used to apply the die to another master wafer. As shown, the islands on the device wafer are facing up. The device wafer may be further processed to form electrical contact with the island by, for example, device wafer interconnect stacking.

Since the temporary adhesive remains on other dies, the second die 104 is pulled away from the main die 122 by the temporary carrier 110. As above As mentioned, the die has been separated or singulated by scribing the trench 106 as shown. Therefore, only the carrier holds the crystal grains together.

Figure 9 is a diagram showing the removal of the temporary carrier and other small crystal grains. The attached small die 105 remains bonded to the mesa of the main die. The master wafer is further processed to completely embed the transferred small die into the interconnect stack. In the illustrated example, further processing includes additional dielectric 134, additional conductive pillars or vias 130, and conductive contact pads or wires 132 for connecting to other components. As shown, the smaller die 105 is completely buried in the ILD of the main die. This allows special functions and dedicated dies to be incorporated into a larger die assembly without any changes to the packaging and other processing aspects of the main die.

In this example, only two small dies 104, 105 are displayed on the donor wafer 102. Usually there will be more small grains. These dies are formed together on the donor wafer, and then the functional dies are carried on the carrier wafer 110 and operated in a group. Likewise, the master wafer 120 is only shown as having a portion of a single die 122, however, there may be more die. The transfer operation can be performed using a wafer handler, so that many small dies are transferred to many main dies in one operation. The temporary carrier can then be moved to transfer more small dies to the same master wafer at different locations on the main die or it can be moved to transfer small dies to different master wafers Grains.

As described, the temporary bonding layer 108 is weakened 109 so that the island can be transferred to the mesa of the device wafer more easily. In order to further stimulate the transfer of the island, the bonding layer can be selectively weakened under the island This makes it easier for the island to be transferred to the device wafer. If the weakening is sufficiently selective, the bonding system for the island to be transferred is weakened, but the bonding system for the other islands is not affected. This is helpful for at least two different aspects. First, for some islands, the lack of bonding-weakening helps to ensure that the non-transferred island maintains good contact with the carrier. Secondly, with sufficient bond weakening for the island, the island can be transferred without the need for a mesa on the device wafer.

There are many different ways to selectively weaken the bond. Some examples of procedures to achieve selective bond weakening include rapid heating of the bond stack from the side of the device wafer. The conductive path through the mesa to the selected island will first cause a temperature deviation at that island before reaching other islands. Timing the thermal deviation will cause the bond of the selected island to be weakened without affecting the other islands.

In another example, the stack can be selectively heated from the side of the carrier wafer. As described in more detail below, this can be accomplished using a micro heater close to the bonding interface.

In another example, compression is applied. Bonding materials that are weakened under compression can be used. In this example, the selected island is pressed against the mesa on the device wafer. Applying a compressive force to the device wafer, the carrier wafer, or both, weakens the bonding interface between the temporary carrier and the island.

In another example, tensile strain can be used. Bonding materials weaker than tensile strain can be used. The carrier wafer is pressed against the mesa of the device wafer with mesa. Debonding can be used to provide the tensile strain required to weaken and debond the temporary material.

In an example, a poly(methyl methacrylate) tie layer can be used. The bonded wafer may be annealed at, for example, about 150°C. The adhesive can be debonded at 400°C. Alternatively, it is also possible to use oxide fusion bonding for permanent bonding of the mesa to the island.

As described, these types of bonding materials allow for heterogeneous integration of different technologies. Materials and manufacturing processes that cannot be manufactured on the same wafer can also be combined. In addition, the circuit blocks can be separated on different wafers, minimizing manufacturing costs. As in the procedure shown in Figure 9, these different blocks can then be integrated onto the same die.

Figure 9 is provided as an example of how to complete the device with the buried island 105. There are various types of connections between the island and the larger main die 122. Different types of through holes 130 with different configurations can be used to connect the island to the main die. There may be a metal pad 132 above the adjacent ILD 134. Although FIG. 9 shows the back side of the island die or the side of the wafer connected to the main die. But the die can also be attached face to face.

As shown in FIG. 9, the main die can be completed after all the islands have been attached. Additional vertical vias 130 and metal wiring layers 132 can be added to provide connections from the main die to external components. The small die may only be connected to the main die, however, there may be additional vias and routing layers to provide direct or indirect connection between the small die and external components.

The technology and structure described in this article can be used not only for back-end level integration, but also for C4 (Controlled Collapse Chip Connection) (Controlled Collapse Chip Connection)) or the integration of the remote and back-end levels. Small or micro C4 bumps can be placed on one or more of the islands or the pads of the main die instead of direct metal compression or thermal bonding. When the small crystal grain is formed in contact with the main crystal grain, the contact layer does not directly contact the main crystal grain but contacts the main crystal grain through the micro C4 bumps. The assembly can then be reflowed so that the C4 bump provides the connection between the two dies. The assembly can be completed using standard C4 or solder bumps attached to the package substrate.

Small dies with thinned wafers can be attached in an array of C4 or solder bumps. Therefore, the additional small die will not affect the size of the entire package. By forming small crystal grains in a separate process, the small crystal grains can contain components that are very different from the components that can be formed on the main crystal grain. Devices that can achieve heterogeneous integration, such as silicon processing dies with gallium nitride voltage regulators, gallium arsenide optical waveguides, various passive devices, or RF modulators.

Figures 10 to 17 show alternative procedures for attaching a smaller die to a larger host die. FIG. 10 is a cross-sectional side view of a group of small dies 204 and 205 formed on the donor wafer 202. The small die is formed on the donor wafer as the substrate. The donor wafer contains many small dies to be transferred to the dies already formed on the master wafer as described above. The adhesive 208 has been applied on the front side of the small die.

The carrier wafer 210 is made of an inert and stable material (such as glass or silicon). The carrier wafer has an array of resistive heater elements 240 on the side facing the island, and the heater elements are configured to have Have the same or similar size as the island. The heater element is coupled to an external power source by passing through a through hole 242 of the carrier wafer. This is provided as an example of how to power resistive heater elements. The heater element can be powered in any other desired way. The top of the carrier wafer is covered in the dielectric layer 244 to cover and protect the heater element. The dielectric can be a rigid material, such as silicon dioxide or additional deposited glass.

In the example described herein, the carrier wafer may alternatively be formed of silicon with resistive metal wires patterned on one side. The wire can be connected to an external power source using a through silicon via (TSV) on the back side of the carrier.

The electrical connection to the resistance heater 240 can be formed by one or more routing layers on the heater side of the temporary carrier 210 instead of using the through hole 242. This will allow the power supply to be connected at the edge of the carrier on the front side of the temporary carrier. Alternatively, the metal wiring layer can be fabricated on the heater side or back side of the carrier 210 with or without TSV 242, so that less contact with the wafer is required to power all heater elements.

The metal wires may alternatively be separated from each other by dielectric materials. The dielectric can allow the top surface of the carrier wafer to be flatter by leveling out any defects. Many dielectrics can also be polished to provide an even flatter surface. The flatness allows a stronger bond with the adhesive 208 to be formed to the island.

The metal wires of the resistance heating element can be coated with a thin protective layer. The protective layer provides a physical separation between the heater wire and the bonding material 208 from. This will protect the wire from corrosion that may be caused to the metal wire by the bonding material.

The heat flow near the heater element can be slowed down and controlled in various ways. As mentioned, the carrier can be formed of a dielectric or non-thermal conductive material. This will reduce the heat flow from the heater element near one island to the heater element near the other island. The heater element may be located in an additional dielectric layer 244 at the top of the carrier wafer between the carrier and the island. The dielectric layer can be used as a thermal insulation layer between the heater and the main body of the carrier. An additional heat mitigation layer can also be fabricated between the heater and the carrier wafer as a thermal buffer.

FIG. 11 is a cross-sectional side view of the device wafer 202 of FIG. 10 attached to a temporary carrier 210 using a temporary adhesive 208. FIG. The front side of the die is covered by the carrier so that the wafer can be handled by the carrier. The donor wafer is aligned with the heater-integrated carrier wafer and is combined with the heater-integrated carrier wafer by providing a temporary adhesive for strong bonding. The temporary adhesive may be coated on the donor wafer, the carrier wafer, or the two wafers. A polymer or any other suitable adhesive can be used. The wafer then makes contacts to bond them together. The wafer can then be annealed at an elevated temperature to increase the bonding strength for the thinning of FIG. 12.

Fig. 12 is a cross-sectional side view of the device wafer and die of Fig. 11 after the device is thinned. The donor wafer can be ground, etched and polished. The carrier wafer provides mechanical stability during this process. The final donor wafer is thin and may have a coefficient of ten microns or less than 10 microns thick.

Fig. 13 is a cross-sectional side view of the die of Fig. 12 after the individual die is singulated by etching, sawing, or any other desired method. In this example, there are scribe trenches 206 between the singulated dies. The die can be further processed by adding vias, liners, metal layers, etc. In one example, the islands are singulated by masking and etching trenches between the islands until the adhesive or carrier wafer is exposed.

Fig. 14 is a cross-sectional side view of the die and the temporary carrier that have been inverted again so that the back side of the die is facing downward. The larger main die 222 is formed on the main wafer 220. The main wafer also has a stack underneath. There are vertical conductive pillars 214 with through-die vias to connect to pads or small die 205. The larger host die has a conductive redistribution layer or other metal or conductive layer with conductive lines or traces 224 above the die.

After alignment, the two wafers are joined together, for example, by moving the carrier wafer 210 toward the device wafer. The back sides of the islands 204 and 205 are pressed against the master wafer so that at least the selected island 205 physically contacts the mesa. Apply heat or pressure or both to form some kind of bond. In this example, the rest of the area of the master wafer, which is mainly made of ILD (Interlayer Dielectric), has little or no contact, and if any, is only a very weak bond, making these The area will be separated later.

The mesa 218 of the above type has been optionally fabricated on the device wafer. The mesa protrudes some thickness above the last layer 216 of the metal wire layer of the ILD. After singulation, the carrier/donor wafer is aligned with the device wafer and bonded to the device wafer using an annealing adhesive 208. When the mesa 218 is used, it protrudes from the surface of the device wafer so that it only makes contact with the selected island.

15 is a side view of the connection wafer of FIG. 14 with an external power supply 250 coupled to a resistive heater element using a through hole through the temporary carrier. This is to indicate that the heater is activated to heat the carrier in the area of the selected island. The actual electrical connection can be permanent, but at this time in the procedure, power is only applied to the desired heater.

The carrier wafer is selectively heated to weaken the adhesive bond 208 in the selected island 205 area. The weakened adhesive 209 will make it easier to transfer the selected island 205 from the carrier wafer to the device wafer. The heat can be used to anneal the fusion bond at the device-island interface. The heat can be used to weaken or de-bond the carrier-island interface. The heat can also be used to perform some combination of these two procedures.

For both organic (polymer) and inorganic adhesives, this heat can be used to drive chemical reactions. The rate of this reaction depends exponentially on temperature. For many adhesives, the reaction rate is slow at low temperatures. At room temperature, there is no significant change in the system for many minutes. The reaction is much faster at elevated temperatures. With an increase of 100°C in temperature, the rate of change can be a thousand times faster. For an increase of 200°C, the rate of change can be a million times faster. In the safe operating range from room temperature to about 400°C, the adhesive can be heated enough to degrade the bond in a short time.

The specific reaction depends on the precise nature of the adhesive. In most of In this case, the reaction system breaks the chemical bond. For polymers, large molecules are broken down into small molecules that cannot be held together well. The solid adhesive can liquefy in a given sufficient time. For inorganic materials, the gas system is released by breaking the chemical bond in the adhesive. The pressure of the released gas from the inside of the solid adhesive material causes the adhesive to break, thereby reducing its strength.

FIG. 16 is a diagram of separating the carrier wafer 210 from the main wafer 220. This causes the two crystal grains to be separated. The weakened bond 209 on the temporary adhesive is weaker than the bond with the main device. The applied heat has weakened the bond between the island die 205 and the temporary carrier wafer. The other dies 204 have strong bonds 208 and are placed on the carrier wafer 210 after separation. After separation, the carrier wafer can be used to apply the die to another master wafer. For this program, different heater elements will be activated.

Figure 17 is a diagram with the temporary carrier and other small dies removed. The one attached small die 205 remains bonded to the main die 222. The master wafer is further processed to completely embed the transferred small die into the interconnect stack. In the illustrated example, further processing includes additional dielectric 234 for connection to other components, additional conductive pillars or vias 230, and conductive contact pads or wires 232. The smaller die 205 is then completely buried in the ILD of the main die. The main die 222 can be implemented in various other ways. In this example, the islands on the device wafer are facing upwards. The device wafer can be further processed to form an electrical connection with the island by the device wafer interconnect stack or in any of various other ways. touch.

As described, specific islands can be selectively transferred by controlling the adhesive layer. Then, several different dies, which may have different technologies and heterogeneous substrates, can be integrated into the same die. This selective heating provides control of the island transfer procedure used in the batch full wafer method. This same or similar technique can also be used to select known good die for transfer and known faulty die not to transfer. This improved control and allows defective die to be rejected while still using the full-wafer method. This allows even smaller dies with poor productivity to be used by selecting only known good dies. This selective heating method is not controlled by the same geometric constraints as the full-wafer method. In other words, the island does not need to be in the same wafer configuration as the location where the island is received. The carrier wafer can be aligned and the islands can be selectively released. The wafer can then be moved again before one or more additional islands are released.

FIG. 18 shows a computing device 11 according to an embodiment of the present invention. The computing device 11 accommodates the board 2. The board 2 may include several components, including (but not limited to) a processor 4 and at least one communication chip 6. The processor 4 is physically and electrically coupled to the board 2. In some embodiments, the at least one communication chip 6 is also physically and electrically coupled to the board 2. In a further embodiment, the communication chip 6 is part of the processor 4.

Depending on its application, the computing device 11 may include other components that may or may not be physically and electrically coupled to the board 2. These other components include (but are not limited to) volatile memory (for example, DRAM) 8, non-volatile memory (for example, ROM) 9, flash memory (not shown), Shape processor 12, digital signal processor (not shown), encryption processor (not shown), chipset 14, antenna 16, display 18 (such as touch screen display), touch screen controller 20, battery 22 , Audio codec (not shown), video codec (not shown), power amplifier 24, global positioning system (GPS) device 26, compass 28, accelerometer (not shown), gyroscope (not shown) Shown), a speaker 30, a camera 32, and a mass storage device 10 (such as a hard disk drive, a compact disc (CD) (not shown), a digital versatile disc (DVD) (not shown), etc.). These components can be connected to the system board 2, mounted to the system board, or combined with any of other components.

The communication chip 6 implements wireless and/or wired communication for transferring data in and out of the computing device 11. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can communicate data through the use of modulated electromagnetic radiation through non-solid media. The term does not imply that the associated device does not contain any wires, although in some embodiments it may not. The communication chip 6 can implement any number of wireless or wired standards or protocols, including (but not limited to) Wi-Fi (IEEE802.11 series), WiMAX (IEEE802.16 series), IEEE802.20, Long Term Evolution (LTE), EvDO , HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, Ethernet and its derivatives, and any other referred to as 3G, 4G, 5G and more advanced wireless and wired protocols . The computing device 11 may include a plurality of communication chips 6. For example, the first communication chip 6 may be dedicated to shorter-distance wireless communication (such as Wi-Fi Fi and Bluetooth), and the second communication chip 6 can be dedicated to long-distance wireless communication (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others).

The processor 4 of the computing device 11 is an integrated circuit die package included in the processor 4. In some embodiments of the present invention, the integrated circuit die containing the processor, memory device, communication device, or other components is packaged together and combined in the main die as described herein on. The term "processor" can refer to any device or device that processes electronic data from a register and/or memory to convert the electronic data into other electronic data that can be stored in the register and/or memory The part.

In various embodiments, the computing device 11 may be a laptop computer, a small notebook computer, a notebook computer, an ultra-thin notebook computer, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile Telephone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player or digital video recorder. In a further embodiment, the computing device 11 may be any other electronic device that processes data including wearable devices.

The embodiment can be implemented as using a motherboard, a dedicated integrated circuit (ASIC) and/or a field programmable gate array (FPGA) to interconnect one or more memory chips, a controller, a CPU (central processing unit) (Central Processing Unit)), a part of a microchip or an integrated circuit.

References to "one embodiment", "embodiment", "embodiment embodiment", "various embodiments", etc. indicate that the embodiment(s) of the invention thus described may include specific features, structures, or characteristics, but Not every embodiment must include the specific feature, structure, or characteristic. Furthermore, certain embodiments may have some, all, or none of the features described for that embodiment.

In the following description and the scope of the patent application, the term "couple" and its derivatives may be used. "Coupling" is used to indicate that two or more elements cooperate or interact with each other, but may or may not have intervening physical or electrical components between them.

As used in the scope of the patent application, unless otherwise stated, the ordinal adjectives "first", "second", "third", etc. are used to describe common elements, which merely indicate that different examples of the same element are mentioned. And, it is not intended to imply that the elements so described must be in a given order in time, space, in order, or in any other way.

The diagram and the following description are examples of embodiments. Those skilled in the art will understand that one or more of the described elements can be appropriately combined into a single functional element. Alternatively, certain elements may be divided into multiple functional elements. Elements from one embodiment can be added to another embodiment. For example, the order of the procedures described herein can be changed and is not limited to the manner described herein. Furthermore, the actions of any flowchart need not be implemented in the order shown; nor are all actions required to be executed. In addition, those actions that are independent of other actions can be executed in parallel with other actions. The scope of the embodiments is by no means limited by these specific examples system. Regardless of whether it is explicitly given in the specification, many changes are possible, such as differences in the structure, size, and use of materials. The scope of the embodiments is at least as broad as given by the scope of the following patent applications.

The following examples are related to further embodiments. Various features of different embodiments can be combined with certain included features and other excluded features to adapt to various applications. Some embodiments relate to a method that includes forming a plurality of small dies on a wafer, attaching the dies to a temporary carrier, forming a plurality of larger main dies on the main wafer, and forming a plurality of large main dies on the main wafer. A raised mesa is formed on the grain at the position of the main die for receiving the small die, the temporary carrier is used to align the small die on the plurality of main die, and the temporary carrier is used for the small die. A die is applied to the main die so that a sub-assembly of the small die physically contacts the raised mesa of the respective main die and the small die that does not belong to the sub-assembly does not contact the main die, And the temporary carrier is separated, so that the sub-collection of the small crystal grains is left on the respective main crystal grains and is in contact with the raised mesa, and the remaining small crystal grains are separated from the main crystal grains and left in the temporary On the carrier.

A further embodiment includes bonding the subset of the small dies to the raised mesas of the respective main die.

In a further embodiment, the subset of the small dies are attached to the respective main die raised mesas after bonding and the remaining small dies are attached to the temporary carrier.

In a further embodiment, the bonding includes pressing the sub-assembly of the small crystal grains on the raised mesa of the respective main crystal grain, and the small crystal grains that do not belong to the sub-assembly do not contact the main crystal grain.

In a further embodiment, each raised mesa includes an additional layer of oxide on the region of the main die for receiving small crystal grains, and the raised mesa protrudes above the surface of the main die. thickness.

Some embodiments relate to a device that includes: a main crystal grain having a plurality of raised mesas, the raised mesa protruding higher than the surrounding layer of the main crystal; a plurality of small crystal grains, each small crystal grain position On the respective raised mesas, physically contact the respective raised mesas, and are electrically connected to the main die via the respective raised mesas; and a package for covering the main die and the small die together .

In a further embodiment, the small crystal grains are bonded to the main crystal grains by metal compression.

In a further embodiment, each raised mesa includes an additional layer of oxide on the region of the main die to be attached to the small die, and the raised mesa is on the periphery of the main die Some thickness protrudes above the layer.

Some embodiments relate to a method that includes forming a plurality of small dies on a wafer, attaching the die to a temporary carrier using an adhesive, and aligning the die on the main wafer using the temporary carrier The temporary carrier is used to apply the small crystal grains to the main crystal grains on the plurality of larger main crystal grains above, so that a subset of the small crystal grains physically contact the respective main crystal grains and weaken the small crystal grains. The adhesive between the sub-collection of grains and the temporary carrier, and the temporary carrier is separated, so that the sub-collection of the small crystal grains is left on the respective main crystal grains and the remaining small crystal grains and the main crystal grain And the temporary carrier is separated.

In a further embodiment, weakening the adhesive includes heating the adhesive Agent.

In a further embodiment, heating the adhesive includes activating an array of heating elements attached to the temporary carrier.

In a further embodiment, the array of heating elements is embedded in a dielectric layer formed on the temporary carrier.

In a further embodiment, the heating element is connected to an external power source through a through hole passing through the temporary carrier.

In a further embodiment, heating the adhesive includes applying heat to the temporary carrier on the side of the temporary carrier opposite the island.

A further embodiment includes singulating the small die after attaching the die to the temporary carrier.

A further embodiment includes encapsulating the main die by covering the small die in a dielectric and forming a metal wiring layer in the dielectric to connect the main die to external components.

A further implementation includes packaging the main die by attaching an array of solder balls to the main die surrounding the small die and attaching the array of solder balls to a packaging substrate.

Some embodiments relate to a carrier wafer that includes: a dielectric substrate; a surface for attaching a plurality of dies formed on a common substrate and attached to the common substrate; and heating An array of elements is attached to the temporary carrier to heat an area of the temporary carrier, the area corresponding to a specific die in the die.

In a further embodiment, the array of heating elements is embedded in the dielectric layer.

In a further embodiment, the heating element is connected to an external power source through a through hole passing through the temporary carrier.

102‧‧‧Donor Wafer

104‧‧‧Small grains

105‧‧‧Small grains

109‧‧‧Weakening

110‧‧‧Carrier wafer

116‧‧‧Last Floor

118‧‧‧Countertop

120‧‧‧Main device wafer

122‧‧‧Main grain

Claims (20)

A method of crystal grain integration includes: forming a plurality of small crystal grains on a wafer; attaching the crystal grains to a temporary carrier; forming a plurality of larger main crystal grains on the main wafer; A raised mesa is formed at the position of the main crystal grain for receiving small crystal grains, and the raised mesa protrudes a certain thickness above the surface of the main crystal grain; the temporary carrier is used to align the small crystal grains on the plurality of On the main die; using the temporary carrier to apply the small die to the main die so that the sub-collection of the small die physically contacts the raised mesa of the respective main die instead of the sub-collection The small crystal grains are not in contact with the main crystal grain; and the temporary carrier is separated so that the subset of the small crystal grains is left in the respective main crystal grains and is in contact with the raised mesa and the remaining small crystal grains and The main crystal grain is separated and left in the temporary carrier. For example, the method for integrating the crystal grains in the scope of the patent application further includes combining the sub-collection of the small crystal grains to the raised mesas of the respective main crystal grains. For example, in the method of die integration of the second item of the patent application, the sub-collections of the small die are attached to the raised mesas of the respective main die after being combined, and the remaining small die is attached to the temporary carrier. For example, the method of die integration of the second item of the patent application, wherein the combination includes pressing the sub-collection of the small die on the respective main die height The small crystal grains on the mesa other than the sub-collection do not touch the main crystal grain. Such as the method of die integration in the first patent application, wherein each raised mesa includes an additional layer of oxide on the region of the main die for receiving small die. An electronic device, comprising: a main crystal grain with a plurality of raised mesas, the raised mesa protruding higher than the surrounding layer of the main crystal; a plurality of small crystal grains, each small crystal grain is located on the respective raised mesa Above, physically contacting the respective raised mesas and electrically connected to the main die via the respective raised mesas; and a package for covering the main die and the small die together. For example, the electronic device of item 6 of the scope of patent application, wherein the small crystal grain is bonded to the main crystal grain by metal compression. For example, the electronic device of item 6 of the scope of patent application, wherein each raised mesa includes an additional layer of oxide on the region where the main die is attached to the small die, and the raised mesa is on the main crystal. Some thickness protrudes above the surrounding layer of the pellets. A die integration method includes: forming a plurality of small die on a wafer; attaching the die to a temporary carrier using an adhesive; using the temporary carrier to align the die on the main wafer A larger main crystal grain; using the temporary carrier to apply the small crystal grain to the main crystal grain, so that the sub-collections of the small crystal grains physically contact the respective main crystal grains; Weaken the adhesive between the sub-collection of the small crystal grains and the temporary carrier; and separate the temporary carrier so that the sub-collection of the small crystal grains remains in the respective main crystal grains and the remaining small crystal grains are connected to the temporary carrier The main die and the temporary carrier are separated. Such as the method of die integration of the 9th patent application, wherein weakening the adhesive includes heating the adhesive. For example, the die integration method of claim 10, wherein heating the adhesive includes activating an array of heating elements attached to the temporary carrier. Such as the die integration method of the 11th patent application, wherein the array of the heating elements is embedded in a dielectric layer formed on the temporary carrier. Such as the method of die integration of the 12th patent application, wherein the heating element is connected to an external power source through a through hole passing through the temporary carrier. Such as the method of die integration of the 10th patent application, wherein heating the adhesive includes applying heat to the temporary carrier on the side opposite to the island portion of the temporary carrier. For example, the method for integrating the die of the 10th patent application scope further includes singulating the small die after attaching the die to the temporary carrier. For example, the method of crystal grain integration of the tenth item of the patent application, which further includes the method of covering the small crystal grains in a dielectric substance and in the dielectric substance A metal wiring layer is formed to connect the main die to external components to encapsulate the main die. For example, the die integration method of claim 10, which further includes packaging the main die by attaching the solder ball array to the main die, surrounding the small die and attaching the solder ball array to the packaging substrate . A carrier wafer includes: a dielectric substrate; a surface for attaching a plurality of dies formed on a common substrate and attached to the common substrate; and an array of heating elements attached to the common substrate The temporary carrier is used to heat the area of the temporary carrier, and the area corresponds to a specific crystal grain in the crystal grain. Such as the carrier wafer of the 18th patent application, wherein the array of the heating elements is embedded in the dielectric layer. For example, the carrier wafer of item 18 of the scope of patent application, wherein the heating element is connected to an external power source through a through hole passing through the temporary carrier.

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