TWI720604B - Semiconductor devices and methods for fabricating the same - Google Patents

Abstract

A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Description

Semiconductor device and manufacturing method thereof

The embodiments of the present invention are related to semiconductor technology, and particularly related to semiconductor devices and manufacturing methods thereof.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each of which has smaller and more complex circuits than the previous generation. In the history of the development of integrated circuits, functional density (that is, the number of interconnected devices per chip area) has increased, while geometric size (that is, the smallest component (or circuit) produced during the manufacturing process) has shrunk. This miniaturization process generally provides advantages by increasing production efficiency and reducing related costs. This miniaturization has also increased the complexity of processing and manufacturing integrated circuits, and in order to realize these advances, similar developments in the processing and manufacturing of integrated circuits are required.

For example, when forming the source/drain (S/D) components of a fin field effect transistor (FINFET), part of the source/drain components is epitaxially grown on the fin In the source/drain region of a FET. Multiple epitaxial source/drain features on different fins can be combined during their growth to form a combined source/drain feature. In this way, a single contact feature can be formed on the combined source/drain feature to control the source/drain of multiple fins. Although the combined source/drain component is a useful integrated circuit structure, the shape and profile of the combined source/drain component are often difficult to control. Although the existing source/drain formation process usually meets its intended purpose, the existing source/drain formation process is not completely satisfactory in all respects (for example, it can be used for n-type or p-type fin field effect transistors). Of different shapes and contours).

In some embodiments, a method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor structure, the semiconductor structure having: a substrate; and a first fin, a second fin, a third fin, and a fourth fin located above the substrate; N-type epitaxy source/drain features are formed on the fin and the second fin; p-type epitaxy source/drain features are formed on the third and fourth fin; and a selective etching process is performed on the semiconductor structure to remove Except for the upper part of the n-type epitaxial source/drain part and the p-type epitaxial source/drain part, the n-type epitaxial source/drain part is removed more than the p-type epitaxial source/drain part There are more parts to remove.

In some other embodiments, a method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor structure having a substrate and a first fin and a second fin on the substrate; removing the upper portion of the first fin and the second fin, and Keep the lower part of the first fin and the second fin; grow the first epitaxial source/drain part and the second epitaxial source/drain part on the lower part of the first fin and the second fin, so that the first epitaxial The source/drain component and the second epitaxial source/drain component are combined to form a combined source/drain component with a controllable combined height; a recessed trench is formed in the combined source/drain component; And filling the recessed trench with the source/drain contacts, the source/drain contacts are electrically connected to merge the source/drain components.

In some other embodiments, a semiconductor device is provided. The semiconductor device includes a substrate; a first fin, a second fin, a third fin, and a fourth fin protruding from the substrate; A fin and a second fin; the first source/drain contact is arranged on the n-type epitaxial source/drain part; the p-type epitaxial source/drain part is arranged on the third fin and the second fin On four fins; the second source/drain contact is arranged on the p-type epitaxial source/drain component, wherein the bottom surface of the first source/drain contact is lower than the second source/drain The bottom surface of the contact.

It should be understood that the following disclosure provides many different embodiments or examples to implement different components of the provided body. Specific examples of each component and its arrangement are described below in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes that a first part is formed on or above a second part, which means that it includes an embodiment in which the formed first part and the second part are in direct contact, and also includes This is an embodiment in which an additional component can be formed between the first component and the second component, and the first component and the second component may not be in direct contact. In addition, different examples in the disclosure may use repeated reference symbols and/or words. These repeated symbols or words are used for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and/or the appearance structure.

Furthermore, the following cases where a component is formed on another component, connected to another component and/or coupled to another component may include an embodiment in which the component is formed in direct contact, or may include forming an additional component and inserting these components Between the embodiments, these components may not be in direct contact. In addition, in order to facilitate the description of the relationship between one component and another component in the diagram, space-related terms can be used, such as "below", "above", "horizontal", "vertical", "above", "above" , "Below", "below", "above", "below", "top", "bottom", etc. and derivatives of the foregoing (such as "horizontally", "vertically", "upwardly "Wait). Spatially related terms are intended to cover different orientations of devices containing components. Furthermore, when "about", "approximately" and similar terms are used to describe numbers or ranges of numbers, the purpose of this term is to cover numbers within a reasonable range, such as within +/- 10% of the number described, or Other numerical values understandable by those skilled in the art. For example, the term "about 5 nm" encompasses the size range of 4.5 nm to 5.5 nm.

During the manufacturing of semiconductor transistor devices, since multiple epitaxial source/drain components are merged during their growth, it is sometimes difficult to precisely control the height of the combined source/drain components (referred to as "merging height" ( merge height, MH)). Since the source/drain contact feature is above the combined source/drain feature, the combined height can affect the capacitance (C) between the source/drain contact feature and the nearby metal gate structure. Furthermore, when etching the contact holes used to deposit the source/drain contact features, it is sometimes difficult to optimize the contact hole profile for both the n-type fin field effect transistor and the p-type fin field effect transistor at the same time. Depending on whether the combined source/drain components are used for n-type fin field effect transistors or p-type fin field effect transistors, the ideal contact hole profile is also different. For example, for an n-type fin field effect transistor, a deeper contact recess on the combined source/drain component can reduce the contact resistance between the contact component and the combined source/drain component (R ). For p-type fin field effect transistors, a deeper contact notch can disadvantageously increase the contact resistance.

The embodiment of the present invention provides a method for forming an epitaxial structure having an optimized shape profile for reducing resistance and capacitance. According to some embodiments, the merged source/drain features may be formed with an elevated merge height (MH). The increased merging height reduces the overlap area between the source/drain components and the nearby metal gate, thus reducing the capacitance (C) therebetween. The increased combined height is achieved through multiple technologies. As a first example, before forming the combined source/drain features, the two lower fins are partially etched to provide space for epitaxial growth of the source/drain features. During this part of the etching process, maintaining a higher height of the remaining fin sidewalls will increase the combined height. The height of the sidewalls of the fins and therefore the increased combined height may be in the range of about 3-15 nm compared to the conventional manufacturing process, or about 0.1-0.5 times the fin pitch. As a second example, the epitaxial growth conditions of the source/drain features can be adjusted to delay the merging of the individual source/drain features on the fin. The details of the embodiments are described below in conjunction with the drawings.

FIG. 1 shows a flowchart of a method 10 of forming a semiconductor device 100 (hereinafter also referred to simply as a device) according to some embodiments of the present invention. Method 10 is only an example, and it is not intended to limit the embodiments of the present invention to the scope clearly stated in the scope of the patent application. Additional operations may be performed before, during, and after method 10, and for other embodiments of this method, some of the operations described may be replaced, eliminated, or moved. The method 10 is described below in conjunction with other figures. The other figures show various three-dimensional views and cross-sectional schematic diagrams of the semiconductor device 100 during the intermediate steps of the method 10. In particular, FIG. 2A shows a three-dimensional view of the semiconductor device 100. Figures 2B, 3A, and 4 show the semiconductor device 100 along the line AA of Figure 2A Schematic cross-section. 2C and 3B show schematic cross-sectional views of the semiconductor device 100 along the line BB of FIG. 2A. Figures 5 and 7 show enlarged views of the semiconductor device 100 along line AA, but with additional combined epitaxial source/drain components. Figures 6A-6E show a partial view of Figure 5 through the notch forming process.

The semiconductor device 100 may be an integrated circuit (IC) or an intermediate device manufactured during the processing of a part of the integrated circuit, which may include static random-access memory (SRAM) and/or other logic circuits, Passive components (e.g. resistors, capacitors, inductors) and active components (e.g. p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), fin field effect transistors (FINFETs), metal oxide semiconductor field effect Transistors (metal-oxide semiconductor field effect transistors, MOSFET), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors and/or others Memory unit). The embodiments of the present invention are not limited to any specific number of devices or device regions or any specific device configuration. For example, although the semiconductor device 100 shown is a three-dimensional field-effect transistor device (such as a fin-type field-effect transistor or a gate-all-around (GAA) transistor), the present disclosure may also provide for manufacturing An embodiment of a planar field effect transistor device.

Referring to FIGS. 1 and 2A-2C, the method 10 provides (or provides) a semiconductor device 100 starting at operation 12. The semiconductor device 100 includes one or more semiconductor fins 106 protruding from the substrate 102 and separated by the isolation structure 104 (Sometimes referred to as "fin"). The dummy gate stack 107 is disposed above the substrate 102 and intersects the semiconductor fin 106. The semiconductor device 100 may include other components, such as gate spacers (not shown) disposed on the sidewalls of the dummy gate stack 107, various hard mask layers disposed on the dummy gate stack 107 (discussed in detail below) , Barrier layer, other suitable layers or a combination of the foregoing.

The substrate 102 may include elemental (single element) semiconductors (e.g., silicon, germanium and/or other suitable materials), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, antimony Indium and/or other suitable materials), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP and/or other suitable materials). The substrate 102 may be a single layer of material with uniform composition. Alternatively, the substrate 102 may include multiple material layers with similar or different compositions suitable for the manufacture of integrated circuit devices. In one example, the substrate 102 may be a silicon-on-insulator (SOI) substrate with a silicon layer formed on a silicon oxide layer. In another example, the substrate 102 may include a conductive layer, a semiconductor layer, other layers, or a combination of the foregoing.

In some embodiments where the substrate 102 includes a field-effect transistor, various doped regions (such as source/drain regions) are disposed in or on the substrate 102. Depending on design requirements, the doped region may be doped with p-type impurities (such as phosphorus or arsenic) and/or n-type impurities (such as boron or BF ₂ ). The doped region may be directly formed on the substrate 102, in a p-type well structure, in an n-type well structure, in a dual-well structure, or use a raised structure. The doped region can be formed by implanting dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques.

The semiconductor fin 106 may be suitable for providing an n-type field effect transistor or a p-type field effect transistor. In some embodiments, the semiconductor fin 106 shown herein can be adapted to provide similar types of fin field effect transistors, that is, all n-type or all p-type. Alternatively, the semiconductor fin 106 shown herein may be adapted to provide opposite types of fin field effect transistors, namely n-type and p-type. This configuration is for display purposes, but not limited to this. The semiconductor fin 106 can be manufactured by using a suitable process (including photolithography and etching processes). The photolithography process may include forming a photoresist layer (photoresist) on the substrate 102, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element (not shown) containing photoresist ). Next, a mask element is used when etching the notch in the substrate 102, leaving the semiconductor fin 106 on the substrate 102. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

Many other method embodiments for forming the semiconductor fin 106 may be suitable. For example, the semiconductor fin 106 can be patterned by using a double patterning or multiple patterning process. Usually In other words, the double patterning or multiple patterning process combines photolithography and self-alignment processes to create a pattern with a smaller pitch. For example, this pattern has a larger pitch than can be obtained using a single direct photolithography process. Small patterns. For example, in one embodiment, the sacrificial layer is formed on the substrate and patterned by using a photolithography process. The spacer is formed beside the patterned sacrificial layer by using a self-aligned process. Next, the sacrificial layer is removed, and the remaining spacers or mandrels can then be used to pattern the fins. In some embodiments, after the semiconductor fin 106 is formed, the semiconductor fin 106 has a height (marked with the symbol F_H in FIG. 2C) between about 50 to about 90 nm. The height of the fin is important for device performance and direct current/alternating current (DC/AC) balance.

Each semiconductor fin 106 includes a channel region 106b and two source/drain regions 106a sandwiching the channel region 106b therebetween. The source/drain region 106a is used as the source and drain of the field effect transistor, and the channel region 106b under the dummy gate stack 107 is used as the channel region connecting the source and drain. In some embodiments, the method 10 may include forming a lightly doped drain (LDD) feature in the source/drain region 106a of the semiconductor fin 106.

The isolation structure 104 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and/or other suitable materials. The isolation structure 104 may include shallow trench isolation (STI) features. In one embodiment, the isolation structure 104 is formed by etching trenches in the substrate 102 during the formation of the semiconductor fin 106. Then, the trench is filled with the above-mentioned isolation material through a deposition process, and then a chemical mechanical planarization (CMP) process is performed. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS) and/or other suitable structures can be used as the isolation structure 104. Alternatively, the isolation structure 104 may include a multilayer structure, for example, having one or more thermal oxide liner layers. The isolation structure 104 can be deposited by any suitable method, such as chemical vapor deposition (chemical vapor deposition, CVD), flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or a combination of the foregoing. The isolation structure 104 can be formed by depositing a dielectric layer above the semiconductor fin 106 as a spacer layer, and then recessing the dielectric layer so that the top surface of the isolation structure 104 is below the top surface of the semiconductor fin 106.

In some embodiments, the dummy gate stack 107 serves as the subsequent formation of a high-k metal gate structure (HKMG) ("high-k" represents a dielectric constant greater than that of silicon dioxide , The dielectric constant of silicon dioxide is about 3.9) placeholder. The dummy gate stack 107 may include an oxide layer 108 disposed above the channel region 106b. The oxide layer 108 may be formed by any suitable method, which may include deposition and etching. The oxide layer 108 may include silicon oxide or high dielectric constant oxide (having a dielectric constant greater than that of silicon oxide), such as Hf oxide, Ta oxide, Ti oxide, Zr oxide, Al oxide or the foregoing的组合。 The combination. The oxide layer 108 may be formed to have a thickness of several angstroms (Å) to several tens of angstroms.

The dummy gate stack 107 may include a dummy gate electrode 110. In some embodiments, the dummy gate electrode 110 includes polysilicon. In the embodiment shown, referring to FIG. 2C, the dummy gate stack 107 also includes a hard mask layer 112 disposed above the dummy gate electrode 110 and/or a hard mask disposed above the hard mask layer 112层114. The sidewall spacer 113 is formed on the sidewall of the dummy gate electrode 110. As will be discussed in detail below, during the gate replacement process after manufacturing other components of the semiconductor device 100 (such as the barrier source/drain component 250), the dummy gate stack 107 is replaced with a high-k gate structure. The hard mask layers 112 and 114 may each include any suitable dielectric material, such as semiconductor oxide and/or semiconductor nitride. In one example, the hard mask layer 112 includes silicon carbide nitride, and the hard mask layer 114 includes silicon oxide. The various material layers of the dummy gate stack 107 can be formed by a suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (atomic layer deposition), chemical oxidation, Other suitable processes or combinations of the foregoing.

Please refer to FIGS. 1 and 3A-3B. In operation 14, the method 10 shortens the source/drain region 106a by removing the upper part of the semiconductor fin 106 while retaining the lower part of the semiconductor fin 106 in the source/drain region 106a. section. In many embodiments, the method 10 uses a suitable etching process, such as a dry etching process, a wet etching process, or a reactive ion etching process. In some embodiments, the method 10 selectively removes the semiconductor fin 106 without etching or substantially without etching other components such as the dummy gate stack 107. The etching process in operation 14 may include bromine-containing gas (such as HBr and/or CHBr ₃ ), fluorine-containing gas (such as CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and/or C ₂ F ₆ ), and others Dry etching process with suitable gas or a combination of the aforementioned etchant. The degree of removing the semiconductor fin 106 can be controlled by adjusting the conditions of the etching process (such as pressure, temperature, and duration). In some embodiments, the etching gas uses an etchant containing HBr and CF ₄ , the pressure is between about 5 and about 30 mTorr, and the temperature is between about 30 and about 60°C. In some embodiments, the etching lasts about 5 to about 10 seconds. In some embodiments, as shown in FIG. 3B, the etching process removes the upper portion of the semiconductor fin 106 in operation 14 so that the remaining height of the semiconductor fin 106 (marked as FSW_H in FIG. 3B, where FSW represents the sidewall of the fin) Between about 30% and about 40% of the original height of the semiconductor fin 106 (ie F_H). As described below, retaining this relatively high remaining fin sidewall height helps increase the combined height of the combined epitaxial source/drain features.

After shortening the source/drain region 106a, method 10 proceeds to forming epitaxial source/drain features on the shortened source/drain region 106a. FIG. 4 shows a simplified view focusing on two epitaxial source/drain components 120A and 120B grown on the semiconductor fin 106 and finally merged into one combined epitaxial source/drain component 120. Referring to FIGS. 1 and 4, in method 10, in operation 16, epitaxial source/drain features 120A and 120B are grown on two source/drain regions 106a located on the same side of the dummy gate stack 107. The epitaxial source/drain components 120A and 120B are initially grown on individual fins individually, and finally merged together at a specific height (called merge height (MH)) to form merged epitaxial source/drain components 120.

The embodiment of the present invention enables the combined epitaxy source/drain component 120 to achieve an optimized shape profile for reducing resistance and capacitance. In some embodiments, by controlling the growth conditions and by increasing the remaining fin height (FSW_H) from about 3 to about 15 nm, the combined epitaxial source/drain component 120 may have an increased combined height (MH) such as ratio The combined epitaxy source/drain features formed using other technologies are about 2 to about 10 nm taller. This increased merging height shrinks the overlapping area of the merged epitaxy source/drain feature 120 and the nearby metal gate (which will be formed as a replacement dummy gate stack 107), and thus reduces the capacitance (C) therebetween.

The increased combined height of the combined epitaxial source/drain component 120 can be achieved through a variety of technologies. In an example (as in reference operation 14 above), before forming the combined epitaxial source/drain feature 120, the two underlying semiconductor fins 106 are partially etched to provide space for epitaxial growth of the source/drain feature . During the partial etching process, retaining a high remaining fin sidewall height (for example, about 30% to about 40% of the fin height) helps to increase the combined height of the combined epitaxial source/drain features 120.

In another example, the epitaxial growth conditions of the source/drain features can be adjusted to delay the merging of the individual epitaxial source/drain features 120A and 120B on the semiconductor fin 106. In one embodiment, the combined epitaxial source/drain component 120 has multiple layers of semiconductor material, and the multiple layers of semiconductor material include a first layer (L1) (sometimes referred to as a first epitaxial layer) (not shown), and a second Layer (L2-1) (sometimes referred to as the second epitaxial layer) (not shown) and the third layer (L2-2) (sometimes referred to as the third epitaxial layer). Changing the formation conditions of these layers can result in a controllable merging height. In some embodiments, the first layer L1 is deposited on the top surface and the sidewall surface of the source/drain region 106a. Furthermore, the second layer L2-1 surrounds the first layer L1. In the embodiment shown in Figure 4, the first layer L1 of the epitaxial source/drain features 120A and 120B is not merged, but the second layer L2-1 of the epitaxial source/drain features 120A and 120B is merged laterally (Ie touching each other). In order to form the structure shown in FIG. 4, before the third layer L2-2 is grown, operation 16 waits until the second layer L2-1 is merged laterally. It can be noted that, depending on the lateral distance (along the "x direction") between the two semiconductor fins 106 and the control of epitaxial growth, the first layer L1 and the second layer L1 The layer L2-1 can be formed with different merged profiles.

In various embodiments, the different epitaxial layers may include the same or different semiconductor materials, such as silicon, germanium, silicon germanium, one or more group III-V materials, compound semiconductors, or alloy semiconductors. In one embodiment, the semiconductor fin 106 includes silicon, and the epitaxial layer includes silicon germanium. The epitaxial growth process can be a low-pressure chemical vapor deposition process with a silicon-based precursor, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process. For example, silicon crystals can be grown by low-pressure chemical vapor deposition with silane (SiH _{4) and dichlorosilane (DCS) gases.} The controllable merging height may depend on _{the ratio between silane (SiH 4} ) and dichlorosilane (DCS) gases, which are used to form the second layer L2-1. In some embodiments, the controllable combined height is not less than about 55% of the height (F_H) of the semiconductor fin 106.

In some embodiments, the combined epitaxial source/drain component 120 includes: a first layer (L1) of semiconductor material grown on the lower portion of the first and second semiconductor fins 106, and a first layer (L1) grown on the first layer L1 The second layer (L2-1) of semiconductor material and the third layer (L2-2) of semiconductor material grown on the second layer L2-1. In an embodiment, the first layer L1 on the first semiconductor fin 106 is not merged with the first layer L1 on the second semiconductor fin 106, and the second layer L2-1 on the first semiconductor fin 106 and the second semiconductor fin 106 The second layer L2-1 on the fin 106 merges at a controllable merge height. _{The controllable merging height depends on the ratio between the silane (SiH 4} ) and dichlorosilane (DCS) gases used to form the second layer L2-1. In some embodiments, _{the ratio between silane (SiH 4} ) and dichlorosilane (DCS) gas may be about 1:15 to about 1:50. In an embodiment, the controllable combined height is not less than about 55% of the height of the first semiconductor fin and the second semiconductor fin. In an embodiment, the third layer L2-2 has a substantially compliant thickness on the first semiconductor fin and the second semiconductor fin.

After the combined epitaxial source/drain feature 120 is formed, the method 10 proceeds to forming on the combined epitaxial source/drain feature 120 for forming the source/drain feature on the combined epitaxial source/drain feature 120 pole The notch of the contact. As described above, depending on the combination of source/drain components for n-type fin field effect transistors or p-type fin field effect transistors, the ideal contact hole profile is different. For example, for an n-type fin field effect transistor, a deeper contact recess on the combined source/drain component can reduce the contact resistance between the contact component and the combined source/drain component (R ). For p-type fin field effect transistors, a deeper contact notch can disadvantageously increase the contact resistance. As described below, the embodiments of the present invention allow an optimized notch profile for n-type fin field effect transistors or p-type fin field effect transistors. In order to show two different profiles for n-type fin field effect transistors or p-type fin field effect transistors, Figure 5 shows a cross-sectional schematic diagram of two combined epitaxy source/drain components, which includes n-type combined epitaxy The source/drain component 130 and the p-type combined epitaxial source/drain component 140, unless otherwise specified, the n-type combined epitaxial source/drain component 130 and the p-type combined epitaxial source/drain component 130 The pole component 140 is similar to the combined epitaxial source/drain component 120.

Referring to FIGS. 1 and 5, the method 10 recesses the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140 in operation 18 to form a recessed trench therein. According to some embodiments, the contour of each notch is optimized to reduce the contact resistance between the contact feature and the epitaxial source/drain feature. Depending on whether the epitaxial source/drain components are used for n-type fin field effect transistors or p-type fin field effect transistors, different notch profiles can be formed. As shown in FIG. 5, for the n-type combined epitaxial source/drain component 130, a relatively deep contact recess 132 (sometimes called a recessed trench, or a recess for short) is formed. The recess 132 is deep enough to ensure that all bottom silicon nitride (SiN) disposed on the n-type combined epitaxial source/drain feature 130 is removed, because any remaining silicon nitride can increase contact resistance. The notch 132 is not deep enough to etch through the n-type combined epitaxial source/drain feature 130. For the p-type combined epitaxy source/drain component 140, a relatively shallow contact notch 142 (sometimes called a recessed trench, or notch for short) is formed so that the source/drain contact can directly contact Source/drain regions with higher Ge and/or B concentration. The notch 132 may have a depth 132a in the range of about 15-20 nm, and the notch 142 may have a depth 142a in the range of about 5-10 nm. In some In an embodiment, the amount of material removed from the n-type field-effect transistor device using the selective etching process described herein may be 1.5-2.5 times the amount of material removed from the p-type field-effect transistor device.

Please refer to FIGS. 6A-6E. In operation 18, the difference in the depth of the notches 132 and 142 can be achieved by adjusting the etching conditions to achieve different etching rates of the source/drain components. In one embodiment, the n-type combined epitaxy source/drain feature 130 includes silicon-doped phosphorus but no silicon germanium, and the p-type combined epitaxy source/drain feature 140 includes silicon germanium. A selective etching process can be performed on the semiconductor structure to remove the upper part of the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140, where the n-type combined epitaxial source/drain feature The removed portion of the pole component 130 is thicker than the removed portion of the p-type combined epitaxial source/drain component 140 (for example, the corresponding point on the epitaxial source/drain component is 1.5 times to 2.5 times thicker). FIG. 6A shows the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140 before applying the selective etching process.

In the illustrated embodiment, the selective etching process includes a plurality of cycles, wherein each cycle includes a first dry etching process of the semiconductor structure using a gas mixture, as shown in FIGS. 6B-6D. As shown in FIG. 6B, the top surfaces of the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140 are in contact with the etching gas. In some embodiments, the etching gas is a mixture containing fluoromethane (CH ₃ F), hydrogen (H ₂ ), and carbonyl sulfide (COS). As an example of the ratio between the gas components, it may be about 1 part of fluoromethane (CH ₃ F), about 10 to 20 parts of hydrogen (H ₂ ), and about 0.5 to about 1.5 parts of carbonyl sulfide (COS). In the first dry etching process, the gas mixture reacts with the silicon germanium in the p-type epitaxial source/drain components to form a polymer layer 150 _{containing germanium sulfide (GeS or GeS 2 ).} The first dry etching process removes the first thickness of the n-type epitaxial source/drain feature and the second thickness of the p-type epitaxial source/drain feature. Due to the presence of the polymer layer 150 on the p-type epitaxial source/drain features, the second thickness (which may be close to 0) may be smaller than the first thickness (for example, less than about 1 nm). _{As shown in FIG. 6B, the first dry etching process also forms carbon fluoride (C x} F _y ) as a by-product on the n-type epitaxial source/drain features and the p-type epitaxial source/drain features. In one embodiment, the thickness of the carbon fluoride layer 160 before washing is equal to or less than about 5 nm. Therefore, as shown in FIG. 6C, each cycle of the selective etching process also includes performing a second dry etching process on the semiconductor structure using a gas _{containing diimide (N 2} H _{2) to remove the first dry etching process.} Carbon fluoride formed during the manufacturing process. In one embodiment, the thickness of the germanium sulfide (GeS or GeS ₂ ) layer after etching is equal to or less than about 1 nm. After multiple cycles of the selective etching process, as shown in FIG. 6D, more n-type combined epitaxial source/drain features 130 can be etched than p-type combined epitaxial source/drain features 140. As shown in FIG. 6E, a wet etching process may be performed to remove the GeS/GeS ₂ formed in the first dry etching process in each cycle to form p-type epitaxial source/drain features.

In one embodiment, the multiple cycles of the selective etching process are performed at a temperature between 20-60° C. and a pressure between 10-30 mTorr. In one embodiment, during each cycle of the selective etching process, the first thickness of the n-type epitaxial source/drain feature is removed than the second thickness of the p-type epitaxial source/drain feature is removed At least 1nm thicker. In one embodiment, the thickness of the removed portion of the n-type epitaxial source/drain component is about 1.5 times to about 2.5 times the thickness of the removed portion of the p-type epitaxial source/drain component.

In one embodiment, the step of forming the recess 132 (or 142) includes etching the combined source/drain features to form an intermediate trench, and depositing silicon nitride (such as Si ₃ N ₄ ) in and above the intermediate trench For the spacer part, use anisotropic etching to remove the bottom of the silicon nitride spacer part, while leaving the sidewall part of the silicon nitride spacer part, and further etch the combined source/drain part in the middle trench, In turn, a notch is formed.

Referring to FIG. 5, the method 10 also forms silicide or germanium silicide on the surface of the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140. For example, metal can be deposited on the n-type combined epitaxial source/drain feature 130 and the p-type combined epitaxial source/drain feature 140 Layer, the metal layer is annealed so that the metal layer reacts with the silicon in the n-type combined epitaxial source/drain part 130 and the p-type combined epitaxial source/drain part 140 to form a metal silicide, and then remove the silicon The reacted metal layer forms a silicide (such as nickel silicide or titanium silicide). In other embodiments, method 10 does not form silicides, and method 10 forms source/drain contacts after etching the contact holes, as described below.

Referring to FIG. 7, in method 10, in operation 20, source/drain contacts 134 and 144 are formed on the n-type combined epitaxial source/drain component 130 and the p-type combined epitaxial source/drain component 140, respectively. . As shown in Figure 7, since the notch 132 on the n-type combined epitaxial source/drain part 130 is deeper than the notch 142 on the p-type combined epitaxial source/drain part 140, the source/drain part The bottom surface of the drain contact 134 is lower than the bottom surface of the source/drain contact 144. The source/drain contact 134 in the n-type combined epitaxial source/drain component 130 may have a depth 134a in the range of about 15-20 nm. The source/drain contact 144 in the p-type combined epitaxial source/drain component 140 may have a depth 144a in the range of about 5-10 nm. Each source/drain contact can include one or more conductive layers, and can be formed using any suitable method, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, and/or other suitable processes . In some embodiments, each source/drain contact includes a seed metal layer and a filler metal layer. In various embodiments, the seed metal layer includes cobalt (Co), tungsten (W), ruthenium (Ru), nickel (Ni), other suitable metals, or a combination of the foregoing. The filling metal layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or a combination of the foregoing.

Please refer to FIG. 1, the method 10 proceeds to operation 22 to perform additional processing steps. For example, additional vertical interconnection features (such as vias), horizontal interconnection features (such as wires), and/or multilayer interconnection features (such as metal layers and interlayer dielectrics) may be formed over the semiconductor device 100. Various conductive materials can be applied to various interconnection components, including copper (Cu), tungsten (W), cobalt (Co), aluminum (Al), titanium (Ti), tantalum (Ta), platinum (Pt), molybdenum (Mo) ), silver (Ag), gold (Au), manganese (Mn), zirconium (Zr), ruthenium (Ru), the aforementioned corresponding alloys, metal silicides, other suitable materials or a combination of the foregoing. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable metal silicides, or a combination of the foregoing.

Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. The embodiment of the present invention provides a method for forming a combined epitaxial source/drain component with an optimized profile. Embodiments of the present invention include forming merged epitaxial source/drain components with controllable merge height and notch depth. Therefore, the disclosed epitaxial source/drain component reduces the contact resistance with the upper source/drain contact and the capacitance with the nearby metal gate structure.

According to an example, a method of manufacturing a semiconductor device includes providing a semiconductor structure having a substrate and a first fin, a second fin, a third fin, and a fourth fin located above the substrate. The method further includes forming n-type epitaxial source/drain (S/D) features on the first and second fins, and forming p-type epitaxial source/drain features on the third and fourth fins , And perform a selective etching process on the semiconductor structure to remove the upper part of the n-type epitaxial source/drain components and the p-type epitaxial source/drain components, so that the n-type epitaxial source/drain components are moved The removed part is more than the removed part of the p-type epitaxial source/drain component.

In some other embodiments, the selective etching process includes a plurality of cycles, and each cycle includes: using a first etching gas to perform a first dry etching process on the semiconductor structure; using a second etching gas different from the first etching gas A second dry etching process is performed on the semiconductor structure; and a wet etching process is performed to remove the polymer layer formed in the first dry etching process.

In some other embodiments, the first etching gas is a gas mixture containing fluoromethane, hydrogen, and carbonyl sulfide, and the gas mixture is combined with the silicon germanium in the p-type epitaxial source/drain component in the first dry etching process. The reaction further forms a polymer layer containing silicon sulfide.

In some other embodiments, the first dry etching process removes the first thickness of the n-type epitaxial source/drain feature, and the first dry etching process removes the second thickness of the p-type epitaxial source/drain feature Thickness. Since the polymer layer is on the p-type epitaxial source/drain part, the second thickness is smaller than the first thickness, and the first dry etching process is also used for the n-type epitaxial source/drain part and the p-type epitaxial source/drain part. Carbon fluoride is formed as a by-product on the epitaxial source/drain components.

In some other embodiments, where the second etching gas includes diimine, the diimine is configured to remove carbon fluoride formed in the first dry etching process.

In some other embodiments, the wet etching process removes the silicon sulfide formed in the first dry etching process in each cycle from the p-type epitaxial source/drain features.

In some other embodiments, the multiple cycles of the selective etching process are performed at a temperature between 20-60° C. and a pressure between 10-30 mTorr.

In some other embodiments, during each cycle of the selective etching process, the first thickness of the n-type epitaxial source/drain feature is at least greater than the second thickness of the p-type epitaxial source/drain feature At least 1nm.

In some other embodiments, the thickness of the removed portion of the n-type epitaxial source/drain component is about 1.5 to about 2.5 times the thickness of the removed portion of the p-type epitaxial source/drain component.

In some other embodiments, the formation of the n-type epitaxial source/drain features includes silicon-doped phosphorous, but does not include silicon germanium, and the formation of the p-type epitaxial source/drain features includes silicon germanium.

According to an example, a method includes providing a semiconductor structure having a substrate and a first fin and a second fin on the substrate, removing the upper part of the first fin and the second fin, and leaving the lower part of the first fin and the second fin , The first epitaxial source/drain (S/D) part and the second epitaxial source/drain part are grown on the lower part of the first fin and the second fin, so that the first epitaxial source/drain part The component and the second epitaxial source/drain component are merged to form a merged source/drain component with a controllable merge height, a recessed trench is formed in the merged source/drain component, and the source/drain component is combined with the source/drain component. The drain contact fills the recessed trench, and the source/drain contact is electrically connected to merge the source/drain component.

In some other embodiments, the remaining height of the lower portion of the first fin and the second fin is about 30 to about 40% of the height of the first fin and the second fin.

In some other embodiments, the merging of the source/drain features includes: the first semiconductor material layer is grown on the lower portion of the first fin and the second fin; the second semiconductor material layer is grown on the first semiconductor material layer; and The third semiconductor material layer is grown on the second semiconductor material layer.

In some other embodiments, wherein the first semiconductor material layer on the first fin is not merged with the second semiconductor material layer on the second fin, and wherein the second semiconductor material layer on the first fin and the second semiconductor material layer on the second fin The second semiconductor material layer on the fin merges at a controllable merge height.

In some other embodiments, the controllable merging height depends on the ratio between the silane gas and the dichlorosilane gas used to form the second semiconductor material layer.

In some other embodiments, the controllable combined height is at a position equal to or greater than about 55% of the height of the first fin and the second fin.

In some other embodiments, wherein the third semiconductor material layer has a substantially compliant thickness above the first fin and the second fin.

In some other embodiments, the step of forming a recessed trench includes: etching and combining source/drain features to form an intermediate trench; depositing silicon nitride spacer features in and above the intermediate trench; Isotropic etching removes the bottom of the silicon nitride spacer part, while leaving the sidewall part of the silicon nitride spacer part; and further etches and merges the source/drain parts in the middle trench to form a recessed trench.

According to an example, the semiconductor device includes a substrate, and a first fin, a second fin, a third fin, and a fourth fin protrude from the substrate; n-type epitaxial source/drain (S/D) components are disposed on the first fin and the second fin. On the two fins, the first source/drain contact is disposed on the n-type epitaxial source/drain component, the p-type epitaxial source/drain component is disposed on the third fin and the fourth fin, and the second The source/drain contact is disposed on the p-type epitaxial source/drain component, wherein the bottom surface of the first source/drain contact is lower than the bottom surface of the second source/drain contact.

In some other embodiments, the n-type epitaxial source/drain features include silicon-doped phosphorous but not silicon germanium, and the p-type epitaxial source/drain features include silicon germanium.

The foregoing text summarizes the features of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand, and can easily design or modify other processes and structures based on the embodiments of the present invention, so as to achieve the same purpose and/or achieve the same purpose as the embodiments described herein. The same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Without departing from the spirit and scope of the invention, various changes, substitutions or modifications can be made to the embodiments of the invention.

10: method 12, 14, 16, 18, 20, 22: operation 100: Semiconductor device 102: Base 104: Isolation structure 106: Semiconductor Fin 106a: source/drain region 106b: Passage area 107: Dummy Gate Stack 108: oxide layer 110: dummy gate electrode 112, 114: Hard mask layer 113: Sidewall spacer 120: Merging epitaxial source/drain components 120A, 120B: epitaxy source/drain components 130: n-type combined epitaxy source/drain components 140: p-type combined epitaxial source/drain components 132, 142: Notch 134, 144: source/drain contacts 132a, 134a, 142a, 144a: depth 150: polymer layer 160: Fluorinated carbon layer L2-2: third layer F_H, FSW_H: height MH: combined height

The embodiments of the present invention can be better understood according to the following detailed description and the accompanying drawings. It should be noted that, according to the standard practice of this industry, the various components in the illustration are not necessarily drawn to scale. In fact, it is possible to arbitrarily enlarge or reduce the size of various components to make a clear description. FIG. 1 is a flowchart of a method of forming a semiconductor device according to various aspects of the present invention. Figure 2A shows a three-dimensional view of a portion of the semiconductor device in an intermediate stage of manufacturing according to some embodiments. FIGS. 2B, 3A, and 4 are schematic cross-sectional views of a part of the semiconductor device along the line "A-A" of FIG. 2A according to some embodiments in the intermediate stages of manufacturing according to the embodiment of the method of FIG. 1. FIGS. 2C and 3B are schematic cross-sectional views of a part of the semiconductor device along the line "B-B" of FIG. 2A according to some embodiments in an intermediate stage of manufacturing according to the embodiment of the method of FIG. 1. FIG. Figures 5 and 7 are intermediate stages of manufacturing according to the embodiment of the method of Figure 1, according to some embodiments along the line "AA" of Figure 2A part of the semiconductor device (with additional merged epitaxy source/ Drain component) is a schematic cross-sectional view. FIGS. 6A-6E show partial views of the semiconductor device of FIG. 5 through a notch forming process.

10: method

12, 14, 16, 18, 20, 22: operation

Claims (14)

A method of manufacturing a semiconductor device includes: providing a semiconductor structure having: a substrate; and a first fin, a second fin, a third fin, and a fourth fin located above the substrate; An n-type epitaxial source/drain part is formed on the first fin and the second fin; a p-type epitaxial source/drain part is formed on the third fin and the fourth fin; and the semiconductor The structure undergoes a selective etching process to remove the n-type epitaxial source/drain component and the upper part of the p-type epitaxial source/drain component, so that the n-type epitaxial source/drain component is moved The removed part is more than the removed part of the p-type epitaxial source/drain component. The method for manufacturing a semiconductor device according to claim 1, wherein the selective etching process includes a plurality of cycles, and each cycle includes: using a first etching gas to perform a first dry etching process on the semiconductor structure Use a second etching gas different from the first etching gas to perform a second dry etching process on the semiconductor structure; and perform a wet etching process to remove a polymer layer formed in the first dry etching process . According to the method for manufacturing a semiconductor device described in claim 2, wherein the first etching gas is a gas mixture containing fluoromethane, hydrogen and carbonyl sulfide, wherein the gas mixture and the first dry etching process The silicon-germanium in the p-type epitaxial source/drain component reacts to form the polymer layer containing silicon sulfide. The method for manufacturing a semiconductor device as described in claim 3, wherein the first dry etching process removes a first thickness of the n-type epitaxial source/drain component, and the first dry etching process removes A second thickness of the p-type epitaxial source/drain component. Since the polymer layer is on the p-type epitaxial source/drain component, the second thickness is smaller than the first thickness, and wherein the The first dry etching process also forms carbon fluoride as a by-product on the n-type epitaxial source/drain component and the p-type epitaxial source/drain component. According to the manufacturing method of the semiconductor device described in claim 4, the second etching gas includes diimine, and the diimine is configured to remove carbon fluoride formed in the first dry etching process. The method for manufacturing a semiconductor device as described in claim 3, wherein the wet etching process removes the p-type epitaxial source/drain components formed in the first dry etching process in each cycle Silicon sulfide. The method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein forming the n-type epitaxial source/drain component includes silicon doped phosphorus, but does not include silicon germanium, and is formed therein The p-type epitaxial source/drain components include silicon germanium. A method of manufacturing a semiconductor device includes: providing a semiconductor structure having a substrate and a first fin and a second fin on the substrate; removing the upper part of the first fin and the second fin, and retaining The lower part of the first fin and the second fin; growing a first epitaxial source/drain part and a second epitaxial source/drain part on the lower part of the first fin and the second fin, The first epitaxial source/drain component and the second epitaxial source/drain component are combined to form a combined source/drain component with a controllable combined height; in the combined source / Forming a recessed trench in the drain component; and filling the recessed trench with a source/drain contact, the source/drain contact is electrically connected to the combined source/drain component. The method of manufacturing a semiconductor device as described in item 8 of the scope of patent application, wherein the merger The source/drain component includes: a first semiconductor material layer grown on the lower portion of the first fin and the second fin; a second semiconductor material layer grown on the first semiconductor material layer; and a first semiconductor material layer Three layers of semiconductor material are grown on the second layer of semiconductor material. The method for manufacturing a semiconductor device as described in claim 9, wherein the first semiconductor material layer on the first fin is not merged with the second semiconductor material layer on the second fin, and wherein The second semiconductor material layer on the first fin merges with the second semiconductor material layer on the second fin at the controllable merging height. According to the method of manufacturing a semiconductor device described in claim 10, the controllable merging height depends on a ratio between the silane gas and the dichlorosilane gas used to form the second semiconductor material layer. According to the method for manufacturing a semiconductor device as described in claim 9, wherein the third semiconductor material layer has a substantially compliant thickness above the first fin and the second fin. The method of manufacturing a semiconductor device according to any one of the 8th to 12th patent applications, wherein the step of forming the recessed trench includes: etching the combined source/drain component to form an intermediate trench; A silicon nitride spacer part is deposited in and above the middle trench; an anisotropic etching is used to remove the bottom of the silicon nitride spacer part while leaving the sidewall part of the silicon nitride spacer part And further etching the combined source/drain component in the intermediate trench to form the recessed trench. A semiconductor device, including: a substrate; A first fin, a second fin, a third fin, and a fourth fin protruding from the substrate; an n-type epitaxial source/drain component disposed on the first fin and the second fin; A first source/drain contact is disposed on the n-type epitaxial source/drain part; a p-type epitaxial source/drain part is disposed on the third fin and the fourth fin ; A second source/drain contact is disposed on the p-type epitaxial source/drain component, wherein the bottom surface of the first source/drain contact is lower than the second source/drain The bottom surface of the pole contact.

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