TWI720426B - Electronic apparatus and method of extending peripheral device - Google Patents

Abstract

An electronic apparatus and a method of extending peripheral devices are provided. The electronic apparatus includes: a controller; a plurality of peripheral devices, electrically connected to the controller, wherein the plurality of peripheral devices comprise a plurality of video graphics array display cards, wherein during an initialization phase of the electronic apparatus, the controller allocates input and output resources to a first portion of the video graphics array display cards and does not allocate the input and output resources to a second portion of the video graphics array display cards, wherein the first portion of the video graphics array display cards allocated the input and output resources are used to display a image during the initialization phase.

Description

Electronic device and method for expanding peripheral equipment

The present invention relates to an electronic device and a method for expanding peripheral equipment, and more particularly to an electronic device and a method for expanding a video graphics array display card.

In recent years, there has been an upsurge in mining around the world. In the past, graphics cards that were widely provided to gamers were used as mining cards for mining. Mining must be calculated through the graphics card, so for mining, the more graphics cards represent the higher the mining efficiency. In other words, miners need a large number of graphics cards to speed up mining. On the other hand, Virtual Reality (VR) also requires a lot of hardware computing. If the hardware computing functions of multiple graphics cards can be connected in series, it can strengthen the real-time computing applications of virtual reality.

However, in current computer systems, in theory, up to 16 Video Graphics Array (VGA) display cards can be supported. In fact, there are other peripheral devices in the system that require input and output (Input/Output; I/O) resources, so usually only 13 VGA display cards can be supported. For this reason, how to configure more VGA display cards in the system has become one of the important topics in this field.

The invention provides an electronic device and a method for expanding peripheral equipment, which can expand more VGA display cards without being restricted by the configuration of I/O resources.

The electronic device of the present invention includes: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices include a plurality of video graphics array (VGA) display cards, wherein the controller is During the initialization phase of the electronic device, input and output (I/O) resources are allocated to the first part of the video graphics array display card, and the input and output are not allocated to the second part of the video graphics array display card Resources, wherein the first part of the video graphics array display card to which the input and output resources are allocated is used to display a screen in the initialization phase.

The method for expanding peripheral devices of the present invention includes: during the initialization phase of the electronic device, allocating input and output (I/O) resources to the first part of the multiple video graphics array (VGA) display cards in the multiple peripheral devices, And the input and output resources are not allocated to the second part of the video graphics array display card, and the first part of the video graphics array display card to which the input and output resources are allocated is used for displaying images in the initialization phase .

The electronic device of the present invention includes: a controller; a chipset; a plurality of peripheral devices, including at least one video graphics array display card, wherein the controller and the peripheral devices are electrically connected to each other through the chipset, and After the electronic device displays the screen, the chipset obtains a configuration cyclic read request for the at least one video graphics array display card from the controller, and transmits the configuration cyclic read request to the at least one video graphics The display card is arrayed, and the configuration cycle reading information corresponding to the configuration cycle reading request is obtained therefrom. The chipset analyzes the configuration cycle reading information and determines whether the configuration cycle reading information has input and output resources When the request for the input and output resources is provided in the configuration cycle reading information, the chipset replaces the request for the input and output resources in the configuration cycle reading information with blank data, And the configuration cycle read information after the replacement is provided to the controller.

The method for expanding peripheral equipment of the present invention includes: after the electronic device displays a screen, obtaining a configuration cyclic reading request for at least one video graphics array display card from a controller; and transmitting the configuration cyclic reading request to the at least one video graphics array display card; A video graphics array display card, from which the configuration cyclic reading information corresponding to the configuration cyclic reading request is obtained; analyzing the configuration cyclic reading information and determining whether the configuration cyclic reading information has input and output resources Request; when the configuration cyclic reading information has the request for the input and output resources, use blank data to replace the request for the input and output resources in the configuration cyclic reading information; and after the replacement The configuration of the cyclic reading information is provided to the controller.

Based on the above, in the electronic device and the method for expanding peripheral equipment provided by the embodiments of the present invention, the VGA display card includes a first VGA display card and a second VGA display card, by allocating I/O resources to the first VGA display card, and Without allocating I/O resources to the second VGA display card, the number of VGA display cards in the electronic device can be expanded without the limitation of I/O resources, so that the electronic device needs multiple VGA display cards (for example, mining digital coins). (Also known as mining) or virtual reality) provide higher hardware computing applications.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

In a computer system, when each video graphics array (VGA) display card announces that it needs input and output (I/O) resources, the Basic Input/Output System (BIOS) often allocates I/O resources to each A VGA display card. However, in the x86 system, the maximum I/O space is 64K bytes (byte), and according to the requirements of the peripheral interconnection standard: when the VGA display card announces that it needs I/O resources, if the VGA display card is located in PCI to PCI After the bridge, the BIOS must at least configure 4K bytes of I/O space for the devices behind the PCI to PCI bridge (including: VGA display card), so theoretically the system can support up to 16 VGA display cards. Each PCI to PCI bridge is connected to a VGA display card. In practical applications, there are other peripheral devices in the system that require I/O resources, so usually only 13 VGA display cards can be supported.

In order to expand the VGA display card under limited I/O resources, the present invention allocates I/O resources to at least one VGA display card, so that the electronic device can use this VGA display with I/O resources allocated during the initialization phase. The card is used to display the picture, and the VGA display card (or the second or more VGA display card) that is insufficiently allocated or requires I/O resources is only allocated memory-mapped input/output (MMIO) resources. In this way, after the electronic device uses the VGA display card allocated with I/O resources to display a picture, it can drive the remaining VGA display cards allocated with MMIO resources. With the above method, the number of VGA display cards in an electronic device can be expanded without limitation of I/O resources, so that the electronic device needs multiple VGA display cards (for example, mining digital coins (also known as mining) or Virtual reality) provides higher hardware computing applications.

FIG. 1 is a block diagram of an electronic device according to an embodiment of the invention. Please refer to FIG. 1, the electronic device 100 includes a controller 110 and a plurality of peripheral devices. The electronic device 100 is, for example, a device with an X86 architecture such as a desktop computer (Desktop), a notebook computer (Notebook), a tablet computer (Tablet PC), etc., which has an expansion capability to provide expanded peripheral device functions, and the present invention is not limited.

For ease of description, the electronic device 100 of this embodiment includes a peripheral device 121, a peripheral device 122, and a peripheral device 123, but the number of peripheral devices is not limited in the present invention. The peripheral device 121, the peripheral device 122, and the peripheral device 123 are electrically connected to the controller 110, and at least one of the peripheral device 121, the peripheral device 122, and the peripheral device 123 is a VGA display card. It is worth mentioning that the non-VGA display card peripheral devices are, for example, network cards, audio cards, modems, TV cards, hard disk controllers, USB and serial ports, etc., which are not limited by the present invention.

The controller 110 controls the display screen during the initialization phase of the electronic device 100. The controller 110 is, for example, a central processing unit (CPU) or a basic input output system (BIOS), which is not limited by the present invention.

In order to be able to expand peripheral equipment under limited input and output (I/O) resources, the controller 110 of the embodiment of the present invention allocates I/O resources to the first part of the multiple VGA display cards during the initialization phase of the electronic device 100 , And does not allocate I/O resources to the second part of the multiple VGA display cards, where the first part of the multiple VGA display cards can be regarded as the first VGA display card; the second part of the multiple VGA display cards The VGA display card can be regarded as the second VGA display card. In this way, the electronic device 100 can use the VGA display card to which I/O resources are allocated to control the display screen during the initialization phase, and then can display the screens of other VGA display cards that have not been allocated I/O resources. The hardware limits the expansion of the number of VGA display cards in the electronic device.

FIG. 2 shows a detailed flowchart of a method for expanding peripheral devices according to an embodiment of the present invention. The method for expanding peripheral devices in the embodiment in FIG. 2 is applicable to the electronic device 100 in the embodiment in FIG. 1. Hereinafter, the method for expanding the peripheral device of the embodiment of FIG. 2 will be described in detail with reference to various elements of the embodiment of FIG. 1.

First, the controller 110 determines the number of VGA display cards in a plurality of peripheral devices (step S220). Specifically, the controller 110 determines whether the peripheral device is a VGA display card according to the device information of the peripheral device configuration header (Configuration Header), such as device identification (Device Identification) and vendor identification (vendor identification), and obtains it accordingly. The number of VGA display cards in the electronic device 100. Subsequently, the controller 110 determines whether the number of VGA display cards is greater than or equal to two.

In one embodiment, if the number of VGA display cards is not greater than or equal to 2 (that is, 1), the controller 110 regards the VGA display card as a VGA display card that needs to allocate I/O information. That is, in the above description, more A VGA display card will include a first part and a second part, and the only one VGA display card belongs to the "first part of multiple VGA display cards, but the number is 1" in the above description (step S240).

In detail, in step S240, because the number of VGA display cards is 1, the controller 110 preferentially defines the VGA display card as the first VGA display card (step S242). That is, the first VGA display card belongs to the "first part of multiple VGA display cards" described above.

After the VGA display card is defined, the controller 110 determines whether each VGA display card is the first VGA display card (step S244). In detail, assuming that multiple VGA display cards are defined as two or more types of VGA display cards such as the first and second VGA display cards, the controller 110 will determine whether the VGA display card is the first VGA display card (that is, multiple VGA display cards). The first part of the VGA display card) to determine whether to allocate I/O resources to the VGA display card.

If the controller 110 determines that the VGA display card is the first VGA display card in step S244, the controller 110 allocates I/O resources to the VGA display card (step S246). Specifically, the controller 110 configures I/O resources in the Base Address Register (BAR) of the VGA display card, and sets the I/O space in the Command Register (Command Register) The bit (IO Space bit) is set to 1. Based on this, after the I/O space bit is enabled, the controller 110 can access the I/O address space of the VGA display card.

For example, referring to Figure 1, only the peripheral device 121 of the peripheral device 121, the peripheral device 122, and the peripheral device 123 is a VGA display card. The controller 110 determines that the number of VGA display cards in the peripheral device is 1, and defines the peripheral The device 121 is the first VGA display card and allocates I/O resources to the peripheral device 121.

It is worth mentioning that, in another embodiment, after the controller 110 determines that the number of VGA display cards is not greater than or equal to 2 (that is, 1), the controller 110 does not need to perform steps S242 and S244 but directly /O resources are allocated to the VGA display card. In detail, the method for the controller 110 to allocate I/O resources is as described in step S246, and will not be described again here.

In another embodiment, if the number of VGA display cards is greater than or equal to 2, the controller 110 sequentially accesses a plurality of basic address registers (BAR) in each peripheral device to obtain the memory resources required by the peripheral device It is required to determine the allocation of I/O resources to the first part of the multiple VGA display cards in the peripheral device, and to initialize the first part of the above-mentioned VGA display card (step S260). Specifically, the controller 110 determines that each of the peripheral devices requires I/O resources or MMIO resources according to the 0th bit of each BAR in each peripheral device. If the 0th bit of the BAR is 1, the The peripheral device requests I/O resources; if the 0th bit of the BAR is 0, the peripheral device requests MMIO resources. Then, obtain the space required by this peripheral device.

In detail, in step S260, if the controller 110 finds after obtaining the I/O resource requirements required by the peripheral device: I/O resources are needed, but the I/O space is insufficient, the controller 110 displays multiple VGAs The cards are respectively defined as a first VGA display card and at least one second VGA display card (step S262). That is, the multiple VGA display cards include a first VGA display card and at least one second VGA display card. In particular, the first VGA display card belongs to the "first part of multiple VGA display cards" described above, and at least one second VGA display card belongs to the "second part of multiple VGA display cards" described above. .

After defining the multiple VGA display cards, the controller 110 determines whether each VGA display card is the first VGA display card (step S244). In detail, the controller 110 sequentially determines whether each VGA display card is the first VGA display card (that is, the first part of multiple VGA display cards) to determine whether to allocate I/O resources to each VGA display card.

If the controller 110 determines that the VGA display card is the first VGA display card in step S244, it will allocate I/O resources to the VGA display card (step S246). If the controller 110 determines in step S244 that the VGA display card is not the first VGA display card, it does not allocate I/O resources to the VGA display card (step S266). Specifically, the controller 110 configures the I/O resource in the BAR of the first VGA display card, and sets the I/O space bit in the command register to 1. Based on this, after the I/O space bit is enabled, the controller 110 can access the I/O address space of the VGA display card.

It should be noted here that for the second VGA display card that does not allocate I/O resources, the way to configure resources is as follows: In one embodiment, the controller 110 configures MMIO resources in the BAR of the second VGA display card. , And set the I/O space bit in the command register to 0 and the Memory Space bit to 1. Based on this, the controller 110 can access the MMIO address space of the VGA display card after the memory space bit is enabled.

For example, referring to FIG. 1, the peripheral device 121, the peripheral device 122, and the peripheral device 123 among the peripheral device 121 and the peripheral device 122 are VGA display cards, and the controller 110 determines that the number of VGA display cards in the peripheral device is 2. And sequentially access the basic address register (BAR) in the peripheral device 121, the peripheral device 122, and the peripheral device 123 to obtain the memory resource requirements of the peripheral device 121, the peripheral device 122, and the peripheral device 123, and define the peripheral device The device 121 is a first VGA display card, and the peripheral device 122 is a second VGA display card. Next, the controller 110 allocates I/O resources to the peripheral device 121, initializes the peripheral device 121, and allocates MMIO resources to the peripheral device 122.

It is worth noting that, in one embodiment, the controller 110 may define only one VGA display card as the first VGA display card, and the remaining VGA display cards are all the second VGA display cards. In other embodiments, the controller 110 may define multiple VGA display cards as the first VGA display card, but the space that does not exceed the I/O resources is limited. For example, if there are a total of 17 VGA display cards, the controller 110 can define 13 VGA display cards (actually the number of VGA display cards for which the system can configure I/O resources) as the first VGA display card and 4 VGA display cards. The display card is the second VGA display card.

FIG. 3 is a block diagram of an electronic device according to another embodiment of the invention. 3, the controller 110, multiple peripheral devices (peripheral device 121, peripheral device 122, peripheral device 123) in FIG. 3 are the same as the controller 110, multiple peripheral devices (peripheral device 121, peripheral device 123) in FIG. 122. Peripheral devices 123), however, the number of peripheral devices is not limited by the present invention. The difference between the two is that the electronic device 300 in FIG. 3 further includes a chipset 330, and the chipset 330 includes a PCI-E bridge 340, and the PCI-E bridge 340 includes at least A PCI-E root port (Root Port) 341, the controller 110 communicates with the peripheral device 121, the peripheral device 122, and the peripheral device 123 through the corresponding PCI-E root port 341.

In this embodiment, it is assumed that the mining mode (Mining Mode) or the virtual reality mode (VR Mode) cannot be enabled, that is, for the second VGA display card (the second VGA display card in the VGA display card) that does not allocate I/O resources. Part 2) When it is unable to enable, the chipset 330 performs the following operations on the second VGA display card. For ease of description, in this embodiment, the peripheral device 121 is classified as a second VGA display card that does not allocate I/O resources.

FIG. 4 shows a detailed flowchart of a method for expanding a peripheral device according to another embodiment of the present invention. The method for expanding peripheral devices in the embodiment in FIG. 4 is applicable to the electronic device 300 in the embodiment in FIG. 3. Hereinafter, the method for expanding the peripheral device of the embodiment of FIG. 4 will be described in detail with reference to various elements of the embodiment of FIG. 3.

First, the chipset 330 obtains a configuration cycle (CFG) read request for the peripheral device 121 from the controller 110 (step S410).

Next, the chipset 330 transmits the configuration cycle read request to the peripheral device 121, and obtains the configuration cycle read information corresponding to the configuration cycle read request from the peripheral device 121 (step S420). Specifically, the chipset 330 transmits the configuration cycle read request to the peripheral device 121 through the PCI-E root port 341, and obtains the configuration cycle read data (CFG read data) corresponding to the configuration cycle read request from the peripheral device 121.

Then, the chipset 330 analyzes the configuration cycle reading information of the peripheral device 121 and determines whether there is a request for I/O resources in the configuration cycle reading information (step S430). In detail, the chipset 330 obtains the information in the configuration cycle read address offset 0x10 to 0x27 of the peripheral device 121 (that is, the information of the BAR). If the configuration cycle read address offset 0x10 to 0x27 has bit 0 and bit Element 1 is a BAR of 1 and 0, which means that the peripheral device 121 has a request for I/O resources. In contrast, if there is a BAR with bit 0 being 0 in the configuration cycle read address offset 0x10 to 0x27, it means that the peripheral device 121 has a request for MMIO resources.

If the chipset 330 determines in step S430 that there is no request for I/O resources in the configuration cycle read information, the resource requested by the peripheral device 121 is allocated to the peripheral device 121 (step S440). Specifically, if the peripheral device 121 requests MMIO resources, the chipset 330 allocates MMIO resources to the peripheral device 121.

If the chipset 330 determines in step S430 that there is a request for I/O resources in the configuration cyclic reading information, blank data is used to replace the I/O resource request in the configuration cyclic reading information (step S450). In detail, the chipset 330 uses 0x00000000 to replace the configuration cyclically reading the I/O resource request in the address offset 0x10 to 0x27.

Finally, the chipset 330 provides the replaced configuration cycle reading information to the controller 110 (step S460). Specifically, the controller 110 reads the replaced configuration and reads data cyclically, so that the chipset 330 hides the peripheral device 121 requests for I/O resources from the controller 110 without affecting the peripheral device 121's MMIO resource request. The request causes the controller 110 to allocate MMIO resources to the peripheral device 121. It is worth mentioning that the previous chipset does not hide the peripheral device's request for I/O resources from the controller, but in this embodiment, because the chipset can use blank data to replace the configuration and read the information in a loop. /O resource request, so you can hide the peripheral device's request for I/O resource.

In one embodiment, after the chip set 330 provides the replaced configuration cycle reading information to the controller 110, the chip set 330 also records the peripheral device 121 (step S470). In detail, the chipset 330 records the information of the peripheral device 121 in a look-up table. The information in the look-up table includes the bus number, device number and function number (Bus/Dev/Fun) of the peripheral device 121 and whether to display to the second VGA The card (VGA display card that does not allocate I/O resources) is enabled. In this embodiment, the chipset 330 records that the peripheral device 121 is "enabled". For example, the information of the peripheral device 121 is shown in Table 1. When the second VGA display card is in the enabled state, it means that the peripheral device 121 is defined as a VGA display card that does not allocate I/O resources, and can operate in a mining mode (Mining Mode) or a virtual reality mode. <Table 1>

Then, the chipset 330 can further modify the command register (Command Register) in the peripheral device 121 so as not to allocate the request for I/O resources in the IO BAR (step S480). In detail, the chipset 330 obtains the configuration cycle write request for the peripheral device 121 from the controller 110, if the bus information/device information/function information of the target device in the configuration cycle write request is recorded in the lookup table, and write The address of the input request is the command register. The chipset 330 records the I/O space bit of the command register in the target device as 0, and modifies the command register in the peripheral device 121.

It is worth mentioning that, in one embodiment, the operations performed by the chipset 330 (eg, step S450) may be performed by the PCI-E root port 341 in the PCI-E bridge 340 of the chipset 330. Therefore, it can be seen from the above-mentioned embodiment and corresponding Figures 3 and 4 that although the chipset 330 determines that there is a request for I/O resources in the configuration cyclic reading information, the PCI-E bridge 340 replaces the configuration cyclic reading with blank data. The I/O resource request in the information is taken, and the chipset 330 does not allocate the I/O resource to the corresponding peripheral device 121. In this way, the use of I/O resources can be reduced to solve the limitation of I/O usage space.

FIG. 5 is a block diagram of an electronic device according to another embodiment of the invention. Please refer to FIG. 5. In FIG. 5, the controller 110, multiple peripheral devices (peripheral device 121, peripheral device 122, peripheral device 123), and chipset 330 are the same as the controller 110 in FIG. 3, and multiple peripheral devices (peripheral devices) 121, peripheral equipment 122, peripheral equipment 123), and chipset 330. However, the number of peripheral equipment is not limited by the present invention. The difference between the two is that the electronic device 500 of FIG. 5 further includes at least one PCI-E switch (Switch) 550. In particular, the PCI-E switch can be regarded as a peripheral device.

For ease of description, the electronic device 500 of this embodiment includes a PCI-E switch 550, but the number of PCI-E switches is not limited in the present invention. The PCI-E switch 550 is electrically coupled to the PCI-E root port 341, the peripheral device 121, the peripheral device 122, and the peripheral device 123 are directly electrically connected to the PCI-E switch 550, and the controller 110 is in the chipset 330 The PCI-E root port 341 of the PCI-E bridge 340 and the PCI-E switch 550 communicate with the peripheral device 121, the peripheral device 122, and the peripheral device 123.

In this embodiment, it is assumed that the mining mode (Mining Mode) or the virtual reality mode (VR Mode) cannot be enabled, that is, for the second VGA display card (the second VGA display card in the VGA display card) that does not allocate I/O resources. Part 2) When it is unable to enable, the chipset 330 performs the following operations on the second VGA display card. For ease of description, in this embodiment, the peripheral device 121 is classified as a second VGA display card that does not allocate I/O resources, and the peripheral device 122 and the peripheral device 123 are not VGA display cards.

FIG. 6 shows a detailed flowchart of a part of a method for expanding a peripheral device according to another embodiment of the present invention. The method for expanding peripheral devices in the embodiment in FIG. 6 is applicable to the electronic device 500 in the embodiment in FIG. 5. Hereinafter, the method for expanding the peripheral device of the embodiment of FIG. 6 will be described in detail with reference to various elements of the embodiment of FIG. 5. It should be particularly noted here that after the chip set 330 of the electronic device 500 executes the step flow of FIG. 6, it continues to execute the similar step flow of FIG. 4 (eg, steps S410 to S480).

First, the chipset 330 obtains a configuration cycle (CFG) read request for peripheral devices from the controller 110 (step S610).

Next, the chipset 330 transmits the configuration cycle read request to the peripheral device, and obtains the configuration cycle read information corresponding to the configuration cycle read request from the peripheral device (step S620). Specifically, the chipset 330 transmits the configuration cycle read request to the PCI-E switch 550 through the PCI-E root port 341. After that, the PCI-E switch 550 transmits the configuration cycle read request to the peripheral device 121, peripheral device 122, and peripheral device 123, and obtains the configuration corresponding to the configuration cycle read request from the peripheral device 121, peripheral device 122, and peripheral device 123 CFG read data (CFG read data). After the PCI-E switch 550 obtains the configuration cycle read data corresponding to the configuration cycle read request, the chipset 330 obtains the configuration cycle read data corresponding to the configuration cycle read request from the PCI-E switch 550.

Then, the chipset 330 analyzes the configuration cyclic reading information of the peripheral devices and determines whether the device information (for example: Device Identification, vendor Identification) in the configuration cyclic reading information is a VGA display card (step S630). In detail, the chipset 330 obtains the configuration of the peripheral device 121, the peripheral device 122, the peripheral device 123, and the PCI-E switch 550 to read the information of the address offset 0x0E (that is, the information of the configuration header), if the configuration is read in a cycle The information of the address offset 0x0E is 0x00, which means that the peripheral device is a VGA display card. In contrast, if the information configured to read the address offset 0x0E cyclically is not 0x00, it means that the peripheral device is not a VGA display card. For example, if the configuration cyclic read address offset 0x0E information is 0x01, because the offset 0x0E information is not 0x00, it means that the peripheral device is a PCI-E switch.

If the chipset 330 determines that the peripheral device is a VGA display card in step S630, the peripheral device is recorded (step S640). If the chipset 330 determines that the peripheral device is not a VGA display card in step S630, the peripheral device is not recorded (step S650). Specifically, the chipset 330 determines that the peripheral device 121 is a VGA display card, and the chipset 330 records the information of the peripheral device 121 in a look-up table. The information in the look-up table includes the bus number, device number, and function number of the peripheral device 121 (Bus /Dev/Fun) and record the effective bits of the peripheral device 121 as "enabled" (representing that the peripheral device 121 is a VGA display card). For example, the information of the first item is shown in Table 2. In contrast, the chipset 330 determines that the peripheral device 122, the peripheral device 123, and the PCI-E switch 550 are not VGA display cards, and does not record the peripheral device 122, the peripheral device 123, and the PCI-E switch 550 in the look-up table. <Table 2>

After completing this look-up table, because there are enabled VGA display cards in the look-up table (for example, the peripheral device 121 is a VGA display card), the chipset 330 can perform the same as that shown in Figure 4 for the VGA display card recorded in the look-up table. Similar steps flow. That is, the chipset 330 of FIG. 3 replaces the request for I/O resources in the configuration cycle reading information with blank data, so that the controller 110 does not allocate IO resources to the peripheral devices 121 that originally requested I/O resources, thereby reducing The use of I/O resources can even enter mining mode (Mining Mode) or virtual reality mode (VR Mode). It is worth mentioning that the previous chipset does not hide the peripheral device's request for I/O resources from the controller, but in this embodiment, because the chipset can use blank data to replace the configuration and read the information in a loop. /O resource request, so you can hide the peripheral device's request for I/O resource.

It should be noted that, different from the aforementioned step S420, in step S420 of this embodiment, the chipset 330 transmits the configuration cycle read request to the peripheral device through the PCI-E root port 341 and the PCI-E switch 550. 121, and obtain the configuration cycle read data (CFG read data) corresponding to the configuration cycle read request from the peripheral device 121.

In another embodiment, the electronic device 500 further includes a plurality of PCI-E switches, and the PCI-E switches are connected in series with each other. Therefore, after first understanding the surrounding environment of the electronic device through the step flow of FIG. 6 and recording one or more peripheral devices that are the VGA display card in the look-up table, the chipset 330 can execute the step flow of FIG. The VGA display card allocates I/O or MMIO resources.

In other embodiments, the method for expanding peripheral devices in the embodiment in FIG. 4 is applicable to the electronic device 500 in the embodiment in FIG. 5. In this embodiment, the electronic device 500 uses the PCI-E switch 550 to execute the method for expanding peripheral devices in FIG. 4.

In summary, in the electronic device and the method for expanding peripheral equipment provided by the embodiments of the present invention, the VGA display card includes a first VGA display card and a second VGA display card. Through software operation, the controller can control the first VGA display card. I/O resources are allocated, and I/O resources are not allocated to the second VGA display card. In this way, the electronic device can use the first VGA display card to which I/O resources are allocated to display images during the initialization phase, and then can display the images of the remaining second VGA display cards that are not allocated I/O resources. In this way, the number of VGA display cards in an electronic device can be expanded without being restricted by I/O resources, so that the electronic device needs multiple VGA display cards (for example, mining digital coins (also known as mining) or virtual reality). Environment) to provide higher hardware computing applications.

On the other hand, you can also use hardware operations (such as the chipset 330 in Figure 3 and Figure 5) to determine whether there is a request for I/O resources in the configuration cycle read information, and whether to replace the configuration cycle read with blank data The request for I/O resources in the information can hide the requests of peripheral devices for I/O resources and provide higher computing applications.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

100, 300, 500‧‧‧Electronic device 110‧‧‧Controller 121, 122, 123‧‧‧peripheral devices 330‧‧‧chipset 340‧‧‧Quick Peripheral Interconnection Standard Bridge 341‧‧‧Standard Root Port for Fast Peripheral Interconnection 550‧‧‧Quick Peripheral Interconnection Standard Switch S220, S240, S242, S244, S246, S260, S262, S266, S410, S420, S430, S440, S450, S460, S470, S480, S610, S620, S630, S640, S650‧‧‧Steps

FIG. 1 is a block diagram of an electronic device according to an embodiment of the invention. FIG. 2 shows a detailed flowchart of a method for expanding peripheral devices according to an embodiment of the present invention. FIG. 3 is a block diagram of an electronic device according to another embodiment of the invention. FIG. 4 shows a detailed flowchart of a method for expanding a peripheral device according to another embodiment of the present invention. FIG. 5 is a block diagram of an electronic device according to another embodiment of the invention. FIG. 6 shows a detailed flowchart of a part of a method for expanding a peripheral device according to another embodiment of the present invention.

100‧‧‧Electronic device

110‧‧‧Controller

121, 122, 123‧‧‧peripheral devices

Claims (22)

An electronic device, comprising: a controller; and a plurality of peripheral devices electrically connected to the controller, wherein the plurality of peripheral devices includes at least one video graphics array display card, wherein the controller is in the electronic device In the initialization phase, input and output resources are allocated to the first part of the video graphics array display card, and the input and output resources are not allocated to the second part of the video graphics array display card. The second part of the memory mapping input and output resources is allocated, and the first part of the video graphics array display card to which the input and output resources are allocated is used to display a screen in the initialization phase. The electronic device according to the first item of the scope of patent application, wherein in the initialization phase, the controller also determines the number of the video graphics array display cards in the plurality of peripheral devices, and when the video graphics When the number of the array display card is not greater than or equal to 2, the controller includes the video graphics array display card only including the first part of the video graphics array display card, and allocates the input and output resources. The electronic device according to the first item of the scope of patent application, wherein in the initialization phase, the controller also determines the number of the video graphics array display cards in the plurality of peripheral devices, and when the video graphics When the number of display cards in the array is greater than or equal to 2, the control The controller sequentially accesses the basic address register in each peripheral device to obtain the input and output resource requirements required by the multiple peripheral devices, so as to determine the video graphics array display card in the multiple peripheral devices The first part allocates the input and output resources, and initializes the first part of the video graphics array display card. The electronic device according to the first item of the patent application, wherein the video graphics array display card includes a first video graphics array display card and at least one second video graphics array display card, and the first video graphics array display card belongs to The first part of the video graphics array display card, and the at least one second video graphics array display card belongs to the second part of the video graphics array display card. The electronic device described in the first item of the scope of patent application, wherein the controller is a central processing unit or a basic input output system. The electronic device described in claim 1 further includes: a chipset, wherein the controller and the peripheral device are electrically connected to each other through the chipset, wherein, when the controller does not support the video When the second part of the graphics array display card allocates the input and output resources, the chipset performs the following operations: obtains the configuration of the second part of the video graphics array display card from the controller Cyclic reading request; passing the configuration cyclic reading request to the second part in the video graphics array display card, and obtaining configuration cyclic reading information corresponding to the configuration cyclic reading request from it; analyzing The configuration cyclically reads the information and determines that the configuration cyclically reads the information Whether the request for the input and output resources is available; when the request for the input and output resources is available in the configuration cyclic reading information, blank data is used to replace all of the input and output resources in the configuration cyclic reading information The request; and the configuration cycle read information after the replacement is provided to the controller. The electronic device described in item 6 of the scope of patent application, wherein the chipset also records the second part of the video graphics array display card, and modifies the second part of the video graphics array display card. Part of the basic address register, so as not to allocate the request for the input and output resources. The electronic device described in item 6 of the scope of patent application, wherein the chipset includes a quick peripheral interconnect standard bridge, wherein the controller and the peripheral device are mutually electrically connected through the quick peripheral interconnect standard bridge connection. The electronic device according to item 8 of the scope of patent application, wherein the quick peripheral interconnect standard bridge includes: at least one quick peripheral interconnect standard root port, wherein the plurality of peripheral devices are directly electrically connected to the at least one A quick peripheral interconnect standard root port, the controller communicates with the multiple peripheral devices through the quick peripheral interconnect standard root port of the quick peripheral interconnect standard bridge in the chipset. The electronic device described in item 8 of the scope of patent application, wherein the quick peripheral interconnect standard bridge includes a quick peripheral interconnect standard root port, and the electronic device further includes at least one quick peripheral interconnect standard switch, wherein The at least one quick peripheral interconnect standard switch is electrically coupled to the quick peripheral interconnect standard root port, The plurality of peripheral devices are directly electrically connected to the at least one quick peripheral interconnection standard switch, and the controller passes through the quick peripheral of the quick peripheral interconnection standard bridge in the chipset. The interconnection standard root port and the at least one quick peripheral interconnection standard switch are set to communicate with the plurality of peripheral devices. A method for expanding peripheral equipment includes: in the initialization phase of an electronic device, allocating input and output resources to the first part of at least one video graphics array display card in a plurality of peripheral equipment, and not assigning input and output resources to the video graphics array display card. The second part allocates the input and output resources, and allocates memory mapping input and output resources to the second part of the video graphics array display card, wherein the video graphics array display card to which the input and output resources are allocated The first part is used to display a screen during the initialization phase. The method according to item 11 of the scope of patent application, wherein in the initialization phase, the number of the video graphics array display cards in the plurality of peripheral devices is also determined, and when the number of the video graphics array display cards is When it is not greater than or equal to 2, the video graphics array display card only includes the first part of the video graphics array display card, and the input and output resources are allocated. The method according to item 11 of the scope of patent application, wherein in the initialization phase, the number of the video graphics array display cards in the plurality of peripheral devices is also determined, and when the number of the video graphics array display cards is When it is greater than or equal to 2, visit in order Ask the basic address register in each peripheral device to obtain the input and output resource requirements required by the plurality of peripheral devices, so as to determine the second order of the video graphics array display card in the plurality of peripheral devices. One part allocates the input and output resources, and initializes the first part of the video graphics array display card. The method according to item 11 of the scope of patent application, wherein the video graphics array display card includes a first video graphics array display card and at least one second video graphics array display card, and the first video graphics array display card belongs to all The first part of the video graphics array display card, and the at least one second video graphics array display card belongs to the second part of the video graphics array display card. As described in item 11 of the scope of patent application, the method further includes: when the input and output resources are not allocated to the second part of the video graphics array display card, obtaining a display of the video graphics array from the controller The configuration cycle read request of the second part in the card; the configuration cycle read request is passed to the second part in the video graphics array display card, and the configuration cycle read request is obtained therefrom Request the corresponding configuration cycle read information; analyze the configuration cycle read information and determine whether the configuration cycle read information has the input and output resource request; when the configuration cycle read information has the input When outputting the request for the resource, replace the request for the input and output resource in the configuration loop reading information with blank data; and The cyclic reading information of the configuration after the replacement is provided to the controller. The method described in item 15 of the scope of patent application further includes recording the second part in the video graphics array display card, and modifying the basic position in the second part in the video graphics array display card. Address register to not allocate the request for the input and output resources. An electronic device comprising: a controller; a chipset; a plurality of peripheral devices, including at least one video graphics array display card, wherein the controller and the peripheral devices are electrically connected to each other through the chipset, and the electronic device After the device displays the screen, the chipset obtains a configuration cyclic read request for the at least one video graphics array display card from the controller, and transmits the configuration cyclic read request to the at least one video graphics array display Card, and obtain the configuration cycle reading information corresponding to the configuration cycle reading request from it, the chipset analyzes the configuration cycle reading information and judges whether there is a request for input and output resources in the configuration cycle reading information , When the request for the input and output resources in the configuration cycle read information is provided, the chipset replaces the request for the input and output resources in the configuration cycle read information with blank data, and replaces the request for the input and output resources in the configuration cycle read information. The replaced configuration cyclically reads information and provides it to the controller. The electronic device described in item 17 of the scope of patent application, wherein the chipset includes a shortcut peripheral interconnection standard bridge, wherein the controller and the peripheral device are mutually electrically connected through the shortcut peripheral interconnection standard bridge connection. The electronic device according to item 18 of the scope of patent application, wherein the quick peripheral interconnection standard bridge includes: at least one quick peripheral interconnection standard root port, wherein the plurality of peripheral devices are directly electrically connected to the at least one A quick peripheral interconnect standard root port, the controller communicates with the multiple peripheral devices through the quick peripheral interconnect standard root port of the quick peripheral interconnect standard bridge in the chipset. The electronic device described in item 18 of the scope of patent application, wherein the quick peripheral interconnect standard bridge includes a quick peripheral interconnect standard root port, and the electronic device further includes at least one quick peripheral interconnect standard switch, wherein The at least one quick peripheral interconnect standard switch is electrically coupled to the quick peripheral interconnect standard root port, wherein the plurality of peripheral devices are directly electrically connected to the at least one quick peripheral interconnect standard switch, and The controller interacts with the plurality of peripheral devices through the quick peripheral interconnect standard root port of the quick peripheral interconnect standard bridge in the chipset and the at least one quick peripheral interconnect standard switch. communication. A method for expanding peripheral equipment includes: after an electronic device displays a screen, obtaining a configuration cyclic reading request for at least one video graphics array display card from a controller; and transmitting the configuration cyclic reading request to the at least one video Graphics array display card, and obtaining configuration cycle reading information corresponding to the configuration cycle reading request from it; analyzing the configuration cycle reading information and determining whether the configuration cycle reading information has a request for input and output resources; When the request for the input and output resources in the configuration cycle read information is available, replace the request for the input and output resources in the configuration cycle read information with blank data; The configuration loop read information is provided to the controller. The method described in item 21 of the scope of the patent application further includes recording the at least one video graphics array display card, and modifying the basic address register in the at least one video graphics array display card so as not to allocate the The said request for input and output resources.

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