TWI720367B - Processor module with integrated packaged power converter - Google Patents

Abstract

A power management module comprises one or more power converter chips that are mounted on a power management package substrate. First and second electrical contacts are disposed on opposing first and second sides of the power management package substrate. The power management module can be mounted on a processor module to supply power to one or more processor chips in the processor module. In one example, the processor chip(s) are mounted on a first side of a processor package substrate and the power management module is mounted on an opposing second side of the processor package substrate. The power management module and the processor module can be centered and aligned with respect to each other or they can be offset laterally from each other. In another embodiment, the power management module and the processor chip(s) are mounted on the same side of the processor package substrate.

Description

Processor module with integrated packaged power converter

The invention relates to a power converter for integrated circuits.

A switched inductor DC-DC power converter, such as a buck converter, provides power conversion from a high voltage potential to a low voltage potential. These types of converters are used in a wide and diverse set of applications. A typical application is the conversion and regulation of power supplies for microprocessors and other sensitive or high-performance integrated circuits.

In current microelectronic systems, the components of the power converter (for example, power control integrated circuits, power switches, inductor(s), and capacitors) are installed at a large lateral vertical distance from the processor The circuit board consumes the power output from the power converter. This large distance results in a large amount of power loss due ^{to the thermal conduction loss (P=I 2} R loss) in the interconnection portion that transfers current from the power converter on the circuit board to the processor chip. The additional power loss is caused by the large AC impedance that usually exists in the interconnection from the circuit board to the processor chip or mold, because the dynamic changes in the processor current consumption will cause significant supply voltage deviations. These supply voltage deviations Forcing an inefficient supply voltage margin ensures that the supply does not fall below the minimum required voltage potential for proper operation of the processor chip. For example, if the minimum supply voltage for the correct operation of the processor is 0.7V, but the "worst case" load current transient may cause a transient error on the 100mV supply voltage across the entire impedance of the power transmission interconnection. , It is necessary to supply >0.8V to the processor chip to ensure that the supply voltage will not drop below 0.7V under the "worst case" load current transient. This supply voltage margin causes more than 15% of additional power consumption for the processor chip. An embodiment of such a known system is illustrated in FIG. 1.

Some attempts have been made to integrate power converters on the processor package substrate. In doing so, the resistance and AC impedance of the electrical interconnection between the power supply regulator and the processor chip are reduced, making it possible to reduce heat conduction loss and power supply. Should the voltage margin loss. However, such attempts cannot achieve high-efficiency power converters that are small enough to be implemented in the processor package, and often cause additional performance or functional damage to the system, such as removal of electrical terminals from the processor package substrate , Which reduces the data bandwidth in and out of the processor.

It would be desirable to overcome one or more of these and other deficiencies in the art.

The example embodiments described herein have innovative features, none of which are indispensable or used alone for their desired attributes. The following description and drawings set forth in detail certain illustrative implementations of the present disclosure, which indicate several exemplary ways in which various principles of the present disclosure can be implemented. However, the illustrative embodiments are not exhaustive of the many possible embodiments of the present disclosure. Without limiting the scope of the claims, some of the advantageous features will now be summarized. The following detailed description of the present disclosure is considered in conjunction with the accompanying drawings, and other purposes, advantages and novel features of the present disclosure will be set forth in the following detailed description. The accompanying drawings are intended to illustrate rather than limit the present invention.

One aspect of the present invention is directed to a component, the component includes: a processor module, the processor module includes: a first side and a second side opposite to the The processor package substrate; the processor chip mounted on the first side of the processor package substrate; and the array of electrical termination portions provided on the second side of the processor package substrate; and the processor package substrate The power management module on the second side of the power management module, the power management module includes: a power management package substrate; and a power converter chip mounted on the power management package substrate, the power converter chip is set in the power management Between the package substrate and the first side or the second side of the processor package substrate.

In one or more embodiments, the power converter die is disposed between the power management package substrate and the second side of the processor package substrate. In one or more embodiments, the processor package substrate and the power management package substrate each include an organic polymer and a conductive interconnect portion that extends across the first side and the second side of the corresponding substrate. In one or more embodiments, the power converter die is in electrical communication with the processor die through conductive interconnects in the processor package substrate.

In one or more embodiments, the height of the power converter module is less than or equal to the height of the electrical termination portion on the second side of the processor package substrate, and the height is relative to the first side of the processor package substrate. Measured on the axis perpendicular to the plane defined on both sides. In one or more embodiments, the height of the power converter is less than or equal to 1 mm, and the array of electrical termination portions includes a ball grid array.

In one or more embodiments, the assembly further includes electrical termination portions disposed on opposite first and second sides of the power management module. In one or more embodiments, the power management module includes a first conductive stud and a second conductive stud extending from the first side of the power management module, and the power converter chip is disposed on the first conductive stud. Electrically communicate with the second conductive stud and with the first conductive stud and the second conductive stud, the first conductive stud conducts the supply current to the first electrical interconnection on the second side of the processor package substrate In part, the second conductive stud conducts ground current from the second electrical interconnection portion on the second side of the processor package substrate. In one or more embodiments, greater than 50% of the electrical termination portion on the first side of the power management module is electrically coupled to the supply power and ground, and greater than 50% on the second side of the power management module % Of the electrical termination is electrically coupled to the input power supply and ground. In one or more embodiments, the electrical termination portion on the second side of the power management module includes a ball grid array.

In one or more embodiments, the combined height of the ball grid array and the power management module is less than or equal to the height of the electrical termination part array in the processor module, and the combined height and the height are relative to and Measured on an axis orthogonal to the plane defined by the second side of the processor package substrate. In one or more embodiments, the array of electrical termination portions in the processor module includes a ball grid array. In one or more In an embodiment, the electrical termination portion provided on the second side of the power management module includes a ball grid array, a pad grid array, or a pin grid array. In one or more embodiments, the electrical termination part provided on the second side of the power management module is designed to closely fit with the electrical socket.

In one or more embodiments, the processor wafer includes silicon. In one or more embodiments, the power converter die includes silicon nitride or gallium nitride. In one or more embodiments, the power converter chip includes: a multilayer wiring network; and an inductor integrated on top of the multilayer wiring network. In one or more embodiments, the inductor includes a conductive winding including: a first lead formed in a first integration plane disposed on the multilayer wiring network; A second lead in a second integration plane above an integration plane; and a conductive VIA formed between the first lead and the second lead, the conductive VIA electrically connecting the first lead to the second lead.

In one or more embodiments, the assembly further includes a plurality of the power converter chips, and each power converter chip is mounted on a power management package substrate. In one or more embodiments, the first power converter chip outputs a first supply current at a first supply voltage, and the second power converter chip outputs a second supply current at a second supply voltage. In one or more embodiments, the first A supply voltage is different from the second supply voltage. In one or more embodiments, the power management module includes one or more capacitors, one or more inductors, one or more transformers, or a combination of any of the foregoing.

In one or more embodiments, the processor module and the power management module are aligned and centered relative to each other to reduce the distance that current travels between the processor module and the power management module. In one or more embodiments, the power management module is composed of wafer-level packages.

Another aspect of the present invention is directed to a power management module. The power management module includes: a power management package substrate having opposite first and second sides; mounted on the first side of the power management package substrate The power converter chip is arranged between the first side or the second side of the processor package substrate and the power management package substrate; the power converter chip extends from the first side of the power management substrate Conductive studs, where each power converter chip is disposed between adjacent first and second conductive studs; and an electrical termination portion disposed on the second side of the power management package substrate Array.

In one or more embodiments, each power converter die includes: a multilayer wiring network; and an inductor integrated on top of the multilayer wiring network. In one or more embodiments, the inductor includes a conductive winding, the conductive The electrical winding includes: a first lead formed in a first integration plane provided above the multilayer wiring network; a second lead formed in a second integration plane provided above the first integration plane; and formed A conductive VIA between the first lead and the second lead, the conductive VIA electrically connecting the first lead to the second lead. In one or more embodiments, the inductor includes a planar magnetic core, and the conductive winding turns around the planar magnetic core in a generally helical manner. In one or more embodiments, the inductor includes a magnetically clad inductor. In one or more embodiments, the power management package substrate and each power converter die include wafer-level packages.

20A, 20B, 20C, 40, 50: components

200: processor

201, 220: Center point

210, 410: processor package substrate

212: first side

214: second side

215: processor package electrical terminals

216: conductive layer

218: Conductive column

22, 42: processor module

220: Power management package substrate

230, 430, 530: power converter chip

24, 44, 54: power management module

240: Power management package substrate

245: Power management package electrical terminals

250: Clearance

260: Conductive stud

270, 280: Section height

400: processor chip

402: Optional memory chip

404: Optional decoupling capacitor

406: Optional accelerometer chip

531: Transformer

532: Inductor

60: small chip

600: power converter

610: Power converter substrate

620: feedback control circuit

630: interface circuit

640: regulation circuit

650: Power System

651A, 651B: Phase

660A: Power switch

662, 662A: PMOS transistor gate

664, 664A: NMOS transistor gate

670, 670A: thin film inductors

70, 80: cross section

700: Multilayer wiring network

720: Wiring plane

722: Integrated plane

730: IC chip contact structure

750, 750’: Lead section

740, 740’: Conductive VIA

760: Dielectric insulating material

775: main plane

770: Magnetic Core Inductor

780: conductive winding

785: Planar core

870: Magnetically Clad Inductor

875: Ferromagnetic Yoke

880: conductive winding

V _DD : supply voltage

V _IN : Input voltage

Vo: output voltage

Figure 1 is a schematic diagram of a prior art component.

Figures 2A, 2B, and 2C are cross-sectional views of components of one or more corresponding embodiments of the present invention.

FIG. 3 includes a representation of the electrical relationship between certain components in the cross-section shown in FIG. 2A.

Figure 4 is a block diagram of the components of one or more embodiments of the present invention.

Figure 5 is a block diagram of the components of one or more embodiments of the present invention.

Fig. 6 is a schematic diagram of a switch inductor type DC-DC power converter chiplet according to one or more embodiments of the present invention.

FIG. 7 is a representative cross-sectional view of the switch inductor type DC-DC power converter chiplet according to the first embodiment shown in FIG. 6.

FIG. 8 is a representative cross-sectional view of the switch-inductance type DC-DC power converter chiplet according to the second embodiment shown in FIG. 6.

In order to allow your reviewer to better understand the technical content of the present invention, preferred specific embodiments are described as follows.

A power management module includes one or more power converter chips mounted on a power management package substrate. The power management module includes electrical contacts on opposite first and second sides. The first electrical contact (for example, a conductive stud) extends to the first side of the power management module. Each power converter chip is placed between adjacent electrical contacts. The second electrical contacts (for example, ball grid array, land grid array, or pin grid array) are arranged on the second side of the power converter module (for example, , On the side of the power management package substrate opposite to the power converter chip(s).

The power management module can be installed on the processor module to supply power to one or more processor chips in the processor module. In one embodiment, the processor chip(s) are mounted on the first part of the processor package substrate. On one side, and the power management module is mounted on the opposite second side of the processor package substrate. The first electrical contact in the power management module can electrically connect the power converter chip(s) to the conductive interconnect portion in the processor package substrate, the conductive interconnect portion being electrically coupled to the processor Wafer (one or more). The power management module and the processor module can be centered and aligned with respect to each other, or they can be laterally offset from each other. In another embodiment, the processor management module and the processor chip(s) are mounted on the same side of the processor package substrate.

Figure 2A is a cross-section of assembly 20A according to one or more embodiments. The component 20A includes a system-on-a-chip (SoC) or processor (generally, a processor) 200, a processor package substrate 210, a power management package substrate 220, and one or more power converter chips 230 . The processor 200 is mounted on the first side 212 of the processor package substrate 210, for example, by wire bonding, flip-chip attachment, or other methods as known in the art. The processor 200 and the processor package substrate 210 form the processor module 22. The processor 200 may include a processor chip (e.g., central processing unit or graphics processing unit), one or more memory chips (e.g., dynamic random access memory or DRAM, high-bandwidth memory, etc.), input/output ports, and the like. The substrate or mold for the processor 200 wafer may include silicon (such as silicon-on-insulator (silicon-on-insulator, SOI), doped silicon (for example, for complementary metal-oxide-semiconductor (complementary metal-oxide-semiconductor, CMOS)), or other forms of silicon, or insulators (such as crystalline two Silica).

The power management package substrate 220 is mounted on the second side 214 of the processor package substrate 210. As shown in the figure, the processor module 22 and the power management module 24 are centered and aligned with respect to each other. For example, the power management package substrate 220 and the processor 200 are centered and aligned with respect to each other such that the center points 220, 201 of the power management package substrate 220 and the processor 200 are aligned, respectively. The alignment of the power management module 24 and the processor 200 chip is useful for shortening the total distance between the processor 200 chip and the power management module 24, and therefore reduces the interconnection of power transmission from the power management module 24 to the processor 200. Part of the broadband electrical impedance is desired. In common commercial implementations of organic packaging substrates for processor wafers, the packaging substrates are generally less than 1 mm thick, while the width can be greater than 50 mm. Therefore, when the power management module 24 is mounted on the second side 214 of the processor package substrate 210 instead of being mounted on the first side 212 of the processor package substrate 210, the effective connection between the processor chip and the power module The resistance and electrical impedance can be lower. However, in other embodiments, the power management package substrate 220 and the processor 200 may be horizontally offset from each other, for example along an axis located in a plane defined by the first side 212 or the second side 214 of the processor package substrate 210.

The power management package substrate 220 includes one or more power converter chips 230 that are mounted on the first side of the power management package substrate 240 to form the power management module 24. In addition, the power management package substrate 220 may include one or more discrete passive electrical components as described herein.

The processor package electrical terminal array 215 is disposed on the second side of the processor package substrate 210. The processor package electrical terminal 215 provides a data signal input/output connection with the processor 200 via a processor package interconnection portion, which includes a conductive layer 216 and a conductive pillar 218 forming the processor package substrate 210. The conductive layer 216 and the conductive pillar 218 may include copper, gold, aluminum, and/or another conductive material. The processor package electrical terminal 215 may include a ball grid array (BGA) (for example, as shown in FIG. 2A), a land grid array (LGA), and/or a pin grid array (pin grid array, PGA), or other custom socket connections.

The power management module 24 is arranged in the gap 250 of the array of the processor package electrical terminals 215. The power management package electrical terminal array 245 is disposed on the second side of the power management package substrate 240. At least some of the power management package electrical terminals 245 provide a power input connection with the power converter chip 230 (for example, to conduct current), And optionally, at least some of the power management package electrical terminals 245 may provide data signal input/output connections with the processor 200. In some embodiments, most (eg, greater than 50%) of the power management package electrical terminals 245 provide a power input connection to the power converter chip 230 and a ground connection.

The power management package electrical terminals 245 and the processor package electrical terminals 215 may include the same type of electrical terminals. For example, the power management package electrical terminals 245 and the processor package electrical terminals 215 may include BGA, LGA, and/or PGA. In some embodiments, one or both of the power management package electrical terminals 245 and the processor package electrical terminals 215 are configured or designed to closely mate with the electrical socket. Examples of electrical terminals configured or designed to closely mate with electrical sockets include LGA and/or PGA.

Conductive studs or an array of conductive studs (generally, conductive studs) 260 are provided in the power management package substrate 220. Each power converter die 230 is arranged between adjacent conductive studs 260. The conductive studs 260 are in electrical communication with the power converter die 230 and the conductive layer 216 and/or the conductive posts 218 to provide an electrical conductive path for sending output power from the power converter die 230 to the processor 200. One or more of the conductive studs 260 conduct the supply power (for example, supply current at the supply voltage V _DD ), and one or more of the conductive studs 260 are grounded and conduct ground current from the processor 200 , For example, as shown in Figure 3. For example, the first conductive stud 260 conducts the supply power (for example, _{the supply current under the supply voltage V DD} ) to the first interconnection portion (for example, the first conductive pillar 218) in the power management package substrate 220, and the second The conductive stud 260 conducts ground current from the second interconnection portion (for example, the second conductive pillar 218) in the power management package substrate 220. The first conductive pillar and the second conductive pillar 218 are in electrical communication with the processor 200. In some embodiments, the conductive stud 260 is also used to send electrical signals between the processor 200 and the power module 24. Therefore, the power management module 24 has electrical termination portions on both sides: the conductive stud 260 on the first or top side and the power management package electrical termination portion 245 on the second or bottom side.

When the power management package substrate 220 and the processor 200 are centered and aligned with respect to each other, as shown in FIG. 2A, the output power flowing through the conductive studs 260 travels vertically through the conductive studs 218 to reach the processor 200. However, when the power management package substrate 220 and the processor 200 are horizontally offset relative to each other, the output power flowing through the conductive studs 260 travels horizontally through the conductive layer 216 and vertically travels through the conductive pillars 218 to reach the processor 200. Although two configurations are conceived, it is recognized that aligning and centering the power management package substrate 220 and the processor 200 shortens the distance that the output power/current must travel, which enables the processing between the power management module 24 and the processor 200 The loss and electrical loss of the interconnection part of the device package (for example, the conductive layer 216 and the conductive pillar 218) Resistance is reduced. For example, the shortened distance that the output power/current must travel can reduce the broadband electrical impedance of the interconnection portion that transmits power from the power management module 24 to the processor 200.

In some embodiments, the power management module 24 (including the power management package substrate 220, the power converter chip 230, and the power management package electrical terminal 245) has a cross-sectional height 270, which is less than or equal to that of the processor package electrical terminal 215 The cross-sectional height 280 is such that the power management module 24 can be assembled beside the processor package electrical terminals 215 without extending vertically beyond the processor package electrical terminals 215 (as shown in FIG. 2A). In some embodiments, the processor package electrical terminal 215 has the following cross-sectional height 280: about 1 mm, about 0.8 mm, about 0.6 mm, any cross-sectional height or range between any two of the foregoing cross-sectional heights, or less Section height. As used herein, "about" means plus or minus 10% of the relevant value.

The cross-sectional height 270 of the power management module 24 is less than or equal to the corresponding cross-sectional height 280 of the processor package electrical terminal 215, for example, less than or equal to about 1 mm, less than or equal to about 0.8 mm, less than or equal to about 0.6 mm, or the processor package The other cross-sectional height of the electrical terminal 215 is 280. In certain embodiments, when the processor package electrical terminals 215 include BGA and/or PGA, the cross-section of the power management module 24 The height 270 is less than or equal to the corresponding cross-sectional height 280 of the processor package electrical terminal 215. In other embodiments, the cross-sectional height 270 of the power management module 24 may be greater than or equal to the cross-sectional height 280 of the processor package electrical terminal 215, for example, when the processor package electrical terminal 215 includes LGA.

The processor package substrate 210 and/or the power management package substrate 220 may include organic polymer materials, resins, epoxy resins, thermoplastics, prepreg materials, and/or another material. In some embodiments, the power management package substrate 220 and the power management die(s) include wafer-level packages, such as wafer-scale packages or fan-out packages. The wafer level package can reduce the cross-sectional height 270 or profile of the power management module 24, which allows the power management module 24 to be assembled within a smaller cross-sectional height 280 of the processor package electrical terminal 215 (such as BGA). For example, using a fan-out wafer level package, the cross-sectional height 270 of the power management module 24 may be about 0.5 mm. Note that in the case of wafer-level packages, the power management package substrate is fabricated on the power converter chip and polymer filler material.

In operation, as shown in FIG. 3, a _{current having an input voltage V IN} is sent to the power management package electrical terminal 245, and the power management package electrical terminal 245 electrically conducts the current to the power converter die 230. The power converter chip 230 _{down-converts the input voltage V IN} to the supply voltage V _DD . The current at the supply voltage V _DD is then sent to the processor 200 via the conductive stud 260 and the conductive stud 218 (optionally, and the conductive layer 216). In one embodiment, the input voltage V _IN is approximately 2V, and the supply voltage V _DD is approximately 0.8V. In some embodiments, the input voltage V _IN is about 5V, about 12V, about 48V, or another input voltage. In some embodiments, the supply voltage V _DD is approximately 1.8V, 1.2V, 1.2V to 0.4V or another output voltage. In some embodiments, one or more of the power converter chips 230 _{down-convert the input voltage V IN} to the first supply voltage V _DD1 , and one or more of the power converter chips 230 convert the input voltage V _{IN is} down-converted to a second supply voltage V _DD2 different from the first supply voltage V _DD1 . For example, the first supply voltage V _DD1 may be used to power the first chip in the processor module 22 (for example, it requires a first current (for example, 200A)), and the second supply voltage V _DD2 may be used Power is supplied to the second chip in the processor module 22 (for example, it requires a second current (for example, 20A)).

Figure 2B is a cross-section of a component 20B according to another embodiment. The component 20B is the same as the component 20A, except that the processor chip 200 and the power management module 24 are laterally offset.

Figure 2C is a cross-section of a component 20C according to another embodiment. The component 20C is the same as the component 20A, except that the processor chip 200 and the power management module 24 are It is provided outside on the same side of the processor package substrate 210. In addition, the power management package substrate 220 includes electrical contacts (power management package electrical terminals 245) on only one side. The power management substrate 220 does not include conductive studs 260. In other embodiments, the power management package substrate 220 includes conductive studs 260 on only one side, and does not include power management package electrical terminals 245.

Figure 4 is a block diagram of component 40 in accordance with one or more embodiments. The component 40 includes a processor module 42 and a power management module 44. The processor module 42 includes one or more processor chips 400, an optional memory chip 402, an optional decoupling capacitor 404, an optional accelerometer chip 406, and a processor package substrate 410. In some embodiments, the processor die(s) 400, and optionally the memory die(s) 402, and the processor/SoC 200 are the same or different. The processor chip(s) 400, the optional memory chip(s) 402, the optional decoupling capacitor 404, and the optional accelerometer chip 406 are mounted on the processor package substrate 410 On the first side, such as by wire bonding, flip chip attachment, or other methods known in the art.

The power management module 44 includes one or more power converter chips 430, an optional decoupling capacitor 434, and a power management package substrate 420. The power converter chip(s) 430 and optional decoupling capacitor 434 are mounted on On the power management package substrate 420, such as by wire bonding, flip chip attachment, or other methods known in the art. In some embodiments, the power converter die(s) 430 includes thin film power inductors, such as magnetic core inductors or magnetic clad inductors, integrated into a multilayer wiring network. For example, the power converter chip(s) 430 may be compatible with the U.S. Patent Application Publication No. 2018 entitled "Integrated Switched Inductor Power Converter" published on April 19, 2018. The power converter chip and the chiplet disclosed in /0110123 are the same or different, and this application is incorporated herein by reference.

The power management module 44 may be installed on the second side of the processor package substrate 410, for example, as shown in FIGS. 2 and 3. Alternatively, the power management module 44, the processor chip(s) 400, the memory chip(s) 402, the optional decoupling capacitor 404, and the optional accelerometer chip 406 may be It is mounted on the same side (for example, the first side) of the processor package substrate 410.

The processor module 42 and the power management module 44 may be the same as or different from the processor module 22 and the power management module 24. Therefore, the component 40 may be the same or different from the components 20A, 20B, and/or 20C.

Figure 5 is a block diagram of component 50 according to one or more embodiments. The assembly 50 includes a processor module 42 and a power management module 54. The power management module 54 includes one or more power converter chips 530, one or more transformers 531, one or more inductors 532, and a decoupling capacitor 434. In this embodiment, the power converter die(s) 530 does not include an integrated thin film power inductor as described above with respect to the power converter die(s) 430. In contrast, the power management module 54 includes an inductor (one or more) 532 and a transformer that are not provided on the same chip(s) as the power converter chip(s) 530, respectively. (One or more) 531.

FIG. 6 is a schematic diagram of a switched inductor type DC-DC power converter chiplet 60 according to one or more embodiments. The switched inductor type DC-DC power converter chiplets 60 may be included in the power converter chip(s) 230 and/or 430. In some embodiments, the power converter chip(s) 230 and/or 430 include a plurality of such chiplets 60. The switched inductor DC-DC power converter chiplet 60 includes a switched inductor DC-DC power converter 600 that is fabricated and/or integrated on a common power converter substrate 610 (such as a silicon substrate). The switched inductor type DC-DC power converter 600 includes a feedback control circuit 620, an interface circuit 630, a regulating circuit 640, and a power train 650.

The power supply system 650 is divided into phases 651A and 651B (generally, phase 651N). Each phase 651N includes a separate power switch 660N and a separate thin film inductor 670N. Each power switch 660N may be a CMOS power switch including a PMOS transistor gate 662N and an NMOS transistor gate 664N, respectively. Each transistor gate 662N, 664N may include two switches connected in series in a cascode configuration. In some embodiments, both the high-side switch and the low-side switch are composed of NMOS transistors (e.g., transistor gate 664N).

For example, phase 600A includes power switch 660A and thin film inductor 670A. The power switch 660A includes a PMOS transistor gate 662A and an NMOS transistor gate 664A, respectively. Phase 651B is the same as phase 651A, and therefore includes its own power switch 660B and thin film inductor 670B (not illustrated in FIG. 6). The switched inductor type DC-DC power converter chiplet 60 may include an additional phase 600N as desired. Each phase 600N is electrically connected in parallel with the other phases 600N. The common output terminal electrically couples the output of each phase of 500N to the output power line. The common input terminal electrically couples the input of each phase of 500N to the input power line.

The feedback control circuit 620 is configured to open and close the PMOS transistor gate 662N and the NMOS transistor gate 664N. When the PMOS transistor gate 662N is open, the corresponding NMOS transistor gate 664N is closed, and vice versa. Opening and closing each group of PMOS transistor gate 662N and NMOS transistor gate 664N generates a corresponding pulse width modulation (PWM) signal at the output of the half-bridge node 665N. The frequency of the PWM signal can be configured in the feedback control circuit as known in the art. The feedback control circuit 620 adjusts the duty ratio of the PWM signal to increase or decrease the output voltage Vo so that the output voltage Vo is equal to the target output voltage, such as V _DD . As shown in FIG. 6, the feedback control circuit 620 monitors the output voltage Vo through the load supply voltage sensing feedback line and the load ground sensing feedback line. Separate supply voltage sensing lines and ground reference sensing lines enable the power converter chiplet 60 to measure the output voltage under load independently of the power transmission channel. In addition, the control circuit 620 may change the number of phases 600N electrically connected to the load current to improve the power conversion efficiency or rapidly supply more or less current as the processor requirements dynamically change. For example, the control circuit 620 may increase the number of phases 600N electrically connected to the load current in response to an increase in the load current.

The feedback control circuit 620 calculates a voltage error, which is the difference between the output voltage Vo and the target output voltage. The target output voltage may be manually set or pre-programmed based on the specification of the load (for example, the load of the processor 200). If there is a positive voltage error (for example, the output voltage Vo is greater than the target output voltage), the feedback control circuit 620 can reduce the voltage generated by the power switch 660 The duty cycle of the PWM signal responds. If there is a negative voltage error (for example, the actual output voltage Vo is less than the target output voltage), the feedback control circuit 620 may respond by increasing the duty cycle of the PWM signal generated by the power switch 660.

The interface circuit 630 provides one or more interface connections between the chiplet 60 or one or more electrical contacts on the circuit and the chiplet 60 or one or more electrical contacts outside the circuit.

The adjustment circuit 640 is configured to open and close the PMOS transistor gate 662 and the NMOS transistor gate 664 according to the PWM signal generated by the control circuit 620.

The thin film inductor 670 and the output capacitor 680 form a low pass filter. As described herein, the thin film inductor 670 is formed in the multilayer wiring network of the power converter substrate 610. The thin film inductor 670 may include a magnetic core inductor and/or a magnetic clad inductor.

FIG. 7 is a representative cross-section 70 of the switched inductor type DC-DC power converter chiplet 60 shown in FIG. 6 according to the first embodiment. In the embodiment shown in FIG. 7, the thin film inductor 670 includes a magnetic core inductor 770 integrated on top of the multilayer wiring network 700.

The cross section 60 illustrates the PMOS transistor gate 662 and the NMOS transistor gate 664 fabricated on the power converter substrate 110. The multilayer wiring network 200 provides electrical connections between the PMOS transistor gate 662 and the NMOS transistor gate 664, the magnetic core inductor 770, and the IC wafer contact structure 730. The multilayer wiring network 700 is arranged in the wiring plane 720. Figure 7 depicts four wiring planes 70, but there is no limit to any actual number of planes. Each wiring plane 720 includes a lead segment 750. The electrical connection between the lead segments 750 of different wiring planes 720 is provided by the conductive VIA 740. The IC chip contact structure 730 may be C4 contacts, solder bumps or copper bumps, but any other contacts used for external communication of the chip are acceptable and are not limited. The contact 730 is electrically coupled to the conductive stud in the power management module (for example, the power management module 24) through the electrical interconnection portion in the power management package (for example, the power management package substrate 220). The space in the multilayer wiring network 700 is filled with a dielectric insulating material 760, such as SiO ₂ .

The magnetic core inductor 670 with a single planar magnetic core 785 is integrated on top of the multilayer wiring network 700. The main plane 775 of the planar core 785 and the wiring plane 720 are substantially parallel. The conductive winding 780 of the magnetic core inductor 770 that forms a substantially spiral shape on the outside of the planar magnetic core 785 is composed of lead segments 750' and VIA 740' segments, and the lead segments 750' and VIA 740' are arranged in the multilayer wiring Network 700 At least two integrated planes 722 on the top. The VIA 740' forming part of the winding 780 is perpendicular to the main plane 775 and electrically interconnects the lead segments 750' in at least two integration planes 722.

The magnetic core 785 may include ferromagnetic materials, such as Co, Ni, and/or Fe, including alloys thereof, such as Ni _x Fe _y or Co _x Ni _y Fe _z . Additionally, or in the alternative, the magnetic core 785 may include multiple layers. The layers may include alternating layers of ferromagnetic layers (for example, Co, Ni and/or Fe, alloys of Co, Ni and/or Fe, etc.) and non-ferromagnetic layers. For example, the non-ferromagnetic layer may be or may include an insulating material, a ferromagnetic material such as an oxide _{(e.g., Co x O y, Ni x} O y and / or Fe _x O _y).

In some embodiments, the interface layer may be deposited on the insulating material layer. The interface layer can be used in the manufacturing process to help deposit the next ferromagnetic layer on the insulating material layer. The material including the interface layer may be selected to improve the adhesion between the ferromagnetic layer and the insulating material layer and/or reduce the roughness at the interface between the ferromagnetic layer and the insulating material layer. Reducing the roughness at the interface between the ferromagnetic layer and the insulating material layer can reduce the coercive force for the magnetic core 180. Improving the adhesion between the ferromagnetic layer and the insulating material layer can reduce the possibility of film delamination. In addition, the interface layer may serve as a diffusion barrier or getter between the ferromagnetic layer and the insulating material layer to prevent material components from diffusing from the insulating material layer to the ferromagnetic layer. Finally, the interface layer can be Choose to reduce or compensate the mechanical film stress in the magnetic core 785. The interface layer can be composed of Ta, Ti, W, Cr or Pt, or any combination of the foregoing, depending on the specific selection of the ferromagnetic material and the insulating material layer.

In some embodiments, the non-ferromagnetic layer may be or may include a current rectifying layer. For example, the current rectifying layer can be based on Schottky diodes. The following sequence can be electrodeposited on the ferromagnetic layer: semi-conductive layer-p-type with a working function smaller than that of the ferromagnetic layer or n-type with a working function larger than that of the ferromagnetic layer; followed by the interface metal layer-with a working function smaller than The working function of the p-type semiconductor material may be greater than that of the n-type semiconductor material. Then, continue to the next ferromagnetic layer, and so on. Alternatively, for rectification, semiconductor p-n junctions can be used in the non-ferromagnetic layer. Any semiconductor can be suitable, and one will have to be selected based on several criteria (such as, without limitation, ease of contact with the magnetic material of the p-part and n-part, how narrow the junction can be made) and other criteria.

In some embodiments, the magnetic core inductor 770 is compatible with one or more of the inductors described in U.S. Patent Application No. 15/391,278, U.S. Patent Application Publication No. 2014/0071636, and/or U.S. Patent No. 9.647,953. Many are the same, substantially the same, or similar, and these applications and patents are hereby incorporated by reference. In some embodiments, the switched inductor type DC-DC power converter chiplets 60 and cross-sectional 70 includes multiple inductors, each of which may be the same or similar to inductor 670. The plurality of inductors may be arranged in electrical parallel with each other, in electrical series with each other, or in a combination thereof. The multiple inductors may be integrated in the same integration plane 222 or in different integration planes.

FIG. 8 is a representative cross-section 80 of the switched inductor type DC-DC power converter chiplet 60 shown in FIG. 1 according to the second embodiment. Section 80 is the same or substantially the same as section 70, except as described below. In the embodiment shown in FIG. 8, the thin film inductor 670 includes a magnetic clad inductor 870 integrated on top of the multilayer wiring network 700. The magnetically clad inductor 870 includes a ferromagnetic yoke 875 surrounding a conductive winding 880. The ferromagnetic yoke 875 may include Co, Ni, and/or Fe, such as Ni _x Fe _y or another material as known in the art. The conductive winding 880 forms a generally spiral shape over which the yoke 875 is disposed.

The conductive winding 880 is composed of at least two lead segments 750' and VIA 740' segments in the integration plane 722. The VIA 740' forming part of the winding 880 interconnects the at least two integrated planes 722. Note that the lead segments 750' in the top integration plane 722 are not illustrated in FIG. 8 because they will be invisible in the cross section 80.

In some embodiments, the switched inductor type DC-DC power converter chiplet 60 and cross section 80 include multiple inductors, each of which is the same or similar to inductor 870. The plurality of inductors may be arranged in electrical parallel with each other, in electrical series with each other, or in a combination thereof. The multiple inductors may be integrated in the same integration plane 722 or different integration planes 722. In some embodiments, the switched inductor type DC-DC power converter chiplet 60 includes one or more inductors 770 and one or more inductors 870.

It should be noted that the above-mentioned implementation manners are only examples of preferred embodiments of the present invention, and in order to avoid redundant description, all possible variations and combinations are not described in detail. However, those skilled in the art should understand that not all of the above-mentioned modules or components are necessary. In order to implement the present invention, other detailed conventional modules or components may also be included. Each module or component may be omitted or modified as required, and there may not be other modules or components between any two modules. As long as it does not deviate from the basic structure of the present invention, the scope of the rights claimed in this patent shall be the scope of the patent application.

20A: Components

200: processor

201, 220: Center point

210: processor package substrate

212: first side

214: second side

215: processor package electrical terminals

216: conductive layer

218: Conductive column

22: processor module

220: Power management package substrate

230: power converter chip

24: Power Management Module

240: Power management package substrate

245: Power management package electrical terminals

250: Clearance

260: Conductive stud

270, 280: Section height

Claims (30)

A microelectronic component, the microelectronic component includes: a processor module, the processor module includes: a processor package substrate, the processor package substrate has a first side and a second side opposed to each other; The processor chip, the processor chip is mounted on the first side of the processor package substrate; and an array of electrical termination portions, the array of electrical termination portions is provided on the second side of the processor package substrate And a power management module, the power management module is disposed on the second side of the processor package substrate, the power management module includes: a power management package substrate; and is installed on the power management package substrate The power converter chip is arranged between the power management package substrate and the first side or the second side of the processor package substrate; wherein the height of the power converter module is less than Or equal to the height of the electrical termination portion on the second side of the processor package substrate, the height being measured with respect to an axis orthogonal to the plane defined by the second side of the processor package substrate. The microelectronic component as described in the first item of the scope of patent application, wherein the power converter chip is disposed between the power management package substrate and the second side of the processor package substrate. The microelectronic component as described in the first item of the scope of patent application, wherein the processor package substrate and the power management package substrate each include an organic polymer and a conductive interconnection portion, the conductive interconnection portion straddling the first side of the corresponding substrate And the second side extends. The microelectronic component described in item 3 of the scope of patent application, wherein the power converter chip is in electrical communication with the processor chip through the conductive interconnect portion in the processor package substrate. The microelectronic component as described in item 1 of the scope of patent application, wherein the height of the power converter is less than or equal to 1 mm, and the array of electrical termination portions includes a ball grid array. The microelectronic assembly described in the first item of the scope of the patent application further includes electrical termination portions arranged on the first side and the second side opposite to the power management module. According to the microelectronic component described in item 6 of the scope of patent application, the power management module includes a first conductive stud and a second conductive stud extending from the first side of the power management module, and the power supply The converter chip is arranged between the first conductive stud and the second conductive stud and is in electrical communication with the first conductive stud and the second conductive stud, and the first conductive stud conducts the supply current To deal with The first electrical interconnection portion on the second side of the processor package substrate, and the second conductive stud conducts a ground current from the second electrical interconnection portion on the second side of the processor package substrate. The microelectronic component as described in item 6 of the scope of patent application, wherein more than 50% of the electrical termination portion on the first side of the power management module is electrically coupled to the power supply terminal and the ground terminal, and the power supply More than 50% of the electrical termination portion on the second side of the management module is electrically coupled to the power input terminal and the ground terminal. The microelectronic component as described in claim 7, wherein the electrical termination portion on the second side of the power management module includes a ball grid array. For the microelectronic component described in claim 9, wherein the combined height of the ball grid array and the power management module is less than or equal to the height of the electrical termination part array in the processor module, and the combined height And the height is measured relative to an axis orthogonal to the plane defined by the second side of the processor package substrate. In the microelectronic component described in item 9 of the scope of patent application, the array of electrical termination portions in the processor module includes a ball grid array. The microelectronic component as described in item 6 of the scope of the patent application, wherein the electrical termination portion provided on the second side of the power management module includes a ball grid array, a pad grid array, or a pin grid Array. In the microelectronic component described in item 6 of the scope of patent application, the electrical termination portion provided on the second side of the power management module is designed to closely fit with an electrical socket. The microelectronic component described in claim 1, wherein the processor chip includes silicon. The microelectronic component described in claim 1, wherein the power converter chip includes silicon nitride or gallium nitride. According to the microelectronic component described in claim 1, wherein the power converter chip includes: a multilayer wiring network; and an inductor, and the inductor is integrated on a top of the multilayer wiring network. The microelectronic component according to the 16th patent application, wherein the inductor includes a conductive winding, and the conductive winding includes: a first lead formed on a first lead arranged on the multilayer wiring network In an integration plane; a second lead formed in a second integration plane that is disposed on the first integration plane; and A conductive VIA is formed between the first lead and the second lead, and the conductive VIA electrically connects the first lead to the second lead. As described in the first item of the scope of the patent application, the microelectronic component further includes a plurality of the power converter chips, and each power converter chip is mounted on the power management package substrate. As described in the 18th patent application, a first power converter chip outputs a first supply current at a first supply voltage, and a second power converter chip outputs a first supply current at a second supply voltage. 2. Supply current. The microelectronic component described in item 19 of the scope of patent application, wherein the first supply voltage is different from the second supply voltage. The microelectronic component according to the 19th patent application, wherein the power management module includes one or more capacitors, one or more inductors, one or more transformers, or a combination of any of the foregoing . The microelectronic component described in item 2 of the scope of patent application, wherein the processor module and the power management module are aligned and centered with respect to each other to reduce current between the processor module and the power management module The distance traveled. In the microelectronic component described in the first item of the scope of patent application, the power management module is composed of wafer-level packages. A microelectronic component, the microelectronic component includes: a processor module, the processor module includes: a processor package substrate, the processor package substrate has a first side and a second side opposed to each other; A processor chip, the processor chip is mounted on the first side of the processor package substrate; an array of electrical termination portions, the array of electrical termination portions is provided on the second side of the processor package substrate; And a power management module, the power management module is disposed on the second side of the processor packaging substrate, the power management module includes: a power management packaging substrate; and installed on the power management packaging substrate A power converter chip, the power converter chip is disposed between the power management package substrate and the first side or the second side of the processor package substrate; and is disposed on the opposite side of the power management module The electrical termination portion on the first side and the second side; wherein the power management module includes a first conductive stud and a second conductive stud extending from the first side of the power management module, the The power converter chip is set in The first conductive stud and the second conductive stud are in electrical communication with the first conductive stud and the second conductive stud, and the first conductive stud conducts the supply current to the processor package substrate The first electrical interconnection portion on the second side of the second side, the second conductive stud conducts ground current from the second electrical interconnection portion on the second side of the processor package substrate; wherein the power management module The electrical termination portion on the second side includes a ball grid array; and wherein the combined height of the ball grid array and the power management module is less than or equal to the height of the electrical termination portion array in the processor module The combined height and the height are measured with respect to an axis orthogonal to a plane defined by the second side of the processor package substrate. The microelectronic assembly according to item 24 of the scope of patent application, wherein the processor package substrate and the power management package substrate each include an organic polymer and a conductive interconnection portion, and the conductive interconnection portion straddles the first side of the corresponding substrate And the second side extends. In the microelectronic assembly described in the 25th patent application, the power converter chip communicates with the processor chip through the conductive interconnection part in the processor package substrate. As for the microelectronic component described in claim 24, wherein the height of the power converter is less than or equal to 1 mm, and the electrical termination part array includes a ball grid array, and the height is relative to that of the processor package Measured on an axis orthogonal to the plane defined by the second side of the substrate. The microelectronic component according to item 24 of the scope of patent application, wherein more than 50% of the electrical termination portion on the first side of the power management module is electrically coupled to the power supply terminal and the ground terminal, and the power supply More than 50% of the electrical termination portion on the second side of the management module is electrically coupled to the power input terminal and the ground terminal. The microelectronic component described in the 24th patent application, wherein the array of electrical terminations in the processor module includes a ball grid array. According to the microelectronic component described in item 24 of the scope of the patent application, the electrical termination portion provided on the second side of the power management module is designed to closely fit with an electrical socket.

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