TWI719195B - Dynamic clock gating frequency scaling - Google Patents

Abstract

An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.

Description

Dynamic clock gating frequency scaling technology

FIELD OF THE INVENTION Embodiments may be related to controlling a clock gate based on a specific frequency of a clock signal.

BACKGROUND OF THE INVENTION Clock gating is a technique used to reduce the power consumption of idle logic. In order to save power, clock gating can mean that the clock is activated at the logic block only when there is work to be performed. However, clock gating may introduce additional timing constraints. For example, it may be difficult to include clock gating in complex logic where timing tolerances may be extremely tight.

According to an embodiment of the present invention, an electronic device is specifically proposed, which includes: a clock device for providing a clock signal; a clock gate for receiving the clock signal, and the clock gate for selecting Is set in an enabled state or a disabled state; and a controller for determining a specific frequency of the clock signal, and for controlling the clock gate on the basis of the determined specific frequency In the enabled state or in the disabled state.

Detailed Description of the Preferred Embodiment In the following detailed description, similar reference numerals and characters can be used to designate the same, corresponding and/or similar components in different drawings. In addition, in the following detailed description, the instance size/model/value/range may be given, although the embodiment is not limited thereto. When specific details are described in order to describe example embodiments, it is obvious to those skilled in the art that the embodiments can be practiced without such specific details.

The embodiments may be applicable to electronic systems, and electronic equipment and/or electronic devices. The electronic system and/or electronic device can be any of the following: mobile terminal, mobile device, mobile computing platform, mobile platform, server, laptop, tablet, ultra-mobile personal computer, mobile internet Network devices, smart phones, personal digital assistants, display devices, televisions (TV), etc.

The embodiment may be related to an electronic system and/or electronic device, which may also be referred to as a platform. The platform may include hardware and software. The processor may be a component of the platform.

Figure 1 is a block diagram of an electronic system configured according to an example. Other combinations and configurations can also be provided.

More specifically, FIG. 1 shows an electronic system 100 that may include a system-on-chip (SOC) 120, a system memory 150, and a display 160. For ease of discussion and description, the components shown in FIG. 1 are only an example. Other components can also be provided. The electronic system 100 can also be referred to as an electronic device and/or an electronic device.

As an example, the system-on-a-chip 120 may include a processor 122, a power management unit (PMU) 124, a memory controller 126, a video controller 128 and a clock device 140. These elements are only shown as an example, and other components may also be provided.

The clock device 140 can provide a clock signal for use by the SOC 120. The clock signal can be used to drive logic at the SOC 120. As an example, logic can be provided as a functional block (or logic block), and the functional block can be driven by a clock signal. In at least one configuration, the clock device may include a phase-locked-loop (PLL) circuit to provide a clock signal. The clock signal can be provided at a single frequency. However, the frequency of the clock signal can be changed at the clock device, or can be changed by the components of the PMU 124.

The power management unit (PMU) 124 may be coupled to receive the clock signal from the clock device 140. In at least one configuration, the PMU 124 can manage the clock signal (or clock signal) and provide the clock signal to individual components, such as the processor 122 (and/or functional blocks of the processor 122), memory The controller 126 and the video controller 128.

The processor 122 may include logic that can operate based on the received clock signal. In at least one example, the logic (of the processor 122) may include at least one functional block (or logic block). In at least one example, the logic (of the processor 122) may include multiple functional blocks. Each functional block can individually receive a clock signal and perform a specific function based on the received clock signal.

The function block can be operated at different frequencies. For example, the functional block (or logic block) can operate in a first mode (which uses a clock signal at a first frequency), and can operate in a second mode (which uses a clock signal at a second frequency) ). In other words, in order for the functional block to operate in the first mode (or first operating mode), the clock signal must be provided to the block at the first frequency, and for the block to operate in the second mode (or second operating mode) Mode), the clock signal must be provided to the block at the second frequency.

The memory controller 126 can be installed on the SOC 120 and can communicate with the system memory 150. The system memory 150 can store information in the system memory 150 and/or can provide information from the system memory 150 to the SOC 120. The memory controller 126 can receive signals and/or information from the PMU 124.

The video controller 128 can be installed on the SOC 120 and can operate with the display 160 to display images, objects, and the like. The display 160 may be external to the SOC 120. The video controller 128 can control the display 160. The video controller 128 can receive signals and/or information from the PMU 124.

Figure 2 is a diagram showing the clock pulse source and intellectual property (IP) configured according to the example. The clock pulse source and IP can be set in an electronic device, electronic device or electronic system. As an example, the clock pulse source and IP can be provided with the electronic system 100 of FIG. 1. Other combinations and configurations are also possible.

More specifically, FIG. 2 shows the clock device 140 and the intellectual property (IP) 200. The IP 200 may include any of several different logics, circuits, etc. IP can refer to functional modules, processors, video controllers, memory controllers, interconnects, etc.

In at least one example, IP 200 may correspond to processor 122 on SOC 120. IP 200 can correspond to other components of electronic systems and/or electronic devices/equipment. In at least one configuration, IP 200 may be part of processor 122 and/or PMU 124. IP can include logic. Logic may include circuits, firmware, functional blocks, etc. in order to perform desired tasks or functions.

The IP 200 components/components can be set up and/or configured in any of several different ways. Therefore, although Figure 2 shows one configuration, other configurations and components can also be provided.

As shown in FIG. 2, the IP 200 may include a clock gate 210 and a logic tree. As an example, the logic tree may include a logic block 220, a logic block 230, and a logic block 240. Other numbers of logic blocks can also be provided. Logic blocks can be provided to perform any of several different functions, operations, and/or applications. Each logic block may include logic and/or circuits for performing specific functions of the logic block.

As an example, the logic block 220 may be designed to perform a first function (or operation or application) by receiving a clock signal, and the logic block 230 may be designed to perform a second function by receiving a clock signal ( Or operation or application), and the logic block 240 can be designed to perform a third function (or operation or application) by receiving a clock signal. Each logic block can perform a separate function or application in response to receiving a clock signal.

The clock device 140 can provide a clock signal at a specific frequency. The clock signal can be provided from the clock device 140 to the clock gate 210 of the IP 200. The specific frequency of the clock signal can be changed and/or changed.

The clock gate 210 can be set in two different states, namely: (1) enabled state and (2) disabled state. The activated state can also be referred to as activated mode or closed mode. The disabled state can also be referred to as a disabled mode or a disconnected mode.

If the clock gate 210 is set in the enabled state, the clock signal can pass through the clock gate 210 to each of the respective logic blocks 220, 230, and 240 of the logic tree. In other words, the clock signal can be provided to the logic block when the clock gate is set in the enabled state. On the other hand, if the clock gate 210 is set in the disabled state, the clock signal may not pass through the clock gate 210 to each of the respective logic blocks 220, 230, and 240 of the logic tree. In other words, when the clock gate is in the disabled state, the clock signal can be blocked (or rejected) from being provided to (or reached) the logic block of the logic tree.

In at least one example, the clock gate 210 may include a switch that can be opened or closed to set the clock gate in an enabled state or a disabled state, respectively. For example, when the switch (of the clock gate 210) is closed, the clock gate is regarded as being set in the enabled state (or closed state). When the clock gate is in the active state, the clock signal from the clock device 140 can pass through the clock gate 210 (that is, through the switch), and can be provided to the respective logic blocks 220, 230, 240 of the logic tree Each of them. On the other hand, when the switch (of the clock gate 210) is turned off, the clock gate is regarded as being set in a disabled state (or an open state). When the clock gate is in the disabled state, the clock signal from the clock device 140 may not pass (or be refused to pass) the clock gate 210, and the logic block may not receive any clock signal. Therefore, the logic blocks 220, 230, and 240 may not operate when the clock 210 is in the disabled state.

The embodiment can implement dynamic clock gating frequency scaling (DCFS). An embodiment may implement clock gating at an IP (such as a processor, a chip, etc.) only at a specific frequency. A specific frequency can be provided because some specific frequencies may not meet the timing on the clock gating path, and therefore clock gating can be disabled for certain high frequencies. At lower frequencies where the time period increases, more timing margins can be provided on the clock gating timing path, thereby enabling clock gating at lower frequencies. Embodiments may include determining a specific operating frequency and determining whether the clock will be in an enabled state or a disabled state. For example, the controller can determine the frequency transition, which is the time point at which the frequency of the clock signal can be changed. The controller may control the clock gate to be in an enabled state or a disabled state based on the determined frequency (and/or frequency transition).

In at least one example, during the operation time of the IP, the firmware (or software) can selectively enable and/or disable the clock gate based on the respective frequency of the clock device. This can control whether the clock signal can be provided to at least one of the logic blocks (or functional blocks). Therefore, the logic block can perform a specific function based on a specific frequency. The selective provision of enabling and/or disabling of the clock gate can be performed by the controller, firmware, logic, and/or circuit. The selective provision of enabling or disabling may be based on specific frequencies and/or frequency transitions, such as when the clock signal frequency will change.

During operation, the bandwidth to be used at the IP (or electronic device) can be determined. In other words, the amount of bandwidth to be used (or being used) at the IP (or electronic device/system) can be monitored or determined. To save power, different frequencies can be used based on the amount of data being used. As an example, an application can be executed (or run) and can consume a certain amount of data. The application can operate at any of a number of different frequencies. Therefore, based on the determined bandwidth and possible frequencies, the specific frequency (and therefore the frequency transition) can be determined. Based on frequency (and/or frequency transition), the clock gate at the IP can be selectively enabled or disabled. The enabling and/or disabling of the clock gate (clock signal) can control whether to provide the clock signal to each logic block. In other words, the logic block can receive the clock signal (or not receive the clock signal) based on the selective activation or deactivation of the clock gate. The selective activation or deactivation can be based on a specific frequency (and/or frequency transition).

In at least one embodiment, the controller can use firmware (such as p-code) to operate to monitor the bandwidth, determine the frequency (of the clock signal), and enable/disable the clock gate to provide (or No clock signal is provided to each logic block. The firmware (or p-code) can be stored in a memory (such as an IP memory).

In at least one embodiment, the controller can monitor the amount of data being used at the IP (such as processor, chip, SOC, etc.). For example, the controller can monitor data when a specific application (at the logical block) of the IP is being used (or will be used). The controller can therefore determine the amount of bandwidth that is being used (or will be used). Based on the determined amount of bandwidth, the controller may determine at least one of a plurality of different frequencies that can be used. Multiple different frequencies can be stored previously. As an example, the new determined frequency may be more efficient in terms of IP (or electronic device/system) power consumption. Based on the new frequency, the controller can control the activation and/or deactivation of the clock gate.

More specifically, the controller (by using firmware and/or software) can determine a specific operating frequency. The specific operating frequency can be based on the frequency of the clock signal from the clock device (the clock device can provide clock signals at different frequencies). Therefore, the clock gate can be selectively activated or deactivated based on the determined new frequency.

Embodiments can implement clock gating at a specific frequency based on available timing tolerances and by adding support in firmware (and/or software) to selectively enable/disable clock gating at an appropriate frequency. This can generate optimal power across workloads operating across different frequency ranges.

As stated above, different clock signals can be provided from the clock device at different frequencies, such as. The different clock signals may originate from one or more clock devices (such as different phase-locked loops) and/or in the PMU 120.

FIG. 3 is a diagram of a clock pulse source and intellectual property (IP) according to an example embodiment. The clock pulse source and IP can be set in electronic equipment, electronic devices and/or electronic systems. Other configurations and embodiments are also possible. The diagram of FIG. 3 may include the components shown in FIG. 2. For ease of discussion, similar or identical components may not be described further.

More specifically, FIG. 3 shows the clock device 140 and the IP 200. The IP 200 can be, for example, a platform or a SOC. FIG. 3 also shows a controller 300 (or control device) that can be operated based on firmware (such as p-code). For example, firmware (such as p-code) may be provided in the memory 310. The memory 310 can also be used to provide logic for memory bandwidth. The controller 300 can selectively control the activation or deactivation of the clock gate 210. In at least one embodiment, multiple clock gates may be provided, and each gate may be individually and selectively controlled by the controller 300 or other devices (such as a processor).

The clock gate 210 can be set and controlled by a statically configured register during startup. This can be done to control hardware (HW) settings. The register can be a collection of flip-flops to preset values during startup.

表1The controller 300 can control the state (enabled or disabled) of the clock 210 based on firmware (such as p-code). The controller 300 can enable/disable the clock gating (to operate the components of the IP) based on the IP frequency and/or the frequency of the clock signal. As an example, the memory (or storage) may include information related to the enabling/disabling of the IP frequency (or clock signal frequency) and clock gating. This information may be referred to as the information in Table 1 below. The look-up table (shown below) may include this information in Table 1 related to IP frequency and clock gating activation/deactivation. This information can be previously determined and stored in the electronic equipment, device or system. As an example, the information of the look-up table can be pre-stored as p-code. The p code can be a software (SW) program code executed by a controller (or other device). The information in Table 1 can be stored in the memory 310 and/or other memories of the SOC.

Table 1

The information in Table 1 (shown above) shows that the clock gate 210 can be controlled based on the IP frequency, which is the specific frequency that will be used to operate the logic block of the IP. The frequency can be determined based on the determined bandwidth that is being used (or will be used). As discussed above, the determination can be performed by any of the following (ie, the controller 300, firmware, p-code, etc.).

The embodiment can provide a clock gate to control whether to provide a clock signal (at a specific frequency) to the logic (or logic block) of the IP. This determination can be based on previously obtained information such as shown in Table 1. The information in Table 1 can be based on the timing tolerances available at each frequency of a specific IP.

As shown in Table 1, the clock gate 210 can be selectively set in the enabled state only at a specific frequency. For example, the clock gate 210 can be selectively set in the enabled state (or closed state) when the specific frequency of the clock signal will be 1.35 GHz or 1.1 GHz. Therefore, when the clock signal is provided at 1.35 GHz or 1.1 GHz, the clock signal can pass through the clock gate 210 and be provided to the logic block.

On the other hand, the clock gate 210 can be selectively set in the disabled state (or disconnected state) when the specific frequency of the clock signal will be 1.6 GHz or 2.1 GHz. Therefore, when the clock signal is provided at 1.6 GHz or 2.1 GHz, the clock signal may not pass through the clock gate 210, and the respective logic block may not operate (this is because the logic block does not receive the clock signal).

Figure 4 is a flowchart showing operations according to example embodiments. Other operations, sequences of operations, and embodiments can also be used. For ease of discussion, FIG. 4 shows operation with respect to, for example, an embodiment of the electronic system shown in FIG. 3 (which may be a component of the electronic system of FIG. 1). Figure 4 does not show all the operations of the electronic system.

The flowchart of FIG. 4 can be executed at least in part by a controller, firmware, p-code, etc. This can dynamically control the clock gating of the IP based on the running time IP frequency.

More specifically, Figure 4 shows a method of controlling an electronic device, device, or system. The electronic device, device, or system may be powered on initially in operation 402. In operation 404, a clock signal may be provided (such as from a clock device). The initial clock signal can, for example, be preset.

In operation 406, clock gating may be selectively enabled (or kept in an enabled state) at a clock gate (such as clock gate 210). This allows the clock signal to be provided to the logic block of the IP. It can be gated at the initial start of the electronic system according to the preset activation clock.

In operation 408, the bandwidth may be monitored (or determined) by the controller, for example. The controller can monitor (or determine) the amount of data being used (or will be used) when the electronic equipment, device, or system is operating at the frequency of the clock signal.

Based on the monitoring, the controller (or firmware) can determine that a new frequency can be used for efficiency purposes. In operation 410, the controller may (when determining that the new frequency is to be used) determine the frequency transition. For example, at the frequency transition point, the firmware (or p-code) can refer to (such as) the information in Table 1. This information can be used to determine whether clock gating should be enabled or disabled.

In operation 412, a determination may be made as to whether the clock gate should be selectively set in the activated state or the deactivated state. This determination can be made based on the controller, firmware, p-code, etc. For example, based on the frequency of the clock signal, it can be determined whether to enable or disable the clock gate.

Operation 414 involves deactivating the clock gate. This causes the clock signal to not be provided to the logic block. Therefore, the logic block will not perform a specific function. For example, if the IP cannot support clock gating at the new determined frequency, the clock gating can be disabled ("0") in operation 414. Operation can then return to operation 420, in which the electronic system (or part of the electronic system) can be restarted. Operation 416 may involve enabling a clock gate. This can cause the clock signal (at a specific frequency) to be provided to the logic block. Therefore, logic blocks (or functional blocks) will perform specific functions. For example, if the IP can support clock gating at the new determined frequency, the clock gating can be enabled ("1") in operation 416. Operation may then return to operation 408, where the bandwidth may be monitored.

Figure 5 shows an electronic system according to an example embodiment. Other embodiments and combinations can also be provided. An electronic system is provided to show the components of the system that can be operated as discussed above.

FIG. 5 shows a system 500 including a processor 510, a power supply 520, a display 525, and a memory 530. For example, the processor 510 may include an arithmetic logic unit and internal cache memory. The processor 510 may perform operations by using received instructions, such as instructions received via a non-transitory computer-readable medium (or machine-readable medium). The processor 510 may correspond to any of the previously described processors. A controller can also be provided.

The features described above can be arranged in the electrical system 500 shown in FIG. 5.

The system 500 may also include a graphic interface 540, a chipset 550, a cache memory 560, a network interface 570, and a wireless communication unit 580. The wireless communication unit 580 may be incorporated into the network interface 570. Alternatively or in addition, the wireless communication unit 590 may be coupled to the processor 510, and a direct connection may exist between the memory 530 and the processor 510.

The processor 510 may be a CPU, a microprocessor, or any other type of processing or calculation circuit, and may be included on a chip die having all or any combination of the remaining features, or one or more of the remaining features may be It is known that the connector and the interface are electrically coupled to the microprocessor die. The connections shown are merely illustrative, because other connections between or among the depicted elements may exist, for example, depending on the chip platform, functionality, or application requirements.

In at least one embodiment, the processor 510 may be provided on a chip (such as a system-on-a-chip as discussed above). The processor may include and/or be coupled to components such as a memory controller and a graphics device.

In at least one embodiment, the computer-readable medium (or machine-readable medium) can store a program for controlling the clock gate. The program can be stored in the system memory, which can be (for example) inside or outside the processor (or controller). The program may include instructions or program code.

The instructions or program code executed by the processor (or by the controller) may be from a machine-readable medium, or may be via a remote connection that provides access to one or more electronically accessible media (e.g., via an antenna and/ Or the external storage device accessed via the network via a network interface is provided to the memory. A machine-readable medium may include any mechanism that provides (ie, stores and/or transmits) information in a form readable by a machine (for example, a computer). For example, machine-readable media may include random access memory (RAM), read-only memory (ROM), magnetic or optical storage media, flash memory devices, electrical, optical, acoustic, or other forms of propagating signals (For example, carrier wave, infrared signal, digital signal) and so on. In alternative embodiments, hard-wired circuits may be used in place of or in combination with instructions or program codes, and therefore the embodiments are not limited to any specific combination of hardware circuits and software instructions.

The program may include program code or instructions to perform any of the operations or functions performed in the previously discussed embodiments above.

The features of the above-mentioned embodiments can be provided in code segments or instructions for performing tasks. The code segments or tasks can be stored in a processor- or controller-readable medium (or machine-readable medium), or be transmitted by a calculation data signal in a carrier wave via a transmission medium or a communication link. The processor- or controller-readable medium, machine-readable medium, and/or computer-readable medium may include any medium that can store or transmit information.

The following examples refer to other embodiments.

Example 1 is an electronic device that includes: a clock device for providing a clock signal; a clock gate for receiving the clock signal, the clock gate for selectively setting in an active state or In a disabled state; and a controller for determining a specific frequency of the clock signal, and for controlling the clock gate based on the determined specific frequency to be in the enabled state or the disabled state .

In Example 2, the subject matter of Example 1 may optionally include: a first logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 3, the subject matter of Example 1 and Example 2 may optionally include: a second logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 4, the subject matter of Example 1 and Example 2 may include: not receiving the clock signal at the first logic block when the clock gate is in the disabled state.

In Example 5, the subject matter of Example 1 and Example 2 may include: the first logic block is used to perform a specific function in response to receiving the clock signal.

In Example 6, the subject matter of Example 1 may optionally include: the controller is used to change the state of the clock gate based on a determined new frequency.

In Example 7, the subject matter of Example 1 may optionally include: a memory for storing information about enabling or disabling the clock gate based on a plurality of different frequencies.

In Example 8, the subject matter of Example 1 may optionally include: the controller is used to determine an amount of bandwidth, and determine the specific frequency based at least in part on the determined amount of bandwidth.

In Example 9, the subject matter of Example 1 may optionally include: the controller is used to determine a new frequency and used to change the state of the clock gate based on the determined new frequency.

Example 10 is an electronic device that includes: a timing component for providing a clock signal; a gate control component for receiving the clock signal, and the gate control component is used to selectively set in an active state or a stop And a control member for determining a specific frequency of the clock frequency, and the control member is used for controlling the gate control member to be in the activated state or the deactivated state based on the determined specific frequency.

In Example 11, the subject of Example 10 may optionally include: a first logic block for receiving the clock signal when the gate control member is in the activated state.

In Example 12, the subject matter of Example 10 and Example 11 may optionally include: a second logic block for receiving the clock signal when the gate control member is in the activated state.

In Example 13, the subject matter of Example 10 and Example 11 may optionally include: not receiving the clock signal at the first logic block when the gate control member is in the disabled state.

In Example 14, the subject matter of Example 10 and Example 11 may include: the first logic block is used to perform a specific function in response to receiving the clock signal.

In Example 15, the subject matter of Example 10 may optionally include: the control member is used to control the state of the gate control member based on a determined new frequency.

In Example 16, the subject matter of Example 10 may optionally include a storage member for storing information about enabling or disabling the gate control member based on a plurality of different frequencies.

In Example 17, the subject matter of Example 10 may optionally include: the control component is used to determine an amount of bandwidth, and used to determine the specific frequency based at least in part on the determined amount of bandwidth.

In Example 18, the subject matter of Example 10 may optionally include: the control member is used to determine a new frequency and used to change the state of the clock gate based on the determined new frequency.

Example 19 is a method of controlling an electronic device, which includes: providing a clock signal; determining a specific frequency of the clock signal; based on the determined specific frequency, controlling a clock gate to be selectively set in a In an enabled state or a disabled state; when the clock gate is selectively set in the enabled state, the clock signal is provided to a first logic block; and when the clock gate is selectively set in the When in the disabled state, the clock signal is rejected to reach the first logic block.

In Example 20, the subject matter of Example 19 may include receiving the clock signal at the first logic block when the clock gate is in the enabled state.

In Example 21, the subject matter of Example 19 and Example 20 may include: receiving the clock signal at a second logic block when the clock gate is in the enabled state.

In Example 22, the subject matter of Example 19 and Example 20 may include: not receiving the clock signal at the first logic block when the clock gate is in the disabled state.

In Example 23, the subject matter of Example 19 and Example 20 may include: performing a specific function in response to the first logic block receiving the clock signal.

In Example 24, the subject matter of Example 19 may optionally include: the control of the clock gate is based on a determined new frequency.

In Example 25, the subject matter of Example 19 may include storing information about enabling or disabling the clock based on multiple different frequencies.

In Example 26, the subject matter of Example 19 may include: determining an amount of bandwidth, and determining the specific frequency based at least in part on the determined amount of bandwidth.

In Example 27, the subject matter of Example 19 may include: determining a new frequency, and changing the state of the clock gate based on the determined new frequency.

Example 28 is an electronic system that includes: a memory for storing information related to multiple frequencies; a clock device for providing a clock signal; and a clock gate for selectively setting in In an activated state or in a disabled state; a controller for determining a specific frequency based on the stored information, and the controller for controlling the clock based on the determined specific frequency to be in the activated state Or in the disabled state; and a first logic block for receiving the clock signal from the clock gate when the clock gate is set in the enabled state, and the first logic block is used A specific function is executed based on the received clock signal.

In Example 29, the subject matter of Example 28 may optionally include: a second logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 30, the subject matter of Example 28 may include: not receiving the clock signal at the first logic block when the clock gate is in the disabled state.

In Example 31, the subject matter of Example 28 may optionally include: the memory is used to store information about enabling or disabling the clock based on the stored frequencies.

In Example 32, the subject matter of Example 28 may optionally include: the controller is used to determine an amount of bandwidth, and used to determine the specific frequency based at least in part on the determined amount of bandwidth.

In Example 33, the subject matter of Example 28 may optionally include: the controller is used to determine a new frequency and used to change the state of the clock gate based on the determined new frequency.

Example 34 is an electronic device, which includes: a first logic, at least a part of which is hardware, which is used to determine a specific frequency; and a second logic, at least a part of which is hardware, which is used to determine a specific frequency based on the A clock gate is controlled at a specific frequency to be in an active state or a disabled state.

In Example 35, the subject matter of Example 34 may optionally include: a first logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 36, the subject matter of Example 34 and Example 35 may optionally include: a second logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 37, the subject matter of Example 34 and Example 35 may optionally include: not receiving the clock signal at the first logic block when the clock gate is in the disabled state.

In Example 38, the subject matter of Example 34 and Example 35 may include: the first logic block is used to perform a specific function in response to receiving the clock signal.

In Example 39, the subject matter of Example 34 may optionally include: a memory for storing information about enabling or disabling the clock gate based on a plurality of different frequencies.

In Example 40, the subject matter of Example 34 may optionally include: the first logic is used to determine an amount of bandwidth, and used to determine the specific frequency based at least in part on the determined amount of bandwidth.

In Example 41, the subject matter of Example 34 may include: the first logic is used to determine a new frequency and used to change the state of the clock gate based on the determined new frequency.

Example 42 is a non-transitory machine-readable medium that includes, when executed, one or more instructions that cause a controller to perform one or more of the following actions: determining a specific frequency of a clock signal; And based on the determined specific frequency of the clock signal, a clock gate is controlled to be in an activated state or a deactivated state.

In Example 43, the subject of Example 42 may optionally include: a first logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 44, the subject matter of Example 42 and Example 43 may optionally include: a second logic block for receiving the clock signal when the clock gate is in the enabled state.

In Example 45, the subject matter of Example 42 and Example 43 may include: not receiving the clock signal at the first logic block when the clock gate is in the disabled state.

In Example 46, the subject matter of Example 42 and Example 43 may include: the first logic block is used to perform a specific function in response to receiving the clock signal.

In Example 47, the subject matter of Example 42 may optionally include: the one or more operations include determining an amount of bandwidth, and determining the specific frequency based at least in part on the determined amount of bandwidth.

In Example 48, the subject matter of Example 42 may include: the one or more operations include determining a new frequency, and changing the state of the clock gate based on the determined new frequency.

Any reference in this specification to “one embodiment”, “one embodiment”, “example embodiment”, etc. means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment. The appearances of these phrases in various places in this specification do not necessarily all refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in combination with any embodiment, it is considered that implementing this feature, structure, or characteristic in combination with other embodiments in the embodiment belongs to those skilled in the art.

Although the embodiments have been described with reference to several exemplary embodiments of the embodiments, it should be understood that many other modifications and embodiments that fall within the spirit and scope of the principles of the present invention can be devised by those skilled in the art. More specifically, there may be various changes and modifications to the components and/or configurations of the subject combination configuration within the scope of the invention, the drawings, and the appended patents. In addition to changes and modifications of components and/or configurations, alternative uses will also be obvious to those familiar with the technology.

100‧‧‧Electronic system 120‧‧‧System on a chip (SOC) 122, 510‧‧‧Processor 124‧‧‧Power management unit (PMU) 126‧‧‧Memory controller 128‧‧‧Video controller 140 ‧‧‧Clock device 150‧‧‧System memory 160, 525‧‧‧Display 200‧‧‧Intellectual property (IP) 210‧‧‧Clock 220,230,240‧‧‧Logic block 300‧‧ ‧Controller 310, 530‧‧‧Memory 402,404,406,408,410,412,414,416,420‧‧‧Operation 500‧‧‧Electrical system 520‧‧‧Power supply 540‧‧‧Graphics Interface 550‧‧‧Chipset 560‧‧‧Cache memory 570‧‧‧Network interface 580, 590‧‧‧Wireless communication unit

The configuration and embodiments can be described in detail with reference to the following drawings, in which similar reference numerals refer to similar elements and among them: Figure 1 is a block diagram of an electronic system configured according to an example; Figure 2 is a diagram showing an electronic system according to an example embodiment Diagram of a clock pulse source and intellectual property (IP); FIG. 3 is a diagram of a clock pulse source and intellectual property (IP) according to an example embodiment; FIG. 4 is a diagram showing operations according to an example embodiment Flow chart; and Figure 5 shows an electronic system configured according to an example.

140‧‧‧Clock device

200‧‧‧Intellectual Property (IP)

210‧‧‧Clock

220, 230, 240‧‧‧Logic block

300‧‧‧Controller

310‧‧‧Memory

Claims (21)

An electronic device comprising: a clock device for providing a clock signal; a clock gate for receiving the clock signal, the clock gate for being selectively set in an active state or a stop And a controller for determining a specific frequency of the clock signal, and when the determined specific frequency is a first frequency, the controller is used for controlling the clock gate to be in the activated state, And when the determined specific frequency is different from a second frequency of the first frequency, the controller is used to control the clock gate to be in the disabled state. Such as the electronic device of claim 1, which further includes: a first logic block for receiving the clock signal when the clock gate is in the enabled state. Such as the electronic device of claim 2, wherein when the clock gate is in the disabled state, the clock signal will not be received at the first logic block. Such as the electronic device of claim 2, wherein the first logic block is used to perform a specific function in response to receiving the clock signal. Such as the electronic device of claim 1, wherein the controller is used to change the state of the clock based on a determined new frequency. Such as the electronic device of claim 1, which further includes a memory for storing information about enabling or disabling the clock based on a plurality of different frequencies. Such as the electronic equipment of claim 1, where the controller uses The amount of a bandwidth is determined, and the specific frequency is determined based at least in part on the determined amount of the bandwidth. An electronic device comprising: a first logic, at least a part of which is hardware, which is used to determine a specific frequency; and a second logic, at least a part of which is hardware, which is used as the determined specific frequency When it is a first frequency, control a clock gate to be in an active state, and to control the clock gate to stop when the determined specific frequency is different from a second frequency of the first frequency Use state. Such as the electronic device of claim 8, which includes: a first logic block for receiving a clock signal when the clock is in the enabled state. Such as the electronic device of claim 9, wherein when the clock is in the disabled state, the clock signal will not be received at the first logic block. For example, the electronic device of claim 9, wherein the first logic block is used to perform a specific function in response to receiving the clock signal. Such as the electronic device of claim 8, which includes a memory for storing information about enabling or disabling the clock based on a plurality of different frequencies. Such as the electronic device of claim 8, wherein the first logic is used to determine the amount of a bandwidth, and used to determine the specific frequency based at least in part on the determined amount of the bandwidth. Such as the electronic device of claim 8, wherein the first logic Used to determine a new frequency, and used to change the state of the clock gate based on the determined new frequency. A non-transitory machine-readable medium, which includes one or more instructions, when executed, the one or more instructions cause a controller to perform one or more operations to: determine a specific frequency of a clock signal ; When the determined specific frequency is a first frequency, control a clock gate to be in an active state; and when the determined specific frequency is different from the first frequency and a second frequency, control the clock The gate must be in a disabled state. For example, the machine-readable medium of claim 15, wherein a first logic block is used to receive the clock signal when the clock is in the enabled state. Such as the machine-readable medium of claim 16, wherein when the clock is in the disabled state, the clock signal will not be received at the first logic block. For example, the machine-readable medium of claim 16, wherein the first logic block is used to perform a specific function in response to receiving the clock signal. Such as the machine-readable medium of claim 15, wherein the one or more operations include determining the amount of a bandwidth, and determining the specific frequency based at least in part on the determined amount of the bandwidth. For example, the machine-readable medium of claim 15, wherein the one or more operations include determining a new frequency, and based on the determined The new frequency changes the state of the clock gate. An electronic device comprising: a clock device for providing a clock signal; a clock gate for receiving the clock signal, the clock gate for being selectively set in an active state or a stop And a controller for determining a specific frequency of the clock signal, for controlling the clock gate to be in the activated state or the deactivated state based on the determined specific frequency, wherein, The controller is used to determine the amount of a bandwidth, and used to determine the specific frequency based at least in part on the determined amount of the bandwidth.

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