TWI717953B - Storage controller, memory management method and storage device - Google Patents

Abstract

A memory management method, including: maintaining a plurality of segment logical to physical addresses mapping (SL2P) tables in a buffer memory of a storage controller, wherein each of the SL2Ps is configured to record a relationships between a plurality of logical addresses and a plurality of physical addresses; maintaining a segment mapping table list (SMT list) in the buffer memory, wherein the SMT list includes a plurality of entries respectively corresponding to the SL2P tables; in response to a first SL2P table among the SL2P tables is stored into a first system physical address of a rewriteable non-volatile memory module, recording the first system physical address into a first entry among the entries of the SMT list; and storing the SMT list into the rewriteable non-volatile memory module.

Description

Storage controller, memory management method and storage device

The invention relates to a storage controller, and more particularly to a storage controller, a memory management method and a storage device equipped with a rewritable non-volatile memory module.

Generally speaking, for a storage device configured with a rewritable non-volatile memory module, the storage controller of the storage device uses a logical to physical address mapping table maintained in the buffer memory to manage the The mapping relationship between multiple physical addresses (eg, physical page addresses) of the copy-type non-volatile memory module and multiple logical addresses (eg, logical page addresses) corresponding to the host system.

However, with the development of technology, the capacity of the rewritable non-volatile memory module is getting larger and larger (for example, the size of a single physical page and the total number of multiple physical pages both increase), and the maintenance is in the buffer memory The space occupied by the logical-to-physical address mapping table in the body has also become larger, which reduces the execution efficiency and maintenance efficiency of management operations related to the logical-to-physical address mapping table.

The present invention provides a storage controller, a memory management method, and a storage device, which can use a section mapping table list to effectively manage multiple section logic to entity address mapping tables, thereby improving multiple logic addresses and multiple entities The efficiency of the management operation of the mapping relationship between addresses.

An embodiment of the present invention provides a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module. The storage controller includes a connection interface circuit, a buffer memory, a memory interface control circuit, a mapping table management circuit unit, and a processor. The connection interface circuit is used for coupling to a host system. The memory interface control circuit is used for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and the plurality of Each physical block has multiple physical pages. The processor is coupled to the connection interface circuit, the buffer memory, the memory interface control circuit, and the mapping table management circuit unit. The processor is used to maintain a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the buffer memory, wherein each of the plurality of SL2P tables is used to record a plurality of logical bits Mapping relationship between multiple physical addresses and multiple physical addresses, wherein the multiple physical addresses correspond to a portion of the multiple physical pages, and the multiple logical addresses correspond to a portion of the configured Multiple logical pages for the host system. The mapping table management circuit unit is used to maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory, The SMT list includes multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system entity corresponding to the system block identification code The system physical address in the block, wherein the first SL2P table reflected in the plurality of SL2P tables is stored in the first system physical address in the rewritable non-volatile memory module, the The mapping table management circuit unit is further configured to record the first system physical address to the first entry corresponding to the first SL2P table among the multiple entries in the SMT list. The processor is further used for storing the SMT list in the rewritable non-volatile memory module.

An embodiment of the present invention provides a memory management method suitable for a storage controller for controlling a storage device equipped with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory The module has multiple physical blocks, and each of the multiple physical blocks has multiple physical pages. The method includes: maintaining a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the buffer memory of the storage controller, wherein each of the plurality of SL2P tables is used for recording The mapping relationship between multiple logical addresses and multiple physical addresses, wherein the multiple physical addresses correspond to a portion of the multiple physical pages, and the multiple logical addresses correspond to a portion Copies are configured to multiple logical pages of the host system; maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory, wherein the SMT list includes multiple entries, wherein The multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system entity address in the system entity block corresponding to the system block identification code; reverse The first SL2P table in the plurality of SL2P tables is stored in the first system physical address in the rewritable non-volatile memory module, and the first system physical address is recorded to the The multiple entries of the SMT list correspond to the first entry of the first SL2P table; and the SMT list is stored in the rewritable non-volatile memory module.

An embodiment of the present invention provides a storage device. The storage device includes a rewritable non-volatile memory module and a storage controller. The rewritable non-volatile memory module has multiple physical blocks, and each of the multiple physical blocks has multiple physical pages. The storage controller is coupled to the rewritable non-volatile memory module. The storage controller is used to maintain a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the buffer memory, wherein each of the plurality of SL2P tables is used to record a plurality of logic The mapping relationship between addresses and multiple physical addresses, wherein the multiple physical addresses correspond to a part of the multiple physical pages, and the multiple logical addresses correspond to a part of the A plurality of logical pages allocated to the host system, wherein the storage controller is further used to maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory, wherein the SMT list It includes multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system in the system entity block corresponding to the system block identification code Physical address. In addition, the first SL2P table reflected in the plurality of SL2P tables is stored to the first system physical address in the rewritable non-volatile memory module, and the storage controller further uses To record the physical address of the first system to the first entry of the first SL2P table among the multiple entries in the SMT list, wherein the storage controller is further used to store the SMT list to In the rewritable non-volatile memory module.

In summary, the storage controller, the memory management method, and the storage device provided by the embodiments of the present invention can use the section mapping table list to generate corresponding mapping table load command queues to effectively manage multiple The section logic is converted to the physical address mapping table, thereby improving the efficiency of the management operation of the mapping relationship between multiple logical addresses and multiple physical addresses.

10: Host system

20: storage device

110, 211: processor

120: host memory

130: data transmission interface circuit

210: storage controller

212: Data Transmission Management Circuit

213: Memory interface control circuit

220: rewritable non-volatile memory module

230: connection interface circuit

215: Mapping table management circuit unit

2151: Mapping table list management circuit

2152: Mapping table loading management circuit

S210, S220, S230, S240: Process steps of the memory management method

SB(1), B1~B5: system physical block

PL1, PL2: plane

SMT1, SMT2, SMT3: Section mapping table list

SL2P(1)~SL2P(11): Segment logical to physical address mapping table

300, 310: logical to physical address mapping table

LCQ1~LCQ3: Mapping table load command queue

PG1~PG3, Page(1.1)~Page(M.P): System entity page/Entity page

SPA(1)~SPA(N): physical address

LA(0)~LA(2047): logical address

A31, A32, A41, A61, A71, A72, A81~A88, A91~A97, A1201: Arrow

BMP_B3, BMP_B4, BMP_B3’, BMP_B4’: mapping table bit map

BMP_B3.1, BMP_B3.1’, BMP_B3.2, BMP_B3.2’, BMP_B4.1, BMP_B4.1’, BMP_B4.2, BMP_B4.2’: sub-matrix

S1010, S1020: Process steps for loading the section logic to entity mapping table

S1110, S1120, S1130, S1140: Process steps for loading the section logic to entity mapping table

MRI1: Mapping table records information

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention.

Fig. 2 is a flowchart of a memory management method according to an embodiment of the invention.

FIG. 3A is a schematic diagram of the structure of a system physical block according to an embodiment of the invention.

FIG. 3B is a schematic diagram illustrating a mapping table from logical to physical address of a storage section to a system physical block according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a conventional mapping table for loading a logical to physical address of multiple sectors.

FIG. 5A is a diagram according to a section mapping table according to an embodiment of the present invention; Single to generate a schematic diagram of the mapping table load command queue.

5B is a schematic diagram of generating a mapping table load command queue according to a section mapping table list according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a conventional mapping table for loading a logical to physical address of multiple sectors.

FIG. 7 is a schematic diagram of generating a mapping table bitmap according to a section mapping table list according to an embodiment of the present invention.

FIG. 8A is a schematic diagram of an adjustment mapping table bitmap according to an embodiment of the invention.

FIG. 8B is a schematic diagram of generating a mapping table load instruction queue according to an adjusted mapping table bitmap according to an embodiment of the present invention.

FIG. 9A is a schematic diagram illustrating an adjustment mapping table bitmap according to another embodiment of the present invention.

9B is a schematic diagram of generating a mapping table load instruction queue according to an adjusted mapping table bitmap according to another embodiment of the present invention.

FIG. 10 is a flowchart of loading a segment logic to entity mapping table according to an embodiment of the present invention.

FIG. 11 is a flowchart of loading a section logic to entity mapping table according to another embodiment of the present invention.

FIG. 12 is a schematic diagram of information recorded in a mapping table according to an embodiment of the present invention.

In this embodiment, the storage device includes a rewritable non-volatile memory module and a storage device controller (also referred to as a storage controller or a storage control circuit). In addition, the storage device is used with the host system so that the host system can write data to the storage device or read data from the storage device.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention. 1, the host system (Host System) 10 includes a processor (Processor) 110, a host memory (Host Memory) 120, and a data transfer interface circuit (Data Transfer Interface Circuit) 130. In this embodiment, the data transmission interface circuit 130 is coupled (also referred to as electrically connected) to the processor 110 and the host memory 120. In another embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 are coupled to each other by a system bus.

The storage device 20 includes a storage controller (Storage Controller) 210, a rewritable non-volatile memory module (Rewritable Non-Volatile Memory Module) 220 and a connection interface circuit (Connection Interface Circuit) 230. The storage controller 210 includes a processor 211, a data management circuit (Data Management Circuit) 212, and a memory interface control circuit (Memory Interface Control Circuit) 213.

In this embodiment, the host system 10 is coupled to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can use the data transmission interface circuit 130 Store data to the storage device 20 or read data from the storage device 20.

In this embodiment, the processor 110, the host memory 120, and the data transmission interface circuit 130 may be disposed on the main board of the host system 10. The number of the data transmission interface circuit 130 may be one or more. Through the data transmission interface circuit 130, the motherboard can be coupled to the storage device 20 in a wired or wireless manner. The storage device 20 may be, for example, a flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy memory storage device Devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be coupled to various I/O devices such as Global Positioning System (GPS) modules, network interface cards, wireless transmission devices, keyboards, screens, speakers, etc. through the system bus.

In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use a non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol for data transmission.

However, it must be understood that the present invention is not limited to this, and the data transmission interface circuit 130 and the connection interface circuit 230 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, electrical and electronic engineers Association (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, serial advanced attachment (Serial Advanced Technology Attachment, SATA) standard, universal serial bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I, UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, Multi-Chip Package interface Standard, Multi Media Card (MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, integrated drive electronic interface (Integrated Device) Electronics, IDE) standards or other suitable standards. In addition, in another embodiment, the connection interface circuit 230 and the storage controller 210 may be packaged in a chip, or the connection interface circuit 230 may be arranged outside a chip including the storage controller 210.

In this embodiment, the host memory 120 is used to temporarily store commands or data executed by the processor 110. For example, in this exemplary embodiment, the host memory 120 may be a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), etc. However, it must be understood that the present invention is not limited to this, and the host memory 120 may also be other suitable memory.

The storage controller 210 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type and to write data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10 , Read and erase operations.

In more detail, the processor 211 in the storage controller 210 is capable of operating Computing power hardware, which is used to control the overall operation of the storage controller 210. Specifically, the processor 211 has a plurality of control commands, and when the storage device 20 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data.

It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor (micro-processor), or other programmable processing units. (Microprocessor), Digital Signal Processor (DSP), Programmable Controller, Application Specific Integrated Circuits (ASIC), Programmable Logic Device (PLD) or other Similar to circuit elements, the present invention is not limited to this.

In one embodiment, the storage controller 210 also has a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the storage controller 210 is enabled, the processor 211 will first execute the boot code to store it in the rewritable non-volatile memory module The control command in 220 is loaded into the random access memory of the storage controller 210. After that, the processor 211 runs these control commands to perform data writing, reading, and erasing operations. In another embodiment, the control commands of the processor 211 may also be stored in a specific area of the rewritable non-volatile memory module 220 in the form of program codes, for example, a dedicated area of the rewritable non-volatile memory module 220 In the physical storage unit storing system data.

In this embodiment, as described above, the storage controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that storage control The operations performed by the components of the controller 210 can also be regarded as operations performed by the storage controller 210.

The data management circuit 212 is coupled to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used for receiving instructions from the processor 211 to transmit data. For example, read data from the host system 10 (eg, the host memory 120) via the connection interface circuit 230, and write the read data to the rewritable non-volatile memory module via the memory interface control circuit 213 220 (for example, the write operation is performed according to the write command from the host system 10). For another example, data can be read from one or more physical units of the rewritable non-volatile memory module 220 through the memory interface control circuit 213 (data can be read from one or more of the one or more physical units). Memory cells), and write the read data to the host system 10 (for example, the host memory 120) via the connection interface circuit 230 (for example, perform a read operation according to a read command from the host system 10) . In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

The memory interface control circuit 213 is used to receive instructions from the processor 211, and cooperate with the data management circuit 212 to perform writing (also known as programming) operations and reading to the rewritable non-volatile memory module 220 Operate or erase operation.

For example, the processor 211 can execute a write instruction sequence to instruct the memory interface control circuit 213 to write data into the rewritable non-volatile memory module 220; the processor 211 can execute a read instruction sequence, To instruct the memory interface control circuit 213 to read the corresponding read instructions from the rewritable non-volatile memory module 220 Order to read data from one or more physical units (also known as target physical units); the processor 211 can execute an erase instruction sequence to instruct the memory interface control circuit 213 to perform an operation on the rewritable non-volatile memory module 220 performs an erasing operation. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct to perform corresponding writing, writing, and writing to the rewritable non-volatile memory module 220. Read and erase operations. In one embodiment, the processor 211 may also send other types of instruction sequences to the memory interface control circuit 213 to perform corresponding operations on the rewritable non-volatile memory module 220.

In addition, the data to be written into the rewritable non-volatile memory module 220 is converted into a format acceptable by the rewritable non-volatile memory module 220 through the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to execute the corresponding operating. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing presets). It is assumed that a plurality of preset read voltage values of the read voltage group are used to perform a read operation, or execute a garbage collection program, etc.). These command sequences can include one or more signals, or data on the bus. These signals or data may include script or program code. For example, in the read command sequence, information such as the read identification code and memory address will be included.

The rewritable non-volatile memory module 220 is coupled to the storage controller 210 (memory interface control circuit 213) and used to store data written by the host system 10. The rewritable non-volatile memory module 220 can be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), Three-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quadruple Level Cell (QLC) NAND flash memory modules Flash memory module (ie, a flash memory module that can store 4 bits in a memory cell), 3D NAND flash memory module, or vertical NAND flash memory Other flash memory modules such as Vertical NAND flash memory module or other memory modules with the same characteristics. The memory cells in the rewritable non-volatile memory module 220 are arranged in an array.

In this embodiment, the rewritable non-volatile memory module 220 has a plurality of character lines, and each of the plurality of character lines is coupled to a plurality of memory cells. Multiple memory cells on the same character line form one or more physical programming units. In addition, multiple physical programming units can form a physical unit (physical block or physical erase unit).

In this embodiment, the memory cell is used as the smallest unit for writing (programming) data. The physical unit is the smallest unit of erasure, that is, each physical unit contains one of the smallest number of memory cells that are erased.

Each physical unit will have multiple physical sub-units. The physical subunit can be a physical page (page) or a physical sector (sector). In this embodiment, the physical subunit includes a data bit area and a redundancy bit area. The data bit area is used to store user data, and the redundant bit area is used to store system data. The system data is, for example, error correction code, error check code, or metadata (Meta Data).

It should be noted that, in this embodiment, the system data used to record the information of a physical unit can be recorded by one or more physical subunits in the physical unit, or can be recorded in a system area for recording all One or more physical sub-units of a specific physical unit (also known as a system physical block) of the system data are recorded. In this embodiment, the system data corresponding to a physical unit includes information such as a program erase cycle (PEC) of the physical unit, a block identification code, and a block physical to logic mapping table.

FIG. 3A is a schematic diagram of the structure of a system physical block according to an embodiment of the invention. Please refer to FIG. 3A. In this embodiment, a system physical block (eg, the first system physical block SB(1)) may have multiple planes (eg, Plane(1)~Plane(M)). Multiple physical pages (also known as system physical pages), such as system physical pages Page(1.1), (1.2)~(1.P) belonging to Plane(1); system entities belonging to Plane(M) Page (M.1), (M.2)~(MP). M represents the total number of planes of a system physical block, which is a positive integer greater than 1, and P represents the total number of system physical pages of each plane, which is a positive integer. In addition, each system physical page is used to store multiple code words, and each code word corresponds to a system physical address. For example, the system physical page Page (1.1) can store N codes in sequence Each of the N codewords is stored in multiple system entity addresses SPA(1)~SPA(N) of the system entity page Page(1.1). N is a preset positive integer. It should be noted that the present invention is not limited to the above-mentioned specific values of N, P, and M, and manufacturers or those skilled in the art can preset N, P, and M according to requirements or the hardware specifications of the rewritable non-volatile memory module 220. The specific values of P and M.

In the following embodiments, a physical block is used as an example of a physical unit. However, in another embodiment, a physical unit can also refer to any number of memory cells, depending on practical requirements. In addition, it must be understood that when the storage controller 211 groups the memory cells (or physical units) in the rewritable non-volatile memory module 220 to perform corresponding management operations, these memory cells (or physical units) Units) are logically grouped, and their actual locations have not changed.

The storage controller 210 allocates a plurality of logic units to the rewritable non-volatile memory module 220. The host system 10 accesses user data stored in multiple physical units through a plurality of configured logical units (the configured multiple logical units correspond to the host system 10). Here, each logical unit can be composed of one or more logical addresses. For example, the logical unit may be a logical block (Logical Block), a logical page (Logical Page) or a logical sector (Logical Sector). A logical unit can be mapped to one or more physical units, where the physical unit can be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasures unit. In this embodiment, the logical unit is a logical block, and the logical sub-unit is a logical page. Each logic unit has multiple logic sub-units.

In addition, the storage controller 210 creates a logical to physical address mapping table (Logical To Physical address mapping table) and a physical to logical address mapping table (Physical To Logical address mapping table) to record the configuration to the rewritable non-volatile The address mapping relationship between logical units (eg, logical blocks, logical pages, or logical sectors) of the memory module 220 and physical units (eg, physical erase units, physical programming units, and physical sectors). In other words, the storage controller 210 can use the logical-to-physical address mapping table to find the physical unit to which a logical unit is mapped, and the storage controller 210 can use the physical-to-logical address mapping table to find the physical unit to which a physical unit is mapped. Logical unit. For example, the host system 10 may be configured with multiple logical pages, and the multiple logical pages may be mapped to multiple physical pages.

FIG. 3B is a schematic diagram illustrating a mapping table from logical to physical address of a storage section to a system physical block according to an embodiment of the present invention. Referring to FIG. 3B, in this embodiment, the processor 211 further divides the logical-to-physical address mapping table 300 into a plurality of section logical-to-physical address mapping tables (as shown in FIG. 3B). Physical address mapping table SL2P(1), SL2P(2)...). The present invention is not limited to the total number of logical-to-physical address mapping tables divided from one logical-to-physical address mapping table. In addition, the total number of multiple logical addresses and corresponding multiple physical addresses recorded in the logical-to-physical address mapping table of each section can also be preset, and the present invention is not limited to this. For example, in this embodiment, a sector logic-to-physical address mapping table (eg, sector logic-to-physical address mapping table SL2P(1)) is used to record 1024 logical addresses (eg, logical address LA (0)~(1023)) are mapped to 1024 physical addresses (for example, physical addresses "PA(XXXX)"~"PA(XYXX)"). Of course However, in other embodiments, the total number of logical addresses and physical addresses recorded in the logical-to-physical address mapping table of each sector may be greater than or less than 1024.

In addition, in this embodiment, when the physical address mapped by a logical address is changed, the processor 211 can correspondingly update the logical conversion entity of the section to which the logical address belongs and maintained in the buffer memory 216 The information/entry corresponding to the physical address of the logical address recorded in the address mapping table. In another embodiment, in response to a segment logical-to-physical address mapping table is updated, the processor 211 further changes the value of an update flag corresponding to the segment logical-to-physical address mapping table from the first The value (for example, "0") is adjusted to the second value (for example, "1"). In this way, the processor 211 can identify one or more segment logical to physical address mapping tables that have been updated in the buffer memory 216 according to the update flag. In this way, under certain conditions (for example, when performing a normal shutdown operation, or determining that the storage device has been idle for a predetermined period of time), the processor 211 can identify one or more sections that have been updated through the update flag Logical-to-physical address mapping table, and only one or more segments of the updated logical-to-physical address mapping table stored in the buffer memory 216 to the rewritable non-volatile memory module 220 The system physical block (as shown by arrow A31) to back up the one or more sector logic to physical address mapping tables that have been updated to avoid backing up other sector logic that has not been updated. The time/space cost caused by the conversion of the physical address mapping table.

In this embodiment, the error checking and correcting circuit 214 is coupled to the processor 211 and used to perform error checking and correcting procedures to ensure the correctness of the data. Specifically, when the processor 211 receives a write command from the host system 10, the error The error checking and correction circuit 214 will generate corresponding error correcting code (ECC) and/or error detecting code (EDC) for the data corresponding to the write command, and the processor 211 will correspond to this The data of the write command and the corresponding error correction code and/or error check code are written into the rewritable non-volatile memory module 220. After that, when the processor 211 reads data from the rewritable non-volatile memory module 220, it will also read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 214 will follow This error correction code and/or error check code performs error checking and correction procedures on the read data.

In an embodiment, the storage controller 210 further includes a buffer memory 216 and a power management circuit 217. The buffer memory 216 is, for example, a static random access memory, a dynamic random access memory, or other suitable high-speed memory. The buffer memory 216 is coupled to the processor 211 and used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other storage devices 20 System data (such as multiple section logic to physical address mapping table, block entity to logical address mapping table, section mapping table list, mapping table bitmap, mapping table load command queue, etc.) to allow The processor 211 can quickly access the data, instructions or system data from the buffer memory 216. The power management circuit 217 is coupled to the processor 211 and used to control the power of the storage device 20.

In this embodiment, the mapping table management circuit unit 215 includes a mapping table management circuit unit 2151 and a mapping table loading management circuit 2152. The mapping table management circuit unit 215 is used to manage the data corresponding to the logical-to-physical address mapping table (or multiple sector logical-to-physical address mapping tables) of the rewritable non-volatile memory module 220 News. The operations of the components of the mapping table management circuit unit 215 may also represent the operations of the mapping table management circuit unit 215. The function of the mapping table management circuit unit 215 and the corresponding memory management method provided in this embodiment are described below using FIG. 2.

Fig. 2 is a flowchart of a memory management method according to an embodiment of the invention. Please refer to FIG. 2, in step S210, the processor 211 is configured to maintain a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the buffer memory 216, wherein the plurality of SL2P Each table is used to record the mapping relationship between multiple logical addresses and multiple physical addresses, where the multiple physical addresses correspond to a part of the multiple physical pages of the rewritable non-volatile memory module , And the multiple logical addresses correspond to a part of multiple logical pages configured to the host system (for example, as shown in FIG. 3B).

Next, the mapping table management circuit unit 215 (or the mapping table list management circuit 2151) is used to maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory 216, wherein the SMT list includes Multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system entity in the system entity block corresponding to the system block identification code Address.

Specifically, in this embodiment. Whenever the processor 211 writes an SL2P table to a system physical address of a system physical block in the rewritable non-volatile memory module 220, the mapping table management circuit unit 215 records the corresponding system The information of the physical block (such as the system block ID) and the corresponding The information of the system physical address is sent to the SMT list 300. For example, in step S230, the plurality of first SL2P tables reflected in the plurality of SL2P tables are stored to the plurality of first system physical addresses in the rewritable non-volatile memory module, and map The table management circuit unit 215 (or the mapping table list management circuit 2151) records the plurality of first system physical addresses to the plurality of entries of the plurality of first SL2P tables in the SMT list. One entry

Please refer to FIG. 3B. For example, as shown by arrow A31, suppose the processor writes the segment logic to the physical address mapping table SL2P(1) to the system physical page Page(1.1) of the system physical block SB(1) The system entity address in SPA(1). As indicated by arrow A42, the logical to physical address mapping table SL2P(1) is written to the system physical address SPA(1) in the system physical page Page(1.1) of the system physical block SB(1) Afterwards, the mapping table management circuit unit 215 can identify the information related to the system physical address SPA(1), such as "system block(1), plane(1), page(1.1), SPA(1)" or "B1, PL1, PG1, CD1", each content of the information respectively represents: System Block ID, Plane ID, Page ID and Code Codeword ID. The mapping table management circuit unit 215 (or the processor 211) can locate the storage location of the segment logical-to-physical address mapping table SL2P(1) according to the system entity block identification code in the information. The information is recorded in the SMT list through the mapping table management circuit unit 215 (or the processor 211) to the entry corresponding to the segment logical to physical address mapping table SL2P(1). It should be noted that the present invention is not limited to the specific format/aspect of information related to the physical address of the system used to store the SL2P table.

Then, in step S240, the processor 211 stores the SMT list in the rewritable non-volatile memory module 220. Specifically, under some specific conditions (such as performing a normal shutdown operation, or determining that the storage device has been idle for a predetermined period of time), the processor 211 may store the SMT list in the rewritable non-volatile memory model In the preset specific system physical address/system physical block of the group 220 (after all the segment logical to physical mapping tables have been backed up to the rewritable non-volatile memory module 220). In addition, in another embodiment, when an abnormal power-off event occurs in the storage device 20, the processor 211 can also forcefully store the SMT list in the buffer memory 216 to the rewritable non-volatile memory module 220 in the specific system entity address/system entity block. In this way, when the storage device 20 is turned on or the storage device 20 performs an abnormal power-off recovery operation, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can obtain the specific system physical address/ Read the latest SMT list stored in the system entity block. Then, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) may generate a mapping table load command queue according to the SMT list, so as to execute the generated mapping table load command queue in sequence. Load a plurality of mapping table instructions in the row to load a plurality of SL2P tables to the buffer memory 216 (read the plurality of SL2P tables from the rewritable non-volatile memory module 220 to the buffer memory 216 ). The loaded SL2P tables can be combined into a complete logical to physical address mapping table corresponding to the rewritable non-volatile memory module 220.

FIG. 4 is a schematic diagram of a conventional mapping table for loading a logical to physical address of multiple sectors. Please refer to Figure 4, assuming that the logical to physical address mapping table is divided into multiple sections The logical to physical address mapping table SL2P(1)~SL2P(6), the effective multiple SL2P tables stored in the system physical blocks B1 and B2 (the logical conversion of the section shown in the gray block in Figure 4) Physical address mapping table SL2P(1)~SL2P(6)), and multiple entries in the section mapping table list SMT1 are also recorded to store the logical to physical address mapping table SL2P(1)~SL2P(6 ) System physical address information. It should be noted that the order of the multiple entries in the section mapping table list SMT1 is set as the arrangement of the section logical-to-physical address mapping table SL2P(1)~SL2P(6) in the corresponding logical-to-physical address mapping table order. For example, the first entry of the section mapping table list SMT1 corresponds to the first section logical-to-physical address mapping table SL2P(1) of the logical-to-physical address mapping table. For another example, the last entry of the section mapping table list SMT1 corresponds to the last section logic-to-physical address mapping table SL2P(6) of the logical-to-physical address mapping table.

Generally speaking, as indicated by arrow A41, the traditional method is that the processor 211 converts the physical address of the respective system into the physical address mapping table SL2P(1)~SL2P(6) according to the logical segment recorded in each entry, and directly Generate multiple corresponding single-plane mapping table load instructions (read each SL2P table via a single-plane read method). Then, the processor 211 sequentially executes the generated multiple single-plane mapping table load instructions to read the corresponding segment logical-to-physical address mapping table SL2P(1) from the system physical blocks B1 and B2. ~SL2P(6) to the buffer memory 216. In addition, the multiple segment logical-to-physical address mapping tables SL2P(1)-SL2P(6) can be combined into a whole logical-to-physical address mapping table 310.

However, in the example of FIG. 4, since the multiple single-plane mapping table load instructions generated are read through a single-plane instead of using a multi-plane read To read a corresponding SL2P table, the overall efficiency of loading the segment logical to physical address mapping table SL2P(1)~SL2P(6) to the buffer memory 216 is not high.

Based on this, in an embodiment of the present invention, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can correspondingly generate a single-plane mapping table load based on multiple entries recorded in the SMT list. Input command (Single plane mapping table loading command, SPLC) or multiple planes mapping table loading command (MPLC). The single-plane mapping table load instruction is used to instruct to read a stored SL2P table from the corresponding system physical address via a single-plane reading method. The multi-plane mapping table load instruction is used to instruct the read method via multi-plane to read the stored multiple SL2P tables from corresponding multiple system physical addresses respectively belonging to M planes. M is a positive integer greater than 1, used to represent the total number of multiple planes of the system physical block. In this way, the corresponding multiple SL2P tables can be loaded more efficiently by executing the generated multi-plane mapping table load instruction. The following uses a plurality of drawings for description.

5A is a schematic diagram of generating a mapping table load command queue according to a section mapping table list according to an embodiment of the present invention. Referring to FIG. 5A, it is assumed that each system physical block has 2 planes (M=2), and each system physical page can store 2 SL2P tables (N=2). In addition, assuming that the logical-to-physical address mapping table is divided into multiple sections, the logical-to-physical address mapping table SL2P(1)~SL2P(6), the effective multiple SL2Ps stored in the system entity blocks B1 and B2 Table is shown in the gray block in Figure 5A. The logical to physical address mapping table SL2P(1)~SL2P(6), and the effective multiple SL2P tables stored in the system physical blocks B1 and B2 ( As shown in Figure 5A The section logic shown in the color block is converted to the physical address mapping table SL2P(1)~SL2P(6)), and the mapping table management circuit unit 215 (or the mapping table list management circuit 2151) is also based on the stored section logic The entity address mapping tables SL2P(1)~SL2P(6) produce the section mapping table list SMT1 in FIG. 5A. In addition, the segment mapping table list SMT1 is stored in a specific system physical address of a predetermined specific system physical block in the rewritable non-volatile memory module 220.

In this example, in response to the storage device 20 being turned on or the processor 211 performing an abnormal power-off recovery operation, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) obtains data from the specific system entity block The section mapping table list SMT1 is read from the specific system physical address, and the mapping table management circuit unit 215 (or mapping table load management circuit 2152) generates all the data according to the section mapping table list SMT1 The mapping table loading command queue (Mapping table loading command queue) LCQ1.

Specifically, in this embodiment, in the operation of generating the mapping table load instruction queue according to the SMT list, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) identifies the area The plane to which the plurality of system entity addresses of the plurality of entries of the segment mapping table list SMT1 belong is one of M planes. For example, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) recognizes the storage based on the multiple entries corresponding to the segment logical-to-physical address mapping tables SL2P(1)~SL2P(6) respectively. The segment logic-to-physical address mapping table in the rewritable non-volatile memory module 220 SL2P(1), SL2P(2), SL2P(3), SL2P(4), SL2P(5), SL2P( 6) Respectively belong to the system The plane PL1 of the volume block B1, the plane PL1 of the system entity block B2, the plane PL1 of the system entity block B1, the plane PL2 of the system entity block B1, the plane PL2 of the system entity block B1, the plane PL2 of the system entity block B1 The plane PL1 and the plane PL1 of the system physical block B1.

Next, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) determines whether there are one or more second target entries adjacent to the first target entry according to the arrangement order of the multiple entries. The first system physical address corresponding to the first target entry and the one or more second system physical addresses corresponding to the one or more second target entries belong to M planes of a system physical block. Physical pages.

In response to determining that there is no one or more second target entries adjacent to the first target entry, the mapping table management circuit unit records the physical address of the first system to a single-plane mapping table. Instruction

For example, assuming that the first target entry is an entry corresponding to SL2P(1) in the section mapping table list SMT1, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) determines that it is adjacent to the entry corresponding to SL2P(1) The system entity address recorded in the entry corresponding to SL2P(2) (e.g., "B2, PL1, PG1, CD1") and the first system entity address recorded in the entry corresponding to SL2P(1) (e.g., "B1 ,PL1,PG1,CD1”) are not two planes belonging to the same system entity block, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) determines that the entry corresponding to SL2P(2) is not the second target entry , And directly record the first system entity address (such as "B1, PL1, PG1, CD1") recorded in the entry corresponding to SL2P(1) to the mapping table load instruction queue A single-plane mapping table load instruction in LCQ1 (for example, a single-plane mapping table load instruction SPLC: "B1, PL1, PG1, CD1").

In response to determining that the one or more second target entries are adjacent to the first target entry, the mapping table management circuit unit records the first system entity address and the one or more second target entries The system entity addresses to one of the multi-plane mapping table load instructions.

For example, assuming that the first target entry is an entry corresponding to SL2P(3) in the section mapping table list SMT1, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) determines that it is adjacent to the entry corresponding to SL2P(3) The system entity address recorded in the entry corresponding to SL2P(4) (e.g., "B1, PL2, PG1, CD2") and the first system entity address recorded in the entry corresponding to SL2P(3) (e.g., "B1 ,PL1,PG1,CD2”) belong to two planes of the same system entity block, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) determines that the entry corresponding to SL2P(4) corresponds to the first target The second target entry of the entry, and it is determined that the system entity address recorded in the entry corresponding to SL2P(4) is the second system entity address. In addition, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) further records the first system physical address (e.g., "B1, PL1, PG1, CD2") and the second system physical address (e.g., " B1,PL1,PG1,CD2") to a multi-plane mapping table load instruction in the mapping table load instruction queue LCQ1 (e.g., multi-plane mapping table load instruction MPLC: "B1,PL1,PG1,CD2", "B1, PL2, PG1, CD2"). It should be noted that since the system entity address recorded in the entry corresponding to SL2P(5) and the second system entity address do not belong to the same system entity page, the system entity address recorded in the entry corresponding to SL2P(5) is Physical address of the second system It cannot be read together by the multi-plane read operation, and the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) determines that the entry corresponding to SL2P(5) is not the second target entry corresponding to the first target entry.

By analogy, in the example of FIG. 5A, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) finally generates the mapping table load command queue LCQ1 according to the section mapping table list SMT1.

On the other hand, in another embodiment, in the operation of generating the mapping table load instruction queue according to the SMT list, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) may Directly select multiple SL2P tables stored in the same system entity block on different system entity pages belonging to different planes to generate a multi-plane mapping table load instruction.

In detail, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes that the planes to which the multiple system entity addresses of the multiple entries of the SMT list belong are M planes. One of them. The mapping table management circuit unit 215 (or the mapping table load management circuit 2152) selects multiple groups of M multi-plane system physical addresses from the multiple system physical addresses, wherein all the selected groups of each group The M multi-plane system physical addresses belong to different M planes, and the M multi-plane system physical addresses of the selected groups are recorded in one of the multi-plane mapping tables. Input command, where M is a positive integer greater than 1. Then, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) records the remaining system physical addresses that have not been selected among the plurality of system physical addresses to one of the single planes. Mapping table load instruction. This will be explained below using FIG. 5B.

5B is a schematic diagram of generating a mapping table load command queue according to a section mapping table list according to another embodiment of the present invention. Referring to FIG. 5B, it is assumed that each system physical block has 2 planes (M=2), and each system physical page can store 2 SL2P tables (N=2). In addition, assuming that the logical-to-physical address mapping table is divided into multiple sections, the logical-to-physical address mapping table SL2P(1)~SL2P(6), the effective multiple SL2Ps stored in the system entity blocks B1 and B2 Table 5B shows the section logical to physical address mapping table SL2P(1)~SL2P(6) as shown in the gray block in Fig. 5B, and the effective multiple SL2P tables stored in the system physical blocks B1 and B2 ( The section logic-to-physical address mapping table SL2P(1)~SL2P(6) as shown in the gray block in FIG. 5B, and the mapping table management circuit unit 215 (or the mapping table list management circuit 2151) is also based on all The stored segment logical to physical address mapping tables SL2P(1)~SL2P(6) generate the segment mapping table list SMT1 in FIG. 5B. In addition, the segment mapping table list SMT1 is stored in a specific system physical address of a predetermined specific system physical block in the rewritable non-volatile memory module 220.

In this example, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can scan the section mapping table list SMT1 to find two system entities that belong to two planes in the same system block. Multiple SL2P tables on the page to record the multiple SL2P tables found to a multi-plane mapping table load instruction. For example, according to the section mapping table list SMT1 in FIG. 5B, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) determines that the corresponding section logical to physical address mapping table SL2P(1) entry records System physical address "B1, PL1, PG1, CD1", the system physical address recorded by the entry of the corresponding section logical to physical address mapping table SL2P(3) and the corresponding section logical to physical address mapping table SL2P( The system entity addresses "B1, PL2, PG1, CD2" recorded in the entry of 3) are multiple system entity addresses on two system entity pages belonging to two planes in the same system entity block, and The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) can assign the multiple system entity addresses "B1, PL1, PG1, CD1", "B1, PL1, PG1, CD2" as shown by the arrow in FIG. 5B "And "B1, PL2, PG1, CD2" are recorded together in a multi-plane mapping table load instruction in the mapping table load instruction queue LCQ2 (ie, multi-plane mapping table load instruction "MPLC: "B1, PL1 ,PG1,CD1-2","B1,PL2,PG1,CD2""). Among them, the multi-plane mapping table load instruction "MPLC: "B1, PL1, PG1, CD1-2", "B1, PL2, PG1, CD2"" is used to instruct to read from the system physical area through the multi-plane read operation The block B1 simultaneously reads the first and second codewords of the system physical page PG1 on the plane PL1 and the second codeword of the system physical page PG1 on the plane PL2.

By analogy, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can further map the multiple system physical addresses "B1, PL2, PG3, CD1" (corresponding to the sector logic to physical address mapping Table SL2P (5) entry) and "B1, PL1, PG2, CD2" (corresponding to the segment logical to entity address mapping table SL2P (6) entry) are recorded together in one of the mapping table load instruction queue LCQ2 In the multi-plane mapping table load command (ie, the multi-plane mapping table load command "MPLC: "B1, PL2, PG3, CD1", "B1, PL1, PG2, CD2"").

It should be noted that when generating the multi-plane mapping table load instruction "MPLC:" B1, PL1,PG1,CD1-2","B1,PL2,PG1,CD2"" and multi-plane mapping table loading instructions "MPLC: "B1,PL2,PG3,CD1","B1,PL1,PG2,CD2"" After that, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) recognizes the remaining entries in the corresponding section logical to physical address mapping table SL2P(2), and converts the section logic to physical address mapping table The system physical address "B2, PL1, PG1, CD1" recorded in the entry of SL2P(2) is recorded in the single-plane mapping table load command in the mapping table load command queue LCQ2 (ie, multi-plane mapping table load Command "SPLC: "B2,PL1,PG1,CD1"".

It is worth mentioning that, compared with the multiple mapping table load instructions in FIG. 4, the memory management method of the present invention described in FIGS. 5A and 5B can effectively reduce the total number of mapping table load instructions. And can apply multi-plane read operation to accelerate the loading speed of SL2P table.

In one embodiment, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) may further generate a mapping table load instruction queue corresponding to the plurality of system physical blocks through a plurality of mapping table bitmaps .

Specifically, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can generate a plurality of mapping table bitmaps according to the SMT list, wherein the plurality of mapping table bitmaps respectively correspond to multiple systems Physical block. Wherein, a mapping table bit map corresponding to a system physical block records multiple bit values corresponding to multiple system physical addresses of the one system physical block, wherein respective values of the multiple bit values Including 0 or 1, where the bit value of 0 is used to indicate that the corresponding system physical address stores invalid SL2P tables or invalid data, and is 1 The bit value is used to indicate that the corresponding system physical address stores a valid SL2P table.

In addition, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) may further generate a mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps, wherein The mapping table load instruction queues each have a plurality of mapping table load instructions, wherein each of the plurality of mapping table load instructions includes a single-plane mapping table load instruction and a multi-plane mapping table load instruction, wherein when the When the storage device is turned on, the mapping table management circuit unit executes the mapping table load command queue to load the plurality of SL2P tables from the rewritable non-volatile memory module to the buffer memory Body. The following uses Figures 6-9B to illustrate.

FIG. 6 is a schematic diagram of a conventional mapping table for loading a logical to physical address of multiple sectors. Please refer to FIG. 6, assuming that the logical-to-physical address mapping table is divided into a plurality of section logical-to-physical address mapping tables SL2P(1)~SL2P(11), and the plurality of sections are mapped Tables SL2P(1)~SL2P(11) are stored in the system physical blocks B3 and B4 (the effective segment logic to physical address mapping table SL2P(1)~SL2P shown in the gray block in Figure 6) (11)), and multiple entries in the section mapping table SMT2 also record the information used to store the system physical addresses of the section logical to physical address mapping tables SL2P(1)~SL2P(11).

Generally speaking, as indicated by the arrow A61, the traditional method is that the processor 211 converts the physical address of each system into the physical address mapping table SL2P(1)~SL2P(11) directly according to the segment logic recorded in each entry. Generate multiple corresponding single-plane mapping table load instructions (read each SL2P through the single-plane read method table). The processor 211 may sequentially execute the generated multiple single-plane mapping table load instructions to read the corresponding segment logic-to-physical address mapping table SL2P(1) from the system physical blocks B3 and B4. SL2P(11) to the buffer memory 216.

In this embodiment, in response to the storage device 20 being turned on or the processor 211 performing an abnormal power-off recovery operation, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) from the specific system entity area The section mapping table list SMT2 is read from the specific system physical address of the block, and the mapping table management circuit unit 215 (or mapping table load management circuit 2152) generates according to the section mapping table list SMT2 The corresponding multiple mapping table bitmaps. In another embodiment, in response to the shutdown of the storage device 20, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) generates a plurality of corresponding sections according to the section mapping table list SMT2 in the buffer memory 216 A plurality of mapping table bitmaps of the system entity block, and the plurality of mapping table bitmaps are respectively stored in the corresponding system entity block.

FIG. 7 is a schematic diagram of generating a mapping table bitmap according to a section mapping table list according to an embodiment of the present invention. Referring to FIG. 7, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can identify the valid section logic conversion stored in the system physical block B3 according to the section mapping table list SMT2. Multiple locations of the physical address mapping table SL2P(1), SL2P(3), SL2P(2), SL2P(4), SL2P(5), SL2P(9), SL2P(10), SL2P(11), and As shown by the arrow A71, the mapping table bit map BMP_B3 corresponding to the system physical block B3 is generated by the identified positions. The multiple bit values in the mapping table bitmap BMP_B3 are arranged according to the matrix form of PxQ, and the value of each bit value is used to indicate the corresponding code Whether the word is valid, for example, a bit value of 0 indicates that the corresponding codeword/SL2P table is invalid (invalid codeword/invalid SL2P table), and a bit value of 1 indicates the corresponding codeword/ The SL2P table is valid (valid codeword/valid SL2P table).

By analogy, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) can identify the valid section logical conversion entity stored in the system entity block B4 according to the section mapping table list SMT2 Multiple locations of the address mapping table SL2P(6), SL2P(8), SL2P(7), and as shown by the arrow A72, the identified multiple locations are used to generate a mapping corresponding to the system entity block B4 The epitope map BMP_B4.

After obtaining a plurality of mapping table bitmaps, the mapping table management circuit unit 215 (or mapping table loading management circuit 2152) can generate all corresponding to the plurality of system entity blocks according to the plurality of mapping table bitmaps. The mapping table is loaded into the command queue.

In detail, for the target mapping table bitmap corresponding to the target system physical block in the plurality of mapping table bitmaps (the target system physical block is selected from the plurality of system physical blocks to generate a Or a plurality of system physical blocks that are input to the mapping table load instruction queue), the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes the PxQ matrix Multiple target bit values of the target mapping table bitmap, where P is the total number of multiple target system physical pages of the target system physical block, and each of the multiple target system physical pages stores at most Q SL2P tables Q system physical addresses to each of the multiple target system physical pages, where Q is a positive integer. The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) identifies M in the PxQ matrix A sub-matrix, wherein each of the M sub-matrices includes P×N target bit values, where M*N is equal to Q.

Next, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) reorders each sub-matrix according to the sum of all the target bit values of the P rows of each sub-matrix, from large to small The P rows of the sub-matrix are used to obtain the adjusted target mapping table bitmap.

Next, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) generates a plurality of P rows corresponding to the ordered P rows according to the ordered P rows of the adjusted target mapping table bitmap. Mapping table loading instructions, and sequentially inputting the generated multiple mapping table loading instructions into the mapping table loading instruction queue. Wherein, one or more bit values of 1 in a first type row in the sorted P rows are distributed in the M sub-matrices, and corresponding to all 1 in the first type row The one or more first-type target system physical addresses of the one or more bit values are recorded in one of the multi-plane mapping table load instructions in the mapping table load instruction queue; the sorted One or more bit values of 1 in a second type row of P rows are not distributed in the M sub-matrices, and corresponding to the one or more of 1 in the second type row One or more second-type target system physical addresses of the bit value are recorded to one of the single-plane mapping table load instructions in the mapping table load instruction queue. Simply put, the multiple bit values in the first type row will be scattered in all sub-matrices (that is, the first type row of each sub-matrix of the M sub-matrices has at least one 1 Bit value). Conversely, the second type rows of one or more of the M sub-matrices (corresponding to M planes) may be It only has a bit value of 0.

FIG. 8A is a schematic diagram of an adjustment mapping table bitmap according to an embodiment of the invention. Referring to FIG. 8A, suppose that after obtaining the mapping table bitmaps BMP_B3 and BMP_B4, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) identifies the two sub-matrices (M=2) of the mapping table bitmap BMP_B3 BMP_B3.1, BMP_B3.2 and 2 sub-matrices (M=2) BMP_B4.1, BMP_B4.2 of the mapping table bitmap BMP_B4. Each sub-matrix has 3 rows (P=3) corresponding to the three system physical pages, each row of each sub-matrix can store 2 SL2P tables (N=2), and each sub-matrix corresponds to 1 plane .

In this example, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) according to the three rows of the sub-matrix BMP_B3.1 (for example, corresponding to the system physical pages PG1, PG2, PG3) The sum of the bit values (target bit values) of (eg, 2, 0, 1), from large to small, reorders the sub-matrix BMP_B3.1 into the sub-matrix BMP_B3.1' (as shown by arrow A81). The sum of the target bit values of the three rows of the corresponding system physical pages PG1, PG3, and PG2 of the sub-matrix BMP_B3.1' is 2, 1, and 0. By analogy, the mapping table management circuit unit 215 (or mapping table loading management circuit 2152) readjusts the sub-matrix BMP_B3.2 to the sub-matrix BMP_B3.2' (as shown by the arrow A82); readjusts the sub-matrix BMP_B4. 1 is the sub-matrix BMP_B4.1' (as shown by the arrow A83); re-adjust the sub-matrix BMP_B4.2 to the sub-matrix BMP_B4.2' (as the arrow A84).

FIG. 8B is a schematic diagram of generating a mapping table load instruction queue according to an adjusted mapping table bitmap according to an embodiment of the present invention. Please refer to Figure 8B, in After adjusting each sub-matrix, the adjusted sub-matrix BMP_B3.1' and the adjusted sub-matrix BMP_B3.2' can be combined into the adjusted mapping table bitmap BMP_B3', and the adjusted sub-matrix BMP_B4.1' and the adjusted sub-matrix BMP_B4 .2' can be combined into the adjusted mapping table bit map BMP_B4'.

The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) generates a plurality of rows corresponding to the sorted 3 rows according to the sorted 3 rows of the adjusted target mapping table bitmap BMP_B3' Mapping table loading instructions, and sequentially inputting the generated multiple mapping table loading instructions into the mapping table loading instruction queue. For example, as indicated by arrow A85, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) identifies the value of the multiple target bit values in the first row of the adjusted target mapping table bitmap BMP_B3' Multiple locations, and generate a multi-plane mapping table load instruction "MPLC: "B3, PL1, PG1, CD1-2", "B3, PL2, PG2, CD1-2"" according to the multiple positions; such as arrows As shown in A86, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes multiple positions of multiple target bit values in the second row of the adjusted target mapping table bitmap BMP_B3', And according to the multiple positions, a multi-plane mapping table load instruction "MPLC: "B3, PL1, PG3, CD2", "B3, PL2, PG3, CD1-2" is generated; as shown by arrow A87, The mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes the positions of the plurality of target bit values in the first row of the adjusted target mapping table bitmap BMP_B4', and according to the plurality of positions Position to generate the multi-plane mapping table load instruction "MPLC: "B4, PL1, PG3, CD1", "B4, PL2, PG2, CD1-2"". It should be noted that the multiple rows corresponding to arrows A85~87 belong to the first type of row, and The multiple bit values located in the first type row belong to two system physical pages on two planes of the same system physical block.

After generating multiple multi-plane mapping table loading instructions corresponding to multiple rows of the first type, the mapping table management circuit unit 215 (or mapping table loading management circuit 2152) starts to adjust the target mapping table bitmap BMP_B3 'In the second type line to generate a single plane mapping table load instruction. For example, as indicated by arrow A88, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) identifies the value of the multiple target bit values in the third row of the adjusted target mapping table bitmap BMP_B3' A plurality of positions, and a multi-plane mapping table load instruction "SPLC: "B3, PL2, PG1, CD2"" is generated according to the plurality of positions. In this way, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) generates a corresponding multi-plane mapping table load according to the multiple bit values of all the first type rows and the second type rows. After inputting the instruction or/and the single plane mapping table load instruction to the mapping table load instruction queue LCQ3, the operation of generating the mapping table load instruction queue LCQ3 is completed.

However, in another embodiment, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) may not adjust the target mapping table bitmap through adjusting the sub-matrix. Specifically, for the target mapping table bitmap corresponding to the target system physical block in the plurality of mapping table bitmaps, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes that it is based on PxQ The multiple target bit values of the target mapping table bitmap arranged in a matrix form, where P is the total number of multiple target system physical pages of the target system physical block, and the multiple target system physical pages Each store up to Q SL2P tables to the multiple target system entities Q system physical addresses of each page, where Q is a positive integer. The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) directly re-orders according to the sum of all the target bit values of the P rows of the target mapping table bitmap, from large to small The P rows of the target mapping table bitmap are used to obtain the adjusted target mapping table bitmap. Next, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) generates a plurality of P rows corresponding to the ordered P rows according to the ordered P rows of the adjusted target mapping table bitmap. Mapping table load instructions, and sequentially input the generated mapping table load instructions into the mapping table load instruction queue. Similarly, one or more bit values of 1 of a first type row in the P rows are distributed in M planes, and corresponding to the first type row of 1 One or more first-type target system physical addresses of one or more bit values are recorded in one of the multi-plane mapping table load instructions in the mapping table load instruction queue; the sorted One or more bit values of 1 in a second type row in the P rows are not distributed in the M planes, and correspond to the one or more bit values of 1 in the second type row One or more second-type target system physical addresses of the meta value are recorded to one of the single-plane mapping table load commands in the mapping table load command queue. Hereinafter, it will be described using FIGS. 9A and 9B.

FIG. 9A is a schematic diagram illustrating an adjustment mapping table bitmap according to another embodiment of the present invention. Please refer to FIG. 9A, assuming that the mapping table bitmaps BMP_B3 and BMP_B4 have been obtained. The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) can identify the sum of bit values (also known as the sum of bit values) of each row in the bitmaps BMP_B3 and BMP_B4 of the mapping table. For example, the mapping table bitmap BMP_B3 The total bit value of row 1 (corresponding to the system physical page PG1) is "3"; the second row of the mapping table bitmap BMP_B3 (corresponding to the system physical page PG2) has a total bit value of "2"; mapping table bitmap BMP_B3 The total bit value of the third line (corresponding to the system physical page PG1) is "3". The mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) can reorder the three rows from large to small according to the order of the sum of the bit values of the three rows of the mapping table bitmap BMP_B3. Row to obtain the mapping table bitmap BMP_B3' (as shown by arrow A91). By analogy, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) can re-sort from large to small according to the order of the sum of the bit values of the three rows of the mapping table bitmap BMP_B4 The three rows are used to obtain the mapping table bitmap BMP_B4' (as shown by arrow A92).

9B is a schematic diagram of generating a mapping table load instruction queue according to an adjusted mapping table bitmap according to another embodiment of the present invention. Referring to FIG. 9B, after obtaining the adjusted mapping table bitmaps BMP_B3' and BMP_B4', the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) according to the adjusted target mapping table bitmap BMP_B3' To generate a plurality of mapping table load instructions corresponding to the sorted 3 rows, and sequentially input the generated mapping table load instructions to the mapping table load In the command queue. For example, as indicated by arrow A93, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes the number of target bit values in the first row of the adjusted target mapping table bitmap BMP_B3' Multiple locations, and according to the multiple locations, a multi-plane mapping table load instruction "MPLC: "B3, PL1, PG1, CD1-2", "B3, PL2, PG1, CD2""; as indicated by arrow A94, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes multiple targets in the second row of the adjusted target mapping table bitmap BMP_B3' Multiple positions of the bit value, and generate a multi-plane mapping table load instruction "MPLC: "B3, PL1, PG3, CD2", "B3, PL2, PG3, CD1-2"" according to the multiple positions; As indicated by arrow A95, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes multiple target bit values in the third row of the adjusted target mapping table bitmap BMP_B3' Position, and generate a single-plane mapping table load instruction "SPLC: "B3, PL2, PG2, CD1-2"" according to the multiple positions; as indicated by arrow A96, the mapping table management circuit unit 215 (or The mapping table load management circuit 2152) recognizes the multiple positions of the multiple target bit values in the first row of the adjusted target mapping table bitmap BMP_B4', and generates a single-plane mapping table load based on the multiple positions The input command "SPLC: "B4, PL2, PG2, CD1-2"" is shown by arrow A97, and the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) recognizes the adjusted target mapping table bit The multiple positions of the multiple target bit values in the second row of Figure BMP_B4', and the single-plane mapping table load instruction "SPLC: "B4, PL1, PG3, CD1"" is generated according to the multiple positions. It should be noted that the multiple rows corresponding to arrows A93 to 94 belong to the first type row, and the multiple bit values located in the first type row belong to two systems in two planes of the same system physical block. Physical page. In addition, the multiple rows corresponding to arrows A95-97 belong to the second type row, and the multiple bit values located in the second type row only belong to one of the two planes of the same system physical block. A system entity page.

In this way, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) generates a corresponding multi-plane mapping table load according to the multiple bit values of all the first type rows and the second type rows. After inputting the instruction or/and the single plane mapping table load instruction to the mapping table load instruction queue LCQ4, the operation of generating the mapping table load instruction queue LCQ4 is completed.

In this embodiment, reflecting that the mapping table load instruction queue LCQ4 has been generated, the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) can sequentially execute the mapping table load instructions A plurality of mapping table load commands in LCQ4 are queued to load all the SL2P tables from the rewritable non-volatile memory module 220 into the buffer memory 216. In this way, the processor 211 can use all the SL2P tables loaded into the buffer memory 216 to perform subsequent management operations or data access operations.

It is worth mentioning that, compared with the multiple mapping table load instructions in FIG. 6, the memory management method of the present invention described in FIGS. 8B and 9B can effectively reduce the total number of mapping table load instructions. And multi-plane read operations can be applied to further accelerate the loading speed of SL2P tables.

In addition, in one embodiment, the mapping table management circuit unit 215 can also only update/maintain multiple mapping table bitmaps in the buffer memory 216 (ie, without using the SMT list) to record and store them in a rewritable non-volatile The location of the valid SL2P table of the sexual memory module 220. The multiple mapping table bitmaps in the buffer memory 216 can also be backed up to the rewritable non-volatile memory module 220. Thereafter, the mapping table management circuit unit 215 can directly read the multiple backed up mapping table bitmaps to generate the corresponding mapping table. The firing table is loaded into the command queue, and then all the SL2P tables are loaded into the buffer memory 216.

FIG. 10 is a flowchart of loading a segment logic to entity mapping table according to an embodiment of the present invention. 10, in step S1010, the mapping table management circuit unit 215 (or the mapping table loading management circuit 2152) reads the section mapping table (SMT) list from the rewritable non-volatile memory module 220, And generate a mapping table load instruction queue according to the read SMT list, wherein the mapping table load instruction queue has multiple mapping table load instructions, wherein the multiple mapping table load instructions include single plane mapping Table load instructions and multi-plane mapping table load instructions.

Next, in step S1020, the mapping table management circuit unit 215 (or the mapping table load management circuit 2152) executes the mapping table load instructions according to the sequence of the mapping table load instructions in the mapping table load instruction queue. A plurality of mapping table loading instructions reads a stored logical-to-physical mapping (SL2P) table from the corresponding system physical address by reading through a single plane, or reading through multiple planes, At the same time, the stored SL2P tables are read from corresponding multiple system physical addresses respectively belonging to M planes.

FIG. 11 is a flowchart of loading a section logic to entity mapping table according to another embodiment of the present invention. Referring to FIG. 11, in step S1110, the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) reads from the last system entity page of each of the multiple system entity blocks To read the mapping table record information, and generate a section mapping table (SMT) list of each system physical block according to the read mapping table record information from each system physical block. Specifically, in this embodiment, the mapping table management circuit unit 215 (the processor 211 or the mapping table list management circuit 2151) will record the mapping table record information of each system entity block to each system entity block when the storage device is turned off, and sort the last used system entity The system entity page behind the page (also known as the specific system entity page). The mapping table record information is used to record the effective system physical addresses of a plurality of SL2P tables and the identification codes of the plurality of SL2P tables (also referred to as SL2P table identification codes) stored in the system entity block to which they belong. The processor 211 can identify multiple logical addresses of the corresponding SL2P table through the SL2P table identification code. For example, the SL2P table identification code "ST1" can be used to identify the corresponding segment logical to physical address mapping table SL2P(1) (for example, the number part "2" in "ST1"), as shown in Figure 3B As shown, the section logical to physical address mapping table SL2P(1) contains logical addresses LA(0)~LA(1023) (that is, (1-1)*1024=0, and 1*1024-1= 1023). For another example, the SL2P table identification code "ST2" can be used to identify the corresponding segment logical to physical address mapping table SL2P(2) (for example, the number part "2" in "ST1"), as shown in the figure As shown in 3B, the section logical to physical address mapping table SL2P(2) contains logical addresses LA(1024)~LA(2047) (ie, (2-1)*1024=0, and 2*1024-1 =2047).

FIG. 12 is a schematic diagram of information recorded in a mapping table according to an embodiment of the present invention. 12, in this embodiment, assume that the system physical block B5 stores a plurality of valid segment logical to physical address mapping tables SL2P(1)~SL2P(5), and the system physical block B5 is the last one The used physical page is the physical page PG3 of the plane PL1 (the physical page PG3 of the plane PL2 is left unused in the system physical block B5). Mapping table management circuit unit 215 (place The processor 211 or the mapping table list management circuit 2151) also correspondingly records the section mapping table list SMT3.

In one embodiment, the mapping table management circuit unit 215 (the processor 211 or the mapping table list management circuit 2151) can identify multiple entries related to the system entity block B5 according to the section mapping table list SMT3, and according to the related The multiple entries of the system entity block B5 are used to generate the mapping table record information MRI1 of the system entity block. In another embodiment, the mapping table management circuit unit 215 (the processor 211 or the mapping table list management circuit 2151) does not need to generate the mapping table record information MRI1 of the system entity block B5 according to the section mapping table list SMT3, and may It directly reflects that multiple valid SL2P lists are stored in the system entity block B5 and the related information is recorded to the mapping table record information MRI1. The mapping table record information MRI may also have a predetermined tag, so that the mapping table management circuit unit 215 (the processor 211 or the mapping table list management circuit 2151) recognizes that the read data is the mapping table record information.

At a specific point in time, as indicated by the arrow A1201, the mapping table record information MRI1 can be stored in the first available physical address/codeword of the plane PL2 in the system physical block. The specific time point includes but is not limited to: when the storage device 20 is closed; and when the system physical block B5 is closed. The mapping table record information MRI1 can be used to reconstruct the mapping table list SMT3 corresponding to the system entity block B5.

Then, in step S1120, reflecting that the last system physical page of a specific system physical block of the plurality of system physical blocks does not have mapping table record information, the mapping table management circuit unit 215 (processor 211 Or mapping table load management circuit 2152) scan all the areas stored in the specific system physical block Segment logic into a physical address mapping table to reconstruct the mapping table record information of the specific system physical block, and generate the specific mapping table record information based on the reconstructed mapping table record information of the specific system physical block SMT list of system entity blocks.

Specifically, when the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) determines through the tags in the read data that the last data read from the system physical block B5 is not The mapping table records information, and the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) needs to rescan all the valid SL2P tables in the system physical block B5 (eg, judge every time it is read Whether the information in the obtained SL2P table is valid) to reconstruct the mapping table record information MRI1 of the system entity block B5, and generate the section mapping table corresponding to the system entity block B5 according to the reconstructed mapping table record information MRI1 List SMT3.

Next, in step S1130, the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) generates a mapping table load instruction queue according to all the obtained SMT lists, wherein the mapping table load The instruction queue has a plurality of mapping table load instructions, wherein the plurality of mapping table load instructions includes a single plane mapping table load instruction and a multi-plane mapping table load instruction.

Next, in step S1140, the mapping table management circuit unit 215 (the processor 211 or the mapping table load management circuit 2152) according to the sequence of the multiple mapping table load instructions in the mapping table load instruction queue, Execute the multiple mapping table load instructions to read a stored logical-to-physical mapping (SL2P) table from the corresponding system physical address by reading through a single plane, or read through multiple planes In this way, the stored multiple SL2P tables are read together from corresponding multiple system physical addresses belonging to M planes.

It is worth mentioning that the function of the above-mentioned mapping table management circuit unit 215 is implemented in a hardware circuit, but the present invention is not limited to this. For example, in one embodiment, the functions of the mapping table management circuit unit 215, the mapping table list management circuit 2151, and the mapping table load management circuit 2152 can be implemented by the processor 211 in software or firmware, respectively. Code. For example, the functions of the mapping table management circuit unit 215, the mapping table list management circuit 2151, and the mapping table load management circuit 2152 can be implemented as a mapping table management program module, a mapping table list management program module, and a mapping table load management program. Module, and the processor 211 can load and execute the mapping table management program module, the mapping table list management program module, and the mapping table load management program module to realize corresponding functions.

In summary, the storage controller, the memory management method, and the storage device provided by the embodiments of the present invention can use the section mapping table list to generate corresponding mapping table load command queues to effectively manage multiple The section logic is converted to the physical address mapping table, thereby improving the efficiency of the management operation of the mapping relationship between multiple logical addresses and multiple physical addresses.

S210, S220, S230, S240: Process steps of the memory management method

Claims (21)

A storage controller is used to control a storage device equipped with a rewritable non-volatile memory module. The storage controller includes: a connection interface circuit for coupling to a host system; and a buffer memory ; A memory interface control circuit for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical blocks, and the multiple Each physical block has a plurality of physical pages; a mapping table management circuit unit, and a processor, coupled to the connection interface circuit, the buffer memory, the memory interface control circuit, and the mapping table The management circuit unit, wherein the processor is used to maintain a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the buffer memory, wherein each of the plurality of SL2P tables is used Record the mapping relationship between multiple logical addresses and multiple physical addresses, wherein the multiple physical addresses correspond to a part of the multiple physical pages, and the multiple logical addresses correspond to one Part of it is configured to multiple logical pages of the host system, wherein the mapping table management circuit unit is used to maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory, The SMT list includes multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system entity corresponding to the system block identification code The physical address of the system in the block, The first SL2P table reflected in the plurality of SL2P tables is stored in the first system physical address in the rewritable non-volatile memory module, and the mapping table management circuit unit is further used for recording The first system entity address corresponds to the first entry of the first SL2P table among the multiple entries in the SMT list, wherein the processor is further configured to store the SMT list to the available In the non-volatile memory module of copy type. According to the storage controller described in claim 1, wherein the mapping table management circuit unit generates a mapping table load instruction queue according to the SMT list, wherein the mapping table load instruction queue has a plurality of A mapping table load instruction, wherein each of the plurality of mapping table load instructions includes a single-plane mapping table load instruction and a multi-plane mapping table load instruction, wherein when the storage device is turned on, the mapping table management circuit unit The mapping table load command queue is executed to load the plurality of SL2P tables from the rewritable non-volatile memory module into the buffer memory. The storage controller described in item 2 of the scope of patent application, wherein the single-plane mapping table load instruction is used to instruct to read a stored SL2P table from the corresponding system physical address via a single-plane reading method , Wherein the multi-plane mapping table load instruction is used to instruct to read through the multi-plane, read the stored multiple SL2P tables from the corresponding multiple system physical addresses respectively belonging to M planes, where M It is a positive integer greater than 1. The storage controller described in claim 2, wherein in the operation of generating the mapping table load command queue according to the SMT list, the mapping table management circuit unit identifies the SMT list The plurality of bars Purpose The plane to which each of the multiple system entity addresses belongs is one of M planes, and the mapping table management circuit unit selects multiple sets of M multi-plane system entities from the multiple system entity addresses Address, wherein the M multi-plane system physical addresses of each selected group belong to different M planes, and the M multi-plane system physical addresses of the selected groups are Each address is recorded in one of the multi-plane mapping table load instructions, where M is a positive integer greater than 1, and the mapping table management circuit unit records multiple remaining system addresses that have not been selected among the multiple system physical addresses The physical addresses are respectively recorded in one of the single-plane mapping table load instructions. The storage controller described in claim 2, wherein in the operation of generating the mapping table load command queue according to the SMT list, the mapping table management circuit unit identifies the SMT list The plane to which the plurality of system entity addresses of the plurality of entries belong is one of the M planes, wherein the mapping table management circuit unit determines that the plurality of entries are adjacent to one another according to the arrangement order of the plurality of entries Whether there are one or more second target entries after the first target entry, wherein the first system entity address corresponding to the first target entry and one or more second target entries corresponding to the one or more second target entries The two system physical addresses respectively belong to M physical pages of M planes of a system physical block, wherein it is reflected in determining that there is one or more second target entries adjacent to the first target entry, and the mapping The table management circuit unit records the first system entity Address and the one or more second system physical addresses to one of the multi-plane mapping table load instructions, where M is a positive integer greater than 1, which is reflected in the determination that there is no adjacent address after the first target entry For the one or more second target entries, the mapping table management circuit unit records the physical address of the first system to a single-plane mapping table load instruction. The storage controller according to the first item of the patent application, wherein the mapping table management circuit unit generates a plurality of mapping table bitmaps according to the SMT list, wherein the plurality of mapping table bitmaps respectively correspond to multiple systems A physical block, wherein a mapping table bitmap corresponding to a system physical block records multiple bit values corresponding to multiple system physical addresses of the one system physical block, wherein the multiple bit values Each value includes 0 or 1, where the bit value of 0 is used to indicate that the corresponding system physical address stores an invalid SL2P table or invalid data, and the bit value of 1 is used to indicate all The corresponding system physical address stores a valid SL2P table. According to the storage controller described in claim 6, wherein the mapping table management circuit unit generates a mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps, The mapping table load instruction queues each have a plurality of mapping table load instructions, wherein each of the plurality of mapping table load instructions includes a single-plane mapping table load instruction and a multi-plane mapping table load instruction, where When the storage device is turned on, the mapping table management circuit unit executes the mapping A table load command queue is used to load the plurality of SL2P tables from the rewritable non-volatile memory module into the buffer memory. The storage controller described in item 7 of the scope of patent application, wherein the single-plane mapping table load instruction is used to instruct to read a stored SL2P table from the corresponding system physical address via a single-plane reading method , Wherein the multi-plane mapping table load instruction is used to instruct to read through the multi-plane, read the stored multiple SL2P tables from the corresponding multiple system physical addresses respectively belonging to M planes, where M It is a positive integer greater than 1. The storage controller according to item 7 of the scope of patent application, wherein in the operation of generating the mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps, The target mapping table bitmap corresponding to the physical block of the target system in the multiple mapping table bitmaps, and the mapping table management circuit unit recognizes the multiple targets of the target mapping table bitmap arranged in the form of a PxQ matrix Bit value, where P is the total number of multiple target system physical pages of the target system physical block, and each of the multiple target system physical pages stores at most Q SL2P tables to the multiple target system physical pages Respective Q system physical addresses, where Q is a positive integer, the mapping table management circuit unit identifies M sub-matrices in the PxQ matrix, wherein each of the M sub-matrices includes PxN the target bit values, where M *N is equal to Q, where the mapping table management circuit unit is based on the P of each sub-matrix The sum of all the target bit values of each row, from large to small, to reorder the P rows of each sub-matrix to obtain the adjusted target mapping table bitmap, wherein the mapping table management circuit unit is based on The ordered P rows of the adjusted target mapping table bitmap are used to generate a plurality of mapping table load instructions corresponding to the ordered P rows, and the generated mapping tables are loaded in sequence The instruction is input into the mapping table loading instruction queue, wherein one or more bit values of 1 in a first type row among the P rows sorted are distributed in the M sub-matrices, And one or more first type target system physical addresses of the one or more bit values of 1 corresponding to the first type row are recorded in one of the mapping table load instruction queues The multi-plane mapping table load instruction, wherein one or more bit values of 1 in a second type row in the sorted P rows are not distributed in the M sub-matrices and correspond to the One or more second type target system physical addresses of the one or more bit values of the second type row are recorded to one of the single plane mappings in the mapping table load instruction queue Table load instructions. The storage controller according to item 7 of the scope of patent application, wherein in the operation of generating multiple mapping table load instruction queues corresponding to the multiple system physical blocks according to the multiple mapping table bitmaps, The target mapping table bitmap corresponding to the physical block of the target system among the plurality of mapping table bitmaps, and the mapping table management circuit unit recognizes the ones arranged in the form of PxQ matrix The multiple target bit values of the target mapping table bitmap, where P is the total number of multiple target system physical pages of the target system physical block, and each of the multiple target system physical pages stores at most Q The SL2P table to the Q system entity addresses of the multiple target system entity pages, where Q is a positive integer, and the mapping table management circuit unit is based on all the P rows of the target mapping table bitmap. The P rows of the target mapping table bitmap are reordered to obtain the adjusted target mapping table bitmap by the sum of the target bit values, from large to small, wherein the mapping table management circuit unit is based on the adjusted The sorted P rows of the target mapping table bitmap are used to generate a plurality of mapping table load instructions corresponding to the sorted P rows, and the generated mapping table load instructions are sequentially input to all The mapping table is loaded into the instruction queue, wherein one or more bit values of 1 in a first type row in the sorted P rows are distributed in M planes and correspond to the first The one or more first type target system physical addresses of the one or more bit values of 1 in the type row are recorded in one of the multi-plane mapping table loads in the mapping table load instruction queue Input instruction, wherein one or more bit values of 1 in a second type row in the P rows are not distributed in the M planes, and the row corresponding to the second type is One or more second-type target system physical addresses of the one or more bit values of 1 are recorded to one of the single-plane mapping table load instructions in the mapping table load instruction queue. A memory management method is suitable for a storage controller for controlling a storage device configured with a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has multiple physical areas Block, and the plurality of physical blocks each have a plurality of physical pages, the method includes: maintaining a plurality of segment logical to physical address mapping (Segment Logical To Physical addresses mapping, SL2P) tables in the storage controller In the buffer memory, each of the plurality of SL2P tables is used to record the mapping relationship between a plurality of logical addresses and a plurality of physical addresses, wherein the plurality of physical addresses correspond to a part of the Multiple physical pages, and the multiple logical addresses correspond to a part of multiple logical pages configured to a host system; maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the In the buffer memory, the SMT list includes multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and the multiple entries each include a system block identification code and a corresponding system block The system physical address in the system physical block of the identification code; the first SL2P table reflected in the plurality of SL2P tables is stored in the first system physical bit in the rewritable non-volatile memory module Record the address of the first system entity to the first entry of the first SL2P table among the entries in the SMT list; and store the SMT list in the rewritable non-volatile Sexual memory module. The memory management method described in item 11 of the scope of patent application further includes: Generate a mapping table load instruction queue according to the SMT list, wherein the mapping table load instruction queue has a plurality of mapping table load instructions, wherein each of the plurality of mapping table load instructions includes a single plane mapping table Load instruction and multi-plane mapping table load instruction, wherein when the storage device is turned on, the mapping table management circuit unit executes the mapping table load instruction queue to retrieve from the rewritable non-volatile memory The volume module loads the plurality of SL2P tables into the buffer memory. The memory management method described in item 12 of the scope of the patent application, wherein the single-plane mapping table load instruction is used to instruct to read a stored SL2P from the corresponding system physical address via a single-plane reading method Table, wherein the multi-plane mapping table load instruction is used to instruct to read through the multi-plane mode, and read the stored multiple SL2P tables from corresponding multiple system physical addresses respectively belonging to M planes, wherein M is a positive integer greater than 1. The memory management method as described in item 12 of the scope of patent application, wherein the step of generating the mapping table load instruction queue according to the SMT list includes: identifying all of the multiple entries of the SMT list The plane to which each of the multiple system physical addresses belongs is one of the M planes; multiple sets of M multi-plane system physical addresses are selected from the multiple system physical addresses, and each of the selected The M multi-plane system physical addresses of the group belong to different M planes, and the M multi-plane system physical addresses of the selected groups are respectively recorded in one of the multi-planes A mapping table load instruction, where M is a positive integer greater than 1; and Recording a plurality of remaining system physical addresses that have not been selected among the plurality of system physical addresses into one single plane mapping table load instruction. The memory management method as described in item 12 of the scope of patent application, wherein the step of generating the mapping table load instruction queue according to the SMT list includes: identifying all of the multiple entries of the SMT list The plane to which the multiple system entity addresses belong is one of the M planes; according to the arrangement order of the multiple entries, it is determined whether there is one or more second target entries adjacent to the first target entry, The first system physical address corresponding to the first target entry and the one or more second system physical addresses corresponding to the one or more second target entries respectively belong to M of a system physical block M physical pages of the plane; in response to determining that the one or more second target entries are adjacent to the first target entry, recording the physical address of the first system and the one or more second systems Physical address to one of the multi-plane mapping table load instructions, where M is a positive integer greater than 1; and in response to determining that there is no one or more second target entries adjacent to the first target entry, record The first system physical address is to a single plane mapping table load instruction. As described in item 11 of the scope of patent application, the memory management method further includes: generating a plurality of mapping table bitmaps according to the SMT list, wherein the plurality of mapping table The mapping table bitmap corresponds to a plurality of system physical blocks, wherein a mapping table bitmap record corresponding to a system physical block corresponds to a plurality of bit values of a plurality of system physical addresses of the one system physical block. , Wherein the respective values of the multiple bit values include 0 or 1, and the bit value of 0 is used to indicate that the corresponding system physical address stores invalid SL2P tables or invalid data, and is 1 The bit value is used to indicate that the corresponding system physical address stores a valid SL2P table. According to the 16th item of the scope of patent application, the memory management method further includes: generating a mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps, wherein the mapping The table load command queues each have a plurality of mapping table load commands, wherein each of the plurality of mapping table load commands includes a single-plane mapping table load command and a multi-plane mapping table load command, wherein when the storage device When it is turned on, the mapping table loading command queue is executed to load the plurality of SL2P tables from the rewritable non-volatile memory module into the buffer memory. The memory management method described in item 17 of the scope of patent application, wherein the single-plane mapping table load instruction is used to instruct to read a stored SL2P from the corresponding system physical address via a single-plane reading method Table, wherein the multi-plane mapping table load instruction is used to instruct to read through the multi-plane mode, and read the stored multiple SL2P tables from corresponding multiple system physical addresses respectively belonging to M planes, wherein M is a positive integer greater than 1. The memory management method according to claim 17, wherein the step of generating the mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps includes : For the target mapping table bitmaps corresponding to the physical block of the target system in the plurality of mapping table bitmaps, identify the multiple target bit values of the target mapping table bitmaps arranged in the form of a PxQ matrix, where P is the total number of multiple target system physical pages of the target system physical block, and each of the multiple target system physical pages stores a maximum of Q SL2P tables to the respective Q systems of the multiple target system physical pages Physical address, where Q is a positive integer; identify the M sub-matrices in the PxQ matrix, wherein each of the M sub-matrices includes PxN the target bit values, where M*N is equal to Q; according to the P of each sub-matrix The sum of all the target bit values of each row, from large to small, to reorder the P rows of each sub-matrix to obtain an adjusted target mapping table bit map; and according to the adjusted target mapping P rows of the epitope map are sorted to generate a plurality of mapping table load instructions corresponding to the sorted P rows, and the generated mapping table load instructions are sequentially input to the mapping The table load command queue, wherein one or more bit values of 1 in a first type row in the P rows are distributed in the M sub-matrices and correspond to the first type One or more target systems of the first type with the one or more bit values of 1 The physical address is recorded in one of the multi-plane mapping table load instructions in the mapping table load instruction queue, wherein one of the second type rows in the ordered P rows is one or Multiple bit values are not distributed in the M sub-matrices, and one or more second type target system physical addresses of the one or more bit values of 1 corresponding to the second type row are One of the single-plane mapping table load instructions recorded in the mapping table load instruction queue. The memory management method according to claim 17, wherein the step of generating the mapping table load instruction queue corresponding to the plurality of system physical blocks according to the plurality of mapping table bitmaps includes : For the target mapping table bitmaps corresponding to the physical block of the target system in the plurality of mapping table bitmaps, identify the multiple target bit values of the target mapping table bitmaps arranged in the form of a PxQ matrix, where P is the total number of multiple target system physical pages of the target system physical block, and each of the multiple target system physical pages stores a maximum of Q SL2P tables to the respective Q systems of the multiple target system physical pages Physical address, where Q is a positive integer; according to the sum of all the target bit values of the P rows of the target mapping table bitmap, from large to small, reorder the P of the target mapping table bitmap Rows to obtain the adjusted target mapping table bitmap; and according to the ordered P rows of the adjusted target mapping table bitmap to generate a plurality of mapping table load instructions corresponding to the ordered P rows, And in turn The generated multiple mapping table load instructions are input to the mapping table load instruction queue, wherein one or more bits of 1 in a first type row in the sorted P rows Values are distributed in M planes, and one or more first-type target system physical addresses corresponding to the one or more bit values of 1 in the first-type row are recorded in the mapping table Enter one of the multi-plane mapping table load instructions in the instruction queue, wherein one or more bit values of 1 in a second type row in the P rows are not distributed in the M One or more second-type target system physical addresses of the one or more bit values of 1 in each plane in the second-type row are recorded in the mapping table load instruction queue One of the single-plane mapping table load instructions. A storage device, the storage device comprising: a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical blocks, and the plurality of physical blocks Each has a plurality of physical pages; and a storage controller coupled to the rewritable non-volatile memory module, wherein the storage controller is used to maintain a plurality of segment logical to physical address mappings (Segment Logical Address Mapping). To Physical addresses mapping (SL2P) table is in a buffer memory, wherein each of the plurality of SL2P tables is used to record a plurality of logical addresses and a mapping relationship between a plurality of physical addresses, wherein the plurality of physical addresses Addresses correspond to a part of the multiple physical pages, and the multiple logical addresses correspond to a Part of it is allocated to multiple logical pages of a host system, wherein the storage controller is further used to maintain a segment mapping table list (Segment Mapping Table List, SMT list) in the buffer memory. The SMT list includes multiple entries, wherein the multiple entries respectively correspond to the multiple SL2P tables, and each of the multiple entries includes a system block identification code and a system entity block corresponding to the system block identification code The first SL2P table reflected in the plurality of SL2P tables is stored to the first system physical address in the rewritable non-volatile memory module, and the storage controls The device is further used to record the first system physical address to the first entry of the first SL2P table in the plurality of entries in the SMT list, wherein the storage controller is further used to store the SMT list to the rewritable non-volatile memory module.

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