TWI713648B - Queuing of decoding tasks according to priority in nand flash controller - Google Patents

Abstract

Apparatus, for performing decoding tasks in a NAND5 Flash memory controller, includes a first task queue for queuing decoding tasks of a first priority, a second task queue for queuing decoding tasks of a second priority higher than the first priority, and control circuitry that, on receipt of portions of data for a plurality of decoding tasks, releases, from the first and second task queues, respective decoding tasks to operate on respective portions of data, according to priorities of the decoding tasks.

Description

Queue the decoding tasks in the NAND flash controller according to the priority order [Cross references to related applications]

This document claims the rights and interests of the pending co-assigned U.S. Provisional Patent Application No. 61/266,193 filed on December 11, 2015, the entire contents of which are incorporated herein by reference.

The implementation of the subject matter of the present disclosure generally belongs to a method and apparatus for assigning decoding tasks to different queues according to their priority order in a NAND flash controller, including different decoders suitable for tasks with different priority orders.

The background description provided herein is for the purpose of generally presenting the context of the disclosure. The inventor’s work may not be otherwise limited to the various aspects of the description of the prior art to the extent that the work is described in the background art section and at the time of submission, it is neither expressly nor implicitly admitted to contradict the prior art of the present disclosure. technology.

Multi-level cell (MLC) NAND flash memory is becoming popular because the cost per unit of data storage is reduced relative to the cost of single-level cell (SLC) NAND flash memory. However, because more than one bit of information is stored in each cell, MLC NAND flash memory also experiences a higher original bit error rate than SLC NAND flash memory.

In order to meet the reliability requirements, it is similar to the SLC NAND flash memory device. In comparison, more advanced error correction schemes can be used in MLC NAND flash memory devices. However, the complexity of advanced error correction schemes such as read retry decoding and soft decision decoding can increase the latency of data access operations in NAND flash memory. For different applications, the impact of data access delay will be different. For example, some key operations such as host data reading may require relatively low memory access latency, while other operations such as some background operations (for example, data access for garbage collection) may have a greater degree of latency. Not sensitive.

A device for performing decoding tasks in a NAND flash memory controller. The device includes: a first task queue for queuing decoding tasks in a first priority order; A second task queue in which decoding tasks in a second priority order of a priority order are queued; and a control circuit that, when receiving data parts for multiple decoding tasks, queues from the first task And releasing the corresponding decoding task of the plurality of decoding tasks in the second task queue to operate the corresponding part of the data part according to the priority order of the corresponding decoding task of the plurality of decoding tasks .

In such a device, wherein the NAND flash memory controller includes a plurality of memory channels, the device may further include a corresponding first task queue for each corresponding channel of the plurality of channels, and The corresponding second task queue of each corresponding channel in the plurality of channels. At least one first decoder operates under a first error correction code decoding scheme, and at least one second decoder operates under a second error correction code decoding scheme, which is in terms of speed and complexity One or both of them are different from the first error correction code decoding scheme. The input switching circuit controllably connects each data channel to one of the first decoder and the second decoder. The control circuit includes the corresponding channel task control block for each corresponding channel for Release the decoding task from the corresponding first task queue and second task queue for the corresponding channel to control the input switching circuit to guide the corresponding data for the corresponding channel to the first decoder and the second decoder one of.

In such an implementation, at least one first decoder includes multiple first decoders, at least one second decoder includes multiple second decoders, and the input switching circuit includes a corresponding demultiplexer for each corresponding channel , Used to guide the data on the corresponding channel to one of a plurality of first decoders and a plurality of second decoders; the first switch is used to de-multiplex the multiple first decoders The output of the user is directed to the available first decoder among the plurality of first decoders; and a second switch for guiding the output of the demultiplexer for the plurality of second decoders to the plurality of second decoders Available decoders.

Such an implementation may further include a corresponding buffer for each corresponding channel for holding the data received on the corresponding channel until the decoding task corresponding to the data is from the first task queue and the second task queue One of the releases.

Such an implementation may further include an output switching circuit for outputting the output of one of the first decoder and the second decoder. In this implementation, the control circuit includes a decoder completion control circuit that selects the first decoder and the second decoder when a decoder completion signal is received from one of the first decoder and the second decoder. The output of one of the two decoders. Such an implementation may further include a first task completion queue for queuing completed decoding tasks in the first priority order, and a second task completion queue for queuing completed decoding tasks in the second priority order. The task completion queue, wherein the decoder completion control circuit loads each completed decoding task into one of the first task completion queue and the second task completion queue, and the control circuit further includes decoder completion status control Electricity The decoder completion status control circuit reports the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks.

Such a device may further include a buffer for holding data received from the NAND flash memory until the decoding task corresponding to the data is removed from one of the first task queue and the second task queue released.

Such an apparatus may further include a first task completion queue for queuing completed decoding tasks in a first priority order; and a second task completion queue for queuing completed decoding tasks in a second priority order A queue, wherein the control circuit reports the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks.

A method for executing decoding tasks in a NAND flash memory controller may include: queuing the decoding tasks of the first priority order in a first task queue; and queuing higher than all decoding tasks in a second task queue. The decoding tasks in the second priority order of the first priority order are queued; and when data parts for multiple decoding tasks are received, the multiple decoding tasks are released from the first task queue and the second task queue The corresponding decoding task in the task operates on the corresponding part of the data part according to the priority order of the corresponding decoding task among the multiple decoding tasks.

In an implementation of this method, when the NAND flash memory controller includes multiple memory channels, queuing the decoding tasks of the first priority order may include: for each corresponding channel of the multiple channels Queuing the decoding tasks in the corresponding first task queue; and queuing the decoding tasks in the second priority order may include: queuing the decoding tasks in the corresponding second task queue for each corresponding channel in the plurality of channels Line up. this method It may further include controllably connecting each data channel to one of a first decoder and a second decoder, the first decoder operates under the first error correction code decoding scheme, and the second decoder operates under the second correction code decoding scheme. The second error correction code decoding scheme is different from the first error correction code decoding scheme in one or both of speed and complexity.

In such an implementation, the controllable connection includes: each data channel is controllably connected to one of a plurality of first decoders and a plurality of second decoders, and the plurality of first decoders can correct errors in the first The operation is performed under the code decoding scheme, and multiple second decoders are operated under the second error correction code decoding scheme.

Such an implementation may further include: for each corresponding channel, keeping the data received on the corresponding channel in the buffer until the decoding task corresponding to the data is released from the first task queue and the second task queue.

Such an implementation may further include: queuing the completed decoding tasks of the first priority order in the first task completion queue; and queuing the completed decoding tasks of the second priority order in the second task completion queue Queuing; and reporting the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks.

Such a method may further include keeping the data received from the NAND flash memory in the buffer until the decoding task corresponding to the data is released from one of the first task queue and the second task queue.

The implementation of this method may further include: queuing completed decoding tasks in the first priority order in the first task completion queue, and queuing the completed decoding tasks in the second priority order in the second task completion queue , And according to the priority of the completed decoding task In order to report the completed decoding tasks from the first task completion queue and the second task completion queue.

In such an implementation, according to the priority order of the completed decoding tasks, the completed decoding tasks from the first task completion queue and the second task completion queue are reported including: any completed decoding tasks in the first priority order are reported Before decoding tasks, report all completed decoding tasks in the second priority order. The implementation may further include changing the priority level of the completed decoding tasks from the first priority order to the second priority order after a predetermined duration after the queuing of the completed decoding tasks in the first task completion queue.

In such an implementation, reporting the completed decoding tasks in the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks may include: reporting from the second task completion queue After the predetermined number of tasks in the column, report the tasks from the first task to complete the queue.

In the implementation of such a method, the corresponding decoding tasks among the plurality of decoding tasks are released from the first task queue and the second task queue to be based on the priority of the corresponding decoding tasks among the plurality of decoding tasks. Performing operations on corresponding parts in the data part in order may include: releasing all decoding tasks in the second priority order before releasing any decoding tasks in the first priority order.

Such an implementation may further include changing the priority level of the decoding tasks from the first priority order to the second priority order after a predetermined duration after the queuing of the decoding tasks in the first task queue.

In such a method, the corresponding decoding tasks among the plurality of decoding tasks are released from the first task queue and the second task queue, so that the corresponding decoding tasks among the plurality of decoding tasks Operating the corresponding parts in the data part in the order of priority may include: releasing the tasks from the first task queue after the predetermined number of tasks in the second task queue are released.

130‧‧‧Processor

102‧‧‧Host

111‧‧‧Host Interface

112‧‧‧ECC encoder

113‧‧‧NAND flash interface

123‧‧‧Host Interface

122‧‧‧ECC Decoder

121‧‧‧NAND flash interface

100‧‧‧NAND Flash Controller

101‧‧‧NAND flash memory

235‧‧‧Decoder complete status control

233‧‧‧Complete status queue in normal priority order

234‧‧‧High priority completion status queue

232‧‧‧Decoder complete control

223‧‧‧Decoder start control

224‧‧‧Channel mission control

225‧‧‧Level 1 decoder switch control

226‧‧‧Level 2 decoder switch control

201: Level 1 decoder

202: Level 2 decoder

After considering the following detailed description in conjunction with the accompanying drawings, other features, properties and various advantages of the present disclosure will be apparent. In the accompanying drawings, the same reference numerals denote the same components throughout the text, and among them: FIG. 1 shows A block diagram of a NAND flash memory controller that can be implemented using the present disclosure; Figure 2 shows a block diagram of the structure of an error correction code decoder according to an implementation of the subject of the present disclosure that can be used in a NAND flash controller Figure; Figure 3 is a flowchart of the process of implementing the subject of the present disclosure, by which the decoding task queue for each data channel in the decoder of Figure 2 can be filled; Figure 4 shows the subject of the present disclosure A flowchart of the process of implementing the process for selecting a task for execution from one of the normal priority task queue or the high priority task queue; FIG. 5 is a diagram showing the implementation of the subject of the present disclosure for A flowchart of the operation of selecting a rule set between a normal priority decoding task and a high priority decoding task; and FIG. 6 is a flowchart showing a process for reporting the completion of a decoding task according to an implementation of the subject of the present disclosure.

As mentioned above, MLC NAND flash memory may experience a higher raw bit error rate than SLC NAND flash memory. Therefore, in order to meet the reliability requirements, more advanced error correction solutions can be used in MLC NAND flash memory devices than in SLC NAND flash memory devices. Used in memory devices. However, the complexity of advanced error correction schemes such as read retry decoding and soft decision decoding can increase the latency of data access operations in NAND flash memory.

Because the impact of the data access delay described above is different for different applications, according to the implementation of the present disclosure, memory access operations of different priority orders can be handled differently. In addition, a trade-off can be achieved between using more complex and time-consuming decoding schemes and using simpler and faster decoding schemes. More complex and time-consuming decoding schemes are more likely to succeed at the first attempt, simpler and faster The decoding scheme may occasionally fail and require more than one attempt.

All in all, even if accidental failures that require retry operations may occur, simpler and faster decoding schemes can be used for most memory access operations, while more complex and time-consuming decoding tasks can be used for higher priority decoding tasks. Decoding scheme to maximize the overall throughput.

In addition, under the "insertion" feature, even if the higher priority decoding task is started later, the higher priority decoding task can be executed before the normal priority decoding task.

The implementation of the subject matter of the present disclosure can be understood with reference to FIGS. 1-6.

FIG. 1 shows a NAND flash memory controller 100 between one or more NAND flash memory devices 101 and a host device 102. The NAND flash controller 100 includes a "programming" or write path 110 and a read path 120. Data from the host device 102 can be written to the NAND flash memory device 101 along the write path 110 and pass through the host device. 102 can read data from the NAND flash memory device 101 along the read path 120. The write path 110 includes a host interface 111 for receiving data in a host format, an encoder 112 for converting the data received by the host interface 111 in a host format into a format used by the NAND flash memory device 101, and an encoder 112 for converting The encoded data is sent to the NAND flash memory of the NAND flash memory device 101 Memory body interface 113. Similarly, the read path 120 includes a NAND flash interface 121 for receiving data from the NAND flash memory device 101 in the format used by the NAND flash memory device 101, and a NAND flash interface 121 for flashing the NAND flash memory interface 121 with NAND flash memory. The data received in the format used by the memory device 101 is converted into a decoder 122 in the format used by the host device 102 and a host interface 123 for transmitting the decoded data to the host device 102. The processor 130, which may be a microprocessor, controls various elements of the write path 110 and the read path 120.

The encoder 112 and the decoder 122 are complementary, that is, the encoder 112 and the decoder 122 use complementary versions of the same scheme to encode and decode data, so that the data is received from the host device 102 and encoded by the encoder 112 for storage in the NAND The data on the flash memory device 101 can be decoded by the decoder 122 after being read back from the NAND flash memory device 101. Usually and in the implementation discussed herein, such an encoding/decoding scheme is Error Correction Code (ECC), so that the data can be reconstructed even after an error in the writing or reading process.

Figure 2 shows details of an implementation 200 of the ECC decoder 122 according to the present disclosure. The ECC decoder 200 includes a first plurality of n decoder circuits 201 and a second plurality of m decoder circuit circuits 202. Each of the decoder circuits 201 can implement a relatively simpler and faster error correction decoding scheme than the error correction decoding scheme implemented by each of the decoder circuits 202, while each of the decoder circuits 202 can implement The error correction decoding scheme implemented by each of the decoder circuits 201 is relatively more complex and time-consuming error correction decoding scheme. Generally, compared with the decoder circuit 202 that implements a relatively more complex and time-consuming error correction decoding scheme, there may be more decoder circuits 201 that implement a relatively simpler and faster error correction decoding scheme—that is, generally It can be expected that n>m, but there can be implementations of m>n. The relatively simpler and faster error correction decoding scheme may be referred to as "level 1", and the relatively more complex and time-consuming error correction decoding scheme may be referred to as "level 2".

Under the control of the processor 130 described below, the data received from the NAND flash interface 121 on the channel 203 is guided to the decoder circuit 201 or the decoder circuit 202 through the switch circuit 204. Similarly, the decoded data from the decoder circuit 201 or the decoder circuit 202 is transmitted to the host interface 123 at 208 through the n:1 multiplexer 205, the m:1 multiplexer 206 and the 2:1 multiplexer 207, As discussed further below.

The processor 130 controls the switch circuit 204 as described above via the decoding task control block 210. The decoding task control block 210 includes a decoding task start part 220 and a decoding task completion part 230.

The decoding task start portion 220 of the decoding task control block 210 includes a corresponding pair of decoding task queues 221, 222 for each data channel 203. In each pair of decoding task queues 221, 222, one decoding task queue (for example, decoding task queue 221) is a normal priority task queue, and another decoding task queue (for example, decoding task queue 222) It is a high priority task queue. The decoder start control 223 distributes the incoming decoding task 211 from the processor 130 to the appropriate decoding task queue pair 221 and 222 according to the data channel 203 to which the decoding task 211 is applied, such as determined based on, for example, the task ID field. Each pair of decoding task queues 221, 222 feeds a corresponding channel task control block 224. Each channel task control block 224 passes tasks (including at least task ID and information about priority) to level 1 decoder switch control block 225 and level 2 decoder switch control block 226, and also controls the data to enter the demultiplexer 227 to be able to route the incoming data to the level 1 decoder switch 228 or the level 2 decoder switch 229 on the channel 203.

The processor 130 sends a read request corresponding to each decoding task 211 to the NAND flash memory device 101 via the NAND flash interface 121. Each read request has the same task ID as its corresponding decoding task 211. When the NAND flash interface 121 flashes from NAND flash memory When the body device 101 returns the corresponding data, it sends a decoded data ready signal to the channel task control block 224 through the NAND flash interface 121 at 231, and identifies the returned data through the task ID.

One of the channel task control blocks 224 that owns the task identified by the received task ID (ie, one of the channel task control blocks 224 associated with one of the channels 203 on which the data has been returned) will The queue 221 or 222 (according to the priority order of the tasks) associated with one of the channels 2103 selects the identified task. Then, one of the channel task control blocks 224 passes the task to the level 1 decoder switch control block 225 or the level 2 decoder switch control block 226 to activate the level 1 decoder switch 228 or the level 2 decoder switch 229 according to The priority of the task routes the data to be decoded from the incoming channel 203 to the available one of n level 1 decoder circuits 201 or m level 2 decoder circuits 202, respectively. At the same time, one of the channel task control blocks 224 will also activate the data on the appropriate channel 203 to enter one of the demultiplexers 227 to route the data to the level 1 decoder switch 228 or the level 2 decoder switch 229. One.

After the data is routed to one of the n level 1 decoder circuits 201 or m level 2 decoder circuits 202, the data will be appropriately routed by one of the n level 1 decoder circuits 201 or m level 2 decoder circuits 202. decoding. After the decoding is completed, depending on the situation, the level 1 decoder circuit 201 or the level 2 decoder circuit 202 will send a completion signal to the decoding task completion section 230 of the decoding task control block 210. The completion signal will be received by the decoder completion control block 232, which will make the multiplexer 205 (in the case of one of the n level 1 decoder circuits 201) or the multiplexer 206 (in the case of m level 2 decoder circuits 202) In the case of one of the decoder circuits 201 or 202, the correct one of the decoder circuits 201 or 202 is selected, and the multiplexer 207 (in the case of one of the n level 1 decoder circuits 201) is also selected to select the multiplexer 205 , Or multiplexer 206 (in the case of one of m level 2 decoder circuits 202) for output to the host interface 123 at 208.

In addition to controlling the multiplexers 205, 206, 207 at 208 to select the correct output, the decoding task completion section 230 of the decoding task control block 210 also notifies the processor 130 when the decoding task is completed. For example, for any completed task, the decoder completion control block 232 can output the task ID of the completed task to the normal priority order completion status queue 233 or the high priority order completion status queue according to the priority order of the completed tasks. 234. At 236, the decoder completion status control block 235 sends a completion indication from the normal priority order completion status queue 233 and the high priority order completion status queue 234 to the processor 130.

Any completed instructions in the high priority completion queue 234 related to the high priority tasks may be sent before any completion instructions in the normal priority completion status queue 233. Alternatively, the completion indication may be extracted from both the normal priority order completion status queue 233 and the high priority order completion status queue 234 in some predetermined order. For example, even if other completion instructions remain in the high priority completion status queue 234, after a certain number of completion instructions are extracted from the high priority completion status queue 234, they can be extracted from the normal priority completion status queue 233 A completion instruction. As another alternative, any completion indication in the high priority completion status queue 234 related to the high priority task may be sent before any completion indication in the normal priority completion status queue 233, unless the completion indication already resides The normal priority order completion status queue 233 is longer than the predetermined duration (it can be considered as changing the priority order of the completion indication to "high").

Returning to the decoding task start part 220 of the decoding task control block 210, one of the channel task control blocks 224 selects a task from its corresponding low-priority task queue 221 and high-priority task queue 222, which may have priority than normal The order completion status queue 233 and the high priority completion status queue 234 selection completion instructions are more complicated, because as described above, regardless of their status Regardless of the state, the decoding task cannot be selected until the data associated with the task has been returned from the NAND flash memory device 101. A solution for processing data accesses with different priorities in a NAND flash memory controller is described in US Patent 9,092,156, the entire content of which is incorporated herein by reference. However, other solutions can be used to prioritize the reading of data.

When the data has been read and returned, the NAND flash interface 121 may include a priority level for indicating the priority associated with the data. If more than one decoding task is still to be processed, the signal indicating the priority order will be used in the selection of the decoding task, where it is preferably selected in the higher order than the normal priority order decoding task in the normal priority order task queue 221. The higher priority order decoding task in the priority order task queue 222.

Part of the selection involves routing the data to the correct decoder. If the decoding task being performed uses the level 1 decoder, it will be sent to the level 1 decoder switch control block 225 in the assigned priority order; otherwise, it will be sent to the level 2 decoder switch control block 226. The level 1 decoder switch control block 225 and the level 2 decoder switch control block 226 can be regarded as arbitration blocks. For example, the tasks assigned to each of the level 1 decoder switch control block 225 and the level 2 decoder switch control block 226 may be allocated according to weighted loop arbitration.

As described above, each level 1 decoder 201 can implement a relatively simpler and faster decoding scheme, and each level 2 decoder 202 can implement a relatively more complex and time-consuming decoding scheme. As a general case, level 1 decoding scheme can be used for normal priority tasks, and level 2 decoding schemes can be used for higher priority tasks. However, in some implementations, there may be cases where level 1 decoding schemes are used for higher priority tasks, just as there may be cases where level 2 decoding schemes are used for normal priority tasks.

For example, if the task has a higher priority because it uses level 1 solution If the read retry task of the normal priority task of the code scheme is used for the failed normal priority task, then the read retry attempt can use the level 1 decoding scheme again, regardless of its higher priority. As another example, if a task has a normal priority order and there is no level 1 decoder available, but there is an unused level 2 decoder, then a level 2 decoder can be used regardless of the normal priority order of the task. One such example may involve data that is not delay-critical, such as garbage collection tasks where level 1 decoding fails; using a slower level 2 decoding for the second attempt will make level 1 decoders available for delay-critical data. There may be other cases where the level 1 decoding scheme is used for higher priority tasks or the level 2 decoding scheme is used for normal priority tasks.

The operation of the ECC decoder 200 can be better understood with reference to the flowcharts in FIGS. 3-5.

3 is a flowchart showing the implementation of a process 300 according to an embodiment, by which the decoding task queues 221, 222 for each data channel 203 are filled. A new decoding task for the channel in question is received at 301. At 302, it is determined whether the task received at 301 is a high priority task. If the task received at 301 is determined to be a high priority task at 302, then at 303, the task is placed in the high priority task queue 222 for the channel. However, if it is determined at 302 that the received task is not a high priority task, then at 304, the task is placed in the normal priority task queue 221 for the channel. At 305, it is determined whether there are any other decoding tasks for the channel. If it is determined at 305 that there are no other decoding tasks for the channel, the process 300 ends. But if it is determined at 305 that there are other decoding tasks for the channel, the process 300 returns to 301 to receive a new decoding task.

4 is a flowchart showing the implementation of a process 400 for selecting a task for execution from one of the normal priority task queue 221 or the high priority task queue 222. in At 401, a NAND data ready signal is received from the NAND flash memory device 101 (for example, on one of the channels 203) indicating that the data has been returned (for example, in response to a request). At 402, it is determined whether the returned material belongs to a high-priority task (as described above, the task ID can be returned with the material). If it is, then at 403, the associated task is released from the high priority task queue 222 of the corresponding channel 203. Otherwise, if it is determined at 402 that the returned data does not belong to a high priority task, then at 404, the associated task is released from the normal priority task queue 221 of the corresponding channel 203.

As mentioned above, the choice of decoder is not necessarily determined by the priority order of tasks. Although most high priority tasks will be level 2 decoder tasks, and most normal priority tasks will be level 1 decoder tasks, there may be exceptions. Therefore, once the task to be executed has been released, it is determined at 405 whether the task is a level 1 decoding task. If so, then the task is directed to the level 1 decoder at 406 (via the appropriate channel task control block and the appropriate decoder switch control block), and the process 400 ends. Otherwise, if it is determined at 405 that the task is not a level 1 decoding task, then the task is directed to a level 2 decoder at 407 and the process 400 ends.

The actual order of releasing tasks from the queues 221 and 222 can be controlled according to predetermined rules. Therefore, if the data is returned, but is associated with a task with a lower priority order than another task (ie, a normal priority task), the data can be saved in a buffer (not shown) until the task is ready to be executed , Has returned information for another task.

According to a set of possible rules, high priority tasks will always take priority over normal priority tasks. According to a variation of the rule set, excessive dwell time in the normal priority queue (over a predetermined limit) causes tasks to be moved to the high priority queue. According to another A set of capable rules to execute a normal priority task for every p high-priority tasks executed, which makes it impossible to spend too much time in the normal priority queue. A combination of these rule sets can be used, where for every p high-priority tasks executed, a normal priority task is executed, but excessive residence time in the normal priority queue (this should be rare) makes the task change from normal The priority queue is moved to the high priority queue. Other rule sets can be developed.

An example 500 of a possible set of such rules is shown in FIG. 5. At 501, it is determined whether the number of high priority tasks that have been executed (from the last time the counter was reset) exceeds a threshold. If not, it is determined at 502 whether there are any high priority tasks waiting in the high priority task queue. If so, the high priority task is selected at 503 and sent to the appropriate decoder (see, for example, FIG. 4), where the selected task is executed at 504. If it is determined at 502 that there are no high-priority tasks waiting in the high-priority task queue, or it is determined at 501 that the number of high-priority tasks that have been executed (from the last reset of the counter) does not exceed the threshold, Then it is determined at 505 whether there are any normal priority tasks waiting in the normal priority task queue. If so, the normal priority task is selected at 506 and sent to the appropriate decoder (see, for example, FIG. 4), where the selected task is executed at 504.

After the selected task has been executed at 504 (regardless of whether it is a high-priority task or a normal-priority task), at 507, the result is sent to the completion status queues 233, 234 for example as shown in FIG. 6 Make a report. After the results have been reported or if it is determined at 505 that there are no normal priority tasks waiting in the normal priority task queue, it is determined at 508 whether there are any tasks to be executed. If so, the process returns to 501. Such as If it is determined at 508 that there are no tasks to be executed, the process 500 ends.

Fig. 6 is a flowchart showing the implementation of one possible process 600 for reporting the completion of a decoding task. At 601, it is determined whether there are any unreported completed high-priority decoding tasks (e.g., in the high-priority completion status queue 234). If it is, the notification of the next completed high priority task is reported at 602, and the flow returns to 601 to find more completed decoding tasks that have not been reported. If it is determined at 601 that there are no unreported completed high-priority decoding tasks, then it is determined at 603 whether there are any unreported completed normal priority decoding tasks (for example, in the normal priority order completion status queue 233). If it is, the notification of the next completed normal priority task is reported at 604, and the flow returns to 601 to find more unreported completed high priority decoding tasks. If it is determined at 603 that there are no unreported completed normal priority decoding tasks, the process 600 ends. However, it should be noted that other reporting rule sets similar to the various possible rule sets for releasing tasks from the queues 221, 222 described above can also be applied to the task completion report.

Therefore, it can be seen that a decoding device and corresponding method are provided, in which a simpler and faster decoding scheme can be used for most memory access operations even if an accidental failure requiring retry operations may occur, while Higher priority decoding tasks use more complex and time-consuming decoding schemes to maximize overall throughput. It can also be seen that under the "jump in queue" feature, the higher priority decoding task can be executed before the normal priority decoding task, even if the higher priority decoding task starts later, but as mentioned above, if the normal priority task Because the higher priority tasks arriving later have to wait too long, the normal priority tasks themselves can also increase their priority.

Other aspects of the invention involve one or more of the following clauses:

Clause 1: A device for executing decoding tasks in a NAND flash memory controller, the device comprising: a first task queue for queuing decoding tasks in a first priority order; The second task queue in which the decoding tasks in the second priority order of the first priority order are queued; and a control circuit that, when receiving data parts for multiple decoding tasks, starts from the first task queue and the The second task queue releases corresponding decoding tasks among the plurality of decoding tasks, so as to operate corresponding parts in the data part according to the priority order of the corresponding decoding tasks among the plurality of decoding tasks.

Clause 2: The device according to Clause 1, wherein the NAND flash memory controller includes a plurality of memory channels, and wherein the device further includes: a corresponding first channel for each of the plurality of channels The task queue and the corresponding second task queue for each corresponding channel in the multiple channels; at least one first decoder operating under the first error correction code decoding scheme; at least one second decoder operating under the It operates under the second error correction code decoding scheme, which is different from the first error correction code decoding scheme in one or both of speed and complexity; and the input switching circuit, which controllably switches each Data channels are connected to one of the first decoder and the second decoder; wherein, the control circuit includes a corresponding channel task control block for each corresponding channel for downloading from the corresponding first decoder for the corresponding channel The decoding task is released in the first task queue and the second task queue to control the input switching circuit to guide the corresponding data for the corresponding channel to the first solution One of the encoder and the second decoder.

Clause 3: The device according to Clause 2, wherein: at least one first decoder includes a plurality of first decoders; at least one second decoder includes a plurality of second decoders; and the input switching circuit includes: for each The corresponding demultiplexer of the corresponding channel is used to guide the data on the corresponding channel to one of a plurality of first decoders and a plurality of second decoders. The demultiplexer output of a decoder is directed to the available first decoder among the plurality of first decoders, and a second switch is used to direct the output of the demultiplexer for the plurality of second decoders To an available second decoder among the plurality of second decoders.

Clause 4: The device according to Clause 2, further comprising: a corresponding buffer for each corresponding channel for holding the data received on the corresponding channel until the decoding task corresponding to the data starts from the first One of the first task queue and the second task queue is released.

Clause 5: The device according to Clause 2, further comprising: an output switching circuit for outputting the output of one of the first decoder and the second decoder; wherein: the control circuit includes a decoder completion control circuit , The decoder completion control circuit, when receiving a decoder completion signal from one of the first decoder and the second decoder, selects one of the first decoder and the second decoder Output.

Clause 6: The device according to Clause 5, further comprising: a first task completion queue for queuing completed decoding tasks in the first priority order; and The second task completion queue for queuing the completed decoding tasks in the second priority order; wherein: the decoder completion control circuit loads each completed decoding task into the first task completion queue and the second One of the task completion queues; and the control circuit further includes a decoder completion status control circuit, the decoder completion status control circuit reports from the first task completion queue and the second task completion according to the priority order of the completed decoding tasks The completed decoding tasks in the queue.

Clause 7: The device according to clause 1, further comprising: a buffer for holding the data received from the NAND flash memory until the decoding task corresponding to the data is queued from the first task and the second task One of the queues was released.

Clause 8: The device according to clause 1, further comprising: a first task completion queue for queuing completed decoding tasks in the first priority order; and a completed decoding task in the second priority order The second task completion queue where tasks are queued; wherein: the control circuit reports the completed decoding from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks task.

Clause 9: A method for executing decoding tasks in a NAND flash memory controller, the method comprising: queuing decoding tasks of the first priority in a first task queue; and in a second task queue Queuing decoding tasks in a second priority order higher than the first priority order; and When the data part for multiple decoding tasks is received, the corresponding decoding tasks in the multiple decoding tasks are released from the first task queue and the second task queue, so that the corresponding decoding tasks in the multiple decoding tasks are The priority of the task is to operate on the corresponding part of the data part.

Clause 10: The method according to Clause 9, wherein the NAND flash memory controller includes a plurality of memory channels, and wherein: queuing the decoding tasks in the first priority order includes: Queuing the decoding task in the corresponding first task queue for each corresponding channel; and queuing the decoding task in the second priority order includes: performing the corresponding second task on each corresponding channel in the plurality of channels The decoding tasks are queued in the queue; the method further includes: each data channel is controllably connected to one of the first decoder and the second decoder, and the first decoder is in the first error correction code decoding scheme The second decoder operates under the second error correction code decoding scheme, and the second error correction code decoding scheme is different from the first error correction code decoding scheme in one or both of speed and complexity.

Clause 11: The method according to clause 10, wherein the controllably connecting includes: connecting each data channel to one of a plurality of first decoders and a plurality of second decoders, and a plurality of first decoders The decoder operates under the first error correction code decoding scheme, and multiple second decoders operate under the second error correction code decoding scheme.

Clause 12: The method according to Clause 10, further comprising: for each corresponding channel, keeping the data received on the corresponding channel in a buffer until the decoding task corresponding to the data is removed from the first task Release in the queue and the second task queue.

Clause 13: The method according to clause 10, further comprising: queuing the completed decoding tasks of the first priority order in a first task completion queue; and queuing a second task in a second task completion queue The completed decoding tasks in the priority order are queued; and the completed decoding tasks from the first task completion queue and the second task completion queue are reported according to the priority order of the completed decoding tasks.

Clause 14: The method according to clause 9, further comprising keeping the data received from the NAND flash memory in a buffer until the decoding task corresponding to the data is queued from the first task and the One of the second task queue is released.

Clause 15: The method according to Clause 9, further comprising: queuing the completed decoding tasks in the first priority order in the first task completion queue; and queuing the second priority order in the second task completion queue Queue the completed decoding tasks; and report the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority of the completed decoding tasks.

Clause 16: The method according to Clause 15, wherein the reporting of completed decoding tasks from the first task completion queue and the second task completion queue according to the priority of the completed decoding tasks includes: Before reporting any completed decoding tasks in the first priority order, report all completed decoding tasks in the second priority order.

Article 17: Further includes: the completed solution in the first task completion queue After a predetermined duration after the queuing of the code task, the priority level of the completed decoding task is changed from the first priority order to the second priority order.

Clause 18: The method according to clause 15, wherein reporting the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority of the completed decoding tasks includes: After the second task completes the predetermined number of tasks in the queue, the task from the first task complete queue is reported.

Clause 19: The method according to Clause 9, wherein the corresponding decoding task among the plurality of decoding tasks is released from the first task queue and the second task queue, so that the corresponding decoding task in the plurality of decoding tasks The priority order to operate the corresponding part of the data part includes: releasing all decoding tasks in the second priority order before releasing any decoding tasks in the first priority order.

Clause 20: The method according to Clause 19, further comprising: after a predetermined duration after queuing the decoding tasks in the first task queue, changing the priority level of the decoding tasks from the first priority order to all the decoding tasks. The second priority order.

Clause 21: The method according to Clause 9, wherein the corresponding decoding task among the plurality of decoding tasks is released from the first task queue and the second task queue, so that the corresponding decoding task in the plurality of decoding tasks Prioritizing operations on corresponding parts in the data part includes: releasing tasks from the first task queue after releasing a predetermined number of tasks from the second task queue.

As used herein and in the scope of the appended application, the structure "one of A and B" will mean "A or B."

It should be understood that the foregoing is only to illustrate the principle of the present invention, and the present invention can be It is practiced through other embodiments in addition to the described embodiments, which are presented for the purpose of illustration rather than limitation, and the present invention is only limited by the scope of the attached patent application.

130‧‧‧Processor

102‧‧‧Host

111‧‧‧Host Interface

112‧‧‧ECC encoder

113‧‧‧NAND flash interface

123‧‧‧Host Interface

122‧‧‧ECC Decoder

121‧‧‧NAND flash interface

100‧‧‧NAND Flash Controller

101‧‧‧NAND flash memory

Claims (19)

A device for performing decoding tasks in a NAND flash memory controller, wherein the NAND flash memory controller includes a plurality of memory channels, and the device includes: a corresponding first task queue for Each corresponding channel of the plurality of channels queues the decoding tasks of the first priority; the corresponding second task queue is used for each corresponding channel of the plurality of channels, and the pair is higher than the first priority. The decoding tasks in the second priority order of a priority order are queued; at least one first decoder, the at least one first decoder operates under the first error correction code decoding scheme; at least one second decoder, the At least one second decoder operates under a second error correction code decoding scheme, which is different from the first error correction code decoding scheme in one or both of speed and complexity An input switching circuit, the input switching circuit controllably connects each data channel to one of the first decoder and the second decoder; and a control circuit, the control circuit including for each corresponding The corresponding channel task control block of the channel is used to release the decoding task from the corresponding first task queue and the corresponding second task queue for the corresponding channel to control the input switching circuit to be used for all The corresponding data of the corresponding channel is guided to one of the first decoder and the second decoder, wherein: when the control circuit receives the data part for multiple decoding tasks, the data from the corresponding first decoder In a task queue and the corresponding second task queue, the corresponding decoding tasks among the plurality of decoding tasks are released, so that the corresponding decoding tasks among the plurality of decoding tasks are released according to the priority order of the corresponding decoding tasks among the plurality of decoding tasks. Operate the corresponding part in the data section. The apparatus according to claim 1, wherein: the at least one first decoder includes a plurality of first decoders; the at least one second decoder includes a plurality of second decoders; and the input switching circuit includes : The corresponding demultiplexer for each corresponding channel is used to selectively guide the data on the corresponding channel to one of the plurality of first decoders and the plurality of second decoders, the first A switch for directing the output of the demultiplexer for the plurality of first decoders to the available first decoder among the plurality of first decoders, and a second switch, so The second switch is used to direct the output of the demultiplexer for the plurality of second decoders to the available second decoder among the plurality of second decoders. The device according to claim 1, further comprising: a corresponding buffer for each corresponding channel, configured to hold the data received on the corresponding channel until the decoding task corresponding to the data changes from the corresponding One of the first task queue and the corresponding second task queue is released. The apparatus according to claim 1, further comprising: an output switching circuit configured to output an output of one of the first decoder and the second decoder; wherein: the control The circuit includes a decoder completion control circuit, and the decoder completion control circuit selects the first decoder when a decoder completion signal is received from the one of the first decoder and the second decoder. The output of the one of the decoder and the second decoder. The apparatus according to claim 4, further comprising: a first task completion queue for queuing the completed decoding tasks in the first priority order; and a second task completion queue for queuing the The completed decoding tasks in the second priority order are queued; wherein: the decoder completion control circuit loads each completed decoding task into the first task completion queue and the second task completion queue And the control circuit further includes a decoder completion status control circuit, the decoder completion status control circuit reports from the first task according to the priority order of the completed decoding tasks Completing the queue and the second task completing the completed decoding task of the queue. The device according to claim 1, further comprising: a buffer for holding the data received from the NAND flash memory until the decoding task corresponding to the data is queued from the corresponding first task And the corresponding second task queue is released in one task queue. The apparatus according to claim 1, further comprising: a first task completion queue for queuing the completed decoding tasks in the first priority order; and a second task completion queue for queuing the The completed decoding tasks in the second priority order are queued; wherein: the control circuit reports from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks The completed decoding task. A method for performing decoding tasks in a NAND flash memory controller, Wherein, the NAND flash memory controller includes a plurality of memory channels, and the method includes: for each corresponding channel of the plurality of channels, performing a first priority order in the corresponding first task queue Queue the decoding tasks; queue the decoding tasks in the second priority order higher than the first priority order in the corresponding second task queue for each corresponding channel of the plurality of channels; The channel is controllably connected to one of the first decoder and the second decoder. The first decoder operates under the first error correction code decoding scheme, and the second decoder performs the second error correction code decoding scheme. Operating under the scheme, the second error correction code decoding scheme is different from the first error correction code decoding scheme in one or both of speed and complexity; and after receiving data for multiple decoding tasks Partially, the corresponding decoding task among the plurality of decoding tasks is released from the corresponding first task queue and the corresponding second task queue, so that the corresponding decoding task among the plurality of decoding tasks The order of priority to operate on the corresponding part of the data section. The method according to claim 8, wherein the controllably connecting includes: connecting each data channel to one of a plurality of first decoders and a plurality of second decoders, the plurality of The first decoder operates under the first error correction code decoding scheme, and the plurality of second decoders operate under the second error correction code decoding scheme. The method according to claim 8, further comprising: for each corresponding channel, keeping the data received on the corresponding channel in a buffer until the decoding task corresponding to the data starts from the corresponding first A task queue in a task queue and the corresponding second task queue is released. The method according to claim 8, further comprising: queuing the completed decoding tasks in the first priority order in a first task completion queue; and queuing the second task in a second task completion queue The completed decoding tasks in the priority order are queued; and according to the priority order of the completed decoding tasks, the completed decoding tasks from the first task completion queue and the second task completion queue are reported. The method according to claim 8, further comprising keeping the data received from the NAND flash memory in the buffer until the decoding task corresponding to the data is queued from the corresponding first task and the A task queue in the corresponding second task queue is released. The method according to claim 8, further comprising: queuing the completed decoding tasks in the first priority order in a first task completion queue; and queuing the second task in a second task completion queue The completed decoding tasks in the priority order are queued; and according to the priority order of the completed decoding tasks, the completed decoding tasks from the first task completion queue and the second task completion queue are reported. The method according to claim 13, wherein the reporting of the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks includes: Before reporting any completed decoding tasks in the first priority order, report all completed decoding tasks in the second priority order. The method according to claim 14, further comprising: after a predetermined duration after queuing the completed decoding tasks in the first task completion queue, prioritizing the completed decoding tasks The level is changed from the first priority order to the second priority order. The method according to claim 13, wherein the reporting of the completed decoding tasks from the first task completion queue and the second task completion queue according to the priority order of the completed decoding tasks includes: After reporting a predetermined number of tasks from the completion queue of the second task, report the tasks from the completion queue of the first task. The method according to claim 8, wherein the corresponding decoding task of the plurality of decoding tasks is released from the corresponding first task queue and the corresponding second task queue to be based on The priority order of the corresponding decoding task in the task to operate on the corresponding part in the data part includes: releasing all decoding tasks in the second priority order before releasing any decoding tasks in the first priority order . The method according to claim 17, further comprising: changing the priority level of the decoding task from the first priority order after a predetermined duration after the queuing of the decoding task in the first task queue Is the second priority order. The method according to claim 8, wherein the corresponding decoding task of the plurality of decoding tasks is released from the corresponding first task queue and the corresponding second task queue to be based on The priority sequence of the corresponding decoding task in the task to operate the corresponding part in the data part includes: after releasing a predetermined number of tasks from the corresponding second task queue, releasing the tasks from the corresponding second task queue. A task in a task queue.

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