TWI713044B - Memory device and memory peripheral circuit - Google Patents

Abstract

A memory device and a memory peripheral circuit are provided. The memory peripheral circuit includes a redundancy column data circuit and a column selection control circuit. The redundancy column data circuit is configured to provide a redundancy test mode data signal and a column address signal. The column address signal includes a redundancy column address signal. The column selection control circuit includes a column decoder and a redundancy column decoder. The column decoder disables a bad column address of a main memory block according to the redundancy test mode data signal and the redundancy column address signal. The redundancy column decoder latches redundancy column address signal and compares the column address signal with the latched redundancy column address to obtain a comparison result, and enables a redundancy column address of a redundancy memory block according to the comparison result.

Description

Memory device and memory peripheral circuit

The present invention relates to a memory device and a memory peripheral circuit, and more particularly to a memory device and a memory peripheral circuit in which a bad row address is replaced with a redundant row address.

In the redundant row operation of a general memory device, a metal fuse can be configured in each row decoder, and the bad row address can be disabled by turning on or blowing the metal fuse. However, once the metal fuse is blown or turned on, it cannot return to the state before the redundant row operation. In addition, the metal fuse requires a large space for disposition, and it is difficult to apply it to a miniaturized memory device.

The invention provides a memory device and a memory peripheral circuit. The memory peripheral circuit of the memory device is configured to disable the bad row address of the memory device, thereby replacing the conventional metal fuse.

The memory peripheral circuit of the present invention is coupled to the memory array. The memory peripheral circuit includes a redundant row data circuit and a row selection control circuit. The redundant row data circuit stores redundant row information, and provides redundant test data signals and row address signals based on the redundant row information. The row address signals include redundant row address signals. The row selection control circuit is coupled between the redundant row data circuit and the memory array. The row selection control circuit receives the redundant test data signal and the row address signal. The row selection control circuit includes a row decoder and a redundant row decoder. The row decoder is coupled between the main memory block of the memory array and the redundant row data circuit. The row decoder disables the bad row address of the main memory block according to the redundant test data signal and the redundant row address signal. The redundant row decoder is coupled between the redundant memory block of the memory array and the redundant row data circuit. The redundant row decoder latches the redundant row address signal according to the redundant test data signal, compares the row address signal with the latched redundant row address signal to obtain the comparison result, and activates the redundant memory according to the comparison result The redundant row address of the body block.

The memory device of the present invention includes a memory array and the aforementioned memory peripheral circuit. The memory array includes a main memory block and a redundant memory block.

Based on the above, the memory peripheral circuit of the memory device of the present invention disables the bad row address of the main memory block according to the redundant test data signal and the row address signal, and enables the redundant row of the redundant memory block Address. In this way, the memory peripheral circuit can replace the decoder and the metal fuse, thereby reducing the layout space of the peripheral circuit and recovering the state before the redundant row operation.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1, the memory device 10 includes a memory peripheral circuit 100 and a memory array 200. The memory peripheral circuit 100 includes a redundant row data circuit 110 and a row selection control circuit 120. The memory array 200 includes a main memory block 210 and a redundant memory block 220. The redundant row data circuit 110 is used to store the redundant row information CRD. The redundant row information CRD records the bad row addresses detected by the main memory block 210 during the testing phase. The redundant row data circuit 110 provides redundant test data signals TRDB1, TRDB2 and a row address signal YA to the row selection control circuit 120 according to the redundant row information CRD. The row address signal YA includes a redundant row address signal, which is a row address signal YA corresponding to the redundant test data signals TRDB1 and TRDB2. The row selection control circuit 120 is coupled between the redundant row data circuit 110 and the memory array 200. The row selection control circuit 120 disables the defective row address of the main memory block 210 according to the redundant test data signals TRDB1, TRDB2 and the redundant row address signal of the row address signal YA, and enables the redundant memory block 220 The redundant row address.

2, the redundant row data circuit 110 includes a redundant clock generating circuit 112, a redundant row data and timing generating circuit 114, a bank address signal generating circuit 116 and a row address signal generating circuit 118. The row selection control circuit 120 includes a pre-row decoder 122, a row decoder 124, a redundant row decoder 126, and a post-redundant row decoder 128. The pre-row decoder 122 is coupled between the redundant row data circuit 110 and the row decoder 124. The redundant clock generating circuit 112 is used for receiving the global reset signal RESETB to provide the redundant test clock TRICLK to the redundant row data and timing generating circuit 114. The redundant clock generating circuit 112 is also used to provide a local reset signal RESETBD to the row selection control circuit 120. The row selection control circuit 120 is used for resetting the row decoder 124 and the redundant row decoder 126 according to the first logic level of the local reset signal RESETBD. Thereby, the row decoder 124 and the redundant row decoder 126 are restored to the state before the redundant row operation. The row selection control circuit 120 is also used to initialize the row decoder 124 and the redundant row decoder 126 according to the transition point of the local reset signal RESETBD, so that the row decoder 124 and the redundant row decoder 126 start to perform redundant row operations .

The redundant row data and timing generating circuit 114 is coupled to the redundant clock generating circuit 112, the bank address generating circuit 116, the row address generating circuit 118, and the row selection control circuit 120. The redundant row data and timing generating circuit 114 is used to store redundant row information, and provide a redundant area address signal RXA13, a redundant bank address signal RBAm, and a redundancy corresponding to the redundant row information according to the redundant test clock TRICLK The switching signal RCSW and the redundancy mode command RCCMD are sent to the library address signal generating circuit 116. The redundant row data and timing generating circuit 114 provides the redundant row address signal RCYAj, the redundant switching signal RCSW, and the redundant mode command RCCMD to the row address signal generating circuit 118 according to the redundant test clock TRICLK.

The bank address signal generating circuit 116 receives the redundant area address signal RXA13, the redundant bank address signal RBAm, the redundant switch signal RCSW and the redundancy mode command RCCMD, and according to the bank address signal BAm, the area address signal CXA13, read/ The write command RWCMD and the address buffer control signal ADBC provide the bank selection signal BNKSk and the area selection signals XAD13Nk, XAD13Tk.

The row address signal generating circuit 118 receives the read/write row address signal CYAj, the redundant row address signal RCYAj, the redundant switch signal RCSW, the read/write command RWCMD, and the redundant mode command RCCMD, and thereby generates the row address signal YAj and row selection drive signal CSLD.

In the embodiment of FIG. 2, the pre-row decoder 122 is used to decode the row address signal YAj. The row decoder 124 is coupled between the redundant row data circuit 110 and the main memory block 210. The row decoder 124 can select the row address CSLrk in the main memory block according to the row address signal YAj. The row decoder 124 also disables the bad row address of the main memory block 210 according to the redundant test data signals TRDB1, TRDB2 and the redundant row address signal RCYAj in the row address signal YAj. The redundant row decoder 126 is coupled between the redundant row data circuit 110 and the post redundant row decoder 128. The redundant row decoder 126 is used to latch the redundant row address signal RCYAj according to the redundant test data signals TRDB1 and TRDB2, and compare the row address signal YAj with the latched redundant row address signal RCYAj to obtain a comparison result , And activate the redundant row address RCSLnk of the redundant memory block 220 according to the comparison result. The rear redundant row decoder 128 is used for selecting the redundant row address RCSLnk corresponding to the redundant row address signal RCYAj according to the redundant row address signal RCYAj provided by the redundant row decoder 126. In this embodiment, m is equal to 0~2, k is equal to A~H, j is equal to 3~8, r is equal to 0~36, and n is equal to 0~3, but it is not limited to this.

Further, the library address signal generating circuit 116 further includes a library address signal buffer 1162, a library address signal selector 1164, and an area address signal buffer and selector 1166. Please refer to FIG. 3, the library address signal buffer 1162 includes inverter gates A01~A10, transmission gates T01~T04, and latch circuits L01 and L02. The input terminal of the inverter gate A01 is used to receive the bank address signal BAm. The output terminal of the inverter gate A01 is coupled to the input terminal of the transmission gate T01. The input terminal of the inverter gate A02 is used to receive the read/write command RWCMD. The output terminal of the inverter gate A02 is coupled to the P channel gate of the transmission gate T01 and the input terminal of the inverter gate A03. The output terminal of the inverter gate A03 is coupled to the N-channel gate of the transmission gate T01. The output terminal of the transmission gate T01 is coupled to the input terminal of the latch circuit L01. The input terminal of the inverter gate A04 is used to receive the redundant bank address signal RBAm. The output terminal of the inverter gate A04 is coupled to the input terminal of the transmission gate T02. The input terminal of the inverter gate A05 is used to receive the redundancy mode command RCCMD. The output terminal of the inverter gate A05 is coupled to the P channel gate of the transmission gate T02 and the input terminal of the inverter gate A06. The output terminal of the inverter gate A06 is coupled to the N-channel gate of the transmission gate T02. The output terminal of the transmission gate T02 is coupled to the input terminal of the latch circuit L02. The input terminal of the inverter gate A07 is used to receive the redundancy switching signal RCSW. The output terminal of the inverter gate A07 is coupled to the N channel gate of the transmission gate T03, the input terminal of the inverter gate A08 and the P channel gate of the transmission gate T04. The output terminal of the inverter gate A08 is coupled to the P channel gate of the transmission gate T03 and the N channel gate of the transmission gate T04. The output terminal of the latch circuit L01 is coupled to the input terminal of the transmission gate T03. The output terminal of the latch circuit L02 is coupled to the input terminal of the transmission gate T04. The latch circuit L01 includes inverter gates A11 and A12. The input terminal of the inverter gate A11 is coupled to the output terminal of the inverter gate A12 and the output terminal of the transmission gate T01. The output terminal of the inverter gate A11 is coupled to the input terminal of the inverter gate A12 and the input terminal of the transmission gate T03. The latch circuit L02 includes inverter gates A13 and A14. The input terminal of the inverter gate A13 is coupled to the output terminal of the inverter gate A14 and the output terminal of the transmission gate T02. The output terminal of the inverter gate A13 is coupled to the input terminal of the inverter gate A14 and the input terminal of the transmission gate T04. The output terminals of the transmission gates T03 and T04 are used to output the selected bank address signal BNKAm through the inverter gates A09 and A10. In this embodiment, m is equal to 0~2.

In the embodiment of FIG. 3, the transmission gate T01 is controlled by the read/write command RWCMD, and the transmission gate T02 is controlled by the redundancy mode command RCCMD. When the library address signal buffer 1162 receives the read/write command RWCMD with a high logic level, the library address signal buffer 1162 can latch the library address signal BAm corresponding to the read/write command RWCMD in the latch circuit L01. When the library address signal buffer 1162 receives the high logic level redundancy mode command RCCMD, the library address signal buffer 1162 can latch the redundancy library address signal RBAm corresponding to the redundancy mode command RCCMD in the latch circuit L02. The transmission gates T03 and T04 are controlled by the redundancy switching signal RCSW. When the library address signal buffer 1162 receives the low logic level redundancy switch signal RCSW, it uses the library address signal BAm latched in the latch circuit L01 as the selected library address signal BNKAm, and passes through the transmission gate T03 and The path of inverter gates A09 and A10 outputs the selected bank address signal BNKAm. Conversely, when the library address signal buffer 1162 receives the high logic level redundant switching signal RCSW, the redundant library address signal RBAm latched in the latch circuit L02 is used as the selected library address signal BNKAm, and The selected bank address signal BNKAm is output through the path of transmission gate T04 and inverter gates A09 and A10.

Referring to FIG. 4, the library address signal selector 1164 is used to receive the selected library address signals BNKA0~BNKA2, and generate the library selection signal BNKSk according to the selected library address signals BNKA0~BNKA2. In this embodiment, the library address signal selector 1164 may be implemented by a demultiplexer (demultiplexer). The library address signal selector 1164 includes inverter gates B01~B11 and inverter gates BNAND1~BNAND8.

The multiple input terminals of the inverter BNAND1 respectively receive the selected bank addresses BNKA0~BNKA2. The output terminal of the inverter gate BNAND1 is coupled to the input terminal of the inverter gate B04. The output terminal of the inverter gate B04 is used to output the bank selection signal BNKSH. The inverter gate BNAND2 receives the selected bank address signal BNKA1~BNKA2 and is coupled to the output terminal of the inverter gate B01 to receive the inverted bank address signal BNKA0. The output terminal of the inverter gate BNAND2 is coupled to the input terminal of the inverter gate B05. The output terminal of the inverter gate B05 is used to output the bank selection signal BNKSG, and so on.

Please refer to FIG. 5, the zone address signal buffer and selector 1166 includes a zone address signal buffer 1166_1 and a zone address signal selector 1166_2. The area address signal buffer 1166_1 is used to receive and generate an area selection signal XA13k corresponding to the bank address signal BAm according to the bank address signal BAm, the area address signal CXA13 and the address buffer control signal ADBC.

The zone address signal selector 1166_2 includes inverter gates C01 to C08, transmission gates T05 to T07, and a latch circuit L03. The input terminal of the inverter gate C01 is used to receive the redundant area address signal RXA13. The output terminal of the inverter gate C01 is coupled to the input terminal of the transmission gate T05. The input terminal of the inverter gate C02 is used to receive the redundancy mode command RCCMD. The output terminal of the inverter gate C02 is coupled to the P channel gate of the transmission gate T05 and the input terminal of the inverter gate C03. The output terminal of the inverter gate C03 is coupled to the N-channel gate of the transmission gate T05. The output terminal of the transmission gate T05 is coupled to the input terminal of the latch circuit L03. The input terminal of the inverter gate C04 is used to receive the redundancy switching signal RCSW. The output terminal of the inverter gate C04 is coupled to the N-channel gate coupled to the transmission gate T06, the input terminal of the inverter gate C05, and the P-channel gate of the transmission gate T07. The output terminal of the inverter gate C05 is coupled to the P channel gate of the transmission gate T06 and the N channel gate of the transmission gate T07. The input terminal of the transmission gate T06 is used to receive the zone selection signal XA13k provided by the zone address signal buffer 1166_1. The input terminal of the transmission gate T07 is coupled to the output terminal of the latch circuit L03. The output terminals of the transmission gates T06 and T07 are coupled to the inverter gates C06 and C07, wherein the zone selection signal XAD13Nk is output through the inverter gate C06, and the zone selection signal XAD13Tk is output through the inverter gate C07 and C08. The logic levels of the zone selection signals XAD13Nk and XAD13Tk are opposite to each other. The latch circuit L03 includes inverter gates C09 and C10. The input terminal of the inverter gate C09 is coupled to the output terminal of the inverter gate C10 and the output terminal of the transmission gate T05. The output terminal of the inverter gate C09 is coupled to the input terminal of the inverter gate C10 and the input terminal of the transmission gate T07.

In the embodiment of FIG. 5, the transmission gate T05 is controlled by the redundant mode command RCCMD. When the zone address signal selector 1166_2 receives the high logic level redundancy mode command RCCMD, the zone address signal selector 1166_2 can latch the redundancy zone address signal RXA13 corresponding to the redundancy mode command RCCMD in the latch circuit L03. The transmission gates T06 and T07 are controlled by the redundancy switching signal RCSW. When the zone address signal selector 1166_2 receives the low logic level redundancy switching signal RCSW, it uses the zone selection signal XA13k provided by the zone address signal buffer 1166_1 as the zone selection signals XAD13Nk, XAD13Tk, and outputs it via the path of the transmission gate T06 Zone selection signals XAD13Nk, XAD13Tk. Conversely, when the zone address signal selector 1166_2 receives the redundancy switch signal RCSW with a high logic level, it uses the redundancy zone address signal RXA13 latched in the latch circuit L03 as zone selection signals XAD13Nk, XAD13Tk, and passes through the transmission gate. T07 path output area selection signal XAD13Nk, XAD13Tk.

Please refer to FIG. 6, the row address signal generating circuit 118 includes a row address signal buffer 1181 and a row selection driving signal generator 1182. The row address signal buffer 1181 includes inverter gates D01 to D10, transmission gates T08 to T11, and latch circuits L04 and L05. The input terminal of the inverter gate D01 is used to receive the read/write row address signal CYAj. The output terminal of the inverter gate D01 is coupled to the input terminal of the transmission gate T08. The input terminal of the inverter gate D02 is used to receive the read/write command RWCMD. The output terminal of the inverter gate D02 is coupled to the P channel gate of the transmission gate T08 and the input terminal of the inverter gate D03. The output terminal of the inverter gate D03 is coupled to the N-channel gate of the transmission gate T08. The output terminal of the transmission gate T08 is coupled to the input terminal of the latch circuit L04. The input terminal of the inverter gate D04 is used to receive the redundant row address signal RCYAj. The output terminal of the inverter gate D04 is coupled to the input terminal of the transmission gate T09. The input terminal of the inverter gate D05 is used to receive the redundancy mode command RCCMD. The output terminal of the inverter gate D05 is coupled to the P channel gate of the transmission gate T09 and the input terminal of the inverter gate D06. The output terminal of the inverter gate D06 is coupled to the N-channel gate of the transmission gate T09. The output terminal of the transmission gate T09 is coupled to the input terminal of the latch circuit L05. The input terminal of the inverter gate D07 is used to receive the redundancy switching signal RCSW. The output terminal of the inverter gate D07 is coupled to the N channel gate of the transmission gate T10, the input terminal of the inverter gate D08 and the P channel gate of the transmission gate T11. The output terminal of the inverter gate D08 is coupled to the P channel gate of the transmission gate T010 and the N channel gate of the transmission gate T11. The output terminal of the latch circuit L04 is coupled to the input terminal of the transmission gate T10. The output terminal of the latch circuit L05 is coupled to the input terminal of the transmission gate T11. The latch circuit L04 includes inverter gates D11 and D12. The input terminal of the inverter gate D11 is coupled to the output terminal of the inverter gate D12 and the output terminal of the transmission gate T08. The output terminal of the inverter gate D11 is coupled to the input terminal of the inverter gate D12 and the input terminal of the transmission gate T10. The latch circuit L05 includes inverter gates D13 and D14. The input terminal of the inverter gate D13 is coupled to the output terminal of the inverter gate D14 and the output terminal of the transmission gate T09. The output terminal of the inverter gate D13 is coupled to the input terminal of the inverter gate D14 and the input terminal of the transmission gate T11. The output terminals of the transmission gates T10 and T11 are used to output the row address signal YAj through the inverter gates D09 and D10. In this embodiment, j is equal to 3-8.

In the embodiment of FIG. 6, the transmission gate T08 is controlled by the read/write command RWCMD, and the transmission gate T09 is controlled by the redundant mode command RCCMD. When the row address signal buffer 1181 receives a high logic level read/write command RWCMD, the row address signal buffer 1181 can latch the read/write row address signal CYAj corresponding to the read/write command RWCMD in the latch Circuit L04. When the row address signal buffer 1181 receives the high logic level redundancy mode command RCCMD, the row address signal buffer 1181 can latch the redundancy row address signal RCYAj corresponding to the redundancy mode command RCCMD in the latch circuit L05. The transmission gates T10 and T11 are controlled by the redundancy switching signal RCSW. When the row address signal buffer 1181 receives the low logic level redundancy switching signal RCSW, it uses the read/write row address signal CYAj latched in the latch circuit L04 as the row address signal YAj, and passes through the transmission gate T10 And the path of inverter gates D09 and D10 output row address signal YAj. Conversely, when the row address signal buffer 1181 receives the high logic level redundancy switching signal RCSW, it uses the redundancy row address signal RCYAj latched in the latch circuit L05 as the row address signal YAj, and passes The path of the transmission gate T11 and inverter gates D09 and D10 outputs a row address signal YAj.

The row selection driving signal generator 1182 receives the read/write command RWCMD and the redundancy mode command RCCMD, and generates the row selection driving signal CSLD accordingly. The row selection driving signal CSLD is used to enable the row selection control circuit 120. In this embodiment, the row selection driving signal generator 1182 includes inverter gates D15 to D17, inverter gates DNAND1, delays DL1, DL2, and inverter gate NOR1. The input terminal of the inverter gate D15 is used to receive the read/write command RWCMD. The input terminal of the inverter gate D16 is used to receive the redundancy mode command RCCMD. The output terminals of the inverter gates D15 and D16 are respectively coupled to the first input terminal and the second input terminal of the inverter gate DNAND1. The output terminal of the inverter gate DNAND1 is coupled to the first input terminal of the inverter gate NOR1 and the input terminal of the delay DL1. The output terminal of the delay DL1 is coupled to the second input terminal of the NOR gate NOR1. The output terminal of the inverting gate NOR1 is coupled to the input terminal of the inverter gate D17 via the delay DL2. The output terminal of the inverter gate D17 is used to output the row selection driving signal CSLD.

When at least one of the read/write command RWCMD and the redundancy mode command RCCMD is at a high logic level, the row selection driving signal generator 1182 can generate a high logic level row selection driving signal CSLD. Among them, the delays DL1, DL2, the inverting gate DNOR1, and the inverter gate D17 can extend the time that the row selection driving signal CSLD is at the high logic level to ensure that the row selection control circuit 120 has a sufficient enabling time.

Please refer to FIG. 7, the pre-row decoder 122 may be implemented by at least one demultiplexer. The pre-row decoder 122 includes inverter gates ENAND1 to ENAND9 and inverter gates E01 to E12. The reverse gate ENAND1 receives the row selection drive signal CSLD and the bank selection signal BNKSk. The output terminal of the inverter gate ENAND1 is coupled to the input terminal of the inverter gate E01. The output terminal of the inverter gate E01 is coupled to one of the input terminals of the inverter gates ENAND6 to ENAND9, so as to enable or disable the pre-row decoder 122 according to the row selection driving signal CSLD and the bank selection signal BNKSk. The other input terminals of the inverters ENAND6~ENAND9 receive the row address signal YAj. The input terminals of the inverters ENAND2~5 respectively receive the row address signal YAj, for example, the row address signal YA3~YA5. The inverter ENAND3 receives the row address signal YA3 through the inverter E02, and the inverter ENAND4 transmits it. The inverter gate E03 receives the row address signal YA4, and the inverter gate ENAND5 receives the row address signals YA3 and YA4 through the inverter gates E02 and E03. The output terminals of the inverter gates ENAND2-9 are respectively coupled to the input terminals of the inverter gates E05-E12. The output terminals of the inverter gates E05~E12 respectively output pre-decoded row address signals YPD3T4T5Tk~YPD3N4N5Nk. The pre-decoded row address signals corresponding to the row address signals YA6~YA8 can also be deduced in this way. In this embodiment, the pre-decoded row address signal YPD3N4T5Tk is the row address signal corresponding to the bank selection signal BNKSk.

Please refer to FIG. 8, when the redundant switching signal RCSW is at a high logic level, the row address signal YAj received by the row decoder 124 is a redundant row address signal. The row decoder 124 includes a row decoding logic circuit FLC, a row decoding buffer YDB, and redundant test data signal latch circuits FL1 and FL2. The row decoding logic circuit FLC of this embodiment may include an inverter FNAND1. The row decoding logic circuit FLC is used to receive redundant row address signals (or pre-decoded row address signals, such as YPD3N4T5Tk, YPD6N7T8Tk) and the redundancy latched in the redundant test data signal latch circuits FL1/FL2 Test data signals TRDB1/TRDB2, and perform logical operations accordingly. The row decoding buffer YDB is coupled to the output terminal of the row decoding logic circuit FLC, and disables the bad row address of the main memory block 210 according to the logic operation result of the row decoding logic circuit FLC.

The redundant test data signal latch circuit FL1 receives the redundant test data signal TRDB1, the local reset signal RESETBD, and the zone selection signals XAD13Nk, XAD13Tk, and also receives the logical operation result provided by the row decoding logic circuit FLC. The redundant test data signal latch circuit FL1 latches the redundant test data signal TRDB1 according to the local reset signal RESETBD and the logical operation result, and outputs the latched redundant test data signal TRDB1 to row decoding according to the zone selection signals XAD13Nk and XAD13Tk Logic circuit FLC. The redundant test data signal latch circuit FL2 receives the redundant test data signal TRDB2, the local reset signal RESETBD, and the zone selection signals XAD13Nk, XAD13Tk, and also receives the logical operation result provided by the row decoding logic circuit FLC. The redundant test data signal latch circuit FL2 latches the redundant test data signal TRDB2 according to the local reset signal RESETBD and the logical operation result, and outputs the latched redundant test data signal TRDB2 to row decoding according to the zone selection signals XAD13Nk and XAD13Tk Logic circuit FLC. The number of redundant test data signal latch circuits of the present invention depends on the number of zones divided by each bank in the main memory block, and the number of redundant test data signal latch circuits of the present invention can be performed according to the number of zones The adjustment is not limited to this embodiment.

Taking the redundant test data signal latch circuit FL1 as an example, the redundant test data signal latch circuit FL1 includes a flip-flop circuit FF1, an inverter FNOR1, a transistor M1, and a transmission gate FT1. The flip-flop circuit FF1 receives and initializes the flip-flop circuit FF1 according to the local reset signal RESETBD. The first input terminal of the NOR gate FNOR1 is coupled to the output terminal of the row decoding logic circuit FLC. The second input terminal of the NOR gate FNOR1 receives the redundant test data signal TRDB1. In this embodiment, the flip-flop circuit FF1 includes an inverter gate FNAND2 and an inverter gate F01. The first input terminal of the inverter FNAND2 receives the local reset signal RESETBD, and the output terminal of the inverter FNAND2 is coupled to the input terminal of the transmission gate FT1 and the first terminal of the transistor M1. The input terminal of the inverter gate F01 is coupled to the output terminal of the inverter gate FNAND2, and the output terminal of the inverter gate F01 is coupled to the second input terminal of the inverter gate FNAND2. The control terminal of the transistor M1 is coupled to the output terminal of the inverter FNOR1, the first terminal of the transistor M1 is coupled to the output terminal of the flip-flop circuit FF1, and the second terminal of the transistor M1 is coupled to the reference voltage VSS.

The transmission gate FT1 is controlled by the zone selection signals XAD13Nk, XAD13Tk, the input terminal of the transmission gate FT1 is coupled to the output terminal of the flip-flop circuit FF1, and the output terminal of the transmission gate FT1 is coupled to the input terminal of the row decoding logic circuit FLC according to The zone selection signals XAD13Nk and XAD13Tk output the latched redundant test data signal TRDB1 to the row decoding logic circuit FLC. In this embodiment, the P-channel gate of the transmission gate FT1 is used to receive the zone selection signal XAD13Tk, and the N-channel gate of the transmission gate FT1 is used to receive the zone selection signal XAD13Nk. Therefore, when the N channel gate of the transmission gate FT1 receives the high logic level zone selection signal XAD13Nk, the P channel gate of the transmission gate FT1 will receive the low logic level zone selection signal XAD13Tk and output the latched The redundant test data signal TRDB1 is sent to the row decoding logic circuit FLC. Conversely, when the N-channel gate of the transmission gate FT1 receives the low logic level zone selection signal XAD13Nk, the transmission gate FT1 will not output the latched redundant test data signal TRDB1.

In detail, when the local reset signal RESETBD is at the low logic level, the output terminal of the flip-flop circuit FF1 is maintained at the high logic level, which is regarded as the state before the redundant row operation. When the local reset signal RESETBD transitions from a low logic level to a high logic level, the flip-flop circuit FF1 can be based on the logic level of the redundant test data signal TRDB1 and the received row address signal YAj decides whether to latch the redundant test data signal TRDB1. When the redundant test data signal TRDB1 is at a low logic level, it means that the row address signal YAj corresponding to the redundant test data signal TRDB1 is judged as a bad row address signal during the test. The invertor gate FNOR1 will output the result of the high logic level due to the low logic level redundant test data signal TRDB1 and the bad row address, thereby turning on the transistor M1 so that the voltage at the output terminal of the flip-flop circuit FF1 is Pull down to the reference voltage VSS. The decoding buffer YDB performs an inversion operation on the logic operation result of the decoding logic circuit FLC, thereby providing a signal with a low logic level. In this way, the row decoder 124 will not output a bad row address signal through the row decode buffer YDB and the row decode logic circuit FLC, thereby disabling the bad row address of the main memory block 210, that is, the row decoder 124 The bad row address of the main memory block 210 is not provided as the row address for data access. Conversely, when the redundant test data signal TRDB1 is at a high logic level, the transistor M1 will be disconnected. At this time, the voltage at the output terminal of the flip-flop circuit FF1 will not be pulled down to the reference voltage VSS, and the corresponding row address CSLrk is provided. On the other hand, when the high logic level of the local reset signal RESETBD is pulled down to the low logic level, the logic level of the output terminal of the redundant test data signal latch circuit FL1 will be reset to return to the high logic level .

It is worth mentioning here that the layout area of the redundant test data signal latch circuit FL1 can be smaller than that of the metal fuse. Therefore, replacing the metal fuse with the redundant test data signal latch circuit FL1 can effectively reduce the layout area of the peripheral circuit of the memory. Moreover, by pulling down the high logic level of the local reset signal RESETBD to the low logic level, the redundant test data signal latch circuit FL1 can be reset to restore to the state before the bad row address is disabled.

Please refer to FIG. 2 and FIG. 9, the redundant row decoder 126 further includes a redundant row selection signal generator 1262. Wherein, the redundant row selection signal generator 1262 may be implemented by a demultiplexer. The redundant row selection signal generator 1262 includes inverter gates G01~G12 and inverter gates GNAND1~GNAND8. The inverter gate G01 receives the redundant row selection signal TRSEL1 and outputs it to inverter gates GNAND2, GNAND4, GNAND6, and GNAND8. The inverter gate G02 receives the redundant row selection signal TRSEL2 and outputs it to inverter gates GNAND3~GNAND5, GNAND7, GNAND8. The inverter gate G03 receives the redundant test data signal TRDB1 and outputs it to inverter gates GNAND1~GNAND4. The inverter gate G04 receives the redundant test data signal TRDB2 and outputs it to inverter gates GNAND5~GNAND8. The inverter gates GNAND1~GNAND8 directly or indirectly (via inverter gates G01, G02) receive the redundant row selection signals TRSEL1 and TRSEL2. The reverse gates GNAND1~GNAND8 also receive the bank selection signal BNKSk. The output terminals of the inverter gates GNAND1~GNAND8 are respectively coupled to the input terminals of the inverter gates G05~G12. The output terminals of the inverter gates G05~G12 respectively output redundant row selection signals TRDS0k~TRDS7k. That is, in this embodiment, the redundant row selection signal generator 1262 can provide redundant row selection signals TRDS0k~TRDS3k according to the redundant row selection signals TRSEL1, TRSEL2, the bank selection signal BNKSk, and the redundant test data signal TRDB1. Similarly, the redundant row selection signal generator 1262 also provides redundant row selection signals TRDS4k to TRDS7k according to the redundant row selection signals TRSEL1, TRSEL2, the bank selection signal BNKSk, and the redundant test data signal TRDB2.

Please refer to FIG. 10, based on each bank in the main memory block 210 and the redundant memory block 220 is divided into two areas, and two redundant row decoders 126_1 and 126_2 are configured. Taking the redundant row decoder 126_1 as an example, the redundant row decoder 126_1 includes judgment circuits HD1 to HD6 and a redundant row decoding logic circuit HLC. Each judgment circuit HD1~HD6 is used to receive the redundant row selection signal TRDSmk, the local reset signal RESETBD and the row address signal YA3~YA8. Taking the judgment circuit HD1 as an example, the judgment circuit HD1 can use the corresponding row address signal YA3 as the redundant row address signal and latch the redundant row address signal according to the redundant row selection signal TRDSmk, and provide the row position. The comparison result of the address signal YA3 and the redundant row address signal is sent to the redundant row decoding logic circuit HLC. The redundant row decoding logic circuit HLC activates the redundant row address RCSLnk of the redundant memory block 220 corresponding to the redundant row address signal according to the comparison results provided by the judgment circuits HD1 to HD6.

The circuit structure of the judgment circuit HD1~HD6 is further explained. Please refer to FIG. 11, taking the judgment circuit HD1 as an example. The judgment circuit HD1 includes a redundant row address signal latch circuit FADL1 and a judgment logic circuit JLC1. The redundant row address signal latch circuit FADL1 is used to use the corresponding row address signal YA3 as the redundant row address signal according to the redundant row selection signal TRDSmk, and to latch the redundant row address signal. The first input terminal of the judgment logic circuit JLC1 is used to receive the row address signal YA3, the second input terminal of the judgment logic circuit JLC1 is coupled to the redundant row address signal latch circuit FADL1, and the output terminal of the judgment logic circuit JLC1 is coupled At one of the input terminals of the redundant row decoding logic circuit HLC. When the judgment logic circuit JLC1 receives the row address signal YA3, the judgment logic circuit JLC1 can judge whether the row address signal YA3 is equal to the redundant row address signal latched in the redundant row address signal latch circuit FADL1, and provide The corresponding judgment result. For example, the judgment logic circuit JLC1 may be a mutually exclusive inverted OR gate XNOR1. When the judgment logic circuit JLC1 judges that the row address signal YA3 is the same as the redundant row address signal, the judgment result provided is a high logic level signal. Conversely, when the judgment logic circuit JLC1 judges that the row address signal YA3 is different from the redundant row address signal, the judgment result provided is a low logic level signal.

The redundant row address signal latch circuit FADL1 includes an inverter gate H01, a H02 transmission gate FADLT1, and a flip-flop circuit HF1. The input terminal of the inverter gate H01 is used to receive the row address signal YA3. The input terminal of the transmission gate FADLT1 is coupled to the output terminal of the inverter gate H01, so as to receive the row address signal YA3 through the inverter gate H01. The P channel gate of the transmission gate FADLT1 is used to receive the redundant row selection signal TRDSmk through the inverter gate H03, and the N channel gate of the transmission gate FADLT1 is used to receive the redundant row selection signal TRDSmk. The flip-flop circuit HF1 is coupled between the transmission gate FADLT1 and the judgment logic circuit JLC1. The transmission gate FADLT1 stops transmitting the row address signal YA3 to the flip-flop circuit HF1 according to the redundant row selection signal TRDSmk of the low logic level. Or, the transmission gate FADLT1 transmits the row address signal YA3 corresponding to the redundant row selection signal TRDSmk according to the redundant row selection signal TRDSmk at a high logic level (the row address signal YA3 is the redundant row address signal at this time ) To the flip-flop circuit HF1, so that the flip-flop circuit HF1 latches the redundant row address signal. The flip-flop circuit HF1 is also used to receive the local reset signal RESETBD, and reset or initialize the flip-flop circuit HF1 according to the local reset signal RESETBD.

The circuit structure of other judgment circuits (such as HD2~HD6) can be similar to the judgment circuit HD1. The difference from the judgment circuit HD1 is that the judgment circuit HD2 is used to receive the row address signal YA4, the judgment circuit HD3 is used to receive the row address signal YA5, and so on.

Please refer to FIG. 10 again, the redundant row decoder 126_1 may further include an enabling signal generating circuit. In this embodiment, the enabling signal generation circuit can be implemented by the inverter HNAND3 and the inverter H04. The inverter HNAND3 is used to receive the row selection driving signal CSLD, the bank selection signal BNKSk, and the area selection signal XAD13Nk. The enabling signal generation circuit can provide the enabling signal to the redundant row decoding logic circuit HLC according to the row selection driving signal CSLD, the bank selection signal BNKSk and the area selection signal XAD13Nk. The enabling signal generation circuit can also be further added with a redundant row address signal latch circuit FADL7. Different from the redundant row address signal latch circuit FADL1, the redundant row address signal latch circuit FADL7 does not receive the row address signal YAj, but receives the system voltage VDD. The enabling signal generating circuit can provide another enabling signal to the redundant row decoding logic circuit HLC according to the redundant row selection signal TRDSmk.

The design of the redundant row decoder 126_2 is similar to the redundant row decoder 126_1. The difference between the redundant row decoder 126_2 and the redundant row decoder 126_1 is that the enable signal generation circuit of the redundant row decoder 126_2 is based on row selection The driving signal CSLD, the bank selection signal BNKSk, and the area selection signal XAD13Tk provide an enabling signal to the redundant row decoding logic circuit HLC.

The redundant row decoders 126_1, 126_2 provide the comparison result to the selector SELC. The selector SELC of this embodiment includes transmission gates HT1, HT2 and inverter gates H05. The transmission gate HT1 is coupled between the redundant row decoder 126_1 and the inverter gate H05. The transmission gate HT2 is coupled between the redundant row decoder 126_2 and the inverter gate H05. The transmission gate HT1 can receive the high logic level zone selection signal XAD13Nk and the low logic level zone selection signal XAD13Tk to transmit the comparison result provided by the redundant row decoder 126_1. The transmission gate HT2 can receive the low logic level zone selection signal XAD13Nk and the high logic level zone selection signal XAD13Tk to transmit the comparison result provided by the redundant row decoder 126_2. The inverter gate H05 is used to output the comparison result provided by the redundant row decoder 126_1/126_2. In other words, the selector SELC selects the comparison results provided by the redundant row decoders 126_1/126_2 according to the zone selection signals XAD13Nk and XAD13Tk. In this embodiment, the comparison result is the decoded redundant row address signal RYPDnk.

Please refer to FIG. 12, the post redundant row decoder 128 includes an inverter K01 and a buffer KB. The post redundant row decoder 128 is used for selecting the redundant row address RCSLnk corresponding to the decoded redundant row address signal RYPDnk according to the decoded redundant row address signal RYPDnk.

Please refer to Figure 2 and Figure 13 at the same time. In this embodiment, when the global reset signal RESETB transitions from a low logic level to a high logic level, the redundancy test clock TRICLK, the redundancy switching signal RCSW, and the redundancy The mode command RCCMD also starts to be generated. When the redundancy switch signal RCSW and the redundancy mode command RCCMD are at a high logic level, the row address signal received by the row selection control circuit 120 is a redundant row address signal, and the row selection drive signal CSLD is raised to a high logic level Level. When the row selection driving signal CSLD is raised to a high logic level and when one of the redundant test data signals TRDB1 and TRDB2 is at a low logic level, the row decoder 124 will respond to the redundant row address signal RCYAj and the redundant The remaining test data signals TRDB1 and TRDB2 disable bad row addresses in the main memory block 210, where j is equal to 0-7. In addition, the redundant row decoder 126 also provides a redundant row selection signal TRDSmk according to the redundant test data signals TRDB1/TRDB2 and the redundant row selection signals TRSEL1 and TRSEL2. And the redundant row address signal RCYAj is latched by the redundant row selection signal TRDSmk. The redundant row decoder 126 compares the row address signal YAj with the latched redundant row address signal RCYAj to obtain a comparison result, and activates the redundant row address RCSLnk of the redundant memory block 220 according to the comparison result.

In summary, the memory peripheral circuit of the present invention disables the bad row address of the main memory block according to the redundant test data signal and the row address signal, and enables the redundant row address of the redundant memory block . The decoder and metal fuse are replaced by the memory peripheral circuit of the present invention, thereby reducing the layout space of the peripheral circuit and quickly recovering to the state before the redundant row operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧Memory device 100‧‧‧Memory peripheral circuit 110‧‧‧Redundant line data circuit 112‧‧‧Redundant clock generation circuit 114‧‧‧Redundant line data and timing generation circuit 116‧‧‧ Library address signal generation circuit 1162‧‧‧ Library address signal buffer 1164‧‧‧ Library address signal selector 1166‧‧‧ District address signal buffer and selector 1166_1‧‧‧ District address signal buffer 1166_2‧‧‧ Area address signal selector 118‧‧‧Line address signal generating circuit 1181‧‧‧Line address signal buffer 1182‧‧‧Line selection drive signal generator 120‧‧‧Line selection control circuit 122‧‧‧Front row Decoder 124‧‧‧Row decoder 126, 126_1, 126_2‧‧‧Redundant row decoder 1262‧‧‧Redundant row selection signal generator 128‧‧‧Back redundant row decoder 200‧‧‧Memory array 210‧‧‧Main memory block 220‧‧‧Redundant memory block A01~A14, B01~B11, C01~C10, D01~D17, E01~E12, F01, G01~G12, H01~H05, K01 ‧‧‧Inverting gate ADBC‧‧‧Address buffer control signal BAm, BNKA0~BNKA2‧‧‧Bank address signal BNAND1~BNAND8, DNAND1, ENAND1~ENAND9, FNAND1, FNAND2, HNAND1~HNAND3, GNAND1~GNAND8‧‧ ‧Reverse gate BNKSk‧‧‧Bank selection signal CRD‧‧‧Redundant row information CSLD‧‧‧Row selection drive signal CXA13‧‧‧District address signal CYAj‧‧‧Read/write row address signal CSLrk‧‧‧Line Address DL1, DL2‧‧‧Delayer FADL1, FADL7‧‧‧Redundant row address signal latch circuit FF1, FF2, HF1‧‧‧Flip-flop circuit FL1, FL2‧‧‧Redundant test data signal latch Circuit FLC‧‧‧Line decoding logic circuit FNOR1, FNOR2, NOR1‧‧‧Inverse OR gate HD1~HD6‧‧‧Judging circuit HLC‧‧‧Redundant row decoding logic circuit JLC1‧‧‧Judging logic circuit KB‧‧‧Buffer L01~L09‧‧‧Latch circuit M1, M2‧‧‧Transistor RBAm‧‧‧Redundant library address signal RCSW‧‧‧Redundant switch signal RCCMD‧‧‧Redundant mode command RCYAj‧‧‧Redundant Row address signal RESETB‧‧‧Global reset signal RESETBD‧‧‧Partial reset signal RWCMD‧‧‧Read/write command RXA13 Redundant area address signal RYPDnk‧‧‧Decoded redundant row address signal RCSLnk‧‧ ‧Redundant row address SELC‧‧‧Selector T01~T11, FT1, FT2, FADLT1, HT1, HT2‧‧‧Transmission gate TRDS0k~TRDS7k, TR DSmk‧‧‧Redundant row selection signal TRICLK‧‧‧Redundant test clock TRDB1, TRDB2‧‧‧Redundant test data signals TRSEL1, TRSEL2‧‧‧Redundant row selection signal VDD‧‧‧System voltage VSS‧‧‧ Reference voltage XAD13Nk, XAD13Tk, XA13k‧‧‧Zone selection signal XNOR1‧‧‧mutually exclusive or gate YAj, YA3~YA8, YPD3N4T5Tk, YPD6N7T8Tk‧‧‧Line address signal YDB‧‧‧Line decoding buffer

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention. FIG. 2 is a schematic diagram of the peripheral circuit of the memory in the embodiment of FIG. 1. FIG. 3 is a schematic diagram of a bank address signal buffer according to an embodiment of the present invention. Figure 4 is a schematic diagram of a library address signal selector according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a zone address signal buffer and selector according to an embodiment of the invention. FIG. 6 is a schematic diagram of a row address signal generating circuit according to an embodiment of the invention. Fig. 7 is a schematic diagram of a pre-row decoder according to an embodiment of the present invention. Fig. 8 is a schematic diagram of a row decoder according to an embodiment of the present invention. FIG. 9 is a schematic diagram of a redundant row selection signal generator according to an embodiment of the invention. Fig. 10 is a schematic diagram of a redundant row decoder according to an embodiment of the present invention. Fig. 11 is a schematic diagram of a judgment circuit according to an embodiment of the present invention. Figure 12 is a schematic diagram of a post-redundant row decoder according to an embodiment of the present invention. FIG. 13 is a timing diagram of redundant row operation according to an embodiment of the present invention.

100‧‧‧Memory peripheral circuit

112‧‧‧Redundant clock generation circuit

110‧‧‧Redundant line data circuit

114‧‧‧Redundant row data and timing generating circuit

116‧‧‧Library address signal generating circuit

118‧‧‧Row address signal generating circuit

120‧‧‧Line selection control circuit

122‧‧‧Front Line Decoder

124‧‧‧line decoder

126‧‧‧Redundant line decoder

128‧‧‧Post redundant line decoder

ADBC‧‧‧Address buffer control signal

BAm‧‧‧Bank address signal

BNKSk‧‧‧Bank selection signal

CSLD‧‧‧row selection drive signal

CXA13‧‧‧area address signal

CYAj‧‧‧Read/write row address signal

CSLrk‧‧‧line address

RBAm‧‧‧Redundant library address signal

RCSW‧‧‧Redundant switching signal

RCCMD‧‧‧Redundant Mode Command

RCYAj‧‧‧Redundant row address signal

RESETB‧‧‧Global reset signal

RESETBD‧‧‧Partial reset signal

RWCMD‧‧‧Read/Write Command

RXA13‧‧‧Redundant area address signal

RCSLnk‧‧‧Redundant row address

TRICLK‧‧‧Redundant test clock

TRDB1, TRDB2‧‧‧Redundant test data signal

TRSEL1, TRSEL2‧‧‧Redundant row selection signal

YAj‧‧‧row address signal

XAD13Nk, XAD13Tk‧‧‧area selection signal

Claims (10)

A memory peripheral circuit coupled to a memory array, the memory peripheral circuit including: a redundant row data circuit, configured to store redundant row information, and provide redundant test data signals according to the redundant row information And a row address signal, the row address signal includes a redundant row address signal; and a row selection control circuit, coupled between the redundant row data circuit and the memory array, and configured to receive The redundant test data signal and the row address signal, the row selection control circuit includes: a row decoder, coupled to the main memory block of the memory array and the redundant row data circuit And configured to disable the bad row address of the main memory block according to the redundant test data signal and the redundant row address signal, wherein the row decoder includes a redundant test data signal A latch circuit, the redundant test data signal latch circuit is configured to latch the redundant test data signal; and a redundant row decoder coupled to the redundant memory block of the memory array and Between the redundant row data circuits and configured to latch the redundant row address signal according to the redundant test data signal, and compare the row address signal with the latched redundancy Row address signal to obtain a comparison result, and activate the redundant row address of the redundant memory block according to the comparison result, wherein the redundant row data circuit is further configured to provide a local reset signal, so The redundant row data circuit resets the redundant test data signal latch circuit according to the first logic level of the local reset signal. The memory peripheral circuit described in claim 1, wherein: the redundant row data circuit resets the row decoder and the redundant row data circuit according to the first logic level of the local reset signal Remaining row decoder, and initialize the row decoder and the redundant row decoder according to the transition point of the local reset signal. The memory peripheral circuit according to the first item of the scope of patent application, wherein the row decoder further includes: a row decoding logic circuit configured to receive the redundant row address signal and the latched redundant Test data signal, and obtain a logical operation result according to the redundant row address signal and the latched redundant test data signal; and a row decoding buffer, coupled to the output end of the row decoding logic circuit, And is configured to disable the bad row address of the main memory block according to the logic operation result, wherein the redundant test data signal latch circuit is configured to receive the logic operation result, the The redundant test data signal, the local reset signal, and the zone selection signal are latched according to the local reset signal and the logic operation result, and the zone selection signal is outputted according to the locked Storing the redundant test data signal to the row decoding logic circuit. The memory peripheral circuit according to the third item of the scope of patent application, wherein the redundant test data signal latch circuit includes: a flip-flop circuit configured to latch the redundant test data signal and receive the Local reset signal, and is reset or initialized according to the local reset signal Inverted OR gate, the first input terminal of the inverter OR gate is coupled to the output terminal of the row decoding logic circuit, and the second input terminal of the inverter OR gate receives the redundant test data signal; transistor , The control terminal of the transistor is coupled to the output terminal of the inverter, the first terminal of the transistor is coupled to the output terminal of the flip-flop circuit, and the second terminal of the transistor is coupled Connected to a reference voltage; and a transmission gate, the input end of the transmission gate is coupled to the output end of the flip-flop circuit, controlled by the zone selection signal, and the output end of the transmission gate is coupled to the The input terminal of the row decoding logic circuit transmits the latched redundant test data signal according to the area selection signal. The peripheral circuit of the memory according to claim 4, wherein the flip-flop circuit includes an inverter, the first input terminal of the inverter receives the local reset signal, and the inverter The output terminal of the gate is coupled to the input terminal of the transmission gate and the first terminal of the transistor; and an inverter gate, the input terminal of the inverter gate is coupled to the output terminal of the inverter, so The output terminal of the inverter gate is coupled to the second input terminal of the inverter gate. A memory peripheral circuit coupled to a memory array, the memory peripheral circuit including: a redundant row data circuit, configured to store redundant row information, and provide redundant test data signals according to the redundant row information And a row address signal, the row address signal The number includes a redundant row address signal; and a row selection control circuit, coupled between the redundant row data circuit and the memory array, and configured to receive the redundant test data signal and the row Address signal, the row selection control circuit includes: a row decoder, coupled between the main memory block of the memory array and the redundant row data circuit, and configured to depend on the redundancy The test data signal and the redundant row address signal disable the bad row address of the main memory block; and a redundant row decoder, coupled to the redundant memory block of the memory array and Between the redundant row data circuits and configured to latch the redundant row address signal according to the redundant test data signal, and compare the row address signal with the latched redundancy Row address signal to obtain a comparison result, and enable the redundant row address of the redundant memory block according to the comparison result, wherein the redundant row data circuit is further configured to provide a first redundant row A selection signal, wherein the redundant row decoder further includes a redundant row selection signal generator, coupled between the redundant row data circuit and the redundant row decoder, and configured to be based on The redundant test data signal and the first redundant row selection signal provide a second redundant row selection signal to the redundant row decoder. The memory peripheral circuit described in the scope of the patent application, wherein the redundant row decoder includes: At least one judgment circuit, the at least one judgment circuit is configured to receive the second redundant row selection signal, the local reset signal, and the redundant row address signal, and select according to the second redundant row The signal uses the corresponding row address signal as the redundant row address signal and latches the redundant row address signal, and compares the row address signal and the redundant row address signal to Providing the comparison result; and a redundant row decoding logic circuit configured to receive the comparison result provided by the at least one judging circuit, and enable the corresponding to the redundant row address signal according to the comparison result The redundant row address of the redundant memory block. The peripheral circuit of the memory according to item 7 of the scope of patent application, wherein the at least one judgment circuit each includes: a redundant row address signal latch circuit, configured to perform all operations according to the second redundant row selection signal The corresponding row address signal is used as the redundant row address signal, and the redundant row address signal is latched; and a judgment logic circuit, the first input terminal of the judgment logic circuit is used to receive the Row address signal, the second input terminal of the judgment logic circuit is coupled to the redundant row address signal latch circuit, and the output terminal of the judgment logic circuit is coupled to the redundant row decoding logic circuit Input terminal. The memory peripheral circuit according to the eighth item of the scope of patent application, wherein the redundant row address signal latch circuit includes: an inverter gate, the input terminal of the inverter gate receives the row address signal; and transmits Gate, the input terminal of the transmission gate is coupled to the output terminal of the inverter gate, And is configured to be controlled by the second redundant row selection signal and transmit the latched redundant test data signal according to the area selection signal; and a flip-flop circuit coupled to the transmission gate And the judgment logic circuit, and is configured to latch the redundant row address signal, receive the local reset signal, and be reset or initialized according to the local reset signal. A memory device, comprising: a memory array, the memory array including a main memory block and a redundant memory block; and a memory such as any one of items 1 to 9 of the scope of patent application Peripheral circuit.

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