TWI710290B - Circuit structure and manufacturing method thereof - Google Patents

Abstract

A circuit structure comprises a dielectric layer, a first conducting wire and a second conducting wire. The dielectric layer has a first surface and a second surface which have a thickness therebetween. The first conducting wire is disposed on the first surface and configured to transmit a first voltage signal. The second conducting wire is disposed on the second surface and configured to transmit a second voltage signal having the voltage level higher than the voltage level of the first voltage signal. The first conducting wire comprises a first section and a second section. The projection of the first section along a first direction and on the second surface of the dielectric layer does not overlap the second conducting wire, and the projection of the second section along a first direction and on the second surface of the dielectric layer partially overlaps the second conducting wire, wherein the first direction parallels to the direction of the thickness of the dielectric layer. The included angle between the extending direction of the projection of the first section and the extending direction of the second conducting wire is smaller than the included angle between the projection of the second section and the second conducting wire.

Description

Circuit structure and manufacturing method thereof

The present invention relates to a circuit structure, and particularly relates to a circuit structure with multiple sets of signal wires.

As the current society requires light, thin, short and small electronic devices, the number of layers and thickness of printed circuit boards in electronic products are compressed. At present, in the circuit layout of printed circuit boards, apart from the specific layout guidelines for special signals such as differential and serial VID, there are no definitions for other signals. Therefore, most of the circuit layouts are inspected manually. In addition to time-consuming, it is also easy to be ignored.

As mentioned above, in order to achieve the lightness, thinness and shortness of the electronic device, multiple groups of signal lines in the circuit structure easily cross each other, that is, the projections on the same plane along the stacking direction cross each other. However, when these signal lines are power signal lines and signal lines with lower voltage levels, since the current power circuits in electronic devices mostly use switching power circuits, the crossover phenomenon of signal lines will cause lower voltage levels. The accurate signal line is coupled with the power signal line with a higher voltage level to generate a coupling voltage, which causes the signal line with a lower voltage level to operate incorrectly, which in turn makes the motherboard function abnormally, poorly stable, and even unable to boot.

In view of the above, the present invention provides a circuit structure and a manufacturing method thereof.

According to an embodiment of the invention, the circuit structure includes a dielectric layer, a first wire and a second wire. The dielectric layer has a first surface and a second surface, wherein there is a thickness between the first surface and the second surface. The first wire is arranged on the first surface of the dielectric layer and used for transmitting the first voltage signal. The second wire is disposed on the second surface of the dielectric layer and is used for transmitting a second voltage signal, wherein the voltage level of the second voltage signal is higher than the voltage level of the first voltage signal. The first wire includes a first wire segment and a second wire segment. The projection of the first wire segment on the second surface of the dielectric layer along the first direction does not overlap the second wire, and the second wire segment is along the first direction on the dielectric layer. The projection on the second surface of the layer partially overlaps the second wire, and the first direction is parallel to the direction of the thickness of the dielectric layer. The angle between the extension direction of the projection of the first line segment and the extension direction of the second wire is smaller than the angle between the projection of the second line segment and the second wire.

According to an embodiment of the present invention, a method of manufacturing a circuit structure includes: disposing a first wire on the base layer; disposing a dielectric layer on the base layer to cover the first wire; and disposing a second wire on the dielectric layer. The dielectric layer between the first wire and the second wire has a thickness. The first wire includes a first line segment and a second line segment. The first line segment is located on the second surface of the dielectric layer along the first direction. The projection does not overlap the second wire, and the projection of the second line segment on the dielectric layer along the first direction partially overlaps the second wire. The angle between the extension direction of the projection of the first line segment and the extension direction of the second wire It is smaller than the angle between the projection of the second line segment and the second wire, and the first direction is parallel to the direction of the thickness of the dielectric layer.

With the above structure, the circuit structure and manufacturing method disclosed in this case, through the special circuit design at the intersection of the two sets of wires, make the wires that transmit lower voltage levels have two line segments with different extension directions near the intersection. , To improve the coupling phenomenon of the wire, that is, reduce the coupling voltage generated on the wire, and solve the problem of incorrect operation due to signal coupling, which makes the motherboard function abnormal, poor stability, and even unable to boot, and in terms of layout Has a high degree of freedom. In addition, the circuit structure and manufacturing method disclosed in this case can eliminate as much as possible the factors affecting the performance of the motherboard during the circuit layout stage, reducing the time and other costs of debugging in the R&D stage.

The above description of the content of the disclosure and the description of the following embodiments are used to demonstrate and explain the spirit and principle of the present invention, and to provide a further explanation of the patent application scope of the present invention.

The detailed features and advantages of the present invention are described in detail in the following embodiments, and the content is sufficient to enable anyone familiar with the relevant art to understand the technical content of the present invention and implement it accordingly, and according to the content disclosed in this specification, the scope of patent application and the drawings Anyone who is familiar with the relevant art can easily understand the related purpose and advantages of the present invention. The following examples further illustrate the viewpoints of the present invention in detail, but do not limit the scope of the present invention by any viewpoint.

The following embodiments of the present invention are related to the circuit design at the intersection of two wires that cross each other, and can be applied to printed circuit boards (PCBs) or integrated circuits in electronic devices. Integrated circuit, IC) on the circuit structure. In particular, one of the two wires that cross each other is a power line or a power signal line with a higher voltage, and the other wire is a signal line with a lower voltage. In addition, the two wires that cross each other can also be two sets of differential signal wires (double strands) that cross each other, or one of the wires is a single wire and the other wire is a double wire.

Please refer to FIG. 1. FIG. 1 is a schematic top view of a circuit structure according to an embodiment of the present invention. As shown in FIG. 1, the circuit structure 1 includes a dielectric layer DL, a first wire L1, and a second wire L2. Wherein, the dielectric layer DL is formed of a dielectric material (the dielectric constant is, for example, 3.8), and the first wire L1 and the second wire L2 are formed of a conductive material. The first wire L1 is used to transmit a first voltage signal, and the second wire L2 is used to transmit a second voltage signal, and the voltage level of the second voltage signal is higher than the voltage level of the first voltage signal. In detail, the line width ratio of the first conductive line L1 and the second conductive line L2 can be between 1/20 and 1. When the line width ratio is smaller, the first conductive line L1 and the second conductive line L2 transmit The voltage difference between the signals can be larger. The first wire L1 and the second wire L2 are respectively disposed on two opposite sides of the dielectric layer DL, which means that the dielectric layer DL is sandwiched between the first wire L1 and the second wire L2. The projections of the first wire L1 and the second wire L2 on the same plane (such as the drawing) along the direction perpendicular to the drawing cross each other, and there is a cross between the projection of the first wire L1 and the projection of the second wire L2 Angle θ1. The crossing angle θ1 can be any angle between 70 degrees and 110 degrees, and 90 degrees is preferred.

To further illustrate the influence of the crossover angle on signal coupling, please refer to Figures 1 and 2 together. Figure 2 is a comparison diagram of the relationship between the angle parameters of the circuit structure of multiple embodiments of the present invention and the coupling voltage generated by it. In other words, Fig. 2 shows the coupling voltages generated by two wires with various line width ratios on wires with lower voltages under various crossing angles. Taking the circuit structure 1 to illustrate, FIG. 2 shows the coupling voltage values generated on the first wire L1 by the first wire L1 and the second wire L2 with various line width ratios under various crossing angles θ1.

In the embodiment corresponding to the data line C1 of FIG. 2, the line widths w1 and w2 of the first conductive line L1 and the second conductive line L2 are 3 mils and 3 mils, respectively, that is, the line width ratio of the two is 1; In the embodiment corresponding to the data line C2, the line widths w1 and w2 of the first conductive line L1 and the second conductive line L2 are 3 mil and 10 mil respectively, that is, the ratio of the line widths between the two is 3/10; corresponding to the data line C3 In the embodiment, the line widths w1 and w2 of the first conductive line L1 and the second conductive line L2 are 3 mil and 20 mil, respectively, that is, the line width ratio of the two is 3/20; in the embodiment corresponding to the data line C4, the first The line widths w1 and w2 of a wire L1 and the second wire L2 are 3 mil and 30 mil, respectively, that is, the ratio of the line width between the two is 1/10; in the embodiment corresponding to the data line C5, the first wire L1 and the second wire L2 The line widths w1 and w2 of the wire L2 are 3 mils and 40 mils, respectively, that is, the line width ratio of the two is 3/40. In particular, FIG. 2 only lists multiple line width combinations within the aforementioned line width ratio range, and does not limit the actual size of the circuit structure of the present invention.

As shown in Figure 2, when the line width ratio of the first wire L1 to the second wire L2 is smaller, the coupling voltage value Vn on the first wire L1 is larger, and for various line width combinations, when the first wire When the crossing angle θ1 between the projection of L1 and the projection of the second wire L2 is between 70 degrees and 110 degrees, the coupling voltage value Vn on the first wire L1 approaches zero, where 90 degrees corresponds to The coupling voltage value Vn is closest to zero. Therefore, the circuit design proposed in this case in which the crossing angle of the two lines is between 70 degrees and 110 degrees can reduce the generation of the coupling voltage on the wires. However, when the crossing angle in the circuit structure is closer to a right angle, the degree of freedom of the layout of the two wires will be lower.

Therefore, the present invention also proposes another circuit structure. Please refer to FIGS. 3A and 3B together, in which FIG. 3A is a schematic top view of a circuit structure according to another embodiment of the present invention, and FIG. 3B is a circuit according to the section line 3B-3B shown in FIG. 3A Schematic cross-section of the structure. As shown in FIGS. 3A and 3B, the circuit structure 2 includes a dielectric layer DL, a first wire L1', and a second wire L2. The dielectric layer DL is formed of a dielectric material (dielectric constant, for example, 3.8). The first wire L1 and the second wire L2 are formed of conductive materials. The dielectric layer DL has a first surface sf1 and a second surface sf2, wherein a thickness h is formed between the first surface sf1 and the second surface sf2. The first wire L1' is arranged on the first surface sf1 and used for transmitting the first voltage signal; the second wire L2 is arranged on the second surface sf2 and used for transmitting the second voltage signal. As described in the previous embodiment of FIG. 1, the voltage level of the second voltage signal is higher than the voltage level of the first voltage signal, and further, the line width ratio of the first wire L1' and the second wire L2 may be between Between 1/20 and 1. In this embodiment, the circuit structure 2 is disposed on a base layer BL. However, in other embodiments, the circuit structure 2 can also be formed independently, and the manufacturing method will be described later.

Compared with the circuit structure 1 shown in FIG. 1, the first wire L1' of the circuit structure 2 includes a first line segment p1 and a second line segment p2. Wherein, the projection of the first line segment p1 on the second surface sf2 of the dielectric layer DL along a direction parallel to the thickness h of the dielectric layer DL (hereinafter referred to as the first direction D1) does not overlap on the second surface sf2 The projection of the second line segment p2 on the second surface of the dielectric layer DL along the first direction D1 partially overlaps the second conductive line L2. In addition, the angle θ2 between the extension direction of the projection of the first line segment p1 and the extension direction of the second wire L2 is smaller than the angle θ3 between the projection of the second line segment p2 and the second wire L2, which means that the first line segment p1 It has a different extension direction from the second line segment p2. Wherein, the included angle θ3, which is the crossing angle θ1 in the circuit structure 1 of FIG. 1, can be designed to be between 70 degrees and 110 degrees, especially 90 degrees, so as to reduce the coupling voltage on the first wire L1' On the build.

Furthermore, there is a connecting portion where the first line segment p1 and the second line segment p2 meet. In the embodiment of FIGS. 3A and 3B, the engagement portion is an engagement surface sf3. There is an interval Xn between the projection of the interface sf3 on the second surface sf2 of the dielectric layer DL along the first direction D1 and the second wire L2 (that is, the minimum distance between the projection of the interface sf3 and the second wire L2) . When the value of the thickness h of the dielectric layer DL is less than a thickness threshold, the interval Xn has a first ideal interval value; and when the value of the thickness h of the dielectric layer DL is greater than or equal to the thickness threshold, the interval Xn has a second ideal interval value. Wherein, the first ideal interval value is twice the second ideal interval value. In detail, the thickness threshold is related to the line width w1' of the first conductive line L1', and in more detail, the thickness threshold is 3 to 5 times the line width of the first conductive line L1'.

In addition, in the embodiment shown in FIG. 3A, the first wire L1' also has another line segment connected to the second line segment p2, and this line segment has the same extension direction as the first line segment p1 and is similar to the second line segment p2. There may also be a gap Xn between the projection of the connecting surface between the second surface sf2 of the dielectric layer DL along the first direction D1 and the second conductive line L2. However, in other embodiments, the another line segment may also have the same extension direction as the second line segment p2, or an extension direction different from both the first line segment p1 and the second line segment p2, or may be along the first line segment p1 and the second line segment p2. The projection of one direction D1 on the second surface sf2 of the dielectric layer DL and the second conductive line L2 have other sizes of intervals.

Please also refer to FIGS. 3A to 4C to illustrate the influence of the thickness h of the dielectric layer DL and the projection of the interface sf3 and the distance Xn of the second wire L2 on the second surface sf2 of the dielectric layer DL on the signal coupling. 4A to 4C are diagrams showing the relationship between the dimensional parameters of the circuit structures of multiple embodiments and the coupling voltages they generate. Furthermore, FIGS. 4A, 4B, and 4C respectively illustrate the coupling voltage values Vn generated by the first conductive line L1' of three thicknesses h under the conditions of various intervals Xn.

In the embodiment corresponding to FIG. 4A, the line width ratio of the first wire L1' and the second wire L2 is 3/40, the crossing angle (the included angle θ3) is 90 degrees, the thickness h of the dielectric layer DL is 3 mils and The line width w1' of the first wire L1' is 3 mil; in the embodiment corresponding to FIG. 4B, the line width ratio of the first wire L1' to the second wire L2 is 3/40, the angle θ3 is 90 degrees, and the thickness h Is 5 mil and the line width w1' is 3 mil; in the embodiment corresponding to FIG. 4C, the line width ratio of the first wire L1' to the second wire L2 is 3/40, the angle θ3 is 90 degrees, the thickness h is 16 mils and The line width w1' is 3mil. As in the design rule proposed in the foregoing embodiment, the ideal value of the interval Xn corresponding to the thickness h equal to or greater than the thickness threshold (3 to 5 times of the line width w1') is the ideal value of the interval Xn corresponding to the thickness h being smaller than the thickness threshold. Twice. Therefore, according to this design rule, the ideal value of the interval Xn in the embodiment corresponding to FIG. 4C should be twice the ideal value of the interval Xn in the embodiment corresponding to FIGS. 4A and 4B.

As shown in FIGS. 4A to 4C, the interval Xn is inversely proportional to the amount of coupling on the first wire L1', which means that when the interval Xn is larger, the amount of coupling generated by the first wire L1' is less, but when the interval Xn is larger , The layout of the first conductive line L1' on the dielectric layer DL will be more restricted, so the parameters corresponding to the point where the data line approaches saturation (indicated by dotted lines in FIGS. 4A-4C) will be ideal parameters. In the embodiment corresponding to FIGS. 4A and 4B, the ideal value of the interval Xn is 20 mils; and in the embodiment corresponding to 4C, the ideal value of the interval Xn is 10 mils. It can be seen that, according to the design rules mentioned in the foregoing embodiments of this case, the circuit structure can have the advantages of low signal coupling and high layout freedom.

In addition to the size combinations in the embodiments corresponding to FIGS. 4A to 4C, the circuit structure 2 can also be designed in other size combinations, as shown in Table 1. Table 1 shows a number of examples of the circuit structure 2 designed according to the aforementioned design rules. Examples A, B, and D correspond to the above-mentioned embodiments of FIGS. 4A, 4B, and 4C, respectively. It should be noted here that the actual dimensions shown in Table 1 are only examples and are not used to limit the present invention.

Table 1 example A B C D E w1'/w2 3/40 3/40 3/40 3/40 3/40 w1'(mil) 3 3 3 3 3 θ3 (degrees) 90 90 90 90 90 h(mil) 3 5 9 16 twenty four Xn(mil) 20 20 20 10 10

In order to further illustrate the comparison between the circuit structure of the present invention and the signal coupling phenomenon of a comparative example, please refer to Table 1, FIG. 1, and FIGS. 3A to 5C together. 5A to 5C are comparison diagrams of coupling voltages generated by comparing the circuit structures of a plurality of embodiments of the present invention with the circuit structures of a comparative example. Furthermore, FIGS. 5A to 5C are diagrams showing the comparison of coupling voltage between the comparative example and the example A/example B/example D of Table 1. The comparative example is similar to the circuit structure 1 shown in FIG. , Example B and Example D have the same line width and thickness, but the crossing angle θ1 of the two wires is 45 degrees. Input a signal with a voltage level of 30 volts (V) and a period of 4 nanoseconds (ns) to the second wire L2 of each example, and measure the voltage waveform on the first wire L1 or L1' to obtain the figure 5A ~5C shows the coupling voltage value Vn. As shown in FIGS. 5A to 5C, the circuit structure proposed in various embodiments of the present invention can greatly reduce the coupling voltage generated on the lower voltage signal line.

In particular, the above figures 2, 4A-4C and 5A-5C are the coupling voltages performed by the High Frequency Structure Simulator (HFSS) and the Advanced Design System (ADS) Simulations, however, those with ordinary knowledge in the art can know that the measurements performed on the actual circuit structure will have similar results to these simulations.

In order to explain the manufacturing method of the circuit structure of one or more embodiments, please refer to FIGS. 3B and 6, where FIG. 6 is a flowchart of the manufacturing method of the circuit structure according to an embodiment of the present invention. In step S101, a first wire L1' is disposed on the base layer BL; in step S103, a dielectric layer DL is disposed on the base layer to cover the first wire L1'; in step S105, a second wire L2 is disposed on the dielectric On layer DL. Furthermore, in this embodiment, the first conductive line L1', the dielectric layer DL, and the second conductive line L2 are sequentially stacked on the base layer BL. The base layer BL can be formed of the same material as the dielectric layer DL. It can be formed of other dielectric materials, and the present invention is not limited.

In addition, the second conductive line L2 can also be covered with the same or different dielectric material as the dielectric layer DL to form another dielectric layer. The two dielectric layers and the base layer BL can jointly form a substrate, and the substrate Metal layers can be formed on both surfaces of the device to serve as grounding layers. In other embodiments, the dielectric layer DL in the circuit structure 2 can also be formed first, and then the first conductive line L1' and the second conductive line L2 are respectively formed on both sides of the dielectric layer DL, or formed by other processes.

The relationship between the projection of the first wire L1' on the second surface sf2 of the dielectric layer DL along the stacking direction (the first direction D1) and the second wire L2 may be as shown in FIG. 1 or FIG. 3A, and , The line width ratio of the first wire L1' and the second wire L2, the thickness h of the dielectric layer DL between the first wire L1' and the second wire L2, and the interface sf3 in the dielectric layer along the first direction D1 The relationship between the projection on the second surface sf2 of the DL and the interval Xn between the second conductive lines L2 is also the same as that described in the previous embodiments, so it will not be repeated here.

With the above structure, the circuit structure and manufacturing method disclosed in this case, through the special circuit design at the intersection of the two sets of wires, make the wires that transmit lower voltage levels have two line segments with different extension directions near the intersection. , To improve the coupling phenomenon of the wire, that is, reduce the coupling voltage generated on the wire, and solve the problem of incorrect operation due to signal coupling, which makes the motherboard function abnormal, poor stability, and even unable to boot, and in terms of layout Has a high degree of freedom. In addition, the circuit structure and manufacturing method disclosed in this case can eliminate as much as possible the factors affecting the performance of the motherboard during the circuit layout stage, reducing the time and other costs of debugging in the R&D stage.

Although the present invention is disclosed in the foregoing embodiments, it is not intended to limit the present invention. All changes and modifications made without departing from the spirit and scope of the present invention fall within the scope of patent protection of the present invention. For the scope of protection defined by the present invention, please refer to the attached patent scope.

1, 2: Circuit structure DL: Dielectric layer L1, L1’: First wire L2: second wire w1, w2: line width θ1: Crossover angle D1: First direction C1～C5: Data cable Vn: Coupling voltage value p1: the first line segment p2: second line segment sf1: first side sf2: second side sf3: interface θ2, θ3: included angle Xn: interval H: thickness BL: grassroots

FIG. 1 is a schematic top view of a circuit structure according to an embodiment of the invention. FIG. 2 is a comparison diagram of the relationship between the angle parameter of the circuit structure of the plurality of embodiments of the present invention and the coupling voltage generated therefrom. 3A is a schematic top view of a circuit structure according to another embodiment of the invention. FIG. 3B is a schematic cross-sectional view of the circuit structure drawn according to the section line 3B-3B shown in FIG. 3A. 4A is a diagram showing the relationship between the size parameter of the circuit structure and the coupling voltage generated by the circuit structure according to an embodiment of the present invention. 4B is a diagram showing the relationship between the size parameters of the circuit structure and the coupling voltage generated by another embodiment of the present invention. 4C is a diagram showing the relationship between the size parameter of the circuit structure and the coupling voltage generated by another embodiment of the present invention. 5A is a comparison diagram of the coupling voltage generated by comparing the circuit structure of an embodiment of the present invention with the circuit structure of a comparative example. 5B is a comparison diagram of the coupling voltage generated by comparing the circuit structure of another embodiment of the present invention with the circuit structure of the comparative example. 5C is a comparison diagram of the coupling voltage generated by comparing the circuit structure of another embodiment of the present invention with the circuit structure of the comparative example. FIG. 6 is a flowchart of a manufacturing method of a circuit structure according to an embodiment of the present invention.

2: Circuit structure

DL: Dielectric layer

L1’: First wire

L2: second wire

w1, w2: line width

p1: the first line segment

p2: second line segment

sf3: interface

θ2, θ3: included angle

Xn: interval

D1: First direction

Claims (9)

A circuit structure includes: a dielectric layer having a first surface and a second surface, a thickness between the first surface and the second surface; a first wire disposed on the first surface, and Used for transmitting a first voltage signal; and a second wire arranged on the second surface and used for transmitting a second voltage signal, the voltage level of the second voltage signal is higher than the voltage of the first voltage signal Level; wherein the first line includes a first line segment and a second line segment, the projection of the first line segment on the second surface of the dielectric layer along a first direction does not overlap the second line , The projection of the second line segment on the second surface of the dielectric layer along the first direction partially overlaps the second wire, the extension direction of the projection of the first line segment and the extension direction of the second wire The included angle between is smaller than the included angle between the projection of the second line segment and the second wire, and the first direction is parallel to the direction of the thickness of the dielectric layer; wherein the angle between the first wire and the second wire The line width ratio is between 1/20 and 1. The circuit structure according to claim 1, wherein the angle between the projection of the second line segment and the second wire is between 70 degrees and 110 degrees. The circuit structure according to claim 1, wherein the first line segment and the second line segment have a connecting portion where the first line segment meets the second line segment, and the connecting portion is on the second surface of the dielectric layer along the first direction There is an interval between the projection of and the second wire. When the thickness of the dielectric layer is less than a thickness threshold, the interval has a first ideal interval value, and when the thickness is greater than or equal to the thickness threshold When, the interval has a second ideal interval value, and the first ideal interval value is twice the second ideal interval value. The circuit structure according to claim 3, wherein the thickness threshold is 3 to 5 times the line width of the first conductive line. A method for manufacturing a circuit structure includes: disposing a first wire on a base layer; disposing a dielectric layer on the base layer to cover the first wire; and disposing a second wire on the dielectric layer; wherein the The dielectric layer between the first wire and the second wire has a thickness, the first wire includes a first line segment and a second line segment, and the first line segment is on the dielectric layer along a first direction The projection on the second surface does not overlap the second wire, and the second line segment is on the second surface of the dielectric layer along the first direction The projection of the part overlaps the second wire, and the angle between the extension direction of the first line segment and the extension direction of the second wire is smaller than the angle between the projection of the second line segment and the second wire , And the first direction is parallel to the direction of the thickness of the dielectric layer. The manufacturing method according to claim 5, wherein the angle between the projection of the second line segment and the second wire is between 70 degrees and 110 degrees. The manufacturing method of claim 5, wherein the first line segment and the second line segment have a connecting portion where the first line segment meets the second line segment, and the connecting portion is on the second surface of the dielectric layer along the first direction There is an interval between the projection of and the second wire. When the thickness of the dielectric layer is less than a thickness threshold, the interval has a first ideal interval value, and when the thickness is greater than or equal to the thickness threshold When, the interval has a second ideal interval value, and the first ideal interval value is twice the second ideal interval value. The manufacturing method according to claim 7, wherein the thickness threshold is 3 to 5 times the line width of the first wire. The manufacturing method according to claim 5, wherein the line width ratio of the first wire to the second wire is between 1/20 and 1.

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