TWI708397B - Non-volatile memory device and operating method thereof - Google Patents

Abstract

A non-volatile memory device includes a substrate layer, a first terminal, a second terminal, a floating gate layer and a contact layer. The first terminal is disposed on the substrate layer and is configured to receive a first voltage. The second terminal is disposed on the substrate layer and is configured to receive a second voltage. The floating gate layer is disposed on the substrate layer. The contact layer is disposed on the floating gate layer and is configured to receive a control voltage. When the non-volatile memory device is operated in a high-performance mode, the control voltage is set to a first high voltage, the first voltage is set to zero, and the second voltage is set to the first high voltage for performing a write operation. The control voltage is set to a negative voltage, the first voltage is set to zero, and the second voltage is set to a positive voltage for performing an erase operation.

Description

Non-volatile memory and its operation method

The present disclosure relates to a non-volatile memory and its operation method, in particular to a non-volatile memory and its operation method that can adjust different input voltages according to usage requirements.

The popularity of portable information, communication and consumer products has greatly increased the demand for memory. In addition, under the trend of diversification of embedded system functions, non-volatile memory is widely used due to memory operating characteristics and process convenience.

In order for the memory to meet the needs of commodities, whether it is high-efficiency or low-power requirements, the memory itself needs different structural designs to meet different usage conditions, reducing convenience. Therefore, it is necessary to design a memory that can meet different needs without changing the memory structure.

In an embodiment of the present disclosure, a non-volatile memory includes a substrate layer, a first end, a second end, a floating gate layer, and a contact layer. The first end is configured on the substrate layer and used for receiving the first voltage. The second end is configured at On the substrate layer and used for receiving the second voltage. The floating gate layer is disposed above the substrate layer. The contact layer is disposed above the floating gate layer and used for receiving the control voltage. When the non-volatile memory is operating in the high-efficiency mode, the control voltage is set to the first high voltage, the first voltage is set to zero, and the second voltage is set to the first high voltage for writing. The control voltage is set to a negative voltage, the first voltage is set to zero, and the second voltage is set to a positive voltage for erasing.

In another embodiment of the present disclosure, a non-volatile memory operating method includes the following operations: receiving a control voltage through a contact layer; receiving a first voltage through a first terminal; receiving a second voltage through a second terminal; operation In the high-efficiency mode, by setting the control voltage to the first high voltage, the first voltage to zero, and the second voltage to the first high voltage for writing; when operating in the high-efficiency mode, by setting the control voltage Is a negative voltage, the first voltage is set to zero, and the second voltage is set to a positive voltage for erasing.

In summary, the non-volatile memory can be set to different control voltages, first voltages, and second voltages according to actual usage conditions, and write or erase according to the control voltages, first voltages, and second voltages.

100‧‧‧Non-volatile memory

110‧‧‧Contact layer

120‧‧‧Floating gate layer

130‧‧‧Dielectric layer

140‧‧‧Substrate layer

PG‧‧‧Control terminal

SL‧‧‧First end

BL‧‧‧Second end

HV, VDD‧‧‧Voltage

400‧‧‧Operation method

S410, S420, S430, S440, S450‧‧‧Step

FIG. 1 is a cross-sectional view of a non-volatile memory according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a write operation of a non-volatile memory according to an embodiment of the disclosure.

FIG. 3 is a schematic diagram of a non-volatile memory erasing operation according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a write operation of a non-volatile memory according to an embodiment of the disclosure.

FIG. 5 is a schematic diagram of a non-volatile memory erasing operation according to an embodiment of the present disclosure.

Fig. 6 is a flowchart of an operation method according to an embodiment of the present disclosure.

The terms "include", "have" and so on used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one of one or more of the related listed items and all combinations thereof.

In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Link" or "coupling" can also be used to indicate mutual operation or interaction between two or more components. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly indicates, the terms do not specifically refer to or imply the order or sequence, nor are they used to limit this disclosure.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a non-volatile memory 100 according to an embodiment of the present disclosure. The non-volatile memory 100 includes a contact layer 110, a floating gate layer 120 (floating gate), a dielectric The electrical layer 130, the substrate layer 140, the control terminal PG, the first terminal SL and the second terminal BL. The contact layer 110 is used for receiving the control voltage of the control terminal FG, the first terminal SL is used for receiving the first voltage, and the second terminal BL is used for receiving the second voltage.

The non-volatile memory 100 is a kind of memory that uses the floating gate layer 120 to store charges to achieve a memory effect. The floating gate layer 120 is surrounded by a dielectric layer 130, which is a kind of that can be polarized. The insulator is used to isolate the floating gate layer 120, and the change of the potential of the non-volatile memory 100 is determined by the amount of charge in the floating gate layer 120.

When electrons are injected into the floating gate layer 120, the threshold voltage of the device will increase, and the operation at this time can be called writing. Conversely, when the electrons in the floating gate layer 120 are discharged, the threshold voltage drops, and the operation at this time can be called erasing.

There are two main carrier injection mechanisms for the non-volatile memory 100. The first is FN tunneling (Fowler-Nordheim tunneling), and the second is hot electron injection.

The tunneling mechanism is a concept in quantum mechanics. Unlike classical mechanics, the tunneling electron does not need to have a higher energy than the potential energy barrier to have the probability of passing through the potential energy barrier. The probability of tunneling is related to the width of the potential energy barrier. The smaller the width, the higher the probability of electron tunneling. As the operating voltage increases, the equivalent width of the dielectric layer 130 will be smaller, so the probability of electrons passing through the dielectric layer 130 will increase.

Hot electron injection is when sufficient electric field is generated so that electrons have enough energy to cross the potential energy barrier, which is faster than FN tunneling.

In one embodiment, the non-volatile memory 100 can be based on Actual use requires operation in high-efficiency mode or low-power mode. Sometimes the non-volatile memory 100 needs to be operated in a high-performance mode that requires high speed, such as a situation where memory access speed is required. Sometimes the non-volatile memory 100 needs to be operated in a low power consumption mode that can be operated for a long time, such as a wearable device that needs to record data for a long time and requires power saving.

Please refer to FIG. 2 and FIG. 3. FIG. 2 is a schematic diagram of a write operation of the non-volatile memory 100 according to an embodiment of the present disclosure, and FIG. 3 is a schematic diagram of the non-volatile memory according to an embodiment of the present disclosure. A schematic diagram of the erasing operation of the body 100. When the non-volatile memory 100 is operated in a low power consumption mode, the write and erase operations use FN tunneling.

When the non-volatile memory 100 uses FN tunneling for writing, the control voltage is set to the voltage HV, the first voltage is set to 0V, and the second voltage is set to 0V for writing. In this embodiment, the voltage HV may be a high voltage.

It should be noted that, for the convenience of description, the circular icon with a negative sign in the substrate layer 140 in FIG. 2 is used as an example of an electron, and does not represent the actual number or size. The control voltage is set to the voltage VDD, so that the electrons in the substrate layer 140 tunnel to the floating gate layer 120, as shown in FIG. 2.

When the non-volatile memory 100 is erased using FN tunneling, the control voltage is set to 0V, the first voltage is set to 0V, and the second voltage is set to voltage HV, so that the electrons in the floating gate layer 120 tunnel to the substrate One end of the layer 140, such as the drain terminal in the transistor, is as shown in FIG. 3.

Please refer to FIG. 4 and FIG. 5. FIG. 4 is a schematic diagram of the writing operation of the non-volatile memory 100 according to an embodiment of the present disclosure. Figure is a schematic diagram of the erasing operation of the non-volatile memory 100 according to an embodiment of the present disclosure. When the non-volatile memory 100 is operated in a high-efficiency mode, the write and erase operations use hot carrier injection.

When the non-volatile memory 100 uses hot carrier injection for writing, the control voltage is set to the voltage VDD, the first voltage is set to 0V, and the second voltage is set to the voltage VDD for writing. In this embodiment, the voltage VDD can be a system high voltage.

It should be noted that, for the convenience of description, the circular icon with a positive sign in the substrate layer 140 in FIG. 4 is used as an example of the hole, which does not represent the actual number or size. By setting the control voltage to voltage VDD, the first voltage to 0V, and the second voltage to voltage VDD to generate a horizontal electric field and a vertical electric field, the increase of the horizontal electric field will accelerate the speed of electrons in the channel, and when the electrons get enough energy At this time, the probability of electron tunneling is increased to allow electrons to enter the floating gate layer 120, and impact ionization occurs at the drain terminal to generate electron-hole pairs, as shown in FIG. 4.

When the non-volatile memory 100 is erased using hot carrier injection, the control voltage is set to voltage HV, the first voltage is set to 0V, and the second voltage is set to a negative voltage HV, so that the floating gate layer 120 and The energy band between the drain terminals is skewed enough to allow the electrons in the floating gate layer 120 to combine with holes to complete the erasure. It is understood that it is like tunneling through holes and the electrons in the floating gate layer 120 combine, as shown in Section 5. As shown in the figure.

Please refer to FIG. 6, which is a flowchart of an operation method 400 according to an embodiment of the present disclosure. To make the operation method 400 shown in Fig. 6 easy to understand, please refer to Figs. 2 and 3 at the same time. Operation method 400 contains steps Step S410, Step S420, Step S430, Step S440, and Step S450.

In step S410, the non-volatile memory 100 receives the control voltage of the control terminal PG through the contact layer 110. In step S420, the non-volatile memory 100 receives the first voltage through the first terminal SL. In step S430, the non-volatile memory 100 receives the second voltage through the second terminal BL.

When the non-volatile memory 100 is operating in the high-performance mode, step S440 is executed for writing, and step S450 is executed for erasing. In step S440, the non-volatile memory 100 sets the control voltage to a high voltage, the first voltage is set to zero, and the second voltage is set to a high voltage for writing. For example, the control voltage and the second voltage are set to the system high voltage voltage VDD, and the first voltage is set to 0V. In step S450, the non-volatile memory 100 sets the control voltage to a negative voltage, the first voltage is set to zero, and the second voltage is set to a positive voltage for writing. For example, the control voltage is set to a negative voltage -HV, the first voltage is set to 0V, and the second voltage is set to voltage HV for erasing.

When the non-volatile memory 100 is operated in the low power consumption mode, the control voltage, the first voltage, and the second voltage can be set to the corresponding parameters, which can be achieved without changing the internal structure of the non-volatile memory 100.

In one embodiment, the non-volatile memory 100 can be further designed to be arranged in a NOR array, such as a NOR flash memory (NOR flash memory), to form a high-density memory, and to be designed as a differential structure. The differential structure does not require an additional reference current source for comparison, but compares with the current generated by itself to increase accuracy.

In summary, non-volatile memory is controlled according to actual applications Different voltages can be used to operate in high-efficiency mode or low-power mode without changing the internal transistor structure. The non-volatile memory can be used in electronic products with different needs.

100‧‧‧Non-volatile memory

110‧‧‧Contact layer

120‧‧‧Floating gate layer

130‧‧‧Dielectric layer

140‧‧‧Substrate layer

PG‧‧‧Control terminal

SL‧‧‧First end

BL‧‧‧Second end

Claims (8)

A non-volatile memory includes: a substrate layer; a first end arranged on the substrate layer and used for receiving a first voltage; a second end arranged on the substrate layer and used for receiving a first voltage; Two voltages; a floating gate layer disposed above the substrate layer; and a contact layer disposed above the floating gate layer and used to receive a control voltage; wherein when the non-volatile memory is operated in a high-performance In the mode, the control voltage is set to a first high voltage, the first voltage is set to zero, the second voltage is set to the first high voltage for writing, the control voltage is set to a negative voltage, the first The voltage is set to zero, the second voltage is set to a positive voltage for erasing, wherein when the non-volatile memory is operating in a low power consumption mode, the control voltage is set to a second high voltage, and the first voltage It is set to zero, the second voltage is set to zero for writing, the control voltage is set to zero, the first voltage is set to zero, and the second voltage is set to the second high voltage for erasing. The non-volatile memory according to claim 1, wherein when the non-volatile memory is operated in the low power consumption mode, the control voltage, the first voltage, and the second voltage make the substrate layer Electrons enter the floating gate layer for writing. The non-volatile memory according to claim 2, wherein when the non-volatile memory is operated in the low power consumption mode, the floating gate layer is made by the control voltage, the first voltage and the second voltage The electrons in it move out to the substrate layer to be erased. The non-volatile memory according to claim 3, wherein when the non-volatile memory is operated in the high-performance mode, the non-volatile memory generates a voltage by the control voltage, the first voltage and the second voltage The horizontal electric field and a vertical electric field cause electrons in the substrate layer to be accelerated by the horizontal electric field and enter the floating gate layer for writing. A method for operating a non-volatile memory includes: receiving a control voltage through a contact layer; receiving a first voltage through a first terminal; receiving a second voltage through a second terminal; operating in a high-performance mode When the control voltage is set to a first high voltage, the first voltage is set to zero, and the second voltage is set to the first high voltage for writing; when operating in the high-efficiency mode, through the The control voltage is set to a negative voltage, the first voltage is set to zero, and the second voltage is set to a positive voltage for erasing; when operating in a low power consumption mode, the control voltage is set to a second high Voltage, the first voltage is set to zero, and the second voltage is set to zero for writing; and when operating in the low power consumption mode, the control voltage is set to zero, The first voltage is set to zero, and the second voltage is set to the second high voltage for erasing. The operation method according to claim 5, further comprising: when operating in the low power consumption mode, allowing electrons in a substrate layer to enter a floating gate layer through the control voltage, the first voltage and the second voltage To write. The operation method according to claim 6, further comprising: when operating in the low power consumption mode, the electrons in the floating gate layer are moved out to the substrate by the control voltage, the first voltage and the second voltage Layer in order to erase. The operation method according to claim 7, wherein when operating in the high-efficiency mode, the control voltage is set to the first high voltage, the first voltage is set to zero, and the second voltage is set to the first high The step of voltage for writing includes: generating a horizontal electric field and a vertical electric field by the control voltage, the first voltage and the second voltage so that the electrons in the substrate layer are accelerated by the horizontal electric field and enter the floating Gate layer for writing.

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