TWI707337B - Circuit for gate driver on array with one to multi-stage output - Google Patents

Abstract

The invention related to a circuit for gate driver on array with one to multi- stage output, in which the circuit has a plurality of driver circuit, each of the driver circuit including a common shift register circuit and an output stage circuit, where the driver circuit is simplified by the common shift register circuit common used to the output stage circuit because of the driving signal respectively generated from the shift register circuit to a plurality of output unit of the output stage circuit.

Description

Array gate drive circuit with a pair of multi-level output design

The present invention relates to a control circuit, in particular to an on-array gate drive circuit with a pair of multi-level output design.

Liquid crystal display technology is a skillful combination of microelectronic technology and optical technology. It is widely used in mobile devices. The liquid crystal display is equipped with an array gate drive circuit and a data drive circuit, and a shift register ) It is widely used in the gate and data drive circuits of liquid crystal displays to generate scanning signals on each gate line according to the timing of sampling data signals of each data line. In the data driving circuit, the shift register is used to output a selection signal to each data line, so that image data can be sequentially written into each data line. In addition, in the gate drive circuit on the array, the shift register is used to generate a scanning signal to each gate line, so that each pixel writes the image signal supplied to each data line into each pixel according to its corresponding timing. .

In response to changes in consumer usage habits, products are gradually evolving towards high reliability, wide area operation and narrow bezels. The gate driver on the traditional array (GOA, Gate driver On Array) can be divided into a signal transmission part, an anti-noise part, and a gate pulse output part. The signal transmission part is required for the internal operation of the GOA drive circuit. The input signal is related to the signal transmission of the GOA drive circuit. The anti-noise part is the internal circuit of the GOA drive circuit for maintaining the stability of the output signal, which is related to its reliability. The Gate pulse output part is the GOA circuit output signal to the gate line (gate line). However, taking an eight-level GOA circuit as an example, with a single-stage GOA circuit that is repeated eight times, it can be observed that the signal transmission part and the anti-noise part occupy most of the area of the eight-level GOA circuit. If the circuit layout area of this function can be reduced , Which can achieve a narrow frame effect.

Based on the above problems, the present invention provides a gate drive circuit on an array with a pair of multi-level output design, which simplifies the connection relationship of the gate drive circuit by sharing the circuit design of the shift register to reduce the circuit area. And further increase the circuit reliability of the output stage circuit by synthesizing the output signal of the shared shift register.

The main purpose of the present invention is to provide an on-array gate drive circuit with a pair of multi-stage output design, which simplifies each stage of the drive circuit by sharing the shift register circuit by a plurality of output units, thus simplifying the gate drive circuit And reduce the circuit area, and can maintain the output voltage of the shared circuit.

The secondary objective of the present invention is to provide an on-array gate drive circuit with a pair of multi-level output design, which provides a pair of multi-level output design of the on-array gate drive circuit to generate a synthesized drive input signal, and further based on the synthesis The drive input signal improves circuit reliability.

The present invention discloses a gate drive circuit on an array with a pair of multi-level output design, which has a plurality of drive circuits, which respectively include a shared shift register circuit and an output stage circuit, wherein the shared shift register The circuit provides a driving input signal to the output stage circuit, and the output stage circuit generates a composite signal by receiving the driving input signal and the driving input signal of another stage through a plurality of output units respectively, for generating the gate driving signal. Since the output units in the above-mentioned output stage circuit share the common shift register circuit, the connection relationship of the gate drive circuit is simplified and the use area of the shift register is reduced.

10: Gate drive circuit on the array

20: Shared shift temporary storage circuit

30: output stage circuit

32: output unit

32A: The first stage output unit

322: The first drive input unit

322A: The first drive input unit

324: second drive input unit

324A: second drive input unit

326: drive output unit

326A: Drive output unit

32B: second level output unit

322B: The first drive input unit

324B: second drive input unit

326B: drive output unit

40: suppression circuit

42: The first noise suppression unit

44: The second noise suppression unit

CLK: Clock signal

CLK4: The fourth clock signal

CLK5: Fifth clock signal

CLK6: The sixth clock signal

CLK7: Seventh clock signal

CLK8: Eighth clock signal

CLK9: Ninth clock signal

CLK10: Tenth clock signal

CLK11: The eleventh clock signal

D: Extreme

G: gate extreme

Gm: drive input signal

Gm1: drive input signal

Gm2: Another level of drive input signal

Gm+1: Another level of drive input signal

Gn: drive output signal

Gu: Node

GuA: Node

GuB: Node

G1: The first drive output signal

G2: Second drive output signal

G3: Third drive output signal

G4: Fourth drive output signal

G5: Fifth drive output signal

G6: sixth drive output signal

G7: seventh drive output signal

G8: Eighth drive output signal

S _Gu : Synthetic signal

S _GuA : Synthetic signal

S _GuB : Synthetic signal

VSS: Reference potential

V1: first potential

V2: second potential

V3: third potential

V4: fourth potential

V5: Fifth potential

V6: sixth potential

V11: Eleventh potential

V12: Twelfth potential

V13: Thirteenth potential

V14: Fourteenth potential

V15: Fifteenth potential

V16: Sixteenth potential

V17: Seventeenth potential

V18: Eighteenth potential

V19: The nineteenth potential

V20: twentieth potential

V21: 21st potential

V22: Twenty-second potential

Figure 1: It is a block diagram of an embodiment of the invention; Figure 2: It is a block diagram of an output unit of an embodiment of the invention; Figure 3: It is a signal synthesis of an embodiment of the invention Fig. 4A: It is a waveform diagram of a composite signal versus a clock signal according to an embodiment of the present invention; Fig. 4B: A waveform of a composite signal versus a driving input signal according to an embodiment of the present invention Figure; Figure 5: It is a waveform diagram of potential improvement according to an embodiment of the present invention; Figure 6: It is a waveform diagram of a clock signal versus a driving input signal according to an embodiment of the present invention; Figure 7: It is this A waveform diagram of a clock signal versus a composite signal of an embodiment of the invention; and Figure 8: it is a block diagram of another embodiment of the invention; Figure 9: it is an output unit of another embodiment of the invention The block diagram.

In order to enable your reviewer to have a further understanding and understanding of the features of the present invention and the effects achieved, I would like to provide examples and accompanying explanations. The description is as follows:

In view of the fact that the conventional signal transmission and anti-noise circuit occupies most of the area of the GOA circuit, if the circuit layout area of this signal transmission and anti-noise circuit can be reduced, the narrow frame effect can be achieved. Accordingly, the present invention proposes a A gate drive circuit on the array with a pair of multi-level output design to solve the circuit area problem caused by the conventional technology.

Hereinafter, the characteristics and the structure of the gate drive circuit on the array disclosed by the present invention will be further explained:

First, please refer to the first figure, which is a block diagram of an embodiment of the present invention. As shown in the figure, the gate driver circuit 10 on the array with a pair of multi-level output design of the present invention includes a shared shift register circuit 20 and an output stage circuit 30, wherein the output stage circuit 30 includes a plurality of outputs Unit 32. The shared shift register circuit 20 is coupled to an output stage circuit 30, that is, is further coupled to each output unit 32. The output stage circuit 30 of this embodiment uses 8 output units as an example, but the invention is not limited to Eight, the shared shift register circuit 20 can be designed to share 2, 4, 16 or even 32 output units 32 according to usage requirements. This embodiment is based on the current technology, and the signal response is better and more simplified The circuit is taken as an example, so the output stage circuit 30 is provided with 8 output units as an example.

Following the above, in addition to receiving the driving input signal Gm generated by the shared shift register circuit 20, the output stage circuit 30 further receives one of the other stage of the shared shift register circuit (not shown) and another stage of driving input signal Gm+1 Therefore, the output units 32 of the output stage circuit 30 respectively generate a synthesized signal S _Gu (as shown in the second figure) according to the driving input signal Gm and the other stage driving input signal Gm+1, and thus respectively according to the received The signal S _Gu is synthesized to generate corresponding drive output signals G1 to G8.

As shown in the first and second figures, the output stage circuits 30 include the output units 32. This embodiment takes the first stage input unit 32A and the second stage input unit 32B as examples. The stage input unit 32A includes a first drive input unit 322A, a second drive input unit 324A, and a drive output unit 326A. The second stage input unit 32B includes a first drive input unit 322B, a second drive input unit 324B, and A drive output unit 326B. Wherein, the output stage circuit 30 further receives a plurality of clock signals CLK4-11, especially the output units 32 respectively receive the clock signals CLK4-11, which can be based on the previous stage circuit. Therefore, the present embodiment starts from the first The four-clock signal CLK4 is input to the first input unit 32, and the fourth clock signal CLK4 to the eleventh clock signal CLK11 are input to the corresponding input unit 32 respectively.

However, the nodes GuA and GuB are based on the first driving input unit 322A and the second driving input unit 324A of the first level input unit 32A to respectively receive the driving input signal Gm and the other level driving input signal Gm+1, and the driving input signal Gm is combined Another level of drive input signal Gm+1 is input to node GuA, and the first drive input unit 322A and second drive input unit 324A of the second level input unit 32B also receive the drive input signal Gm and the other level drive input signal Gm, respectively +1, the drive input signal Gm is combined with another level drive input signal Gm+1 to be input to the node GuB, and the drive output unit 326A of the first level input unit 32A is coupled to the fourth clock signal CLK4 and the reference potential VSS, so that the node GuA The fourth clock signal CLK4 is further coupled to form a composite signal S _{GuA and the} fourth clock signal CLK4 is further coupled to generate the driving output signal G1; and the driving output unit 326B of the second stage input unit 32B is coupled to the fifth clock signal CLK5 and the reference potential VSS enable node GuB to be further coupled with the fifth clock signal CLK5 to form a composite signal S _{GuB is} further coupled with the fifth clock signal CLK5 to generate the driving output signal G2; since the input units of the subsequent stages receive the driving respectively The input signal Gm and the other-level driving input signal Gm+1 are sequentially coupled to the clock signal, so the details are not repeated here.

As shown in the third figure, the output units 32 respectively include a first drive input unit 322, a second drive input unit 324, and a drive output unit 326, and the drive output unit 326 is coupled to the clock signal CLK and the reference The potential VSS. The synthesized signal S _Gu is formed at the node Gu, that is, the node Gu is coupled between the first drive input unit 322, the second drive input unit 324, and the drive output unit 326, so that the first drive input unit 322 and the second drive input The output signal of the unit 324 forms a composite signal S _Gu at the node Gu. Furthermore, when the driving output unit 326 is turned on, the composite signal S _{Gu is} further coupled to the clock signal CLK, so that the composite signal S _Gu will be as shown in Figure 4A and Figure 4 As shown in Figure B, after the driving input signal Gm is coupled to the clock signal CLK, it rises from the first potential V1 to the second potential V2. The second potential V2 is the primary coupling potential, and then falls to the third through the transistor characteristics. If the composite signal S _{Gu does} not have another level of driving input signal Gm+1, the fourth potential V4 will drop from the third level V3. However, the composite signal S _{Gu of the} present invention drives the input signal Gm+1 by another level. However, it has a secondary coupling potential V5, and then through the characteristics of a transistor, it drops to the sixth potential V6, and forms a potential in an operating range from the first potential V1 to the sixth potential V6, that is, the above-mentioned primary coupling potential and secondary coupling The potentials are all located in the operating interval, and the driving input signal Gm and another level of driving input signal Gm+1 also correspond to the operating interval. Moreover, the potential change in the above-mentioned operation interval of the present invention makes the thin film transistor (not shown) driven by the gate driving circuit 10 of the present invention have a better driving current.

As shown in Fig. 5, and referring to Fig. 4B, the composite signal S _{Gu of the} present invention is in the case where the driving input signal Gm is combined with the driving input signal Gm+1 of another level and without the driving input signal Gm+1 of the other level. After the clock signal CLK is coupled, a potential drop will be generated, so that the eleventh potential V11 is boosted to the twelfth potential V12 and falls to the operating range of the sixteenth potential V16 and the eleventh potential V11 is boosted to The seventeenth potential V17 is coupled to the nineteenth potential V19 for the second time, and the operation interval drops to the twenty-second potential V22 is different. For example, the seventeenth potential V17 and the nineteenth potential V19 maintain the drive output signal Gn The signal strength, the twenty-first potential V21 and the twenty-second potential V22 have better potentials than the fifteenth potential V15 and the sixteenth potential V16, so that the pull-down potential of the node Gu increases, so the present invention makes the array on The circuit reliability of the gate drive circuit 10 is increased, for example, the output voltage of the common circuit is maintained.

Therefore, as shown in FIGS. 6 and 7, referring to FIGS. 1 to 3 together, the driving input signal Gm1 and the driving input signal Gm2 of the other stage are provided for the output stage circuit 30 to input to each input unit 32 respectively, and The driving input signal Gm1 and the driving input signal Gm2 of another stage are respectively combined in each input unit 32 to form a composite input signal Gm', thereby coupling the clock signal received by each stage output unit 32, so that the output stage circuit 30 can output The unit 32 outputs the driving output signal Gn, in this embodiment Taking 8 output units as an example, the fourth clock signal CLK4 to the eleventh clock signal CLK11 of the output stage circuit 30 are respectively used as the input driving signals of the output stage circuit 30, so that the synthesized input signal Gm' controls The output stage circuit 30 is turned on, and each stage output unit 32 corresponding to the fourth clock signal CLK4 to the eleventh clock signal CLK11 generates the first drive output signal G1 to the eighth drive output signal G8, which is referred to The four-clock signal CLK4 is input to the corresponding output unit 32 to generate the first driving output signal G1, and the eleventh clock signal CLK11 is sequentially input to the corresponding output unit 32 to generate the eighth driving output signal G8.

Please refer to the eighth and ninth figures, which are block diagrams of another embodiment of the present invention. The difference between the first to second figures and the eighth to ninth figures is that the eighth figure further includes a suppression circuit 40, and the suppression circuit 40 further includes a first noise suppression unit 42 and a second noise suppression unit 44, and the first noise suppression unit 42 is respectively coupled to the gate terminals G of the drive output units 326A and 326B to Suppress the noise of the gate terminal G of the drive output unit 326A, 326B, and the second noise suppression unit 44 is respectively coupled to the drain terminal D of the drive output unit 326A, 326B to suppress the drain terminal D of the drive output unit 326A, 326B Noise.

The above-mentioned embodiments are based on driving input signals Gm, Gm+1 and their related driving circuits as examples. In addition, the present invention can further expand the driving input signal, for example: driving input signal Gm with another driver The input signal Gm+1 and another driving input signal Gm+2, or the driving input signal Gm is combined with another driving input signal Gm+2 to generate a corresponding composite input signal Gm' to drive the output stage circuit 30, Further achieve the goal of simplifying the gate drive circuit, reducing the circuit area and maintaining the output voltage of the shared circuit.

In summary, the gate drive circuit on the array with a one-to-multi-level output design of the present invention provides a driving input signal to each output unit of the output stage circuit through a shared shift register circuit, and allows the output stage circuit to Each of the output units is coupled to another level of driving input signal of another level of the shared shift register circuit, so as to increase the signal strength of the synthesized signal in the output unit and increase the noise suppression strength. At the same time, it further aims to make the composite signal have a secondary coupling potential and a better pull-down potential, thereby enhancing the reliability of the circuit.

Therefore, the present invention is truly novel, progressive, and available for industrial use. It should meet the patent application requirements of my country's patent law. Undoubtedly, I filed an application for a patent for invention in accordance with the law. I pray that the Bureau will grant the patent as soon as possible.

However, the above are only the preferred embodiments of the present invention, and are not used to limit the scope of implementation of the present invention. For example, the shapes, structures, features and spirits described in the scope of the patent application of the present invention are equally changed and modified. , Should be included in the scope of patent application of the present invention.

30: output stage circuit

32A: The first stage output unit

322A: The first drive input unit

324A: second drive input unit

326A: Drive output unit

32B: second level output unit

322B: The first drive input unit

324B: second drive input unit

326B: drive output unit

CLK4: The fourth clock signal

CLK5: Fifth clock signal

CLK6: The sixth clock signal

CLK7: Seventh clock signal

CLK8: Eighth clock signal

CLK9: Ninth clock signal

CLK10: Tenth clock signal

CLK11: The eleventh clock signal

G1: The first drive output signal

G2: Second drive output signal

Gm: drive input signal

Gm+1: Another level of drive input signal

GuA: Node

GuB: Node

VSS: Reference potential

Claims (10)

A gate drive circuit on an array with a pair of multi-level outputs, which includes: at least one drive circuit, which respectively includes: a shared shift register circuit that generates a drive input signal; an output stage circuit that includes a plurality of Output units, the output units respectively receive the drive input signal and at least one other stage shared shift register circuit to generate one another stage drive input signal, the output units respectively synthesize the drive input signal and the other stage The driving input signal generates a composite signal, and the output units respectively generate a gate driving signal according to the composite signal. As described in the first item of the patent application, the output units respectively include: a first drive input unit coupled to the drive input signal; a second drive input unit coupled to the Another level of drive input signal, the drive input signal and the other level of drive input signal are coupled to form the composite signal; and a drive output unit, coupled to a clock signal and a reference potential, and generates the gate drive signal according to the composite signal . In the gate drive circuit on the array as described in claim 2, wherein the drive output unit is further coupled to a node that is also coupled to the first drive input unit and the second drive input unit, the The driving input signal and the other level of driving input signal are coupled to the node to form the composite signal. For the gate drive circuit on the array as described in item 2 or 3 of the scope of patent application, wherein the drive input signal and the other stage drive input signal are respectively made by the first drive input unit and the second drive input unit to make the composite signal It has a primary coupling potential and a secondary coupling potential. In the gate drive circuit on the array as described in item 2 of the scope of patent application, the composite signal has a primary coupling potential and a secondary coupling potential, so that the potential of an operating interval of the drive output unit increases. For the gate drive circuit on the array as described in item 5 of the scope of patent application, the drive input signal and the other level drive input signal correspond to the operation interval. The gate drive circuit on the array as described in the second item of the scope of patent application further includes a suppression circuit including a first noise suppression unit and a second noise suppression unit, the first noise suppression unit The second noise suppression unit is respectively coupled to a gate terminal and a drain terminal of the drive output unit to suppress noise of the gate terminal and the drain terminal. The gate driver circuit on the array as described in item 3 of the scope of the patent application, wherein the composite signal increases the pull-down potential of one of the nodes. In the gate drive circuit on the array as described in the first item of the scope of patent application, an operating interval of the composite signal corresponds to a clock signal. For example, in the gate drive circuit on the array described in item 1 of the scope of patent application, the output units further generate the gate drive signal according to a clock signal.

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