TWI704560B - Storage device, access system and access method - Google Patents

Abstract

A storage device including a volatile memory, an non-volatile memory and a controller is provided. The controller provides a plurality of commands to the non-volatile memory. When the controller receives a reset signal, the controller determines whether a specific action has been finished. When the specific action has not been finished by the controller, the controller continuously provides the commands to the non-volatile memory. When the specific action has been finished by the controller, the controller executes a reset action according to the reset signal. When the specific action has not been finished during a predetermined period, the controller executes the reset action.

Description

Memory device, access system and access method

The present invention relates to an electronic device, in particular to a memory device.

Non-volatile memory such as flash memory has developed rapidly in recent years and is installed in various electronic devices. At present, it seems that whether it is the development of capacity or technology, it will continue to strengthen. Once more and more data is placed in this type of non-volatile memory, the storage mechanism becomes more and more important.

The present invention provides a memory device including a volatile memory, a non-volatile memory and a controller. The controller sends multiple commands to the non-volatile memory. When the controller receives a reset signal, the controller determines whether a specific action is completed. When the controller does not complete a specific action, the controller continues to send the commands to the non-volatile memory. When the controller completes a specific action, the controller performs a reset action according to the reset signal. When the controller does not complete a specific action within an expected time, the controller performs a reset action.

The present invention also provides an access system, which includes a host device and a memory device. The host device is used for providing a reset signal. The memory device receives the reset signal and includes a volatile memory, a non-volatile memory, and a controller. The controller sends multiple commands to the non-volatile memory. When the controller receives a reset signal, the controller determines whether a specific action is completed. When the controller does not complete a specific action, the controller continues to send the commands to the non-volatile memory. When the controller completes a specific action, the controller performs a reset action according to the reset signal. When the controller does not complete a specific action within an expected time, the controller performs a reset action.

The present invention also provides an access method suitable for a memory device. The memory device includes a non-volatile memory and a volatile memory. The access method of the present invention includes: receiving a reset signal; determining whether the non-volatile memory is receiving a command; when the non-volatile memory is receiving the command, determining whether a specific action is completed; when the specific action is not When completed, continue to send the command to the non-volatile memory; and when the specific action has been completed, perform a reset action, wherein the reset action is performed when the specific action is not completed within an expected time.

The access method of the present invention can be implemented by the system of the present invention, which is a hardware or firmware that can perform specific functions, or it can be recorded in a recording medium through a code method and implemented in combination with specific hardware . When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a device or system for implementing the present invention.

In order to make the purpose, features and advantages of the present invention more comprehensible, embodiments are specifically listed below, in conjunction with the accompanying drawings, for detailed description. The specification of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Wherein, the configuration of each element in the embodiment is for illustrative purposes and is not used to limit the present invention. In addition, the part of the repetition of the drawing symbols in the embodiments is for simplifying the description and does not mean the relevance between different embodiments.

Figure 1 is a schematic diagram of the access system of the present invention. As shown in the figure, the access system 100 includes a host device 110 and a memory device 120. The host device 100 is used to access the memory device 120. For example, during a write period, the host device 110 issues a read command to write an external data into the memory device 120. During a reading period, the host device 110 issues a reading command to read the data stored in the memory device 120. In other embodiments, the host device 100 sends a reset signal S _RST to initialize the memory device 120. The invention does not limit the type of the memory device 120. In one possible embodiment, the memory device 120 conforms to an Embedded MultiMediaCard (eMMC) specification or a Universal Flash Storage (UFS) protocol.

In this embodiment, the memory device 120 includes an interface 121, a controller 122, a volatile memory 123, and a non-volatile memory 124. The interface 121 is coupled between the host device 110 and the controller 122, and is used to transmit the information provided by the host device 110 to the controller 122, or transmit the information provided by the controller 122 to the host device 110. The invention does not limit the type of interface 121. The interface 121 may be a parallel transmission interface ( Parallel Interface) or a serial transmission interface (Serial Interface).

The controller 122 accesses at least one of the volatile memory 123 and the non-volatile memory 124 according to the command sent by the host device 110. In this embodiment, when the host device 110 sends a reset signal S _RST to the memory device 120, if the controller 122 is sending a command to the non-volatile memory 124, the controller 122 does not perform the reset operation temporarily. In this example, the controller 122 determines whether a specific action has been completed. When the controller 122 has not completed the specific action, the controller 122 continues to send instructions to the non-volatile memory 124 until the specific action is completed. When the controller 122 completes a specific action, the controller 122 performs a reset action according to the reset signal S _RST .

For example, suppose that for an operation (such as a read operation, a write operation, or a setting operation), the controller 122 needs to issue 100 commands to the non-volatile memory 124, and each command has 32 bits. When the host device 110 sends the reset signal S _RST , the controller 122 may have provided bits 1-16 of the 50th command to the non-volatile memory 124. However, since the controller 122 has not provided the 17th-32th bits of the 50th command to the non-volatile memory 124, the non-volatile memory 124 has not received the complete 50th command. At this time, if the controller 122 directly performs the reset operation according to the reset signal S _RST , it may cause the non-volatile memory 124 to malfunction and no longer be able to access data.

Therefore, in this embodiment, when the controller 122 receives the reset signal S _RST , if the controller 122 is sending a command to the non-volatile memory 124, the controller 122 determines whether a specific action has been completed. When the controller 122 has not completed a specific action, the controller 122 continues to send commands to the non-volatile memory 124. When the controller 122 completes a specific action, the controller 122 performs a reset action according to the reset signal S _RST . For example, after the controller 122 provides bits 17-32 of the 50th command to the non-volatile memory 124, the reset operation is performed. In this example, the specific action is that the controller 122 provides all the bits of a command (such as the 50th command) to the non-volatile memory 124, where the command is that the controller 122 receives the reset signal S At the time of _RST , a command is being provided to the non-volatile memory 124.

In another possible embodiment, the specific action means that the controller 122 transmits all commands to the non-volatile memory 124. For example, suppose that for a single operation, the controller 122 needs to send 100 commands to the non-volatile memory 124. In this example, the controller 122 will perform the reset operation after sending 100 commands to the non-volatile memory 124. In other embodiments, when the controller 122 does not complete a specific action within an expected time, it means that the controller 122 or the non-volatile memory 124 is abnormal. Therefore, the controller 122 stops sending the command to the non-volatile memory 124 and directly performs the reset operation.

In this embodiment, the controller 122 includes a reset processing circuit 125 and a control circuit 126. When the reset processing circuit 125 learns through the interface 121 that the host device 110 sends the reset signal S _RST , the reset processing circuit 125 changes the value of a reset register. In a possible embodiment, the reset register may be located in the reset processing circuit 125, the control circuit 126, the volatile memory 123 or the non-volatile memory 124. In another possible embodiment, the reset processing circuit 125 further has a counter (not shown). When the counter reaches a preset value, the reset processing circuit 125 triggers the control circuit 126. In other embodiments, the counter is located in the control circuit 126.

The control circuit 126 is used to access the volatile memory 123 and the non-volatile memory 124. In a possible embodiment, after the control circuit 126 completes a specific action, it reads a reset register value to determine whether the host device 110 sends the reset signal S _RST . In some embodiments, after the reset processing circuit 125 receives the reset signal S _RST , the reset processing circuit 125 triggers a counter (not shown). When the counter counts to a preset value, the reset processing circuit 125 sends out a trigger signal to command the control circuit 126 to immediately perform the reset action. In this example, even if the control circuit 126 has not completed a specific action, the control circuit 126 will directly perform the reset action.

Figure 2 is a schematic diagram of a possible flow of the access method of the present invention. The access method of the present invention is suitable for a memory device. The memory device includes a non-volatile memory and a volatile memory. First, a reset signal is received (step S211). In one possible embodiment, when the memory device receives the reset signal, a controller in the memory device changes the value of a reset register. The reset register may be located in the non-volatile memory, volatile memory, or controller of the memory device. In this embodiment, the controller is used to access non-volatile memory and volatile memory.

Next, it is determined whether the non-volatile memory is receiving a command (step S212). In a possible embodiment, step S212 is executed by the controller. When the non-volatile memory does not receive the command, a reset operation is directly performed (step S213). In a possible embodiment, the reset operation is to initialize an internal register of at least one of the controller, the volatile memory, and the non-volatile memory. In other embodiments, step S213 is executed by the controller.

However, when the non-volatile memory is receiving a command, it is determined whether a specific action is completed (step S214). In a possible embodiment, the controller determines whether a specific action has been completed. When the controller has completed a specific action, a reset action is performed (step S213). However, when the specific action is not completed, continue to send the command to the non-volatile memory (step S215), and return to step S214 to determine whether the specific action has been completed.

In a possible embodiment, the specific action means that the controller has provided a specific number of commands to the non-volatile memory. For example, suppose that for a single write operation or read operation, the controller provides 100 commands to the non-volatile memory. In this example, when the controller provides all 100 commands to the non-volatile memory, it means that a specific action has been completed. In another possible embodiment, the specific action refers to that the controller provides all bits of a command to the non-volatile memory, where the command is that when the memory device receives a reset command, the non-volatile memory is Instructions received.

Figure 3 is a schematic diagram of another possible flow of the access method of the present invention. Figure 3 is similar to Figure 2, except that Figure 3 has more steps S316 and S317. Since steps S311 to S315 in FIG. 3 are similar to steps S211 to S215 in FIG. 2, they will not be described again. In this embodiment, after receiving the reset command, it is determined whether the non-volatile memory is receiving the command (step S312). If so, trigger the counter (step S316). In one possible embodiment, the counter is located in the controller, non-volatile memory or volatile memory of the memory device.

When a specific action has not been completed, continue to send instructions to the non-volatile memory (step S315), and determine whether the counter counts to a specific value (step S317). When the count value of the counter has not reached the specific value, return to step S314 to continue to determine whether the specific action has been completed. However, when the count value of the counter reaches a specific value, a reset operation is performed to initialize the memory device (step S313).

Since the memory device does not immediately perform the reset operation, it can avoid the non-volatile memory from failing due to not receiving a complete command. In addition, when the memory device cannot complete a specific action within a specific period, it means that the internal components of the memory device may be abnormal. Therefore, immediately perform the reset action to eliminate the abnormal situation.

Unless otherwise defined, all vocabulary (including technical and scientific vocabulary) herein belong to the general understanding of persons with ordinary knowledge in the technical field of the present invention. In addition, unless clearly stated, the definition of a word in a general dictionary should be interpreted as consistent with the meaning in the article in its related technical field, and should not be interpreted as an ideal state or an overly formal voice.

Although the present invention has been disclosed as above in preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. . For example, the system, device, or method of the embodiment of the present invention can be implemented in a physical embodiment of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100‧‧‧Access system; 110‧‧‧Host device; 120‧‧‧Memory device; S _RST ‧‧‧Reset signal; 121‧‧‧Interface; 122‧‧‧controller; 123‧‧‧volatile Memory; 124‧‧‧Non-volatile memory; 125‧‧‧Reset processing circuit; 126‧‧‧Control circuit; S211~S215, S311~S317‧‧‧Steps.

Figure 1 is a schematic diagram of the access system of the present invention. Figure 2 is a schematic diagram of a possible flow of the access method of the present invention. Figure 3 is a schematic diagram of a possible flow of the access method of the present invention.

100‧‧‧Access System

110‧‧‧Host device

120‧‧‧Memory Device

S _RST ‧‧‧Reset signal

121‧‧‧Interface

122‧‧‧Controller

123‧‧‧volatile memory

124‧‧‧Non-volatile memory

125‧‧‧Reset processing circuit

126‧‧‧Control circuit

Claims (10)

A memory device includes: a volatile memory; a non-volatile memory; and a controller, which sends a plurality of instructions to the non-volatile memory, and includes a reset processing circuit and a control circuit; wherein when the control When the controller receives a reset signal, the controller determines whether a specific action is completed. When the controller does not complete the specific action, the controller continues to send the commands to the non-volatile memory. When the controller completes During the specific action, the controller executes a reset action according to the reset signal, wherein when the controller receives the reset signal and the non-volatile memory does not receive the commands, the controller immediately executes the reset When the reset processing circuit receives the reset signal, the reset processing circuit triggers a counter, wherein when the counter does not count to a preset value and the controller does not complete the specific action, the The control circuit does not perform the reset operation, wherein when the counter counts to the preset value, the reset processing circuit commands the control circuit to immediately perform the reset operation. The memory device described in claim 1, wherein when the controller receives the reset signal, the controller changes the value of a reset register. The memory device described in item 2 of the scope of patent application, wherein the reset register is located in the volatile memory. The memory device described in claim 1, wherein the reset operation is to reset at least one of the volatile memory and the non-volatile memory. For the memory device described in item 1 of the scope of patent application, the specific action is that the controller transmits all the commands to the non-volatile memory. The memory device described in the first item of the scope of patent application, wherein when the controller receives the reset signal and the controller is sending one of the commands to the non-volatile memory, the specific action It means that the controller transmits all the bits of the specific command to the non-volatile memory. The memory device described in claim 1, wherein the reset operation is to initialize an internal register of at least one of the controller, the volatile memory, and the non-volatile memory. An access system includes: a host device for providing a reset signal; and a memory device for receiving the reset signal, and including: a volatile memory; a non-volatile memory; and a controller , Issue a plurality of instructions to the non-volatile memory, and include a reset processing circuit and a control circuit; wherein when the controller receives a reset signal, the controller determines whether a specific action is completed, when the controller When the specific action is not completed, the controller continues to send the commands to the non-volatile memory. When the controller completes the specific action, the controller performs a reset action according to the reset signal, wherein when the control When the device receives the reset signal and the non-volatile memory does not receive the instructions, the controller immediately executes the reset action, wherein when the reset processing circuit receives the reset signal, the reset processing circuit Trigger a counter, When the counter has not counted to a preset value and the controller has not completed the specific action, the control circuit does not perform the reset action, and when the counter counts to the preset value, the reset processing circuit commands The control circuit immediately executes the reset action. The access system described in claim 8, wherein the reset action is to initialize an internal register of at least one of the controller, the volatile memory and the non-volatile memory. An access method is suitable for a memory device. The memory device includes a non-volatile memory and a volatile memory. The access method includes: receiving a reset signal; determining whether the non-volatile memory is receiving a Command; when the non-volatile memory is receiving the command, trigger a counter and determine whether a specific action is completed; when the specific action is not completed, continue to send the command to the non-volatile memory; and when the specific action has been Upon completion, perform a reset action, wherein when the reset signal is received and the non-volatile memory does not receive the command, the reset action is performed immediately, wherein when the counter has not counted to a preset value and the specific When the action has not been completed, the reset action is not executed, and the reset action is executed immediately when the counter counts to the preset value.

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