TWI704553B - Display driving circuit, frame rate adjusting method and display device - Google Patents

Abstract

A display driving circuit is used to drive a display panel at a variable frame rate. It has: a data input interface for receiving image data; a counting unit with a first enabling control terminal to be coupled to a first Enable signal, a second enable control terminal is coupled to a second enable signal, a clock input terminal is coupled to a clock signal, and an output terminal is used to output a line scan end signal, wherein, when the first When the enable signal is in the active state, the counting unit will output the line scan end signal when the count reaches a first value, and when the second enable signal is in the active state, the counting unit will count to a second When the value is set, the line scanning end signal is output, the second value is greater than the first value; and a processing unit is electrically connected to the data input interface to perform a comparison procedure on N frames of image data to determine N frames of the image Whether the image data is the same, N is an integer greater than 2, if the same, the first enable signal is output when the line scan end signal is received, if not the same, the first enable signal is output when the line scan end signal is received Two enabling signals.

Description

Display driving circuit, frame rate adjusting method and display device

The present invention relates to a display driving circuit, especially a display driving circuit with adjustable frame rate.

The frame rate of the existing display driving circuit is mainly realized by the clock frequency of an internal clock oscillator and a counter. Under normal circumstances, according to the refresh frame rate and display resolution required by the display panel, the time required for the display drive circuit to scan a row of pixels on the display panel can be calculated, and then the counter can be obtained according to this time and the clock period of the clock oscillator The count value.

However, the clock frequency of the clock oscillator and the count value of the counter after one-time programming are fixed, so the frame rate of the display driving circuit is also fixed. In this case, the display driving circuit will not be able to meet the requirements of different refresh frame rates and resolutions of the display panel.

In order to solve the above problems, a novel frame rate adjustment solution is urgently needed in this field.

An object of the present invention is to provide a frame rate adjustment solution, which can flexibly adjust the frame rate in response to changes in the picture, so as to reduce chip power consumption while maintaining a good display effect.

Another object of the present invention is to provide a frame rate adjustment solution, which can realize the frame rate adjustment function with a simple digital circuit, so as to reduce the power consumption of the chip while maintaining a good display effect.

Another object of the present invention is to provide a frame rate adjustment solution, which can be applied to various displays.

To achieve the above objective, a display driving circuit for driving a display panel at a variable frame rate is proposed. The display driving circuit has:

A data input interface for receiving image data;

A counting unit having a first enabling control terminal, a second enabling control terminal, a clock input terminal and an output terminal. The first enabling control terminal is coupled to a first enabling signal, and the second enabling control terminal is The control terminal is coupled to a second enable signal, the clock input terminal is coupled to a clock signal, the clock signal has a clock period, and the output terminal is used to output a line scan end signal, wherein when the first is enabled When the enabling signal enables the counting unit, the counting unit will output the line scan end signal when the count reaches a first value, and when the second enabling signal enables the counting unit, the counting unit will count to Outputting the line scanning end signal when a second value is greater than the first value; and

A processing unit electrically connected to the data input interface to perform a comparison procedure on the N frames of the image data to determine whether the N frames of the image data are the same, N is an integer greater than 2, and if they are the same, it is received The first enabling signal is output when the line scanning end signal is reached, and if not the same, the second enabling signal is output when the line scanning end signal is received.

In one embodiment, the second value is a time-varying value and is a value that increases with time.

In an embodiment, the counting unit has:

A first counter has an unanimity control terminal for coupling to the first enable signal, a clock input terminal for coupling to the clock signal, and an output terminal for outputting an output when the first counter counts to the first value The first counting end signal;

A second counter has an unanimity control terminal for coupling to the second enable signal, a clock input terminal for coupling to the clock signal, and an output terminal for outputting an output when the second counter counts to the second value The second counting end signal; and

An OR logic gate for performing an OR operation on the first counting end signal and the second counting end signal to generate the row scanning end signal.

In one embodiment, the second value is a time-varying value and is a value that increases with time.

In addition, the present invention also provides a display device having the aforementioned display driving circuit and display panel.

In possible embodiments, the display device may be a cathode ray tube display device, a digital light processing display device, a liquid crystal display, a light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting diode Display device, Mirco-LED display device or Mini-LED display device.

In addition, the present invention also provides a frame rate adjustment method, which is realized by driving a display panel with a display driving circuit. The display driving circuit has a data input interface, a counting unit, and a processing unit, wherein the counting unit has a A first enabling control terminal, a second enabling control terminal, a clock input terminal and an output terminal, the method includes:

Use the data input interface to receive image data;

Utilize the first enable control terminal to be coupled to a first enable signal, the second enable control terminal to couple to a second enable signal, and the clock input terminal to couple to a clock signal, the clock signal having a clock period , And the output terminal outputs a line scanning end signal, wherein when the first enabling signal enables the counting unit, the counting unit will output the line scanning end signal when the count reaches a first value, and when the first enabling signal When the two enabling signals enable the counting unit, the counting unit will output the line scan end signal when the count reaches a second value, the second value being greater than the first value; and

The processing unit is coupled to the data input interface to perform a comparison procedure on the N frames of the image data to determine whether the N frames of the image data are the same. N is an integer greater than 2, and if they are the same, it is received The first enabling signal is output when the line scanning end signal is reached, and if not the same, the second enabling signal is output when the line scanning end signal is received.

In one embodiment, the second value is a time-varying value and is a value that increases with time.

In an embodiment, the counting unit has:

A first counter has an unanimity control terminal for coupling to the first enable signal, a clock input terminal for coupling to the clock signal, and an output terminal for outputting an output when the first counter counts to the first value The first counting end signal;

A second counter has an unanimity control terminal for coupling to the second enable signal, a clock input terminal for coupling to the clock signal, and an output terminal for outputting an output when the second counter counts to the second value The second counting end signal; and

An OR logic gate for performing an OR operation on the first counting end signal and the second counting end signal to generate the row scanning end signal.

In one embodiment, the second value is a time-varying value and is a value that increases with time.

In order to enable your reviewer to further understand the structure, features and purpose of the present invention, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

Please refer to FIG. 1, which shows a block diagram of an embodiment of the display driving circuit of the present invention. The display driving circuit is used to drive a display panel at a variable frame rate.

As shown in FIG. 1, a display driving circuit 100 has a data input interface 110, a counting unit 120 and a processing unit 130.

The data input interface 110 is used to receive image data D _IMG .

The counting unit 120 has a first enabling control terminal, a second enabling control terminal, a clock input terminal and an output terminal. The first enabling control terminal is coupled to a first enabling signal EN1, and the first enabling control terminal is The two enable control terminals are coupled to a second enable signal EN2, the clock input terminal is coupled to a clock signal CLK, the clock signal CLK has a clock period, and the output terminal is used to output a line scanning end signal LINE_END, wherein, When the first enabling signal EN1 enables the counting unit 120, the counting unit 120 will output the line scan end signal LINE_END when the count reaches a first value, and when the second enabling signal EN2 enables the counting unit 120, the counting unit 120 120 will output the line scan end signal LINE_END when the count reaches a second value, and the second value is greater than the first value.

130 is electrically connected to data processing unit input interface 110 for frame N of the image data D _IMG alignment program to determine whether a frame of the image data N are the same D _IMG, N is an integer greater than 2, if the same, Then the first enable signal EN1 is output when the line scan end signal LINE_END is received, and if they are not the same, the second enable signal EN2 is output when the line scan end signal is received.

In a possible embodiment, the second value may be a time-varying value, for example, it may be increased over time to make the frame rate gradually decrease, so as to avoid the display panel from generating an abrupt picture.

Please refer to FIG. 2, which shows a circuit diagram of an embodiment of the counting unit 120 of the display driving circuit 100 of FIG. 1. As shown in FIG. 2, the counting unit 120 has a first counter 121, a second counter 122 and an OR logic gate 123.

The first counter 121 has an enabling control terminal to be coupled to the first enable signal EN1, a clock input terminal to be coupled to the clock signal CLK, and an output terminal to output a first value when the first counter 121 counts to the first value. A count end signal.

The second counter 122 has an enabling control terminal to be coupled to the second enable signal EN2, a clock input terminal to be coupled to the clock signal CLK, and an output terminal to output one when the second counter 122 counts to the second value The second count end signal.

The OR logic gate 123 is used to perform an OR operation on the first counting end signal and the second counting end signal to generate a line scanning end signal LINE_END.

In a possible embodiment, the second value of the second counter 122 may be a time-varying value, for example, a value that increases with time.

In addition, according to the above description, the present invention further proposes a frame rate adjustment method. Please refer to FIG. 3, which shows a flow chart of an embodiment of the frame rate adjustment method of the present invention. The method is implemented by driving a display panel by a display driving circuit as shown in FIG. 1, and the display driving circuit has A data input interface, a counting unit and a processing unit. The counting unit has a first enabling control terminal, a second enabling control terminal, a clock input terminal and an output terminal, and the method includes: using the data The input interface receives image data (step a); the first enable control terminal is used to couple a first enable signal, the second enable control terminal is coupled to a second enable signal, and the clock input terminal is coupled A clock signal, the clock signal has a clock period, and the output terminal outputs a line scanning end signal, wherein, when the first enable signal enables the counting unit, the counting unit will count to a first value Output the line scan end signal, and when the second enable signal enables the counting unit, the counting unit will output the line scan end signal when the count reaches a second value, the second value being greater than the first value (Step b); and using the processing unit to couple to the data input interface to perform a comparison procedure on the N frames of the image data to determine whether the N frames of the image data are the same, and N is an integer greater than 2, If they are the same, the first enable signal is output when the line scan end signal is received, and if they are not the same, the second enable signal is output when the line scan end signal is received (step c).

In a possible embodiment, the second value may be a time-varying value, for example, a value that increases with time.

In one embodiment, the counting unit has: a first counter with a uniform energy control terminal to couple the first enable signal, a clock input terminal to couple the clock signal, and an output terminal to connect to the first enable signal When a counter counts to the first value, it outputs a first counting end signal; a second counter has a uniform energy control terminal for coupling to the second enable signal, a clock input terminal for coupling to the clock signal, and a The output terminal outputs a second counting end signal when the second counter counts to the second value, where the second value can be a fixed value or a time-varying value; and an OR logic gate for the first The counting end signal and the second counting end signal perform an OR operation to generate the row scanning end signal.

Based on the above description, the present invention further provides a display device. Please refer to FIG. 4, which shows a block diagram of an embodiment of the inventive display device. As shown in FIG. 4, a display device 200 has the aforementioned display driving circuit 100 and a display panel 210 to provide a variable frame rate display effect.

In addition, in possible embodiments, the display device 200 may be a cathode ray tube display device, a digital light processing display device, a liquid crystal display, a light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting diode Display device, Mirco-LED display device or Mini-LED display device.

With the design disclosed above, the present invention has the following advantages:

1. The frame rate can be flexibly adjusted to reduce chip power consumption.

2. The frame rate adjustment function can be realized by a simple digital circuit.

3. Can be applied to various displays.

The disclosure in this case is a preferred embodiment, and any partial changes or modifications that are derived from the technical ideas of the case and can be easily inferred by those who are familiar with the art do not deviate from the scope of the patent right of the case.

To sum up, no matter the purpose, means or effect of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. I sincerely ask the examiner to check it out and grant the patent as soon as possible. Society is for the best prayer.

100: Display drive circuit 110: Data input interface 120: counting unit 121: first counter 122: second counter 123: Or logic gate 130: processing unit 200: display device 210: display panel Step a: Use the data input interface to receive image data Step b: Use the first enable control terminal to couple a first enable signal, the second enable control terminal to couple a second enable signal, the clock input terminal to couple a clock signal, the clock signal has One clock cycle, and the output terminal outputs a line scanning end signal, wherein when the first enabling signal enables the counting unit, the counting unit will output the line scanning end signal when the count reaches a first value, and When the second enabling signal enables the counting unit, the counting unit will output the line scan end signal when the count reaches a second value, the second value being greater than the first value Step c: Use the processing unit to couple to the data input interface to perform a comparison procedure on the N frames of the image data to determine whether the N frames of the image data are the same, N is an integer greater than 2, and if they are the same, The first enabling signal is output when the line scanning end signal is received, if not the same, the second enabling signal is output when the line scanning end signal is received

FIG. 1 is a block diagram of an embodiment of the display driving circuit of the present invention. FIG. 2 is a circuit diagram of an embodiment of the counting unit of the display driving circuit of FIG. 1. FIG. FIG. 3 shows a flowchart of an embodiment of the frame rate adjustment method of the present invention. FIG. 4 is a block diagram of an embodiment of the display device of the invention.

100: Display drive circuit

110: Data input interface

120: counting unit

130: processing unit

Claims (10)

A display driving circuit for driving a display panel at a variable frame rate. The display driving circuit has: a data input interface for receiving image data; a counting unit with a first enabling control terminal, a The second enable control terminal, a clock input terminal and an output terminal, the first enable control terminal is coupled to a first enable signal, the second enable control terminal is coupled to a second enable signal, the clock The input terminal is coupled to a clock signal, the clock signal has a clock period, and the output terminal is used to output a line scan end signal, wherein when the first enable signal enables the counting unit, the counting unit When the count reaches a first value, the line scan end signal is output, and when the second enable signal enables the counting unit, the counting unit will output the line scan end signal when the count reaches a second value. Two values are greater than the first value; and a processing unit electrically connected to the data input interface to perform a comparison procedure on N frames of the image data to determine whether the N frames of the image data are the same, and N is greater than 2. If the integers are the same, the first enable signal is output when the line scan end signal is received, and if they are not the same, the second enable signal is output when the line scan end signal is received. The display driving circuit according to claim 1, wherein the second value is a time-varying value and is a value that increases with time. The display driving circuit according to claim 1, wherein the counting unit has: a first counter with a uniform energy control terminal for coupling to the first enable signal, a clock input terminal for coupling to the clock signal, and a The output terminal outputs a first counting end signal when the first counter counts to the first value; a second counter has a uniform energy control terminal for coupling to the second enable signal, and a clock input terminal for coupling The clock signal and an output terminal to output a second counting end signal when the second counter counts to the second value; and an OR logic gate for the first counting end signal and the second counting end The signal performs an OR operation to generate the line scanning end signal. The display driving circuit according to claim 3, wherein the second value is a time-varying value and a value that increases with time. A display device having the display drive circuit and display panel according to any one of claims 1-4. The display device according to claim 5, which is a cathode ray tube display device, a digital light processing display device, a liquid crystal display, a light emitting diode display device, an organic light emitting diode display device, and a quantum dot light emitting diode display A display device selected by the group consisting of a device, Mirco-LED display device and Mini-LED display device. A frame rate adjustment method is realized by driving a display panel by a display driving circuit, the display driving circuit having a data input interface, a counting unit and a processing unit, wherein the counting unit has a first enabling control terminal , A second enabling control terminal, a clock input terminal and an output terminal, the method includes: using the data input interface to receive image data; using the first enabling control terminal to couple a first enabling signal, the The second enable control terminal is coupled to a second enable signal, the clock input terminal is coupled to a clock signal, the clock signal has a clock period, and the output terminal outputs a line scan end signal, wherein, when the first enable signal When the enabling signal enables the counting unit, the counting unit will output the line scan end signal when the count reaches a first value, and when the second enabling signal enables the counting unit, the counting unit will count to When a second value is output, the line scanning end signal is output, and the second value is greater than the first value; and the processing unit is coupled to the data input interface to perform a comparison procedure on N frames of image data to determine Whether the image data of N frames are the same, N is an integer greater than 2, if they are the same, the first enable signal will be output when the line scan end signal is received, if they are not the same, the line scan end will be received The second enable signal is output when the signal is output. The frame rate adjustment method according to claim 7, wherein the second value is a time-varying value and is a value that increases with time. The frame rate adjustment method according to claim 7, wherein the counting unit has: a first counter with a uniform energy control terminal for coupling to the first enable signal, a clock input terminal for coupling to the clock signal, and An output terminal is used to output a first counting end signal when the first counter counts to the first value; a second counter has a uniform energy control terminal to be coupled to the second enable signal, and a clock input terminal is coupled to Connected to the clock signal and an output terminal to output a second counting end signal when the second counter counts to the second value; and an OR logic gate for the first counting end signal and the second counting The end signal performs an OR operation to generate the line scanning end signal. The frame rate adjustment method according to claim 9, wherein the second value is a time-varying value and is a value that increases with time.

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