TWI704461B - Memory device and information processing system - Google Patents

Abstract

According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. The memory controller is configured to analyze an access to the shared memory by the one or more information processing devices and decide on an access method for accessing the shared memory by the one or more information processing devices. The memory controller is configured to give an instruction indicating the decided access method to the one or more information processing devices.

Description

Memory device and information processing system

[0001] The embodiment of the present invention relates to a memory device and an information processing system.

[0002] In recent years, computer systems have implemented large-scale data processing such as online real-time processing, big data processing, and deep learning processing. When performing such processing, the computer system must use a main memory device with a huge capacity. However, in the past, information processing devices such as servers were used as main memory devices and equipped with DRAM (Dynamic-Random Access Memory) with high standby power. Therefore, in the conventional computer system, when large-scale data processing is performed, the power consumption becomes larger.　　[0003] Also, in recent years, there have been known computer systems that connect multiple servers through a network such as an Ethernet or unlimited bandwidth to perform distributed processing. Such a computer system can execute processing at a higher speed than when a server executes processing alone. However, in such a computer system, server data transfer will occur in large numbers. Therefore, in a computer system that performs distributed processing, the processing speed will be reduced when large-scale data processing is performed. [Prior Art Document] [Non-Patent Document] 　　[0004] 　　[Non-Patent Document 1] RF Freitas and WW Wilcke, "Storage-class Memory: The Next Storage System Technology", IBM Journal of Research and Development Vol.52 No.4 , pp.439-447, 2008.

[Problem to be solved by the invention] 　　[0005] The problem to be solved by the present invention is to efficiently process a system using one or more information processing devices. [Means to Solve the Problem] 　　[0006] The memory device of the embodiment is connected to one or more information processing devices. The aforementioned memory device includes a common memory unit, an analysis unit, and a setting unit. The analysis unit analyzes the access of the one or the plural information processing device to the common memory unit, and determines the access method of the one or the plural information processing device to the common memory unit. The setting unit instructs the determined access method to the 1 or plural information processing device.

[0008] Hereinafter, the information processing system 10 according to the embodiment will be described in detail with reference to the drawings. In addition, although a plurality of embodiments are described below, the same reference numerals are attached to blocks having substantially the same functions and configurations, and the description of overlapping contents after the second embodiment will be omitted.　　[0009] (First Embodiment) 　　 FIG. 1 is a diagram showing the configuration of an information processing system 10 according to the first embodiment. The information processing system 10 includes a plurality of information processing devices 20 and a memory device 30.　　[0010] Each plural information processing device 20 is a computer that independently performs information processing. Each plural information processing device 20, for example, executes a separate operating system. Each of the plural information processing devices 20 is, for example, housed in different housings or provided on different substrates.　　[0011] In addition, in the embodiment, an information processing system 10 including a plurality of information processing devices 20 is shown. However, the information processing system 10 may be configured to include one information processing device 20.　　[0012] The memory device 30 is connected to each of the plural information processing devices 20, respectively. The memory device 30 functions as a common main memory device for each plurality of information processing devices 20. The memory device 30 receives an access request for writing and reading data from each of the plural information processing devices 20. In response to the received access request, the memory device 30 stores the data internally, or reads and outputs the internal data to the information processing device 20. The memory device 30 is, for example, housed in a different frame from the plurality of information processing devices 20 or provided on a different substrate.　　[0013] The information processing device 20 has a processing circuit 22 and an individual memory 24.　　[0014] The processing circuit 22 has: 1 or plural processors. The processor is, for example, a CPU (Central Processing Unit). The processor can contain 1 or multiple CPU cores. The processing circuit 22 executes programs and processes data. The processing circuit 22 can be of any kind as long as it can execute programs and process data. For example, the processing circuit 22 may also be a GPU (Graphics Processing Unit) used in a GPGPU (General-purpose computing on Graphics Processing Unit). In addition, the processing circuit 22 may be an accelerator such as FPGA (Field Programmable Gate Array).　　[0015] The processing circuit 22 reads data from the individual memory 24 or the memory device 30 or writes data to the individual memory 24 or the memory device 30 in response to the execution of the program. For example, the processing circuit 22 has hierarchical caches such as L1 data cache, L1 command cache, L2 cache, and L3 cache. The processing circuit 22 uses this cache to temporarily memorize the data. The processing circuit 22, for example, when a cache miss occurs at the lowest level of the cache (the last level of cache) in the hierarchical cache, a cache line unit (Cache line unit) for individual memory 24 or the memory device 30 accesses and reads or writes necessary data.　　[0016] The individual memory 24 is a memory device used as a work area performed by the processing circuit 22. The individual memory 24 is a volatile memory in which the stored data will disappear when power supply such as DRAM (Dynamic Random Access Memory) is stopped. The individual memory 24 may be a non-volatile memory such as MRAM (Magnetoresistive Random Access Memory) capable of high-speed access like DRAM. Alternatively, the individual memory 24 can also be mixed with volatile memory and non-volatile memory. The individual memory 24 is implemented as a memory module connected to DIMMs, for example.　　[0017] The processing circuit 22 can access the individual memory 24 and the memory device 30 by executing a command for memory access such as a storage command or a load command. In addition, the processing circuit 22 can respectively access the individual memory 24 and the memory device 30 in small area units such as cache line units or byte units. The processing circuit 22 and the individual memory 24 are connected by a memory bus. In addition, the processing circuit 22 and the memory device 30 are connected through a shared memory interface.　　[0018] For example, the processing circuit 22 uses the memory device 30 and the individual memory 24 as the main memory device. In addition, the processing circuit 22 can also use the individual memory 24 as a cache memory of the memory device 30. In other words, the processing circuit 22 can use the individual memory 24 as a memory for temporarily storing data stored in the memory device 30.　　[0019] The memory device 30 has a common memory unit 31 and a memory controller 40. The common memory unit 31 includes a first common memory 32, a second common memory 34, and a third common memory 36.　　[0020] The first common memory 32 and the second common memory 34 are large-capacity non-volatile memories (NVM), and the standby power is lower than that of the individual memories 24. For example, the standby power of the first common memory 32 and the second common memory 34 is zero.　　[0021] The response speed of the second common memory 34 is faster than that of the first common memory 32 (in other words, the access delay is small). In addition, the memory capacity of the second common memory 34 may be smaller than that of the first common memory 32.　　[0022] In addition, the first common memory 32 and the second common memory 34 may have a response speed slower than that of the individual memory 24, for example. As an example, the first common memory 32 and the second common memory 34 are memories whose access delay is from 10 n seconds to several μs.　　[0023] In addition, the first common memory 32 and the second common memory 34 can write and read data in the same data unit as the individual memory 24. For example, the first common memory 32 and the second common memory 34 can write and read data in small area units such as byte units. [0024] The first common memory 32 and the second common memory 34 are, for example, MRAM, PCM (Phase Change Memory), PRAM (Phase Random Access Memory), PCRAM (Phase Change Random Access Memory), and ReRAM (Resistance Change). Random Access Memory), FeRAM (Ferroelectric Random Access Memory), 3DXPoint, or Memristor, etc. The first common memory 32 and the second common memory 34 may be so-called storage-level memories (SCM). In addition, the first common memory 32 and the second common memory 34 can continue to be realized by continuously inputting power to a volatile memory that can be accessed with very low standby power and small area units such as byte units. can.　　[0025] The third common memory 36 is a volatile memory in which the stored data will disappear after the power supply of DRAM etc. is stopped. The third common memory 36 may be a non-volatile memory such as MRAM capable of high-speed access like DRAM.　　[0026] The response speed of the third common memory 36 is faster than that of the first common memory 32 and the second common memory 34. In addition, the third common memory 36 has a memory capacity smaller than that of the first common memory 32 and the second common memory 34, and the standby power may be larger.　　[0027] In addition, the common memory portion 31 may have a configuration that does not include the third common memory 36. In addition, the common memory portion 31 may have a configuration that does not include the second common memory 34. In addition, the memory device 30 may further include a non-volatile memory that is faster than the second common memory 34 and can be accessed in small area units such as byte units.　　[0028] The memory controller 40 receives an access request to the common memory unit 31 from the processing circuit 22 included in each of the plural information processing devices 20. The memory controller 40 writes and reads data to the first common memory 32, the second common memory 34, or the third common memory 36 in response to the access request. When the memory controller 40 receives the read request, the data read from the first common memory 32, the second common memory 34, or the third common memory 36 sends the access request to the information processing device 20. The processing circuit 22 has a reply.　　[0029] For example, the memory controller 40 makes the first common memory 32, the second common memory 34, and the third common memory 36 function as a hybrid main memory device of the processing circuit 22. Also, for example, the memory controller 40 may use the second common memory 34 and the third common memory 36 as a cache memory of the first common memory 32. In other words, the memory controller 40 can use the second common memory 34 and the third common memory 36 to temporarily store data stored in the first common memory 32 for the purpose of speeding up access. Of the memory. The common memory unit 31 is a main memory device that mixes three memories with different characteristics. Among the main memory devices, the response speed is fast or the response speed is slow. The memory controller 40 aims at increasing the speed of access, moving data appropriately in the main memory device, or focusing on the arrangement of the data in the main memory device. In this way, the memory controller 40 can store data, so that the memories with different characteristics in the common memory portion 31 can be used efficiently.　　[0030] Here, the storage area of the common storage unit 31 is divided into logically plural areas. Next, the memory controller 40 sets the access method to each plural area. When the memory controller 40 receives an access request for any area from the information processing device 20, it accesses the area by the access method set for the area. [0031] For example, in the memory controller 40, as the access method, it is set: the individual memory 24 is used as a cache memory for hierarchical access processing, and the first common memory 32 is used as the memory. The target is selected for direct access processing, the second common memory 34 is used as the access target for direct access processing, and the third common memory 36 is used as the access target for direct access processing. In addition, the details of specific examples of the access method will be described later.　　[0032] When setting the access method, the memory controller 40 instructs the plural information processing device 20 of the access method for each plural area. For example, the memory controller 40 instructs the access method of each plural area to the information processing device 20 that has access to the area. Then, when the information processing device 20 accesses the memory device 30, it executes data writing and reading in accordance with the access method instructed for the access target area. In addition, the common memory interface connecting each plurality of information processing devices 20 and the memory device 30 has: the information indicating the access method is transferred from the memory controller 40 of the memory device 30 to each of the plurality of information processing devices 20 function.　　[0033] FIG. 2 is a diagram showing an example of the external configuration of the information processing system 10. The information processing system 10 may include a carrier 42, for example. The carrier 42 contains a plurality of information processing devices 20 and a memory device 30. The plural information processing device 20 is connected to the memory device 30 in a state of being stored in the carrier 42. In addition, the information processing system 10 is not limited to the configuration shown in FIG. 2 and may have other configurations.　　[0034] FIG. 3 is a diagram showing the configuration of the memory controller 40 according to the first embodiment. The memory controller 40 has an access control unit 52, an analysis unit 54 and a setting unit 56.　　[0035] The access control unit 52 receives an access request to the common memory unit 31 from each of the plural information processing devices 20. For example, the access control unit 52 receives a write request or a read request to the common memory unit 31 from the plural information processing device 20. Next, the access control unit 52 controls the writing and reading of data to the common memory 31 in response to the access request of the plurality of information processing devices 20 to the common memory 31.　　[0036] The analysis unit 54 analyzes the access to the common memory unit 31 by the plural information processing device 20. Specifically, for example, the analysis unit 54 generates the accessed statistical information and analyzes the statistical information. Next, the analysis unit 54 determines the access method of the plural information processing device 20 to the common memory unit 31 based on the analysis result.　　[0037] The setting unit 56 sets the access method determined by the analysis unit 54 to the access control unit 52. In addition, the setting unit 56 instructs the determined access methods to the plural information processing devices 20 respectively.　　[0038] Moreover, the information processing device 20 accesses the common memory unit 31 by the access method instructed from the setting unit 56. Specifically, each plural information processing device 20 gives an access request to the access control unit 52 in accordance with the instructed access method. Next, when the access control unit 52 receives an access request to the common memory unit 31 from the information processing device 20, it writes and writes data to the common memory unit 31 in accordance with the access method set by the setting unit 56 Data reading.　　[0039] Here, the storage area of the common storage unit 31 is divided into logically plural areas. The analysis unit 54 analyzes the access to each complex area by the complex information processing device 20, and determines the access method to each complex area. Next, the setting unit 56 sets the determined access method to the access control unit 52 for each plural area. In addition, the setting unit 56 instructs the plural information processing device 20 to determine the access method for each plural area.　　[0040] The information processing device 20 accesses the common memory unit 31 in accordance with the access method indicated for the access target area. Specifically, the information processing device 20 makes an access request to the access control unit 52 in accordance with the access method instructed for the plural target areas. In addition, when receiving an access request from the information processing device 20, the access control unit 52 performs data writing and data reading in the corresponding area in accordance with the access method set for the access target. [0041] For example, the analysis unit 54 determines as an access method for each plural area: a first access process of writing and reading data transferred from the common memory unit 31 to the individual memory 24, or The second access process of direct writing and reading is performed on the common memory 31. Next, the setting unit 56 sets either the first access process or the second access process to the access control unit 52 for each plural area, and instructs the plural information processing device 20 to the first access process or the second access process 2 Any one of access processing. [0042] Next, each plural information processing device 20, when accessing the area instructed for the first access processing, causes the access control unit 52 to transfer the data from the common memory unit 31 to the individual memory 24, and to the individual Data in the memory 24 is written and read. In addition, when each plural information processing device 20 accesses the area instructed for the second access processing, the access control unit 52 is given a request to write and read the data stored in the common memory unit 31. In addition, the details of the first access process and the second access process will be described with reference to FIG. 4 again.　　[0043] In addition, when the analysis unit 54 determines the first access process as the access method, it may further determine the used capacity in the individual memory 24. At this time, the setting unit 56 further instructs the plurality of information processing devices 20 to use the determined capacity. Next, each plural information processing device 20 stores the data transferred from the common storage unit 31 in the individual memory 24 within the range of the instructed use capacity. In addition, the used capacity in the individual memory 24 will be described again with reference to FIG. 7.　　[0044] Next, when the analysis unit 54 determines the first access process as the access method, it may determine the backoff method in the individual memory 24. At this time, the setting unit 56 also instructs the plurality of information processing devices 20 to determine the escape method. Next, each plural information processing device 20, when the data transferred from the common memory portion 31 to the individual memory 24 exceeds the instructed use capacity, the data is evacuated from the individual memory 24 to the common memory by the instructed escape method 31. In addition, the back-off method in the individual memory 24 will be described again with reference to FIGS. 8, 9 and 10.　　[0045] In addition, the common memory unit 31 may include a first common memory 32 and a second common memory 34 whose response speed is faster than that of the first common memory 32. At this time, the first common memory 32 corresponds to each of the logically divided plural areas in the common memory portion 31 and includes physical plural memory areas. The analysis unit 54 determines the high-speed processing or the low-speed processing as the access method for the area where the second access processing is set. Next, the setting unit 56 resets the high-speed processing or the low-speed processing to the area for determining the second access processing for the access control unit 52. [0046] The access control unit 52, when receiving an access request due to the second access process from the information processing device 20 for the area where the low-speed processing is set, directs the data to the corresponding area in the first common memory 32 Write and read. In addition, the access control unit 52 transfers the data of the area corresponding to the first common memory 32 to the second common memory 34 in advance when setting high-speed processing. Next, when the access control unit 52 receives an access request due to the second access process from the information processing device 20 for the area where the high-speed processing is set, it transfers it from the first common memory 32 to the second common memory in advance. 34 data is directly written and read.　　[0047] When access is performed by the second access process, if the access delay is greater, the processing performance of the information processing device 20 will decrease. Next, the access control unit 52 transfers the data from the first common memory 32 with a large access delay to the second common memory 34 with a small access delay in advance, so that the processing performance of the information processing device 20 can be improved. In addition, the high-speed processing and low-speed processing will be described with reference to FIG. 5 again.　　[0048] The analysis unit 54 may determine the degree of parallelism indicating the number of processes to be executed in parallel as the access method for the area where the second access process is set. Next, the setting unit 56 may instruct the information processing device 20 that makes an access request in the area where the second access process is determined, and may instruct the determined parallelism.　　[0049] Upon receiving the instruction of the degree of parallelism, the processing circuit 22 of the information processing device 20 executes the parallel processing at the instructed degree of parallelism. For example, when 1 is indicated as the degree of parallelism, the processing circuit 22 executes processing with, for example, one resource (one thread). For example, when 2 is indicated as the degree of parallelism, the processing circuit 22 executes parallel processing with, for example, two resources (two threads). For example, when 4 is indicated as the degree of parallelism, the processing circuit 22 executes parallel processing with, for example, 4 resources (4 threads). [0050] More specifically, for example, the processing circuit 22 uses a hyper-threading (Hyper-Threading) mechanism that uses one processor as a plurality of virtual processors to change the number of threads to be executed (parallelism) . In addition, the processing circuit 22 may change the number of threads (the degree of parallelism) by executing different plural applications at the same time. In addition, the operating system operating on the information processing device 20 may change the switching speed of the context switch for context switching in accordance with the instructed parallelism. For example, the operating system can switch the switch method of the context switch, or switch the switch method according to the instructed parallelism.　　[0051] The analysis unit 54 may determine the degree of parallelism in accordance with the access delay of the area where the data is written by the second access process. At this time, the analysis unit 54 determines the degree of parallelism so that the greater the access delay is, the degree of parallelism is increased. For example, the analysis unit 54 determines the parallelism of the area in which data is written to the second common memory 34 with a small access delay (fast response speed) as the first parallelism (for example, parallelism = 2). In addition, the analysis unit 54 determines the degree of parallelism in the area where data is written to the first common memory 32, which has a large access delay (slow response speed), to a second degree of parallelism that is higher than the first degree of parallelism (for example, , The degree of parallelism = 3).　　[0052] When the degree of parallelism is increased, the processing circuit 22 can enter processing in other threads even if the processing in the thread is delayed due to the large access delay of the memory device 30. Therefore, when the degree of parallelism is increased, the processing circuit 22 can perform processing at high speed without stalling even if processing is performed using data stored in an area with a large access delay. [0053] In addition, when the analysis unit 54 can obtain the CPU utilization rate of the processing circuit 22 of the plural information processing device 20 in the form of the number of stall cycles, etc., the parallel degree may be changed in accordance with the obtained CPU utilization rate. . For example, at this time, the analysis unit 54 increases the degree of parallelism in areas with low CPU utilization, and decreases the degree of parallelism in areas with high CPU utilization. When the CPU utilization is high, the processing circuit 22 cannot perform high-speed processing even if the parallelism is increased. Therefore, by changing the degree of parallelism in this way, the analysis unit 54 can efficiently operate the processing circuit 22.　　[0054] In addition, the analysis unit 54 may determine the degree of parallelism in addition to the high-speed processing or the low-speed processing for the area where the second access processing is set. For example, the analysis unit 54 determines the area determined to be high-speed processing (that is, the area where data is written or read in the second common memory 34) to be the first parallelism. In addition, the analysis unit 54 determines the area determined to be low-speed processing (that is, the area where data is written or read in the first common memory 32) to be a second parallel degree higher than the first parallel degree .　　[0055] With this, the information processing device 20 can perform processing at high speed because data is written and read in the second common memory 34 with a small access delay for the area determined to be high-speed processing. In addition, because the information processing device 20 executes parallel processing with a higher degree of parallelism for the area determined to be low-speed processing, the processing can be executed at high speed. In the second access process, since the access control unit 52 executes the transfer process from the first common memory 32 to the second common memory 34, power consumption is large. Therefore, the second access processing is executed at a high speed with low power consumption, and the analyzing unit 54 may determine the low-speed processing and also set it to increase the degree of parallelism.　　[0056] In addition, when the analysis unit 54 determines the high-speed processing, it may detect a sub-area with a high possibility of being accessed in the area determined to be the high-speed processing. In addition, the access control unit 52 transfers the data of the sub-area to the second common memory 34 in advance. That is, the access control unit 52 does not transfer data to the second common memory 34 for areas other than the sub-area within the area determined to be processed at high speed. Next, the access control unit 52 directly writes and reads the data previously transferred to the second common memory 34 in response to the access request for the sub-area from the second access processing from each of the plural information processing devices 20. In addition, the access control unit 52 responds to the access request from each of the plurality of information processing devices 20 in the second access process to an area different from the sub-area in the area determined to be high-speed processing, and makes a request to the first common memory 32 for direct writing and reading. [0057] Next, the setting unit 56 performs data writing and reading on the information processing device 20 in the subarea (that is, the information processing device 20 that performs data writing or reading on the second common memory 34). ) Indicates the first degree of parallelism. In addition, the setting unit 56 performs data writing and reading of the information processing device 20 in areas other than the sub-areas within the area determined to be high-speed processing (that is, data writing in the first common memory 32). The input or read-out information processing device 20) indicates a second degree of parallelism that is higher than the first degree of parallelism. With this, since data is written to and read from the second common memory 34 with a small access delay for the sub-regions, the information processing device 20 can perform processing at high speed. In addition, because the information processing device 20 executes parallel processing for areas outside the sub-areas among the areas determined to be high-speed processing, the processing can be executed at high speed.　　[0058] FIG. 4 is a diagram for explaining the first access process and the second access process. [0059] The processing circuit 22 of the information processing device 20 performs the first access processing to the memory device 30 when writing or reading data to the first area instructing the first access processing as an access method. The requested access. [0060] When the access control unit 52 of the memory device 30 receives an access request from the information processing device 20 for the first area where the first access process is set, it reads the target data from the first common memory 32 The data block (for example, a unit called page) is forwarded to the information processing device 20 that sends the access request. The processing circuit 22 receives the data block from the access control unit 52 and stores it in the individual memory 24. In this way, the individual memory 24 can store the data block in the first common memory 32 containing the data to be accessed. Next, the processing circuit 22 writes or reads the target data contained in the data block transferred to the individual memory 24, for example, in byte units.　　[0061] Next, when the processing circuit 22 writes or reads data to the first area, it writes and reads data to the individual memory 24. In addition, when the processing circuit 22 writes or reads new object data that is not stored in the individual memory 24, it performs an access request due to the first access processing to the memory device 30, and includes the new object The data block of the data is stored in the individual memory 24. [0062] Furthermore, in the first access process, the processing circuit 22 causes the memory to be stored in the individual memory 24 when a new data block cannot be transferred because the amount of data transferred to the individual memory 24 reaches the previously instructed use capacity. The unnecessary data blocks of the memory 24 are evacuated to the common memory unit 31. In addition, the processing circuit 22 also evacuates the unnecessary data blocks stored in the individual memory 24 to the common memory unit 31 when there is a data block that is determined to not need to be stored in the individual memory 24 in advance.　　[0063] By executing such first access processing, the information processing device 20 can access data at high speed. Thereby, the information processing device 20, for example, when executing an application program that repeatedly accesses the same data, that is, an application program that performs local high memory access, can shorten the memory access time. , To achieve high efficiency processing. [0064] In addition, the processing circuit 22 of the information processing device 20 performs a second access to the memory device 30 when writing or reading data to the second area instructing the second access processing as an access method Process the access request caused. When the access control unit 52 of the memory device 30 receives an access request from the information processing device 20 for the second area for setting the second access process, it responds to the object data stored in the common memory unit 31 in bytes The unit is directly written and read.　　[0065] By executing such second access processing, the information processing device 20 can access data with a low processing amount. Thereby, the information processing device 20 can eliminate the transfer processing when, for example, an application program that accesses multiple different data once, that is, an application program that performs memory access with low locality, is executed. The burden of realizing high-efficiency processing.　　[0066] FIG. 5 is a diagram for explaining high-speed processing and low-speed processing in the second access processing.　　[0067] The access control unit 52 executes high-speed processing when it receives an access request due to the second access processing from the information processing device 20 for the third area set for high-speed processing as an access method. [0068] Specifically, when the setting unit 56 sets the third area to high-speed processing, the access control unit 52 transfers the data of the third area stored in the first common memory 32 to the second common memory in advance. Memory 34. Next, when the access control unit 52 receives an access request due to the second access process from the information processing device 20 for the third area for which high-speed processing is set, it uses the data previously transferred to the second common memory 34 Write and read directly in cache line unit or byte unit.　　[0069] In addition, the access control unit 52 may transfer all the data contained in the third area to the second common memory 34 in advance, or may transfer part of the data in the third area to the second common memory 34. In the third area, when an access request for data that has not been transferred to the second common memory 34 is received, the access control unit 52 performs direct writing and reading in the first common memory 32. Instead, the access control unit 52 transfers the data stored in the first common memory 32 to the second common memory 34 at the time when an access request of a number greater than the threshold is received, and then transfers the data stored in the first common memory 32 to the second common memory 34. 34. Writing and reading are also possible. [0070] In addition, the access control unit 52 further divides the third area into a plurality of sub-areas, and for a sub-area that has received an access request of a number greater than the threshold value, stores the data in the first common memory 32 in the sub-area. All the data may be transferred to the second common memory 34. Then, after that, the access control unit 52, when accessing the memory of the second common memory 34, continuously generates numbers above the threshold value other than the transferred subregion, and transfers it to the second subregion. 2 The data in the common memory 34 may be written back to the first common memory 32. For example, data representing each layer of a neural network in deep learning composed of multiple layers may correspond to each subregion. [0071] In addition, the access control unit 52, for example, when the data contained in the third area is read in parallel by the information processing device 20 more than a predetermined number, or when the number of accesses per unit time is large, The data contained in the third area may be transferred to a plurality of positions in the second common memory 34. Thereby, the access control unit 52 can distribute the access positions in the second common memory 34. [0072] Furthermore, in high-speed processing, the access control unit 52, for example, when the amount of data transferred to the second common memory 34 exceeds a preset capacity, or when there is a judgment that it does not need to be stored in the second common memory in advance In the area of the memory 34, the data stored in the second common memory 34 may be written back to the first common memory 32.　　[0073] In addition, the access control unit 52 executes the low-speed processing when receiving an access request due to the second access processing from the information processing device 20 for the fourth area where the low-speed processing is set as the access method. Specifically, when the access control unit 52 receives an access request due to the second access process from the information processing device 20 for the fourth area where the low-speed processing is set, the access control unit 52 issues a request to the fourth area in the first common memory 32 , To directly write and read data in byte units.　　[0074] The response speed of the second common memory 34 is faster than that of the first common memory 32. Therefore, when high-speed processing is executed, the access control unit 52 can respond to an access request at a high speed.　　[0075] In addition, when performing low-speed processing, the access control unit 52 may not perform transfer from the first common memory 32 to the second common memory 34. Therefore, when performing low-speed processing, the access control section 52 can reduce the processing amount.　　[0076] FIG. 6 is a diagram again used to explain the highest speed processing in the second access processing. The common memory section 31 may include a third common memory 36 in addition to the first common memory 32 and the second common memory 34. At this time, the setting unit 56 can again determine the highest speed processing as the access method for the area where the second access processing is set.　　[0077] The access control unit 52 executes the highest speed processing when it receives an access request from the information processing device 20 for the second access processing for the fifth area where the highest speed processing is set as the access method. [0078] Specifically, when the access control unit 52 sets the fifth area from the setting unit 56 to the highest speed processing, it transfers the data of the fifth area stored in the first common memory 32 to the third Common memory 36. Next, when the access control unit 52 receives an access request due to the second access process from the information processing device 20 for the fifth area for which the highest speed processing is set, it transfers the data in advance to the third common memory 36, Direct writing and reading are performed in units of cache lines.　　[0079] In addition, the access control unit 52 may transfer a part of the fifth area to the third common memory 36 as in the high-speed processing. At this time, the access control unit 52 executes the same processing as the high-speed processing. Also, in high-speed processing, the access control unit 52, for example, when the amount of data transferred to the third common memory 36 exceeds a preset capacity, or when it is judged that it does not need to be stored in the third common memory 36 in advance In the case of the area, the data stored in the third common memory 36 may be written back to the first common memory 32.　　[0080] Since the third common memory 36 is a DRAM, its response speed is faster than that of the first common memory 32 and the second common memory 34. Therefore, by performing such highest-speed processing, the access control unit 52 can respond at a higher speed when, for example, receiving access requests from a very large number of information processing devices 20 simultaneously.　　[0081] FIG. 7 is a diagram for explaining the indication content of the used capacity in the individual memory 24. The information processing device 20 that accesses the first area determined as the first access process further indicates the usage capacity of the individual memory 24. The information processing device 20 that instructs the use process causes the data transferred from the common memory section 31 to be stored in the individual memory 24 within the range of the instructed use capacity.　　[0082] For example, the information processing device 20 inputs power to the DRAM constituting the memory area of the instructed use capacity, stops inputting power to the DRAM constituting other memory areas, or sets it to an automatic update state. The information processing device 20, for example, when running Linux (registered trademark) as an operating system, can control the operation size of this type of DRAM by using the cgroups function. [0083] The analysis unit 54 can determine a power-saving region (sixth region) or a power-saving region (seventh region) for the first region for which the access method is determined as the first access process. . For example, the analysis unit 54 may determine the first area where the number of accesses per unit time is less than a predetermined value as the area for power saving (the sixth area), and the number of accesses per unit time may be lower than the predetermined value. The first area where the predetermined value is still larger is determined as the area where power saving is not performed (the seventh area). [0084] At this time, the setting unit 56 instructs the information processing device 20 that accesses the power-saving area (the sixth area) as the first value for storing the data of the sixth area in the individual memory. 24 usage capacity. The first value may be, for example, a first ratio to the size of the sixth area (for example, a size of 1/5). Then, the information processing device 20 that accesses the sixth area stores the data stored in the sixth area in the individual memory 24, and operates the memory area of the designated use capacity in the individual memory 24, and Stop the movement of other memory areas. [0085] At this time, the setting unit 56 instructs the information processing device 20 that accesses the area (the seventh area) that is not to be power-saving, and instructs the second value greater than the first value as the second value for setting the seventh The data of the area is stored in the used capacity of the individual memory 24. The second value may be, for example, a second ratio to the size of the seventh area (for example, a size of 1/2). Next, the information processing device 20 that accesses the seventh area stores the data stored in the seventh area in the individual memory 24, and operates the memory area of the designated use capacity in the individual memory 24, and Stop the movement of other memory areas.　　[0086] Therefore, the information processing device 20 can make the individual memory 24 operate with an appropriate usage capacity. In this way, the information processing device 20 can suppress the wasted power consumption in the individual memory 24.　　[0087] FIG. 8 is a diagram for explaining the normal back-off process. During the first access process, the information processing device 20 evacuates any data blocks stored in the individual memory 24 to the common memory when the amount of data stored in the individual memory 24 reaches the indicated use capacity. After the part 31 (after writing back), a new data block is stored in the individual memory 24. [0088] When the setting unit 56 specifies the first access process as the access method for the plural information processing device 20, it instructs the data block stored in the individual memory 24 to determine which data block to use The evacuation method of evacuation is also possible.　　[0089] As the retreat method, the setting unit 56 may instruct normal retreat processing or active retreat processing, for example. For example, the setting unit 56 instructs an aggressive back-off process as a back-off method for a power-saving area (a sixth area), and instructs a normal back-off process as a back-off method for a power-saving area (a seventh area).　　[0090] In the normal back-off process, the information processing device 20 sets the queue area in the individual memory 24. The capacity of the queue area is the indicated used capacity. In the example of Figure 8, the queue area can memorize 4 pages.　　[0091] In the normal back-off process, the information processing device 20 is an area where data blocks are backed out from the queue area in an LRU (Least Recently Used) manner. That is, in the normal back-off process, the information processing device 20 stores the new data block transferred from the common memory unit 31 at the end of the queue area. The information processing device 20, in a state where there is no empty capacity in the queue area, when a new data block is transferred, the first data block in the queue area (that is, the earliest written data block) is retracted to The common memory unit 31 (write-back). In the example of FIG. 8, the information processing device 20 evacuates page #1, which is the first data block, to the common memory unit 31. Next, the information processing device 20 retreats the previous data block, and stores the new data block at the beginning of the queue area.　　[0092] FIG. 9 is a diagram for explaining the first processing in the active backoff processing. Fig. 10 is a diagram for explaining the second processing in the active backoff processing.　　[0093] In the normal back-off process, the information processing device 20 sets the individual memory 24: the initial area and the queue area. The total capacity of the initial area and the queue area is the indicated used capacity. The initial area is the area where the data block is backed off by LRU. The queue area is an area where the data block is backed off by LRU. In the example of Fig. 9 and Fig. 10, the initial area can memorize 1 page. The queue area can memorize 4 pages.　　[0094] In the active back-off process, the information processing device 20 stores the new data block transferred from the common memory unit 31 at the end of the initial area. The information processing device 20 retransmits a new data block in a state where there is no empty capacity in the initial area, and re-transmits the first data block in the initial area (that is, the data block written in the first area) Access is to determine whether to write or read data again.　　[0095] When no re-access is performed, the information processing device 20 evacuates the first data block of the initial area to the common memory unit 31. In the example of FIG. 9, the first data block in the initial area, page #5, is not accessed again. Next, in the example of FIG. 9, the information processing device 20 evacuates #5 to the common memory unit 31. Next, the information processing device 20 retreats the data block at the head of the primary area, and stores the new data block at the head of the primary area.　　[0096] On the other hand, when re-accessing, the information processing device 20 stores the first data block of the initial area to the end of the queue area. The information processing device 20, in a state where there is no empty capacity in the queue area, when the data block at the head of the initial area is transferred, the data block at the head of the queue area (that is, the data written in the queue area at the earliest Block) is retreated to the common memory unit 31. In the example of FIG. 10, the information processing device 20 evacuates page #1, which is the first data block of the queue area, to the common memory unit 31. Next, the information processing device 20 retreats the first data block, and stores the first data block of the initial area at the beginning of the queue area.　　[0097] By using such a back-off process, the information processing device 20 can efficiently keep the frequently accessed data in the queue area. Thereby, the information processing device 20 can efficiently perform caching (caching) even when the use capacity of the individual memory 24 is small for power saving.　　[0098] In addition, the setting unit 56 is not limited to the normal back-off process and the active back-off process, and it may instruct the back-off method using any algorithm. For example, it is also possible to instruct an escape method that uses machine learning to escape the data block. In addition, the setting unit 56 can usually instruct the same evacuation method. In addition, the setting unit 56 does not instruct the escape method, and the escape process may be executed by the escape method registered in advance in the information processing device 20.　　[0099] FIG. 11 is a diagram showing an example of a processing procedure of the information processing system 10 according to the first embodiment. For example, the information processing system 10 executes processing in the flow shown in FIG. 11.　　[0100] First, in S11, the plural information processing device 20 starts to execute the application program. Next, in S12, the setting unit 56 of the memory device 30 sets the access method for all areas to the access control unit 52 as the second access process. At the same time, the setting unit 56 instructs the plural information processing device 20 to use the second access process as the access method for all areas.　　[0101] Next, in S13, the analysis unit 54 of the memory device 30 analyzes the access to the common memory unit 31 by the complex information processing device 20 for each complex area. For example, the analyzing unit 54 obtains the locality of access, the number of accesses per unit time (access rate), and the information processing device 20 that performs access, and the like.　　[0102] Next, in S14, the analysis unit 54 of the memory device 30, after starting the execution of the application program, determines whether a predetermined measurement period has elapsed. When the measurement period has not elapsed (No of S14), the analysis unit 54 of the memory device 30 waits for processing in S14. The analysis unit 54 of the memory device 30 advances the process to S15 when the measurement period has elapsed (Yes in S14).　　[0103] In S15, the analysis unit 54 of the memory device 30 determines the access method for each area based on the analysis result. Next, in S16, the setting unit 56 of the memory device 30 sets the determined access method to the access control unit 52, and instructs the access method to the plural information processing device 20.　　[0104] Through the above processing, the analysis unit 54 of the memory device 30 directly writes and reads the data stored in the common memory unit 31 after a predetermined measurement period has passed after the execution of the application program is started. Thereby, the analysis unit 54 can accurately analyze access to all areas and determine an appropriate access method. In addition, after determining the access method, the information processing system 10 may also execute the processing of S12 to S16 every fixed period.　　[0105] Fig. 12 is a diagram showing an example of an analysis result. As an example, the analysis unit 54 obtains the memory access information as an analysis result for each complex area, as shown in FIG. 12. [0106] For example, the analysis unit 54 analyzes the statistical information of the access made by the complex information processing device 20, and obtains information indicating that the locality is higher than a predetermined value or the locality is below (lower) a predetermined value for each complex area. Memory access information. More specifically, for example, the analysis unit 54 measures the number of accesses per minute unit (for example, page or byte, etc.) in each complex area. The analysis unit 54 calculates the access deviation (e.g., dispersion) in the area based on the measured number of accesses per minute unit. Next, the analysis unit 54 can determine that the locality is higher than the predetermined value if the calculated deviation is smaller than the predetermined value. If the deviation is more than the predetermined value, it can be determined that the locality is at the predetermined value. the following. In addition, the analysis unit 54 may also determine whether the locality is higher than a predetermined value by other methods.　　[0107] Also, for example, the analysis unit 54 analyzes the statistical information of the access performed by the plural information processing device 20, and for each plural area, may obtain the memory access information indicating the accessing information processing device 20. For example, the analysis unit 54 may obtain the identification number of the information processing device 20 that is accessed for each area. [0108] In addition, for example, the analysis unit 54 analyzes the statistical information of the accesses performed by the plural information processing device 20, and obtains for each plural area, the number of accesses per unit time (access rate) is more than a predetermined value. The value is still high, or the access rate is below (lower) a predetermined value. More specifically, for example, the analysis unit 54 may detect the number of accesses per predetermined time for each complex number area, and calculate the average of the number of accesses per predetermined time as the access rate.　　[0109] In addition, the analysis unit 54 is not limited to the statistical information of the access mentioned above, and may obtain other statistical information of the access performed by the plural information processing device 20. Furthermore, the analysis unit 54 is not limited to the analysis results (memory access information) mentioned above, and other analysis results may be obtained from the statistical information.　　[0110] FIG. 13 is a diagram showing an example of the procedure of the access method determination process. For each complex area, the analysis unit 54 determines the access method by, for example, the flow shown in FIG. 13.　　[0111] First, in S21, the analysis unit 54 determines whether the locality is higher than a predetermined value. The analysis unit 54 advances the process to S22 when the area is the second area whose locality is less than or equal to the predetermined value (No of S21). The analysis unit 54 advances the process to S26 when the area is the first area whose locality is higher than the predetermined value (Yes in S21).　　[0112] In S22, the analysis unit 54 determines the access method of the area as the second access process. Immediately after S22, the analysis unit 54 advances the process to S23.　　[0113] In S23, the analysis unit 54 determines whether or not the second area for which the access method is determined to be the second access process is an area for high-speed processing. For example, the analysis unit 54 determines whether or not the second area is an area that is accessed from the information processing apparatus 20 of a predetermined number or more.　　[0114] When the area is a high-speed processing area, for example, when the area is accessed from the information processing device 20 of a predetermined number or more (Yes in S23), the analysis unit 54 advances the processing to S24. Next, in S24, the analysis unit 54 determines the second area as the third area for high-speed processing.　　[0115] In addition, when the area is not a high-speed processing area, for example, when the area is not accessed from the information processing device 20 of a predetermined number or more (No of S23), the analysis unit 54 advances the process to S25. Next, in S25, the analysis unit 54 determines the second area as the fourth area for low-speed processing.　　[0116] On the other hand, in S26, the analysis unit 54 determines the access method of the area as the first access process. The analysis unit 54 immediately follows S26 and advances the process to S27.　　[0117] In S27, the analysis unit 54 determines whether or not it is a power-saving area for the first area whose access method is determined as the first access process. For example, the analysis unit 54 determines whether the number of accesses per unit time of the first area is less than or equal to a predetermined value.　　[0118] When the area is a power-saving area, for example, when the number of accesses per unit time is equal to or less than a predetermined value (Yes in S27), the analyzing unit 54 advances the process to S28. Next, in S28, the analysis unit 54 determines the usage capacity of the individual memory 24 in the first area to the first value (for example, the size of 1/5 of the area).　　[0119] The analysis unit 54 advances the process to S29 when the area is not a power-saving area, for example, when the number of accesses per unit time is greater than a predetermined value (No in S27). Next, in S29, the analysis unit 54 determines the use capacity of the individual memory 24 in the first area to a second value (for example, 1/2 of the area) that is larger than the first value.　　[0120] After finishing the processing of S24, S25, S28, or S29, the analysis unit 54 ends this flow for the area.　　[0121] FIG. 14 is a diagram showing an example of a setting table of an access method. The setting unit 56 sets, for example, the access method determined by the analysis unit 54 in the setting table. For example, as shown in FIG. 14, the setting unit 56 sets the first access process or the second access process as the access method for each area of the setting table.　　[0122] Next, when the setting unit 56 sets the first access process as the access method, it sets the used capacity in the individual memory 24 in the setting table. In addition, when setting the second access process as the access method, the setting unit 56 further sets the low-speed process or the high-speed process in the setting table.　　[0123] Again, again, the setting unit 56 sets the identification number of the information processing device 20 to be accessed for each area in the setting table. Next, the setting unit 56 instructs the information processing device 20 that accesses each plurality of areas, and instructs the access method and usage capacity set for the area.　　[0124] (Effect) 　　 As described above, in the information processing system 10, the memory device 30 instructs each of the plural information processing devices 20 to access the common memory unit 31. In the past, the general memory control device would perform passive processing in response to the write or read request of the received data. In contrast, the memory device 30 performs active processing that instructs the plural information processing devices 20 how to act.　　[0125] In this way, the information processing system 10 accesses the memory device 30 for each of the plurality of information processing devices 20 in an appropriate access method through a combination of application programs executed on the plurality of information processing devices 20. Therefore, according to the information processing system 10, the power consumption of the entire system can be suppressed, the processing speed can be increased, or the deterioration speed of the memory device 30 can be slowed down to improve reliability.　　[0126] In addition, the memory device 30 can access the same data to two or more information processing devices 20. Therefore, the information processing system 10 can obtain data between two or more information processing devices 20 without going through the network. Thus, according to the information processing system 10, when large-scale data processing is executed, the transfer processing does not become a bottleneck, and the processing can be executed at a high speed.　　[0127] In addition, the information processing system 10 uses the memory device 30 with low standby power as the main memory device of the plural information processing devices 20. Thus, according to the information processing system 10, even when large-scale data processing is performed, power consumption can be reduced.　　[0128] As described above, the information processing system 10 of the present embodiment uses the plural information processing devices 20 to efficiently perform data processing.　 　　[0129] (Second Embodiment) 　　 FIG. 15 is a diagram showing the configuration of the memory controller 40 of the second embodiment. The memory controller 40 of the second embodiment further includes a prediction model storage unit 72 and a prediction unit 74.　　[0130] The prediction model storage unit 72 stores the prediction model. The predictive model is a model used to access the common memory section 31 from the complex information processing device 20 to specify a model predicted to be the data accessed by the complex information processing device 20. The prediction model is generated in advance through learning and the like. The prediction model storage unit 72 may also be provided outside the memory device 30.　　[0131] The prediction unit 74 acquires the access mode of each complex information processing device 20 to the common memory unit 31 from the access control unit 52. For example, the prediction unit 74 obtains patterns such as the data position of the common memory unit 31 accessed by each complex information processing device 20.　　[0132] The prediction unit 74 specifies the first data that is predicted to be accessed by the information processing device 20 based on the acquired model and prediction model. The first data may be data in units of bytes, or data in units of blocks that are predicted to be data to be accessed. When the prediction unit 74 specifies the first data, among the plural information processing devices 20, the information processing device 20 predicted to access the first data instructs to obtain the first data in advance. Then, the information processing device 20 that has received the instruction issues an access request to obtain the first data to the access control unit 52. For example, the information processing device 20 that has received the instruction may obtain the first data through the second access process.　　[0133] With this, the information processing device 20 can obtain in advance the first data that is predicted to be accessed in the future. Thereby, the information processing device 20 can perform data processing on the first data at a higher speed.　　[0134] Furthermore, the prediction unit 74 specifies the second data that is predicted to be accessed by the information processing device 20 based on the acquired model and prediction model. Next, the prediction unit 74, when specifying the second data, forwards the second data to the access control unit 52 in advance to another storage unit whose transmission response speed is faster than the storage unit storing the second data.　　[0135] For example, the access control unit 52 instructs the information processing device 20 predicted to access the second data to transfer the specific second data to the individual memory 24 in advance. Next, at this time, the information processing device 20 that has received the instruction issues an access request due to the first access process to the access control unit 52 in order to obtain the second data. In this way, the information processing device 20 can transfer the second data predicted to be accessed in the future to the individual memory 24 in advance. [0136] Also, for example, when the common memory portion 31 includes: a first common memory 32 and a second common memory 34, the second data stored in the first common memory 32 can be transferred to the second common memory 34 . The response speed of the second common memory 34 is faster than that of the first common memory 32.　　[0137] With this, the access control unit 52 can store the second data predicted to be accessed in the future in the high-speed memory in advance. Thereby, the information processing device 20 can perform data processing on the second data at a higher speed.　　[0138] (Third Embodiment) 　　 FIG. 16 is a diagram showing the configuration of the information processing system 10 of the third embodiment. The information processing device 20 of the third embodiment further includes a performance collection unit 76.　　[0139] The performance collection unit 76 analyzes the program execution action executed by the processing circuit 22, and obtains the analysis result. The performance collection unit 76, as an example, detects a cache miss that occurs when the processing circuit 22 executes a program. In addition, the performance collection unit 76, as an example, detects branch processing that occurs when the processing circuit 22 executes the program. In addition, the performance collection unit 76, as an example, detects the utilization rate of the program executed by the processing circuit 22. As an example, the performance collection unit 76 may obtain performance counters such as cache miss rate, CPU branch prediction miss rate, and CPU utilization. Next, the performance collection unit 76 provides this analysis result to the memory controller 40 of the memory device 30 as operation statistical information.　　[0140] The shared memory interface that connects each plurality of information processing devices 20 and the memory device 30 has the function of transferring the motion statistics information from each plurality of information processing devices 20 to the memory controller 40 of the memory device 30. The performance collection unit 76 assigns the motion statistical information to the memory controller 40 of the memory device 30 through the shared memory interface.　　[0141] The analysis unit 54 included in the memory controller 40 obtains the analysis result, which is the operation statistical information, from the performance collection unit 76 included in each of the plural information processing devices 20. Next, the analysis unit 54 further determines the access method for each area in the common memory unit 31 based on the obtained analysis result.　　[0142] For example, the analysis unit 54 may determine an area where the frequency of cache misses per unit time is greater than a predetermined value and determine that the locality is less than a predetermined value. In addition, for example, the analysis unit 54 may also determine that the locality is less than or equal to a predetermined value in an area where the frequency per unit time of the branch processing is greater than a predetermined value. In addition, the analysis unit 54 may determine the degree of parallelism of the processing executed by the processing circuit 22 based on the utilization rate of the processor. For example, when the utilization rate of the processor is low, the analysis unit 54 may be changed to increase the degree of parallelism.　　[0143] With this, by using the analysis result of the program execution action executed by the processing circuit 22, the analysis unit 54 can more accurately analyze the access to the common memory unit 31 by the complex information processing device 20. Thereby, the analysis unit 54 can determine a more appropriate access method.　　[0144] (Fourth Embodiment) 　　 FIG. 17 is a diagram showing the configuration of the memory controller 40 of the fourth embodiment. The memory controller 40 of the fourth embodiment further includes a history storage unit 78. The history storage unit 78 stores the history of the access method set in the past in correspondence with the application programs executed in the plural information processing device 20.　　[0145] The analysis unit 54 obtains information identifying the executed application program in the plural information processing device 20. When determining the access method, the analysis unit 54 makes the determined access method correspond to the application program executed in the plural information processing device 20 and stores it in the history storage unit 78.　　[0146] Next, when the analysis unit 54 stores an application program corresponding to the execution of the plural information processing device 20 in the history storage unit 78, it determines an access method based on the history before the elapse of the measurement period.　　[0147] FIG. 18 is a diagram showing an example of a processing procedure of the information processing system 10 according to the fourth embodiment. The information processing system 10 of the fourth embodiment executes processing in the flow shown in FIG. 18.　　[0148] First, in S11, the plural information processing device 20 starts to execute the application program.　　[0149] Next, in S41, the analysis unit 54 of the memory device 30 obtains information identifying the executed application from the plural information processing device 20. Next, the analyzing unit 54 determines whether the same application program has been executed in the past. When the same application program has not been executed in the past (No of S41), the analysis unit 54 advances the process to S12. Since the processing after S12 is the same as the processing shown in FIG. 11, the description will be omitted.　　[0150] When the same application program was executed in the past (Yes in S41), the analysis unit 54 advances the process to S42. In S42, the analysis unit 54 obtains the history of the access method corresponding to the application program executed in the plural information processing device 20 from the history storage unit 78.　　[0151] Immediately after S42, in S43, the analysis unit 54 determines the access method based on the acquired history. For example, the analysis unit 54 determines the access method to have the same content as the acquired history. Next, the analysis unit 54 ends the process of S43, and then advances the process to S16. Since the processing of S16 is the same as the processing shown in FIG. 11, the description will be omitted.　　[0152] As described above, the analysis unit 54 of the fourth embodiment can determine the access method before the elapse of the measurement period when the application program executed by each plural information processing device 20 has been executed in the past. In this way, the information processing device 20 can access the memory device 30 in a suitable access method within a short time after the execution of the application program starts.　　[0153] (Fifth Embodiment) 　　 FIG. 19 is a diagram showing the configuration of the memory controller 40 of the fifth embodiment. The analysis unit 54 of the fifth embodiment includes a determination model storage unit 82, a learning unit 84, and a determination unit 86. In the fifth embodiment, the analysis unit 54 can switch the learning phase and the utilization phase.　　[0154] The judgment model storage unit 82 stores the judgment model (decision model). The decision model is a model used to obtain the most suitable access method from the action information. The decision model, for example, can be realized by a decision tree or the like. The action information is information obtained as a result of the application program being executed by the plural information processing device 20, for example, it includes: statistical information about the action of the processor, and execution time (for example, the yield rate when the plural application programs are operated at the same time) , The power consumption of the entire system, the statistical information accessed to the common memory unit 31, and the analysis results of the analytical statistical information, etc. The statistical information about the operation of the processor is, for example, information that can be obtained by the performance counter of the processor, specifically: cache miss rate, CPU branch prediction miss rate, CPU utilization, etc.　　[0155] In the learning phase, the learning unit 84 trains the judgment model. Specifically, in the learning phase, the learning unit 84 controls the setting unit 56 to change the setting of the access method to the access control unit 52 and the storage of the plural information processing device 20 while operating the plural information processing device 20. Take the instructions of the method to train the judgment model. More specifically, for example, the learning unit 84 causes the setting unit 56 to change the instruction of the access method so that the plural information processing device 20 executes the same application plural times. The learning unit 84 collects: statistical information on access to the common memory unit 31 obtained by executing each application program, statistical information on the operation of the processor, tracking information on execution time and/or power consumption, etc. Then, the collected information is used as input, and the learning unit 84 trains the judgment model so that, for example, the execution time and power consumption of the application program are optimized. In the learning phase, the learning unit 84 changes the application program to be executed by the plural information processing device 20 and trains the judgment model. In addition, in the learning phase, the learning unit 84 simultaneously executes plural applications on the plural information processing device 20, and also changes these combined training judgment models.　　[0156] In the utilization phase, the determination unit 86 operates the plural information processing device 20 to obtain operation information. Next, the determination unit 86 determines the access method based on the acquired motion information and the trained determination model. The determination unit 86 gives the determined access method to the setting unit 56.　　[0157] As described above, the analysis unit 54 of the fifth embodiment uses a pre-trained determination model to determine the access method. In this way, the analysis unit 54 can determine a more appropriate access method.　　[0158] (Sixth Embodiment) 　　 FIG. 20 is a diagram showing an example of processing of the information processing system 10 of the sixth embodiment. The analysis unit 54 determines whether the application program executed in any two or more target information processing devices 20 among the plurality of information processing devices 20 can be executed based on the usage capacity instructed to the plurality of information processing devices 20. One of the information processing devices 20 is executed by a first information processing device 20-1.　　[0159] For example, as shown in FIG. 20(A), the first information processing device 20-1 and the second information processing device 20-2 are instructed to use the capacity of the individual memory 24. The first information processing device 20-1 executes "A" as an application program. The second information processing device 20-2 executes "B" as an application program. In addition, the setting unit 56 instructs "a" for the use capacity of the first information processing device 20-1 as the individual memory 24. In addition, the setting unit 56 instructs "b" as the use capacity of the second information processing device 20-2 as the individual memory 24.　　[0160] The analysis unit 54 compares whether the empty capacity of the individual memory 24 of the first information processing device 20-1 is larger than the used capacity instructed to the second information processing device 20-2. When the empty capacity of the individual memory 24 of the first information processing device 20-1 is larger than the used capacity instructed to the second information processing device 20-2, the analysis unit 54 determines that the first information processing device 20 -1 can execute application programs executed on both the first information processing device 20-1 and the second information processing device 20-2.　　[0161] When it is judged that it is possible, the setting unit 56 instructs the first information processing device 20-1 to indicate the total amount of the usage capacity instructed to the two or more target information processing devices 20 as the usage capacity. At the same time, the setting unit 56 instructs the first information processing device 20-1 to start the execution of the program executed in the two or more target information processing devices 20. Furthermore, the setting unit 56 instructs the information processing device 20 that is not the first information processing device 20-1 among the two or more target information processing devices 20 to stop the execution of the program and shift to the power saving state. Next, the information processing device 20, which is not the first information processing device 20-1, sets the processing circuit 22 and the individual memory 24 to a power saving state such as power OFF or low power mode. In this way, the information processing system 10 sets the power consumption necessary for the entire system to the power used only to operate the first information processing device 20-1, and the power consumption can be reduced in the entire system. [0162] For example, as shown in FIG. 20(B), the setting unit 56 instructs: the sum of the usage capacity instructed to the first information processing device 20-1 and the usage capacity instructed to the second information processing device 20-2 "a +b". At the same time, the setting unit 56 instructs the first information processing device 20-1 to start execution: the application program "A" executed in the first information processing device 20-1, the application program executed in the second information processing device 20-2 "B". Next, the setting unit 56 instructs the second information processing device 20-2 to stop the execution of the application program B.　　[0163] With such processing, the memory device 30 of the sixth embodiment can stop some of the application programs executed by the information processing device 20. Thereby, the information processing device 20 that stops the execution of the application program can stop the power supply of the individual memory 24, or set it to an automatic update state. Therefore, the memory device 30 of the sixth embodiment can reduce power consumption. [0164] In addition, when the analysis unit 54 can select two or more information processing apparatuses 20 as the first information processing apparatus 20-1, it performs processing with a large number of virtual processors due to hyper-threading, etc. The information processing device 20 of the circuit 22 may be selected as the first information processing device 20-1. Thereby, the analysis unit 54 can increase the parallelism of the processing and execute the processing at high speed even when writing and reading data to and from a memory with a small access delay.　　[0165] (Seventh Embodiment) 　　 FIG. 21 is a diagram showing the configuration of the memory controller 40 of the seventh embodiment. The memory controller 40 of the seventh embodiment further includes a wear level management unit 88.　　[0166] The wear level management unit 88 manages the memory area where the number of times of rewriting in the common memory unit 31 becomes a predetermined value or more. For example, the wear level management unit 88 monitors the write processing to the common memory unit 31 and counts the number of times of rewriting for each memory area.　　[0167] The access control unit 52 obtains the number of rewrites for each memory area from the wear level management unit 88. Next, the access control unit 52 may execute the first access process regardless of the set access method when writing and reading data to the memory area where the number of times of rewriting becomes more than a predetermined value. . When the first access process is executed, the access control unit 52 does not perform highly localized writing, so the number of rewriting does not locally increase. Next, the memory device 30 can evenly write data to the entire memory area whose number of times of rewriting is equal to or greater than a predetermined value, and can extend its life.　　[0168] In addition, when determining the access method for each area, the setting unit 56 may determine whether it is an area where life extension processing is performed or an area where life extension processing is not performed. In addition, the setting unit 56 determines whether or not it is an area to be subjected to life extension processing based on the number of times of rewriting of the area. Next, the setting unit 56 sets the first access process as an access method to the area where the life extension process is performed. Thereby, the memory device 30 can evenly write data to the entire area where the number of times of rewriting is equal to or greater than a predetermined value, and can extend the life of the area.　　[0169] Although several embodiments of the present invention have been described above, these embodiments are only examples and are not intended to limit the scope of the present invention. These novel embodiments can also be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and summary of the invention, as well as the equivalent scope of the invention described in the patent application. [0170] (Example 1) 　　 A memory device connected to a 1 or a plurality of information processing devices, the memory device having: 　 a common memory unit; 　 Analyze the access of the 1 or a plurality of information processing devices to the aforementioned common memory unit , An analysis unit that determines the access method of the 1 or plural information processing device to the common memory unit; and a setting unit that instructs the access method determined by the 1 or plural information processing device. (Example 2) 　　 The memory device as described in Example 1 is further equipped with: in response to the access request of the aforementioned 1 or a plurality of information processing devices to the aforementioned common memory, control the writing of data in the aforementioned common memory And the access control unit for reading data; 　　 the aforementioned setting unit, which sets the determined access method to the aforementioned access control unit; 　 the aforementioned access control unit, according to the set access method, performs the common Write and read data in the memory section. (Mode 3) 　　 The memory device as described in Mode 2, wherein the aforementioned 1 or the plural information processing devices each have individual memories; 　　 The aforementioned analysis unit, as the aforementioned access method, is determined: The first access process for writing and reading data transferred from the memory unit to the aforementioned individual memory, or the second access process for directly writing and reading data stored in the aforementioned common memory unit; 　　 each of the aforementioned 1 Or a plurality of information processing devices, 　　 when instructing the first access process, the access control unit transfers data from the common memory unit to the individual memory, and writes and reads the data transferred to the individual memory　　 When instructing the second access process, the access control unit is given a request for writing and reading data stored in the common memory unit. (Example 4) 　　 The memory device described in Example 3, wherein the analysis unit determines the use capacity of the individual memory when determining the first access processing as the access method; The aforementioned setting unit further instructs the aforementioned use capacity for the aforementioned 1 or plural information processing devices; 　　 Each of the aforementioned 1 or multiple information processing devices causes the data transferred from the aforementioned common memory unit to be stored in the indicated range of the aforementioned use capacity The aforementioned individual memory. (Mode 5) 　　 The memory device described in mode 3 or 4, wherein the analysis unit determines the first access process as the access method, and then decides to make the data from the aforementioned individual memory　　The aforementioned setting unit further instructs the aforementioned one or plural information processing device to the aforementioned escape method; 　　each of the aforementioned one or plural information processing device causes the data transferred from the aforementioned common memory to be The instructed save method is saved from the individual memory to the common memory. (Example 6) 　　 The memory device described in any one of Examples 3 to 5, wherein the aforementioned common memory section is further equipped with: a first common memory, and the response speed is faster than the aforementioned first common memory　　The aforementioned analysis unit determines the low-speed processing or high-speed processing when the aforementioned access method determines the aforementioned second access processing; 　　the aforementioned access control unit, 　　 sets the aforementioned low-speed processing as the aforementioned access method In the second access process, in response to the access request caused by the second access process from each of the aforementioned 1 or plural information processing devices, the data stored in the aforementioned first common memory is directly written and read; When the second access process at a low speed is set as the access method, in response to the access request from the second access process from each of the one or plural information processing devices, the memory is transferred from the first common memory The data previously transferred to the aforementioned second common memory is directly written and read. (Mode 7) 　　 The memory device as described in mode 6, in which the aforementioned setting section indicates to the information processing device that makes an access request by the aforementioned second access process, indicating that the process is executed in parallel　　 When the aforementioned analysis unit is determined to be the aforementioned high-speed processing, it also detects the sub-regions that are likely to be accessed in the aforementioned first common memory; 　　 the aforementioned access control unit compares the aforementioned first The data of the aforementioned sub-area in the common memory is transferred to the aforementioned second common memory in advance. In response to the access request for the aforementioned sub-area from the aforementioned second access processing from each of the aforementioned 1 or plural information processing devices, it is forwarded to The data in the second common memory is directly written and read; 　　The access control section responds to the access to an area different from the sub-areas by the second access processing from each of the one or more information processing devices Requires direct writing and reading to the first common memory; 　　The setting section indicates the first parallelism to the information processing device that writes or reads data in the second common memory, and The information processing device for writing or reading data from the first common memory instructs a second parallelism higher than the first parallelism. (Example 8) 　　 is the memory device described in any one of the examples 3 to 5, wherein the setting unit instructs the information processing device that makes an access request by the second access processing Indicates the degree of parallelism of the number of processes executed in parallel; 　　The analysis unit determines the degree of parallelism in response to the access delay of the area where data is written by the second access process. (Example 9) "The memory device as described in Example 3, wherein the common memory portion is divided into plural areas; "The analysis portion analyzes the accesses of the 1 or the plural information processing device to each of the plural areas , Determine the access method for each of the plurality of areas; 　　 the setting section, for each of the plurality of areas, set the determined access method to the access control section, and instruct the 1 or the plurality of information processing devices The aforementioned access method determined; 　　 each of the aforementioned 1 or plural information processing devices accesses each of the aforementioned multiple areas in accordance with the aforementioned access method indicated; 　　 the aforementioned access control unit, according to the aforementioned set of the aforementioned plural areas The access method controls the writing and reading of data in the corresponding area. (Mode 10) 　　 The memory device as described in mode 9, wherein the aforementioned analysis unit, 　　 judges whether the locality of the access is higher than a predetermined value for each of the aforementioned plural areas; 　　 will be the locality of the access The aforementioned access method for the first area higher than the predetermined value is determined as the aforementioned first access processing; 　　 the aforementioned access method for the second area whose access locality is less than the predetermined value is determined as the aforementioned second Access processing. (Aspect 11) 　　 The memory device as described in aspect 10, wherein the common memory section further includes: a first common memory including each of the plurality of regions, and the response speed is faster than the first common memory　　The aforementioned analysis unit, 　　, for the aforementioned second area where the aforementioned access method is determined to be the aforementioned second access process, is determined to be a high-speed processing area or a non-high-speed processing area; 　　The aforementioned access The control unit 　　 when receiving an access request due to the aforementioned second access process for the high-speed processing area, it directly writes and reads the data previously transferred from the aforementioned first common memory to the aforementioned second common memory　　 When an access request caused by the aforementioned second access process is received for an area that is not subject to high-speed processing, the data stored in the aforementioned first common memory is directly written and read. (Aspect 12) 　　 The memory device as described in aspect 11, wherein the analysis unit determines the second area accessed from an information processing device more than a predetermined number to perform high-speed processing In the area, the second area accessed from the information processing device less than the predetermined number is determined as an area where high-speed processing is not performed. (Aspect 13) 　　 As in the memory device described in any one of aspects 10 to 12, the analysis unit determines that the access method is determined to be the first area of the first access process. Area where power saving is performed, or where power saving is not performed; 　　 the aforementioned setting section, 　　 for the aforementioned 1 or plural information processing device, indicate the first value as the use capacity of the aforementioned individual memory in the area for power saving, indicating The second value greater than the first value is used as the use capacity of the area not to be power-saving; 　　 each of the above-mentioned 1 or plural information processing devices is directed to the above-mentioned access method instructed as the above-mentioned first access process In the first area, the data transferred from the common memory unit is stored in the individual memory within the indicated use capacity range. (Aspect 14) 　　 As in the memory device described in the aspect 13, the analysis unit determines the first area where the number of accesses per unit time is less than a predetermined value as a power saving area , The first area in which the number of accesses per unit time is greater than the predetermined value is determined as an area in which power saving is not performed. (Mode 15) 　　 The memory device as described in mode 13 or 14, wherein the analysis unit determines the access method for the first area of the first access process for determining the access method Evacuation method for saving data from the aforementioned individual memory to the aforementioned common memory section; 　　 The aforementioned setting section will instruct the aforementioned 1 or plural information processing devices to the aforementioned 1 or the plural information processing device according to the aforementioned evasion method determined for each of the aforementioned first regions; Or a plurality of information processing devices make the data transferred from the first area of each of the common memory sections escape from the individual memory to the common memory section by the instructed escape method. (Example 16) 　　 The memory device described in any one of the examples 3 to 15, further equipped with: a mode for acquiring the access of the aforementioned 1 or plural information processing device to the aforementioned common memory, based on the acquired The access mode is used to specify the prediction unit predicted to be the first data accessed by the aforementioned 1 or complex information processing device; 　　 the aforementioned prediction unit, when the aforementioned first data is specified, in the aforementioned 1 or complex information processing device , For the information processing device predicted to access the first data, instruct to obtain the first data in advance. (Example 17) 　　 The memory device described in any one of the examples 3 to 15, further equipped with: a mode for acquiring the access of the aforementioned 1 or plural information processing device to the aforementioned common memory, based on the acquired The access mode is used to specify the prediction unit predicted to be the second data accessed by the 1 or the complex information processing device; 　　 the prediction unit, when specifying the second data, the access control unit makes the first 2 The data is forwarded to another memory unit that has a faster response speed than the memory unit storing the second data in advance. (Mode 18) 　　 is the memory device described in any one of modes 3 to 17, wherein the aforementioned analysis unit 　　 obtains the result of the execution operation of the analytical program from the aforementioned 1 or plural information processing device; 　　 is more based on The aforementioned results obtained determine the aforementioned access method. (Mode 19) 　　 is the memory device described in any one of the modes 3 to 18, wherein the aforementioned analysis unit, 　　 in the aforementioned 1 or plural information processing device, after the execution of the program is pre-defined During the measurement period, by directly writing and reading the data stored in the aforementioned common memory section, analyze the access to the aforementioned common memory section caused by the aforementioned 1 or plural information processing device; 　　 after the aforementioned measurement period, determine The aforementioned access method. (Mode 20) 　　 The memory device described in mode 19 is further equipped with: the history of the access method determined in the past corresponds to the program executed in the aforementioned 1 or plural information processing device and memorized History storage unit; 　　 The aforementioned analysis unit, when storing the aforementioned history corresponding to the 1 or the program executed in the plural information processing device in the aforementioned history storage unit, determines the aforementioned access based on the history before the elapse of the aforementioned measurement period method. (Mode 21) 　　 is the memory device described in any one of modes 3 to 18, wherein the analysis unit, 　　 in the learning phase, while operating the 1 or plural information processing device, by changing The aforementioned access method is trained to obtain the most suitable judgment model of the aforementioned access method from the action information obtained as a result of the execution of the application by the aforementioned 1 or plural information processing device; 　　 In the utilization phase, the aforementioned 1 or plural information is processed The device operates to obtain the aforementioned action information, and the aforementioned access method is determined based on the obtained aforementioned action information and the aforementioned determination model. (Mode 22) 　　 The memory device as described in mode 4, wherein the analysis unit determines whether it can be used in the 1 or multiple information processing device based on the use capacity indicated to the 1 or multiple information processing device The program executed in the information processing device of any two or more objects is executed by the first information processing device among the aforementioned 1 or plural information processing devices; 　　 when it is judged as possible, the aforementioned The setting unit 　　 instructs the aforementioned first information processing device as the total amount of the usage capacity indicated to the aforementioned two or more target information processing devices as the aforementioned usage capacity, and instructs the aforementioned first information processing device in the aforementioned 2 The start of the execution of the program being executed in the information processing device of more than one object; 　　 For the information processing device that is not the first information processing device among the information processing devices of the two or more objects, instruct to stop the program execution and move To save power state. (Example 23) 　　 The memory device described in any one of the examples 3 to 22, further equipped with: wear balance management for managing the memory area where the number of rewrites in the aforementioned common memory portion becomes more than a predetermined value　　 The aforementioned access control unit performs the aforementioned first access regardless of the set of aforementioned access methods when writing and reading data to the memory area whose number of times of rewriting is more than a predetermined value deal with. (Example 24) 　　 A memory device connected to a 1 or plural information processing device, the memory device having: 　 　 a common memory section divided into plural areas; and from the 1 or plural information processing device to each of the aforementioned plural The area access is used to generate statistical information of memory access, and the generated statistical information is analyzed to obtain an analysis unit for the memory access information of each of the plurality of areas. (Example 25) 　　 An information processing system comprising: 1 or plural information processing devices; 　 　 A memory device with a common memory unit connected to each of the aforementioned 1 or plural information processing devices through an interface; 　　, 　　 the aforementioned interface, 　　 will The operation statistics information of 1 or plural information processing devices is transferred from each of the aforementioned 1 or plural information processing devices to the aforementioned memory device; 　　 will be the information indicating the access method of the aforementioned 1 or plural information processing devices to the aforementioned common memory unit from the aforementioned The memory device transfers to each of the aforementioned 1 or plural information processing devices. (Example 26) 　　 An information processing system comprising: 1 or plural information processing devices; 　　 A memory device connected to the foregoing 1 or plural information processing devices via a network; 　　 Among them, 　　 The foregoing memory device includes: 　　 Common memory section　　Analyze the access of the aforementioned 1 or plural information processing device to the aforementioned common memory unit, and determine the analysis unit of the access method of the aforementioned 1 or plural information processing device to the aforementioned common memory unit; and the instruction to the aforementioned 1 or plural information processing device The setting part of the aforementioned access method that was determined. (Example 27) 　　 A memory control method that is connected to one or plural information processing devices, wherein 　 the aforementioned memory device includes: 　　 common memory; 　　 The memory control method includes: analyzing the aforementioned 1 or plural information processing The device's access to the common memory section determines the steps of the access method of the one or more information processing device to the common memory section; 　　 instructs the step of the determined access method to the one or more information processing device.

[0171]10‧‧‧Information processing system 20‧‧‧Information processing device 20-1‧‧‧First information processing device 20-2‧‧‧Second information processing device 22‧‧‧Processing circuit 24‧‧‧Individual Memory 30 ‧ ‧ Memory device 31 ‧ ‧ Common memory 32 ‧ ‧ 1st common memory 34 ‧ ‧ 2nd common memory 36 ‧ ‧ 3rd common memory 40 ‧ ‧ Memory control Device 42‧‧‧Carrier 52‧‧‧Access Control Unit 54‧‧‧Analysis Unit 56‧‧‧Setting Unit 72‧‧‧Prediction Model Memory Unit 74‧‧‧Prediction Unit 76‧‧‧Performance Collection Unit 78‧ ‧‧Resume memory unit 82‧‧‧Judgment model memory unit 84‧‧‧Learning unit 86‧‧‧Decision unit 88‧‧‧Wear balance management unit

[0007] 　　 [FIG. 1] A diagram showing the configuration of the information processing system of the first embodiment.　　[Figure 2] A diagram showing an example of the external configuration of an information processing system.　　[FIG. 3] A diagram showing the configuration of the memory controller of the first embodiment.　　[Figure 4] A diagram for explaining the first access process and the second access process.　　[Figure 5] A diagram for explaining high-speed processing and low-speed processing in the second access processing.　　[Figure 6] is again used to illustrate the highest speed processing in the second access processing.　　[Figure 7] A diagram to illustrate the indication content of the used capacity in individual memory.　　[Figure 8] A diagram to explain the normal back-off process.　　[Figure 9] A diagram for explaining the first process in the active backoff process.　　[Figure 10] A diagram for explaining the second process in the active backoff process.　　[FIG. 11] A diagram showing the processing procedure of the information processing system of the first embodiment.　　[Figure 12] A diagram showing an example of the analysis result.　　[FIG. 13] A diagram showing an example of the procedure of the access method determination process.　　[Figure 14] A diagram showing an example of the setting table of the access method.　　[FIG. 15] A diagram showing the configuration of the memory controller of the second embodiment.　　[FIG. 16] A diagram showing the configuration of the information processing system of the third embodiment.　　 [FIG. 17] A diagram showing the configuration of the memory controller of the fourth embodiment.　　[FIG. 18] A diagram showing the processing procedure of the information processing system of the fourth embodiment.　　 [FIG. 19] A diagram showing the configuration of the memory controller of the fifth embodiment.　　[FIG. 20] A diagram showing an example of processing by the information processing system of the sixth embodiment.　　[FIG. 21] A diagram showing the configuration of the memory controller of the seventh embodiment.

20‧‧‧Information Processing Device

31‧‧‧Common Memory Department

40‧‧‧Memory Controller

52‧‧‧Access Control Department

54‧‧‧Analysis Department

56‧‧‧Setting section

Claims (22)

A memory device is connected to one or plural information processing devices each having an individual memory. The memory device is provided with: a common memory section; generating access from the access of the one or plural information processing devices to the common memory section And analyze the generated statistical information to determine the access method of the 1 or plural information processing device to the common memory, which is to determine: write the data transferred from the common memory to the individual memory Determined by the first access process of input and read, or the analysis unit of the second access process of directly writing and reading data stored in the aforementioned common memory; and the instruction to the aforementioned 1 or plural information processing device The setting section of the aforementioned access method. For example, the memory device described in claim 1 is further equipped with: in response to the access request of the aforementioned 1 or a plurality of information processing devices to the aforementioned common memory portion, the storage that controls the writing and reading of data in the aforementioned common memory portion Take the control unit; the setting unit sets the determined access method to the access control unit; the access control unit writes data to the common memory unit in accordance with the set access method And data readout. The memory device described in claim 2, wherein each of the 1 or plural information processing devices, when instructing the first access process, causes the access control unit to transfer data from the common memory unit to the individual memory , To write and read the data transferred to the aforementioned individual memory; when instructing the aforementioned second access process, the aforementioned access control unit is given a request for writing and reading the data stored in the aforementioned common memory unit . For the memory device described in claim 3, the analysis unit further determines the use capacity of the individual memory when determining the first access process as the access method; the setting unit further determines the capacity of the individual memory; Or a plurality of information processing devices indicate the aforementioned use capacity; each of the aforementioned 1 or plural information processing devices causes the data transferred from the aforementioned common memory section to be stored in the aforementioned individual memory within the indicated range of the aforementioned use capacity. The memory device described in claim 3 or 4, wherein the analysis unit determines the first access process as the access method, and then decides to save data from the individual memory to the common memory The back-off method; the aforementioned setting part further instructs the aforementioned back-off method to the aforementioned 1 or plural information processing devices; each of the aforementioned 1 or plural information processing devices makes the aforementioned common memory The data transferred by the part is evacuated from the individual memory to the common memory using the instructed evasion method. The memory device according to claim 3 or 4, wherein the common memory section further includes: a first common memory, a second common memory whose response speed is faster than the first common memory; the analysis section, When the second access process is determined as the access method, then the low-speed process or the high-speed process is determined; the access control unit, when the low-speed second access process is set as the access method, responds from each of the foregoing 1 or the access request caused by the aforementioned second access process of the plural information processing device, directly write and read data stored in the aforementioned first common memory; as the aforementioned access method, set the aforementioned lower speed 2 During the access process, in response to the access request caused by the second access process from each of the aforementioned 1 or plural information processing devices, the data previously transferred from the aforementioned first common memory to the aforementioned second common memory for memory Perform direct writing and reading. The memory device according to claim 6, wherein the setting unit indicates the degree of parallelism of the number of processing executed in parallel to the information processing device that makes the access request by the second access processing; Section, when it is determined to be the aforementioned high-speed processing, it also detects a sub-region with a high possibility of being accessed in the aforementioned first common memory; The access control unit transfers the data of the sub-region in the first common memory to the second common memory in advance, and responds to the second access processing from each of the one or more information processing devices to the sub-region The area’s access request directly writes and reads data previously transferred to the second common memory; the access control unit responds to the second access processing pair from each of the one or more information processing devices The access request for an area different from the aforementioned sub-area is to directly write and read from the first common memory; the aforementioned setting section is to process information for writing or reading data in the second common memory The device indicates the first degree of parallelism, and the information processing device that writes or reads data in the first common memory instructs the second degree of parallelism that is higher than the first degree of parallelism. The memory device described in claim 3 or 4, wherein the setting unit indicates the degree of parallelism of the number of processes that are executed in parallel to the information processing device that performs the access request through the second access process; The analysis unit determines the degree of parallelism in response to the access delay of the area where the data is written by the second access process. The memory device described in claim 3, wherein the common memory section is divided into plural areas; the analysis section analyzes the access to each of the plural areas by the 1 or plural information processing device, and determines the access to each of the plural areas The aforementioned access method; The setting unit sets the determined access method to the access control unit for each of the plural areas, and instructs the 1 or plural information processing device to the determined access method; each of the 1 or plural information The processing device accesses each of the plurality of areas in accordance with the instructed access method; the access control section controls the writing of data in the corresponding area in accordance with the access method set for each of the plurality of areas Input and data readout. For the memory device described in claim 9, wherein the analysis unit determines whether the locality of the access is higher than a predetermined value for each of the plurality of regions; and determines whether the locality of the access is higher than the predetermined value. The access method for the 1 area is determined as the first access process; the access method for the second area whose access locality is less than a predetermined value is determined as the second access process. The memory device according to claim 10, wherein the common memory section further includes: a first common memory including each of the plurality of regions, and a second common memory having a faster response speed than the first common memory; The analysis unit determines whether the second area for which the access method is determined to be the second access process is an area for high-speed processing or not for high-speed processing. The access control unit, when receiving an access request due to the second access processing to the area where the high-speed processing is performed, transfers the data from the first common memory to the second common memory in advance Data is directly written and read; when an access request caused by the aforementioned second access processing is received for an area that is not subject to high-speed processing, the data stored in the aforementioned first common memory is directly written and read . For the memory device described in claim 10 or 11, the analysis unit determines whether or not the first area for which the access method is determined as the first access process is to be power-saving or not The area; the setting section indicates the first value for the 1 or the plural information processing device as the use capacity of the individual memory in the area for power saving, and indicates the second value greater than the first value As the used capacity of the area that is not to be power-saving; each of the 1 or plural information processing devices, for the first area that instructs the access method as the first access process, is transferred from the common memory unit The data is stored in the aforementioned individual memory within the indicated use capacity range. For the memory device described in claim 12, the analysis unit sets the number of accesses per unit time in the first area below a predetermined value, It is determined as an area for power saving, and the first area whose number of accesses per unit time is greater than the predetermined value is determined as an area for not saving power. For the memory device described in claim 12 or 13, wherein the analysis unit determines the access method to be the first area of the first access process, and then determines the data from the individual memory The escape method to the aforementioned common memory unit; the aforementioned setting unit will instruct the aforementioned 1 or plural information processing devices for the aforementioned escape method determined for each of the aforementioned first regions; each of the aforementioned 1 or plural information processing devices enables The data transferred from the first area in each of the common memory portions is evacuated from the individual memory to the common memory portion by the instructed escape method. For example, the memory device described in claim 3 or 4 is further equipped with: acquiring the access pattern of the aforementioned 1 or plural information processing device to the aforementioned common memory unit, and specifying the pattern predicted to be the aforementioned based on the acquired access pattern 1 or the predicting part of the first data accessed by the plural information processing device; the predicting part, when the first data is specified, is predicted to access the first data in the 1 or plural information processing device The information processing device instructs to obtain the aforementioned first data in advance. The memory device described in claim 3 or 4, wherein the aforementioned analysis unit, Obtain the result of the execution operation of the analysis program from the aforementioned 1 or plural information processing device; and determine the aforementioned access method based on the aforementioned result obtained. The memory device described in claim 3 or 4, wherein the analysis unit, in the 1 or plural information processing device, starts the execution of the program and passes a predetermined measurement period by storing it in the common memory The data of the part is directly written and read to analyze the access to the aforementioned common memory part caused by the aforementioned 1 or plural information processing device; after the aforementioned measurement period, the aforementioned access method is determined. For the memory device described in claim 3 or 4, in the learning stage, the analysis unit operates the 1 or the plural information processing device while changing the access method to train to learn from the 1 Or the most suitable judgment model of the aforementioned access method is obtained from the action information obtained as a result of the execution of the application by the plural information processing device; in the utilization stage, the aforementioned 1 or plural information processing device is operated to obtain the aforementioned action information, based on the obtained The aforementioned action information and the aforementioned determination model determine the aforementioned access method. The memory device described in claim 4, wherein the analysis unit is based on the use capacity indicated to the 1 or the plural information processing device Determine whether the program executed in any two or more target information processing devices among the aforementioned 1 or plural information processing devices can be processed by one of the aforementioned 1 or plural information processing devices. When it is judged to be possible, the setting unit indicates to the first information processing device the total amount of the use capacity indicated to the two or more target information processing devices as the use capacity , And instruct the aforementioned first information processing device to start execution of the program executed in the aforementioned two or more object information processing devices; for the aforementioned two or more object information processing devices that are not the aforementioned first information processing The information processing device of the device instructs to stop the program execution and move to a power saving state. The memory device described in claim 3 or 4 further includes: a wear level management unit that manages a memory area in which the number of times of rewriting in the common memory unit becomes a predetermined value or more; When data is written and read in the memory area where the number of times of rewriting becomes more than a predetermined value, the first access process is executed regardless of the set access method. A memory device is connected to a 1 or plural information processing device, the memory device is provided with: a common memory portion divided into plural areas; and generated from the access of the 1 or plural information processing devices to each of the plural areas Statistics of memory access, analysis of the aforementioned statistics generated The analysis unit obtains the memory access information whose locality is higher than the predetermined value or the locality is below the predetermined value in each of the aforementioned plural areas. An information processing system is provided with: 1 or plural information processing devices; a memory device having a common memory unit connected to each of the foregoing 1 or plural information processing devices through an interface; wherein the foregoing memory device includes: from the foregoing 1 or The plural information processing device generates access statistical information for the access to the common memory unit, and analyzes the generated statistical information, as a method for determining the 1 or the access method of the plural information processing device to the common memory unit, is determined: The first access process for writing and reading data transferred from the common memory to the individual memory, or the second access process for directly writing and reading data stored in the common memory The aforementioned interface of the analysis part transfers the operation statistics information of the aforementioned 1 or plural information processing devices from each of the aforementioned 1 or plural information processing devices to the aforementioned memory device; and forwards the information indicating the aforementioned access method from the aforementioned memory device to the aforementioned memory device. Each of the aforementioned 1 or plural information processing devices.

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