TWI703700B - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

Provided are a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor structure and its manufacturing method, and more particularly to a semiconductor package and its manufacturing method.

In the field of semiconductor packaging technology, semiconductor packaging has been developing in terms of size reduction and multi-function. In a general semiconductor package, in order to meet multi-functional requirements, a plurality of semiconductor dies are usually included, and these dies may have different functions and different areas. For example, these dies may include logic dies with a relatively large area and memory dies and controller dies with relatively small areas. In addition, these dies are all disposed on an interposer, and are electrically connected to a printed circuit board (PCB) through the interposer. As a result, the interposer needs to have a larger size, and therefore the semiconductor package cannot be effectively miniaturized. In addition, since the interposer is provided in the semiconductor package, the transmission speed of the electrical signal is also delayed.

The present invention provides a semiconductor package, which includes semiconductor crystal grains of different sizes stacked on each other and does not have an interposer.

The present invention provides a method for manufacturing a semiconductor package, which is used for manufacturing the above-mentioned semiconductor package.

The semiconductor package of the present invention includes a first semiconductor die, a first redistribution layer (redistribution layer, RDL layer), a second semiconductor die, a plurality of conductive vias, an encapsulant, and a second rewiring layer. Wiring layer, third semiconductor die, and third rewiring layer. The first semiconductor die has an active surface and a back surface opposite to each other. The first redistribution layer is disposed on the active surface of the first semiconductor die and is electrically connected to the first semiconductor die. The second semiconductor die has an active surface and a back surface opposite to each other, and is disposed on the first redistribution layer in such a manner that the active surface faces the first redistribution layer, wherein a plurality of first silicon vias A through-silicon via (TSV) is arranged in the second semiconductor die, and the second semiconductor die is electrically connected to the first redistribution layer through the plurality of first silicon vias. The plurality of vias are arranged on the first redistribution layer, located around the second semiconductor die, and are electrically connected to the first redistribution layer. The encapsulation body is disposed on the first redistribution layer, and covers the second semiconductor die and the plurality of via holes. The second rewiring layer is disposed on the encapsulation body and is electrically connected to the plurality of via holes and the plurality of first silicon via holes in the second semiconductor die. The third semiconductor die has an active surface and a back surface opposite to each other, and is disposed on the second redistribution layer in such a manner that the active surface faces the second redistribution layer, wherein a plurality of second silicon vias Is arranged in the third semiconductor die, and the third semiconductor die is electrically connected to the second rewiring layer through the plurality of second silicon vias. The third rewiring layer is disposed on the third semiconductor die and is electrically connected to the plurality of second silicon vias in the third semiconductor die. From the perspective of the top view from the third semiconductor die to the first semiconductor die, the area of the second semiconductor die is smaller than the area of the first semiconductor die, and the third semiconductor die The area of the grain is larger than the area of the second semiconductor die.

The manufacturing method of the semiconductor package of the present invention includes the following steps: providing a first semiconductor die, wherein the first semiconductor die has an active surface and a back surface opposite to each other; on the active surface of the first semiconductor die Forming a first rewiring layer, wherein the first rewiring layer is electrically connected to the first semiconductor die; stacking a second semiconductor die on the first rewiring layer, wherein the second semiconductor die The die has an active surface and a back surface opposite to each other, and the second semiconductor die faces the first rewiring layer with the active surface, and a plurality of first silicon vias are formed in the second semiconductor die And the second semiconductor die is electrically connected to the first redistribution layer through the plurality of first silicon vias; a plurality of vias are formed on the first redistribution layer, wherein The plurality of via holes are located around the second semiconductor die and are electrically connected to the first redistribution layer; an encapsulation body is formed on the first redistribution layer, wherein the encapsulation body covers The second semiconductor die and the plurality of vias; a second redistribution layer is formed on the encapsulation body, wherein the second redistribution layer and the plurality of vias and the second semiconductor The plurality of first silicon vias in the die are electrically connected; a third semiconductor die is stacked on the second rewiring layer, wherein the third semiconductor die has an active surface and a back surface opposite to each other, And the third semiconductor die faces the second rewiring layer with the active surface, and a plurality of second silicon vias are formed in the third semiconductor die, and the third semiconductor die Electrically connected to the second rewiring layer through the plurality of second silicon vias; and forming a third rewiring layer on the third semiconductor die, wherein the third rewiring layer is connected to the The plurality of second silicon vias in the third semiconductor die are electrically connected. From the perspective of the top view from the third semiconductor die to the first semiconductor die, the area of the second semiconductor die is smaller than the area of the first semiconductor die, and the third semiconductor die The area of the grain is larger than the area of the second semiconductor die.

Based on the above, in the semiconductor package of the present invention, the components are electrically connected to each other through the silicon vias and the interposer is omitted, so the transmission speed of electronic signals can be effectively increased. In addition, in the semiconductor package of the present invention, semiconductor dies with a larger size and semiconductor dies with a smaller size are alternately stacked, so warpage caused by uneven stress can be avoided. In addition, since the interposer is omitted and the semiconductor dies are alternately stacked, the size of the semiconductor package can be greatly reduced.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

The following examples are listed in conjunction with the accompanying drawings for detailed description, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. To facilitate understanding, the same elements will be described with the same symbols in the following description.

The terms "include", "include", "have", etc. mentioned in the text are all open terms, which means "including but not limited to". In addition, the directional terms such as "上" and "下" mentioned in the text are only used to refer to the direction of the drawings, and are not used to limit the present invention. When the terms "first", "second", etc. are used to describe elements, they are only used to distinguish these elements from each other, and do not limit the order or importance of these elements. Therefore, in some cases, the first element can also be referred to as the second element, and the second element can also be referred to as the first element, and this does not deviate from the scope of the patent application.

In the following embodiments, the numbers and shapes mentioned are only used to illustrate the present invention in detail to facilitate understanding of the content, but not to limit the present invention.

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor package according to an embodiment of the invention. First, referring to FIG. 1A, a first semiconductor die 100 having an active surface 100a and a back surface 100b opposite to each other is provided. The first semiconductor die 100 is a semiconductor die having a larger size, such as a logic die. In this embodiment, the “size” refers to the area of the semiconductor die viewed from the top of the active surface of the semiconductor die. Various semiconductor elements are formed on the active surface 100a of the first semiconductor die 100 (in order to make the diagram clear, not shown), and these semiconductor elements are, for example, a transistor, an interconnection, and a pad ( pad) etc. In this embodiment, the semiconductor die 100 with a larger size can be used as a supporting substrate in the semiconductor packaging process.

Then, a first rewiring layer 102 is formed on the active surface 100a of the first semiconductor die 100. The first rewiring layer 102 is electrically connected to the first semiconductor die 100. The first rewiring layer 102 may include a dielectric layer 102a and a first circuit layer 102b disposed in the dielectric layer 102a. The first rewiring layer 102 can be connected to the pads of the first semiconductor die 100 through the first circuit layer 102b. In FIG. 1A, the number of layers of the first circuit layer 102b of the first rewiring layer 102 is only for example, and is not intended to limit the present invention. The manufacturing method of the first redistribution layer 102 is well known to those skilled in the art, and will not be repeated here.

Next, referring to FIG. 1B, a second semiconductor die 104 having an active surface 104a and a back surface 104b opposite to each other is stacked on the first redistribution layer 102. The second semiconductor die 104 is a semiconductor die with a smaller size, such as a memory die or a controller die. Various semiconductor elements (not shown for clarity of the drawing) are formed on the active surface 104a of the second semiconductor die 104, and these semiconductor elements are, for example, transistors, interconnects, and pads. The first silicon via 104c is formed in the second semiconductor die 104 and penetrates the second semiconductor die 104. In this embodiment, the second semiconductor die 104 is disposed on the first redistribution layer 102 with the active surface 104a facing the first redistribution layer 102 (ie, in the form of a flip die), and is connected to the first redistribution layer 102. The single wiring layer 102 is electrically connected. In this embodiment, the second semiconductor die 104 is connected to the first circuit layer 102b of the first redistribution layer 102 through the first silicon via 104c and the bump 106 located outside, but the invention is not limited to this. In other embodiments, the second semiconductor die 104 can be connected to the first circuit layer 102b of the first redistribution layer 102 through other external connection members. In addition, in this embodiment, an underfill 108 may be selectively formed between the second semiconductor die 104 and the first redistribution layer 102 to protect the second semiconductor die 104 and the first redistribution layer. 102 between the bumps 106.

Then, referring to FIG. 1C, a plurality of via holes 110 are formed on the first redistribution layer 102. The via hole 110 is located around the second semiconductor die 104 and is electrically connected to the first redistribution layer 102. The via hole 110 is, for example, a copper conductive column, and its formation method is well known to those skilled in the art, and will not be repeated here. In this embodiment, the via holes 110 surround the second semiconductor die 104 and are connected to the first circuit layer 102 b of the first redistribution layer 102. The top surface of the via hole 110 may be coplanar with the back surface 104b of the second semiconductor die 104, or the top surface of the via hole 110 may be higher than the back surface 104b of the second semiconductor die 104, which is not limited in the present invention. Next, an encapsulation body 112 is formed on the first redistribution layer 102. The encapsulation body 112 covers the second semiconductor die 104 and the via hole 110.

In this embodiment, a molding process is performed to form the encapsulation body 112, so that the encapsulation body 112 covers the sidewalls of the second semiconductor die 104 and the sidewalls of the via holes 110, and exposes the second semiconductor die. The back surface 104b of the pellet 104 and the top surface of the via hole 110, but the present invention is not limited thereto. In other embodiments, a molding process is performed to form the encapsulation body 112 such that the encapsulation body 112 covers the entire second semiconductor die 104 and the entire via hole 110. Afterwards, a grinding process is performed to remove part of the encapsulation body 112 (if the top surface of the via hole 110 is higher than the back surface 104b of the second semiconductor die 104, the part is removed at the same time) until the second semiconductor is exposed The back surface 104b of the die 104 and the top surface of the via hole 110. In this way, the back surface 104b of the second semiconductor die 104, the top surface of the via hole 110, and the top surface of the encapsulation body 112 are coplanar, so that other components can be stably disposed thereon.

Next, referring to FIG. 1D, a second rewiring layer 114 is formed on the encapsulation body 112. The second redistribution layer 114 is electrically connected to the via hole 110 and the first silicon via hole 104c in the second semiconductor die 104. The second rewiring layer 114 may include a dielectric layer 114a and a second circuit layer 114b disposed in the dielectric layer 114a. The second rewiring layer 114 can be connected to the via hole 110 and the first silicon via hole 104c in the second semiconductor die 104 through the second circuit layer 114b. In FIG. 1D, the number of layers of the second circuit layer 114b of the second rewiring layer 114 is only for example, and is not intended to limit the present invention. The manufacturing method of the second rewiring layer 114 is well known to those skilled in the art, and will not be repeated here. In this embodiment, since the back surface 104b of the second semiconductor die 104, the top surface of the via hole 110, and the top surface of the encapsulation body 112 are coplanar, the second redistribution layer 114 can be stably disposed thereon .

Then, referring to FIG. 1E, a third semiconductor die 116 having an active surface 116a and a back surface 116b opposite to each other is stacked on the second rewiring layer 114. The third semiconductor die 116 is a semiconductor die having a larger size, such as a logic die. The third semiconductor die 116 may be the same as or different from the first semiconductor die 100, which is not limited in the present invention. In addition, in this embodiment, the third semiconductor die 116 may have the same size as the first semiconductor die 100, but the invention is not limited thereto. In other embodiments, the third semiconductor die 116 may not have the same size as the first semiconductor die 100 as long as the size of the third semiconductor die 116 is larger than the size of the second semiconductor die 104.

Various semiconductor elements are formed on the active surface 116a of the third semiconductor die 116 (in order to make the diagram clear, not shown), and these semiconductor elements are, for example, transistors, interconnects, and pads. The second silicon via 116c is formed in the third semiconductor die 116 and penetrates the third semiconductor die 116. In this embodiment, the third semiconductor die 116 is disposed on the second redistribution layer 114 with the active surface 116a facing the second redistribution layer 114 (that is, in a flip chip), and is connected to the second redistribution layer 114. 114 electrical connection. In this embodiment, the third semiconductor die 116 is connected to the second circuit layer 114 b of the second redistribution layer 114 through the second silicon via 116.

After that, referring to FIG. 1F, a third rewiring layer 118 is formed on the third semiconductor die 116 to form the semiconductor package 10 of this embodiment. The third rewiring layer 118 is electrically connected to the second silicon via 116c in the third semiconductor die 116. The third rewiring layer 118 may include a dielectric layer 118a and a third circuit layer 118b disposed in the dielectric layer 118a. The third rewiring layer 118 can be connected to the second silicon via 116c in the third semiconductor die 116 through the third circuit layer 118b. In FIG. 1F, the number of layers of the third circuit layer 118b of the third rewiring layer 118 is only for example, and is not intended to limit the present invention. The manufacturing method of the third rewiring layer 118 is well known to those skilled in the art, and will not be repeated here.

In the semiconductor package 10 of the present embodiment, two semiconductor crystal grains having a larger size (the first semiconductor crystal grain 100 and the third semiconductor crystal grain 116) and a semiconductor crystal grain having a smaller size (the second semiconductor crystal grain) 104) Alternately stacked, but the invention is not limited to this. In other embodiments, after the semiconductor package 10 is formed, the steps described in FIGS. 1B to 1F may be continued one or more times according to actual needs, so that more semiconductor dies with larger sizes and smaller ones Semiconductor dies of different sizes are alternately stacked on the first semiconductor die 100.

After the semiconductor package 10 of this embodiment is formed, a plurality of solder balls 120 electrically connected to the third redistribution layer 118 may be formed on the third redistribution layer 118.

2 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the invention. Please refer to FIG. 2, a solder ball 120 is formed on the third rewiring layer 118. The solder ball 120 is connected to the third wiring layer 118 b of the third redistribution layer 118. Thereby, the semiconductor package 10 can be electrically connected to external components (such as a printed circuit board) through the solder balls 120.

Hereinafter, the semiconductor package 10 of the present invention will be described as an example. The semiconductor package 10 includes a first semiconductor die 100, a first rewiring layer 102, a second semiconductor die 104, a plurality of via holes 110, an encapsulation body 112, a second rewiring layer 114, a third semiconductor die 116, and The third redistribution layer 118. The first rewiring layer 102 is disposed on the active surface 100 a of the first semiconductor die 100 and is electrically connected to the first semiconductor die 100. The second semiconductor die 104 is disposed on the first redistribution layer 102 in such a manner that the active surface 104a faces the first redistribution layer 102, and the second semiconductor die 104 passes through the first silicon via 104c to interact with the first redistribution layer 102. 102 is electrically connected. The via hole 110 is disposed on the first redistribution layer 102, is located around the second semiconductor die 104, and is electrically connected to the first redistribution layer 102. The encapsulation body 112 is disposed on the first redistribution layer 102 and covers the second semiconductor die 104 and the via hole 110. The second rewiring layer 114 is disposed on the encapsulation body 112 and is electrically connected to the via hole 110 and the first silicon via hole 104 c in the second semiconductor die 104. The third semiconductor die 116 is disposed on the second redistribution layer 114 with the active surface 116a facing the second redistribution layer 114, and the third semiconductor die 116 is connected to the second redistribution layer 114 through the second silicon via 116c. 114 electrical connection. The third rewiring layer 118 is disposed on the third semiconductor die 116 and is electrically connected to the second silicon via 116c in the third semiconductor die 116.

In addition, in the semiconductor package 10, the first semiconductor die 100 and the third semiconductor die 116 have a larger size, and the second semiconductor die 104 has a smaller size. In detail, from the top view of the third semiconductor die 116 to the first semiconductor die 100, the area of the second semiconductor die 104 is smaller than the area of the first semiconductor die 100, and the third semiconductor die 116 The area of is greater than the area of the second semiconductor die 104.

In the semiconductor package of the present invention, the components are electrically connected to each other through the silicon vias and the interposer is omitted, so the transmission speed of electronic signals can be effectively increased. In addition, in the semiconductor package of the present invention, semiconductor dies with a larger size and semiconductor dies with a smaller size are alternately stacked, so that warping caused by uneven stress can be avoided. In addition, since the arrangement of the interposer is omitted and the semiconductor dies are alternately stacked, the size of the semiconductor package can be greatly reduced to meet the requirements of miniaturization.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Semiconductor packaging 100: The first semiconductor die 100a, 104a, 116a: active surface 100b, 104b, 116b: back 102: The first rewiring layer 102a, 114a, 118a: Dielectric layer 102b: The first circuit layer 104: second semiconductor die 104c: The first silicon via 106: bump 108: primer 110: Via 112: Encapsulation body 114: second rewiring layer 114b: second circuit layer 116: The third semiconductor die 116c: second silicon via 118: The third rewiring layer 118b: third circuit layer 120: solder ball

1A to 1F are schematic cross-sectional views of a manufacturing process of a semiconductor package according to an embodiment of the invention. 2 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the invention.

10: Semiconductor packaging

100: The first semiconductor die

102: The first rewiring layer

104: second semiconductor die

104c: The first silicon via

106: bump

108: primer

110: Via

112: Encapsulation body

114: second rewiring layer

116: The third semiconductor die

116b: back

116c: second silicon via

118: The third rewiring layer

118a: Dielectric layer

118b: third circuit layer

Claims (10)

A semiconductor package includes: a first semiconductor die having an active surface and a back surface opposite to each other; a first redistribution layer is disposed on the active surface of the first semiconductor die and is connected to the first semiconductor die The die is electrically connected; the second semiconductor die has an active surface and a back surface opposite to each other, and is arranged on the first redistribution layer in such a way that the active surface faces the first redistribution layer, wherein a plurality of The first silicon via is disposed in the second semiconductor die, and the second semiconductor die is electrically connected to the first redistribution layer through the plurality of first silicon vias; A hole is arranged on the first redistribution layer, is located around the second semiconductor die, and is electrically connected to the first redistribution layer; an encapsulation body is arranged on the first redistribution layer , And encapsulate the second semiconductor die and the plurality of vias; a second rewiring layer is disposed on the encapsulation body and is connected to the plurality of vias and the second semiconductor die The plurality of first silicon vias are electrically connected; the third semiconductor die has an active surface and a back surface opposite to each other, and is disposed on the first rewiring layer in such a manner that the active surface faces the second redistribution layer On the double wiring layer, a plurality of second silicon vias are provided in the third semiconductor die, and the third semiconductor die penetrates the plurality of second silicon vias to communicate with the second The wiring layer is electrically connected; and The third rewiring layer is disposed on the third semiconductor die and is electrically connected to the plurality of second silicon vias in the third semiconductor die, wherein the third semiconductor die From the top view of the first semiconductor die, the area of the second semiconductor die is smaller than the area of the first semiconductor die, and the area of the third semiconductor die is larger than that of the second semiconductor die. The area of the semiconductor die. The semiconductor package according to claim 1, wherein the first semiconductor die and the third semiconductor die include logic die. The semiconductor package according to claim 1, wherein the second semiconductor die includes a memory die or a controller die. The semiconductor package according to claim 1, wherein the encapsulation body exposes the top surface of the plurality of first silicon vias in the second semiconductor die, and the second semiconductor die The back surface and the top surface of the plurality of vias. The semiconductor package described in item 1 of the scope of the patent application further includes a plurality of solder balls, which are arranged on the third redistribution layer and are electrically connected to the third redistribution layer. A method for manufacturing a semiconductor package includes: providing a first semiconductor die, wherein the first semiconductor die has an active surface and a back surface opposite to each other; and forming a first semiconductor die on the active surface of the first semiconductor die. A rewiring layer, wherein the first rewiring layer is electrically connected to the first semiconductor die; A second semiconductor die is stacked on the first rewiring layer, wherein the second semiconductor die has an active surface and a back surface opposite to each other, and the second semiconductor die has the active surface facing the first A re-wiring layer, wherein a plurality of first silicon vias are formed in the second semiconductor die, and the second semiconductor die penetrates the plurality of first silicon vias to communicate with the first The wiring layer is electrically connected; a plurality of via holes are formed on the first redistribution layer, wherein the plurality of via holes are located around the second semiconductor die and are electrically connected to the first redistribution layer Forming an encapsulation body on the first redistribution layer, wherein the encapsulation body encapsulates the second semiconductor die and the plurality of vias; forming a second redistribution wiring on the encapsulation body Layer, wherein the second redistribution layer is electrically connected to the plurality of vias and the plurality of first silicon vias in the second semiconductor die; stacked on the second redistribution layer The third semiconductor die, wherein the third semiconductor die has an active surface and a back surface opposite to each other, and the third semiconductor die has the active surface facing the second redistribution layer, and a plurality of Two silicon vias are formed in the third semiconductor die, and the third semiconductor die is electrically connected to the second redistribution layer through the plurality of second silicon vias; and A third rewiring layer is formed on the third semiconductor die, wherein the third rewiring layer is electrically connected to the plurality of second silicon vias in the third semiconductor die, From the perspective of the top view from the third semiconductor die to the first semiconductor die, the area of the second semiconductor die is smaller than the area of the first semiconductor die, and the third semiconductor die The area of the crystal grain is larger than the area of the second semiconductor crystal grain. According to the method for manufacturing a semiconductor package as described in claim 6, wherein the first semiconductor die and the third semiconductor die include logic die. According to the method for manufacturing a semiconductor package as described in claim 6, wherein the second semiconductor die includes a memory die or a controller die. According to the method for manufacturing a semiconductor package according to claim 6, wherein the encapsulation body exposes the top surface of the plurality of first silicon vias in the second semiconductor die, the second The back surface of the semiconductor die and the top surface of the plurality of via holes. The method for manufacturing a semiconductor package as described in claim 6, wherein after forming the third redistribution layer, it further includes forming a plurality of solder balls on the third redistribution layer, wherein the plurality The solder balls are electrically connected to the third redistribution layer.

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