TWI701764B - Process to insulate defect cells of electronic component and electronic component with self-insulating cells - Google Patents

Process to insulate defect cells of electronic component and electronic component with self-insulating cells Download PDF

Info

Publication number
TWI701764B
TWI701764B TW105127845A TW105127845A TWI701764B TW I701764 B TWI701764 B TW I701764B TW 105127845 A TW105127845 A TW 105127845A TW 105127845 A TW105127845 A TW 105127845A TW I701764 B TWI701764 B TW I701764B
Authority
TW
Taiwan
Prior art keywords
unit cell
electronic component
item
patent application
scope
Prior art date
Application number
TW105127845A
Other languages
Chinese (zh)
Other versions
TW201712801A (en
Inventor
史堤方 史瓦格
約翰尼斯 肯特納
Original Assignee
德商羅伯特博斯奇股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 德商羅伯特博斯奇股份有限公司 filed Critical 德商羅伯特博斯奇股份有限公司
Publication of TW201712801A publication Critical patent/TW201712801A/en
Application granted granted Critical
Publication of TWI701764B publication Critical patent/TWI701764B/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Abstract

一種將電子構件(200)有故障的晶胞(210)絕緣的方法,包括以下步驟:在一半導體基材(280)上產生晶胞(210)(步驟100);在該晶胞(210)和至少二個端子(220)(230)之間產生電連接部(步驟110);將一聚合物層施到該電子構件(200)上(步驟120);將一測量電壓施加到該二端子(220)(230),如此當有晶胞(210)有故障時,至少該電連接部之一由於在有故障的晶胞(210)的區域的聚合物層分解而露出(步驟150);將該露出的電連接部選擇性地蝕刻掉(步驟160);將該聚合物層除去(步驟170)。此外還關於一種電子構件(200),其具有在一半導體基材(280)上的數個晶胞(210),其中各晶胞(210)各有一個具有至少二個端子(220)(230)的電連接部,其特徵在: 該晶胞(210)有故障的情形時,其接到至少一端子(220)(230)的電連接部中斷。 A method for insulating a defective unit cell (210) of an electronic component (200), including the following steps: generating a unit cell (210) on a semiconductor substrate (280) (step 100); in the unit cell (210) Create an electrical connection with at least two terminals (220) (230) (step 110); apply a polymer layer to the electronic component (200) (step 120); apply a measurement voltage to the two terminals (220) (230), so when a unit cell (210) is faulty, at least one of the electrical connections is exposed due to the decomposition of the polymer layer in the region of the faulty unit cell (210) (step 150); The exposed electrical connections are selectively etched away (step 160); the polymer layer is removed (step 170). In addition, it also relates to an electronic component (200), which has a plurality of unit cells (210) on a semiconductor substrate (280), wherein each unit cell (210) has at least two terminals (220) (230). ) The electrical connection part is characterized by: When the unit cell (210) is faulty, its electrical connection to at least one terminal (220) (230) is interrupted.

(圖1) (figure 1)

Description

將電子構件有故障的晶胞絕緣的方法及具有自動絕緣的晶胞的電子構件 Method for insulating a defective unit cell of an electronic component and electronic component having a unit cell with automatic insulation

本發明關於電子構件的有故障的晶胞(Zelle,英:cell)絕緣的方法及一電子構件,其有故障的晶胞可自身絕緣。 The present invention relates to a method for insulating a faulty cell (Zelle, English: cell) of an electronic component and an electronic component. The faulty cell can be insulated by itself.

電子構件,如側功率開關或GaN電晶體可在一矽基材上廉價地製造。基材在實際上絕不會沒有缺陷,且在各部分程序時會發生故障,在電子構件一種常發生的故障為短路,其中承載電流的端子在晶片那一側由於基材或程序瑕疵而迫連接。具有這種故障的構件在實際上不能使用,必須篩選擇,為此,該電子構件在切分前或封裝須著色(inken)。 Electronic components such as side power switches or GaN transistors can be manufactured inexpensively on a silicon substrate. In fact, the substrate will never be defect-free, and will fail during various parts of the process. A common fault in electronic components is a short circuit, where the current-carrying terminal is on the chip side due to substrate or process defects. connection. Components with such failures cannot be used in practice and must be selected by screening. For this reason, the electronic components must be colored (inken) before being cut or packaged.

此處的缺點為:整個電子件化須篩選擇,雖然短路大多只侷限於一個或少許晶胞。 The disadvantage here is: the whole selection of electronic components, although the short circuit is mostly limited to one or a few unit cells.

本發明的目的在將有功能的電子構件的產率提高。 The purpose of the present invention is to increase the yield of functional electronic components.

本發明的用於將一電子構件有故障的晶胞絕緣的方法包含:在一半導體基材上產生晶胞,電子構件包含數個晶胞(它們連製造之容許誤差都相同),這些晶胞有數個同類的個別元件,例如功率電晶體或電 容器或DRAM。「同類」表示相同構造類型的個別元件。將這些晶胞與至少二個端子或導線連接成導電方式,將一聚合物層(特別是可熱分解的聚合物層)施到此電子構件上,此方法另外還包含施加一測量電壓到該至少二個端子,如此當存在有瑕疵的晶胞時,可將電連接部之一藉著將有缺陷的晶胞的區域的聚合物層分解而露空,將該至少一露空的電連接部選擇性地蝕刻,然後將剩餘的聚合物層除去。 The method for insulating a defective unit cell of an electronic component of the present invention includes: generating a unit cell on a semiconductor substrate. The electronic component includes a plurality of unit cells (they have the same manufacturing tolerance), and these unit cells There are several individual components of the same kind, such as power transistors or Container or DRAM. "Same type" refers to individual components of the same structure type. These unit cells are connected to at least two terminals or wires in a conductive manner, and a polymer layer (especially a thermally decomposable polymer layer) is applied to the electronic component. This method additionally includes applying a measuring voltage to the At least two terminals, so when there is a defective unit cell, one of the electrical connections can be exposed by decomposing the polymer layer in the area of the defective unit cell, and the at least one exposed electrical connection The part is selectively etched, and then the remaining polymer layer is removed.

此處的優點為:在製造時,可將有瑕疵的晶胞用簡單方式在該電子構件上絕緣,如此該構件不須整個篩選掉。 The advantage here is that during manufacture, the defective unit cell can be insulated on the electronic component in a simple manner, so that the component does not need to be screened out entirely.

在一進一步特點中,產生至少二個接觸面以施加測量電壓。它們利用光刻板術(Photolithographie)和蝕刻步驟產生。 In a further feature, at least two contact surfaces are created to apply the measurement voltage. They are produced using Photolithographie and etching steps.

此處的優點為:接點的接觸很順手。 The advantage here is that the contact is very smooth.

在另一設計中,晶胞利用一控制電壓關掉。 In another design, the unit cell is turned off using a control voltage.

此處的優點為:晶胞也可具有活性的個別元件,換言之,為自身導通的構件,如功率電晶體,如不用此方式,也可使用自身斷路的構件。 The advantage here is that the unit cell can also have active individual components. In other words, it is a self-conducting component, such as a power transistor. If this method is not used, a self-disconnecting component can also be used.

此電子構件有數個晶胞,其中各晶胞各有至少二個電子連接部與至少二個端子連接。 The electronic component has a plurality of unit cells, and each unit cell has at least two electronic connection parts connected to at least two terminals.

依本發明在晶胞故障的情形,將接到至少一個端子的電連接斷路。 According to the present invention, in the case of a cell failure, the electrical connection to at least one terminal is disconnected.

在此有利的一點為,即使有些晶胞故障,該電構件仍能使用,不必篩選掉。 The advantage here is that even if some unit cells fail, the electrical component can still be used and does not need to be screened out.

在一進一步特點,電子構件的晶胞種類相同。 In a further feature, the unit cell types of the electronic components are the same.

在此的優點為;電子元件可用於高功率用途。 The advantage here is that electronic components can be used for high-power applications.

在一進一步特點中,晶胞具有功率電晶體,特別HEMT。 In a further feature, the unit cell has power transistors, especially HEMTs.

此處的優點為:如此可產生具有高功率相容性的功率開關。 The advantage here is that a power switch with high power compatibility can be produced in this way.

在又一實施例中,晶胞包含電容器。 In yet another embodiment, the unit cell includes a capacitor.

在此的優點為:晶胞也可具有被動構件。 The advantage here is that the unit cell can also have passive components.

在再一實施例,晶胞包含DRAM,此處優點為:受損的區域可有效絕緣。 In still another embodiment, the unit cell includes DRAM, and the advantage here is that the damaged area can be effectively insulated.

在一進一步特色,該電連接的斷路具有一特性形式。 In a further feature, the disconnection of the electrical connection has a characteristic form.

此處的優點為:利用斷路之電連接部的邊緣走勢可斷定故障的種類以及其溫度。 The advantage here is that the type of fault and its temperature can be determined by using the edge trend of the disconnected electrical connection.

在另一實施例,半導體基材具有氮化鎵。 In another embodiment, the semiconductor substrate has gallium nitride.

其他優點見於以下實施例的說明或申請專利範圍的附屬項。 Other advantages can be seen in the description of the following embodiments or the appendix of the scope of patent application.

,本發明利用以下實施例及附圖說明。 The present invention is illustrated by the following embodiments and drawings.

(100):程序步驟:在半導體上產生晶胞 (100):Procedural steps: Generate a unit cell on the semiconductor

(110):程序步驟:將晶胞和至少二個端子連接並產生電連接部 (110): Procedure steps: connect the unit cell to at least two terminals and generate electrical connections

(120):程序步驟:施覆聚合物層 (120): Procedure steps: apply polymer layer

(130):程序步驟:產生至少二個接觸面 (130): Procedure steps: produce at least two contact surfaces

(140):程序步驟:將常閉的功率電晶體關掉 (140): Procedure steps: turn off the normally closed power transistor

(150):程序步驟:施測量電壓到至少二個端子 (150): Procedure steps: apply the measured voltage to at least two terminals

(160):程序步驟:將鬆開的電連接部選擇性蝕刻 (160): Procedure steps: Selectively etch the loose electrical connections

(170):程序步驟:除去聚合物層 (170): Procedure step: remove polymer layer

(200):電子構件 (200): Electronic components

(210):晶胞 (210): unit cell

(220):源極端子 (220): Source Terminal

(230):汲極端子 (230): Die terminal

(250):第一接觸面 (250): first contact surface

(260):第二接觸面 (260): second contact surface

(270):故障位置 (270): Fault location

(280):半導體基材 (280): Semiconductor substrate

(300):電子構件 (300): Electronic components

(310):晶胞(正常者) (310): unit cell (normal)

(320):晶胞(故障者) (320): unit cell (faulty)

(330):短路 (330): Short circuit

(380):半導體基材 (380): Semiconductor substrate

圖1係將一電子構件的故障晶胞絕緣的方法,圖2係在製造時電子構件的上視圖,圖3係製造程序結束後的電子構件上視圖。 Fig. 1 is a method of insulating a faulty cell of an electronic component, Fig. 2 is a top view of the electronic component during manufacture, and Fig. 3 is a top view of the electronic component after the manufacturing process is completed.

圖1顯示將一電子構件的故障晶胞絕緣的方法。此方法以步驟(100)開始,其中晶胞在一半導體基材上產生。在此,電子構件包含數個(特別是並聯的)晶胞。在此,電構件的晶胞功能相同,要產生這些晶胞, 係利用標準程序。在一隨後的步驟(110),晶胞與至少二個端子作導電連接,並產生電連接部該二端子係為在電子構件操作中的導電端子。在一隨後的步驟(120)中,將一種可熱分解的聚合物層(例如可熱分解的聚合物TDP)施到電子構件上。在一隨後的步驟(150)將一測量電壓施加到該至少二個端子,其中將接觸手段(特別是探針)穿過聚合物層,直到與端子造成電接觸為止。在此,測量電壓產生一電流,流過晶胞。如果晶胞完好,則會流過一預定之漏電流,此預定之漏電產生小小的熱量,在自導通電晶體的情形,該電晶體須利用該控制電壓(它經一第三接點通入)斷路。但如果晶胞有故障,則流過較高的漏電流,它和故障有關地產生高熱能。在這類晶胞常常發生的故障為短路。在此,在故障情形產生的熱能比在完好的晶胞大數倍,特別是十倍。這種產生的熱能因此提高晶胞溫度,可能因此會損壞或破壞晶胞。 Figure 1 shows a method of insulating a faulty cell of an electronic component. The method starts with step (100), where the unit cell is generated on a semiconductor substrate. Here, the electronic component includes several (especially parallel) unit cells. Here, the unit cells of the electrical components have the same function. To generate these unit cells, The department uses standard procedures. In a subsequent step (110), the unit cell is conductively connected to at least two terminals, and an electrical connection portion is generated. The two terminals are conductive terminals in the operation of the electronic component. In a subsequent step (120), a thermally decomposable polymer layer (for example, a thermally decomposable polymer TDP) is applied to the electronic component. In a subsequent step (150), a measuring voltage is applied to the at least two terminals, wherein contact means (especially probes) are passed through the polymer layer until electrical contact is made with the terminals. Here, the measured voltage generates a current that flows through the unit cell. If the unit cell is intact, a predetermined leakage current will flow. This predetermined leakage generates a small amount of heat. In the case of a self-conducting transistor, the transistor must use the control voltage (it passes through a third contact). In) open circuit. However, if the unit cell has a fault, a higher leakage current flows, and it generates high heat energy related to the fault. A common fault in this type of unit cell is a short circuit. Here, the heat generated in a fault situation is several times larger than in an intact unit cell, especially ten times. This generated heat energy therefore increases the temperature of the unit cell, which may therefore damage or destroy the unit cell.

因此測量電壓選設成使得在短路的晶胞中的產生的熱量足夠將晶胞溫度提高到夠高,以達到或超過聚合物層的分解溫度,換言之,晶胞的溫度超出超過聚合物層的分解溫度,因此在有故障的晶胞的區域中的電連接部鬆開。在此,聚合物層的分解溫度須在鋁的破壞溫度(熔點)以下。因為電構件的大多電連接部都有鋁。因此使用的聚合物的分解溫度在600℃以下,特別是在200°~300℃範圍。另一變更方式,該電構件的電連接部可由銅構成,如此聚合物的分解溫度在1000℃以下。在隨後的步驟(160)中,將該鬆開的電連接部選擇性地蝕刻,例如利用濕化學方式的鋁蝕刻溶液(ANPE)或用乾化學方式用電漿程序。在此,聚合物層的作用為蝕刻護罩。換言之,電連接部(亦稱為導電鍍金屬部)在不再有聚合物的位 置或由於故障而受高溫度負荷的位置就被除去。在一隨後的步驟(170),剩下的聚合物層,舉例而言,藉加熱到該分解溫度(約200~300℃)以上而除去。因此在電子構件上有故障的晶胞就絕緣。換言之,在終產品或晶片上的有故障的晶胞保持絕緣。 Therefore, the measurement voltage is selected so that the heat generated in the short-circuited unit cell is sufficient to raise the unit cell temperature high enough to reach or exceed the decomposition temperature of the polymer layer. In other words, the temperature of the unit cell exceeds that of the polymer layer. Decomposition temperature, so the electrical connections in the area of the faulty unit cell loosen. Here, the decomposition temperature of the polymer layer must be below the breakdown temperature (melting point) of aluminum. Because most of the electrical connections of electrical components have aluminum. Therefore, the decomposition temperature of the polymer used is below 600°C, especially in the range of 200°~300°C. In another modification, the electrical connection part of the electrical component can be made of copper, so that the decomposition temperature of the polymer is below 1000°C. In the subsequent step (160), the loosened electrical connection is selectively etched, for example, using a wet chemical aluminum etching solution (ANPE) or using a dry chemical plasma process. Here, the polymer layer functions as an etching shield. In other words, the electrical connection part (also known as the conductive metal-plated part) is at a position where there is no longer a polymer. Places or locations subject to high temperature loads due to malfunctions are removed. In a subsequent step (170), the remaining polymer layer is, for example, removed by heating to above the decomposition temperature (about 200-300°C). Therefore, the defective unit cell on the electronic component is insulated. In other words, the defective unit cell on the final product or wafer remains insulated.

本發明的方法主要適合矽與氮化鎵功率電電子技術的功率電子側構件如LDMOS,但也適合製造如矽電容器或DRAM的構件。 The method of the present invention is mainly suitable for power electronics side components of silicon and gallium nitride power electronic technology such as LDMOS, but also suitable for manufacturing components such as silicon capacitors or DRAM.

此方法也可用於矽基體上的垂直電晶體,如SiIGBT、Si-MocFet或在矽基材上的如SiC-MosFet、SiC-JFet。但在此,該方法須在晶圓前側上實施。 This method can also be used for vertical transistors on silicon substrates, such as SiIGBT, Si-MocFet, or silicon substrates such as SiC-MosFet, SiC-JFet. But here, the method must be implemented on the front side of the wafer.

在一實施例,該晶胞具有自身斷路的功率電晶體,換言之,該功率電晶體為常開路者。在此情形,該二端子表示汲極端子和源極端子。 In one embodiment, the unit cell has a power transistor that is open by itself, in other words, the power transistor is a normally open circuit. In this case, the two terminals represent the drain terminal and the source terminal.

在另一實施例中,該晶胞具有主動個別元件或構件。它們在正常操作係自動導通者,這類主動構件,例如為自動導通的功率電晶體。 換言之,該功率電晶體為常閉路者。在此情形中,在步驟(120)之後及步驟(150)之前作另一步驟(140),其中該功率電晶體或功率電晶體晶胞利用一負控制電壓(一般為一閘電壓)關掉。 In another embodiment, the unit cell has active individual elements or components. They are automatically turned on during normal operation. Such active components are, for example, power transistors that automatically turn on. In other words, the power transistor is normally closed. In this case, another step (140) is performed after step (120) and before step (150), in which the power transistor or power transistor unit cell is turned off using a negative control voltage (generally a gate voltage) .

因此要實施此方法和是否所用的功率電晶體在起始狀態自動導通或自動斷路無關。在自動導通的情形,只須確認閘控制電壓(例如利用一第三針)施加,如此在實施本發明方法,功率電晶體就關掉。這表示控制電壓選設成使構件關掉。 Therefore, the implementation of this method has nothing to do with whether the power transistor used is automatically turned on or automatically disconnected in the initial state. In the case of automatic turn-on, it is only necessary to confirm that the gate control voltage (for example, using a third pin) is applied, so that when the method of the present invention is implemented, the power transistor is turned off. This means that the control voltage is selected to turn off the component.

還可視需要在步驟(120)後的一道步驟中至少產生二個接觸面,俾使接觸手段較容易接觸到端子(主要是汲極端子源極端子),或接觸 得較佳,為此將端子上設的二個位置的聚合物層除去。 It is also possible to produce at least two contact surfaces in a step after step (120) as needed to make it easier for the contact means to contact the terminal (mainly the drain terminal source terminal), or contact It is better to remove the polymer layer at two locations on the terminal for this purpose.

在另一實施例中,晶胞包含電容器或DRAM。 In another embodiment, the unit cell includes a capacitor or DRAM.

圖2顯示在本發明方法中步驟(150)結束後時電子構件(200)的上視圖。舉例而言,電子構件(200)有三個具功率電晶體的晶胞(210)。在此,這些晶胞(210)設在一半導體基材(280)(例如氮化鎵或矽),且在此實例中互相並聯或平行電線。各晶胞(210)與一源極端子(220)及汲極端子(230)呈導電連接。電子構件(210)同樣可視需要有第一及第二接觸面(250)(260),在下晶胞(210)中,舉例而言顯示一故障位置(270)例如短路。 Figure 2 shows a top view of the electronic component (200) after the step (150) in the method of the present invention is completed. For example, the electronic component (200) has three unit cells (210) with power transistors. Here, the unit cells (210) are provided on a semiconductor substrate (280) (such as gallium nitride or silicon), and in this example are connected in parallel or parallel wires. Each unit cell (210) is electrically connected to a source terminal (220) and a drain terminal (230). The electronic component (210) may also have first and second contact surfaces (250) (260) as needed. In the lower unit cell (210), for example, a fault location (270) such as a short circuit is displayed.

圖3顯示本發明方法結束後的電子構件(300),電子構件(300)例如有三個具並聯之功率電晶體的晶胞,它們設在一半導體基材(380)上,電子構件(300)在此有二個原封不動的晶胞(310)和一個有短路(330)的絕緣晶胞(320)(其中接到汲極端子和源極端子的連線中斷)。 Figure 3 shows the electronic component (300) after the method of the present invention is completed. The electronic component (300) has, for example, three unit cells with power transistors connected in parallel, which are set on a semiconductor substrate (380), and the electronic component (300) There are two intact unit cells (310) and an insulating unit cell (320) with a short circuit (330) (the connection between the drain terminal and the source terminal is interrupted).

在另一實施例中,晶胞包含具高電子運動性的功率電晶體,例如HEMT,在此功率電晶體在晶胞內互相並聯,如此可產生快速功率開關。 In another embodiment, the unit cell includes power transistors with high electron mobility, such as HEMT, where the power transistors are connected in parallel in the unit cell, so that a fast power switch can be generated.

(100):程序步驟:在半導體上產生晶胞 (100):Procedural steps: Generate a unit cell on the semiconductor

(110):程序步驟:將晶胞和至少二個端子連接並產生電連接部 (110): Procedure steps: connect the unit cell to at least two terminals and generate electrical connections

(120):程序步驟:施覆聚合物層 (120): Procedure steps: apply polymer layer

(130):程序步驟:產生至少二個接觸面 (130): Procedure steps: produce at least two contact surfaces

(140):程序步驟:將常閉的功率電晶體關掉 (140): Procedure steps: turn off the normally closed power transistor

(150):程序步驟:施測量電壓到至少二個端子 (150): Procedure steps: apply the measured voltage to at least two terminals

(160):程序步驟:將鬆開的電連接部選擇性蝕刻 (160): Procedure steps: Selectively etch the loose electrical connections

(170):程序步驟:除去聚合物層 (170): Procedure step: remove polymer layer

Claims (10)

一種將電子構件(200)有故障的晶胞(210)絕緣的方法,包括以下步驟:在一半導體基材(280)上產生晶胞(210)(步驟100);在該晶胞(210)和至少二個端子(220)(230)之間產生電連接部(步驟110);將一聚合物層施到該電子構件(200)上(步驟120);將一測量電壓施加到該二端子(220)(230),如此當有晶胞(210)有故障時,至少該電連接部之一由於在有故障的晶胞(210)的區域的聚合物層分解而露出(步驟150);將該露出的電連接部選擇性地蝕刻掉(步驟160);將該聚合物層除去(步驟170)。 A method for insulating a defective unit cell (210) of an electronic component (200), including the following steps: generating a unit cell (210) on a semiconductor substrate (280) (step 100); in the unit cell (210) Create an electrical connection with at least two terminals (220) (230) (step 110); apply a polymer layer to the electronic component (200) (step 120); apply a measurement voltage to the two terminals (220) (230), so when a unit cell (210) is faulty, at least one of the electrical connections is exposed due to the decomposition of the polymer layer in the region of the faulty unit cell (210) (step 150); The exposed electrical connections are selectively etched away (step 160); the polymer layer is removed (step 170). 如申請專利範圍第1項之方法,其中:至少產生二個接觸面(250)(260)以施到該測量電壓。 Such as the method of item 1 in the scope of patent application, wherein: at least two contact surfaces (250) (260) are generated to apply the measurement voltage. 如申請專利範圍第1或第2項之方法,其中:該晶胞(210)利用一控制電壓關掉。 For example, the method according to the first or second item of the scope of patent application, wherein: the unit cell (210) is turned off by a control voltage. 一種電子構件(200),其具有在一半導體基材(280)上的數個晶胞(210),其中各晶胞(210)各有一個具有接到至少二個端子(220)(230)的電連接部,其特徵在:該晶胞(210)有故障的情形時,其接到至少一端子(220)(230)的電連接部中斷。 An electronic component (200), which has a plurality of unit cells (210) on a semiconductor substrate (280), wherein each unit cell (210) has one connected to at least two terminals (220) (230) The electrical connection part is characterized in that when the unit cell (210) is faulty, the electrical connection part connected to at least one terminal (220) (230) is interrupted. 如申請專利範圍第4項之電子構件,其中:該晶胞(210)係相同方式者。 Such as the electronic component of item 4 in the scope of patent application, in which: the unit cell (210) is in the same manner. 如申請專利範圍第4或第5項之電子構件,其中: 該晶胞(210)具有功率電晶體。 For example, the electronic component of item 4 or 5 of the scope of patent application, of which: The unit cell (210) has a power transistor. 如申請專利範圍第4或第5項之電子構件,其中:該晶胞(210)包含電容器。 For example, the electronic component of item 4 or 5 of the scope of patent application, wherein: the unit cell (210) includes a capacitor. 如申請專利範圍第4或第5項之電子構件,其中:該晶胞(210)包含DRAM。 For example, the electronic component of item 4 or 5 of the scope of patent application, wherein: the unit cell (210) contains DRAM. 如申請專利範圍第4或第5項之電子構件,其中:該電連接部的中斷具特性形式。 For example, the electronic component of item 4 or 5 of the scope of patent application, wherein: the interruption of the electrical connection part has a characteristic form. 如申請專利範圍第4或第5項之電子構件,其中:該半導體基材(280)有氮化鎵。 For example, the electronic component of item 4 or 5 of the scope of patent application, wherein: the semiconductor substrate (280) has gallium nitride.
TW105127845A 2015-09-01 2016-08-30 Process to insulate defect cells of electronic component and electronic component with self-insulating cells TWI701764B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015216694.5 2015-09-01
DE102015216694.5A DE102015216694B3 (en) 2015-09-01 2015-09-01 Electronic device with self-insulating cells and method for the isolation of defective cells

Publications (2)

Publication Number Publication Date
TW201712801A TW201712801A (en) 2017-04-01
TWI701764B true TWI701764B (en) 2020-08-11

Family

ID=56889808

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105127845A TWI701764B (en) 2015-09-01 2016-08-30 Process to insulate defect cells of electronic component and electronic component with self-insulating cells

Country Status (3)

Country Link
CN (1) CN106531695B (en)
DE (1) DE102015216694B3 (en)
TW (1) TWI701764B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW319908B (en) * 1995-05-27 1997-11-11 Bosch Gmbh Robert
TW484229B (en) * 2000-11-22 2002-04-21 Mitsubishi Electric Corp Semiconductor integrated circuit
CN104242257A (en) * 2013-06-20 2014-12-24 沈阳工业大学 Method and device for realizing synergic protection of units of ring main unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680213B2 (en) * 2001-04-02 2004-01-20 Micron Technology, Inc. Method and system for fabricating contacts on semiconductor components
DE102005007423B3 (en) * 2005-02-18 2006-06-14 Atmel Germany Gmbh Integration of electronic component (8) into substrate by formation of dielectric insulating layers on substrate front side useful in structural element modelling in semiconductor flip-chip technology with photoresistive layer in cavity
DE102005029784A1 (en) * 2005-06-24 2007-01-11 Siemens Ag Electronic assembly and method of making an electronic assembly
KR102208918B1 (en) * 2013-10-22 2021-01-29 삼성디스플레이 주식회사 Organic light emitting display apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW319908B (en) * 1995-05-27 1997-11-11 Bosch Gmbh Robert
TW484229B (en) * 2000-11-22 2002-04-21 Mitsubishi Electric Corp Semiconductor integrated circuit
CN104242257A (en) * 2013-06-20 2014-12-24 沈阳工业大学 Method and device for realizing synergic protection of units of ring main unit

Also Published As

Publication number Publication date
CN106531695B (en) 2021-06-29
DE102015216694B3 (en) 2016-09-29
TW201712801A (en) 2017-04-01
CN106531695A (en) 2017-03-22

Similar Documents

Publication Publication Date Title
US9646897B2 (en) Die crack detector with integrated one-time programmable element
EP3293761B1 (en) Semiconductor device and fabrication method thereof
US9589904B2 (en) Semiconductor device with bypass functionality and method thereof
US11610873B2 (en) Semiconductor device and method of manufacturing semiconductor device
TWI701764B (en) Process to insulate defect cells of electronic component and electronic component with self-insulating cells
US10366921B2 (en) Integrated circuit structure including fuse and method thereof
CN102194795A (en) Test structure of dielectric layer under metal layer
JP5908418B2 (en) Semiconductor device inspection circuit, inspection method, and inspection apparatus
US8884398B2 (en) Anti-fuse structure and programming method thereof
JP2007317969A (en) Semiconductor device and method of manufacturing the same
JP2019125743A (en) Method for manufacturing semiconductor device
JP6982549B2 (en) Manufacturing method of silicon carbide semiconductor device and silicon carbide semiconductor inspection device
JP5586025B2 (en) Semiconductor component provided with bus covering entire surface of substrate, method for manufacturing the same, and device provided with semiconductor component
JP2022058877A (en) Packaged electronic circuits with moisture protection seal and formation method thereof
US10319648B2 (en) Conditions for burn-in of high power semiconductors
CN101770964B (en) Test method for introducing charge in technology for forming passivation layer window
EP4020531B1 (en) Power semiconductor module, method for manufacturing the same and electrical converter
US7589546B2 (en) Inspection apparatus and method for semiconductor IC
TWI688072B (en) Semiconductor integrated circuit device
CN105762137B (en) Fuse structure and monitoring method thereof
CN104701295A (en) Electric fuse structure and production method thereof
TWI692111B (en) Semiconductor structure for improving thermal stability and schottky behavior
KR100728963B1 (en) Method for forming anti-fuse of semiconductor device
TWI718233B (en) Device and method for producing a lateral hemt
US8450734B2 (en) Semiconductor device and fabrication method for the same