TWI698881B - Encoding method and memory storage apparatus using the same - Google Patents

Abstract

An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by an ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Description

Coding method and memory storage device using said coding method

The present invention relates to a memory storage device, and particularly relates to an encoding method and a memory storage device using the encoding method.

Generally speaking, the data to be written into the rewritable non-volatile memory (NVM) can be encoded into code words according to the error correcting code (ECC). The codeword read from the rewritable non-volatile memory can also be processed through the corresponding decoding program to restore the data. The codeword is usually a combination of the data itself and the parity data generated according to the following: Bose-Chaudhuri-Hocquenghem (BCH) code, hamming code, with extra parity Checked Hamming code (SECDED), Reed-Solomon (Reed-Solomon) code, Hsiao code, or Lien code, etc.

In order to improve the NVM write power, write time and cycle reliability, a method and an on-chip ECC algorithm are needed to achieve low power design and page write time Time reduction and improvement of device reliability.

Therefore, the present invention provides an encoding method and a memory storage device using the encoding method, in which the ECC algorithm is used to implement the NVM flip bit writing function, so as to reduce writing time, writing power and improve reliability .

An exemplary embodiment of the present invention provides an encoding method for a memory storage device using an error correction code (ECC) algorithm. The encoding method includes: receiving a write command including a write address and write data; reading an existing codeword; appending a flip bit to the written data; writing data and writing data by an ECC encoder based on a preset ECC Flip bits for encoding to generate multiple parity bits, and append the written data and flip bits to the parity bits to generate a new codeword; based on the selected bits, the existing codeword becomes The new codeword needs to change the number of bits to flip the new codeword; and write one of the new codeword and the flipped new codeword to the write address.

Another exemplary embodiment of the present invention provides a memory storage device using an ECC algorithm. The memory storage device includes a connection interface, a memory array and a memory control circuit. The connection interface is configured to be coupled to the host system. The memory control circuit is coupled to the connection interface and the memory array and is configured to perform an encoding operation based on an ECC algorithm in response to receiving a write command including a write address and write data. The encoding operation includes: reading the existing codeword; appending the flip bit to the written data; the ECC encoder encodes the written data and the flip bit based on the ECC algorithm to generate a plurality of parity bits And will write data And a flip bit is appended to the parity bit to generate a new codeword; the new codeword is flipped based on the number of bits that need to be changed from an existing codeword to a new codeword in the selected bits; and the new codeword And one of the flipped new codewords is written to the write address.

Based on the above content, by adopting the encoding method and memory storage device provided in the present invention, in response to receiving a write command, the written data is encoded and compared with the existing code in the written address or with a predefined pattern. Words are compared to determine the number of bits that need to be changed when writing. The bits of the encoded codeword are selectively flipped based on the determined number, and at least one flipped bit indicating bit flipping is added to the codeword. Therefore, the number of bit changes during writing can be reduced, and the writing time and power can be reduced.

100: Memory storage device

110: Connection interface

130: Memory control circuit / memory control circuit unit

131: Error Correction Code (ECC) encoder

150: memory array

CW: 51-bit codeword/51-bit new codeword

EC1, EC2, EC4: 51-bit existing codeword/existing codeword

EC3: Existing codeword

EC3a: Even bits of the existing codeword

EC3b: Odd bits of the existing codeword

f1, f3, f4: flip bit

m1~m32: write data

Mp: matrix

NC1, NC2, NC4: 51-bit new codeword/new codeword

NC1’, NC2’, NC3a’, NC3b’, NC4’: New code words after flipping

NC3: 52-bit new codeword/new codeword

NC3a: Even bits of the new codeword

NC3b: Odd bits of the new codeword

OD: 33-bit data

p1~p18: element

PD: 18-bit parity data

S202, S204, S206, S208, S702, S704, S706, S708, S710, S712, S714, S716, S718, S720, S722: steps

FIG. 1 is a schematic block diagram showing a memory storage device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an encoding method used in a memory storage device according to an embodiment of the present invention.

Fig. 3 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention.

Fig. 4 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention.

FIG. 5 shows the use of BCH (51, 33, 7) according to another embodiment of the present invention Schematic diagram of the encoding method of the modified ECC algorithm.

Fig. 6 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention.

FIG. 7 is a flowchart showing an encoding method used in a memory storage device according to an embodiment of the present invention.

FIG. 8 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (52, 34, 7) according to another embodiment of the present invention.

Reference will now be made in detail to the preferred embodiment of the present invention, and examples of the preferred embodiment are shown in the drawings. In the drawings and descriptions, the same reference numbers are used as much as possible to refer to the same or similar elements.

1, the memory storage device 100 includes a connection interface 110, a memory control circuit 130 and a memory array 150. In one embodiment, the memory storage device 100 is a rewritable nonvolatile memory, and the memory array 150 includes a plurality of rewritable nonvolatile memory cells.

In one embodiment, the connection interface 110 is configured to be coupled to a host system (not shown in the figure) through the Serial Advanced Technology Attachment (SATA) standard. In other embodiments, the connection interface 110 may comply with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, or other suitable This standard is not limited in the present invention. In one embodiment, the connection interface 110 and the memory control circuit unit 130 may be packaged in a chip or placed outside the chip with the memory control circuit unit 130.

The memory control circuit 130 is coupled to the connection interface 110 and the memory array 150, and is configured to execute a plurality of logic gates or control commands. The logic gates or control commands are implemented in hardware or firmware. Operations such as data writing, reading, or erasing are performed in the memory array 150 according to commands from the host system.

In one embodiment, the memory storage device 100 is a rewritable NVM using an ECC algorithm, wherein the memory control circuit 130 further includes an ECC encoder 131, and the ECC encoder 131 uses the ECC algorithm to connect The data received by the interface 110 is encoded to generate codewords and write the codewords into the memory array 150. It should be noted that in the present invention, the one's complement of the codeword generated by the ECC algorithm is still another codeword. The ECC algorithm is, for example, using Lian codes, Bose-Chowdhury-Hokkungum (BCH) codes, Hamming codes, Hamming codes with additional parity (SECDED), Reed-Solomon codes, Or modified ECC such as Xiao's code, which is not limited in this article.

The memory array 150 is coupled to the memory control circuit 130 and includes a plurality of memory cells (for example, rewriteable non-volatile memory cells). In one embodiment, the host system transmits a write command to the memory storage device 100 to write data to the memory storage device 100, and then, the memory control circuit 130 writes in response to the write command. The data is encoded into code words and the code words are stored in the memory array 150.

FIG. 2 is a flowchart showing an encoding method used in a memory storage device according to an embodiment of the present invention. The encoding method can be executed by the memory storage device 100 of the embodiment shown in FIG. 1. Therefore, in this embodiment, the encoding method will be explained by referring to the aforementioned memory storage device 100.

2, the memory control circuit 130 receives a write command including a write address and write data through the connection interface 110 (step S202). In response to the received write command, the ECC encoder 131 of the memory control circuit 130 reads the existing codeword in advance (step S204). In one embodiment, the existing codeword is a codeword pre-stored in the write address, and in another embodiment, the existing codeword has a predefined data pattern (for example, 000000... or FFFFFF...) Codewords, this is not limited in this article.

At the same time, the ECC encoder 131 encodes the written data into a new codeword based on the above-mentioned ECC algorithm, and flips the multiple of the new codeword based on the number of bits that need to be changed from the existing codeword to the new codeword. Bit (step S206). Specifically, in step S206, the ECC encoder 131 may add the flipped bit to the written data, calculate the written data and the parity data of the flipped bit based on the ECC algorithm, and combine the parity data, Write data and flip the bit combination to generate a new codeword. Next, the ECC encoder 131 compares the multiple selected bits of the new codeword with multiple selected bits of the existing codeword to determine the number of bits that need to be changed from the existing codeword to the new codeword, and determines the number of bits that need to be changed. Whether the determined number of bits exceeds a predetermined threshold. It should be noted that in the present invention, the one's complement of the encoded new codeword is also a codeword.

In some embodiments, the predetermined threshold is data bits and parity The total number of bits is half, which is not limited in this article.

If the determined number of bits is determined to exceed a predetermined threshold, the ECC encoder 131 flips the bits of the new codeword including data bits, parity bits, and flipped bits. On the other hand, if the determined number of bits is determined to be lower than the predetermined threshold, the ECC encoder 131 does not perform bit flipping on the bits of the new codeword. It should be noted that if the predetermined threshold is equal to half the number of codeword bits and the determined number of bits is determined to be equal to the predetermined threshold, that is, the number of bits to be changed is the same as the number of bits to be unchanged, then the ECC The encoder 131 also does not perform bit flipping on the bits of the encoded new codeword.

Finally, the ECC encoder 131 writes one of the new codeword and the inverted new codeword to the write address (step S208).

Based on the above, since the number of bits changed from the existing codeword to the new codeword is reduced to less than half of the number of codeword bits by selectively flipping the bits of the codeword to be written, the writing time And power can be reduced, and reliability and durability can be improved.

For example, FIG. 3 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention.

3, based on the ECC algorithm modified by BCH (51, 33, 7), the ECC encoder 131 encodes 33-bit data OD including 32-bit write data m1 to m32 and a flip bit f1 into 51 The bit code word CW, and the matrix Mp is the 18*33 matrix used when calculating the 18-bit parity data PD of the 33-bit data OD. Specifically, when the memory storage device 100 receives 32-bit write data At this time, the ECC encoder 131 first adds the flip bit f1 to the 32-bit write data. Then, the 33-bit data OD including the 32-bit write data and the flip bit f1 can be written into the single-row vector. Next, the 33-bit data OD is multiplied by the matrix Mp to obtain a single-row vector having 18 elements p1 to p18, each of the 18 elements p1 to p18 representing one bit of the 18-bit parity data PD. Then, the ECC encoder 131 appends the 33-bit data OD to the 18-bit parity data PD to generate a 51-bit new codeword CW.

In some embodiments, the flipped bit f1 indicates bit flipping of the codeword. In some embodiments, the additional flipping bit f1 is set with a first value (ie, logic 1), which indicates that bit flipping is not performed on the codeword. When bit flipping is performed on the codeword, the flipping bit f1 is also flipped to a second value (ie, logic 0), which indicates that bit flipping is performed on the codeword.

Based on the encoding method described above, the ECC encoder 131 generates a new code word including flipped bits from the written data. It should be noted that in one embodiment, the number of bits changed from the existing codeword read from the self-write address becomes the new codeword is minimized, and in another embodiment, from the The number of bits changed when an existing codeword becomes a new codeword is minimized. Exemplary embodiments are given below for further description.

Fig. 4 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention. Referring to FIG. 4, when receiving the written data, the ECC encoder 131 encodes the written data into a 51-bit new code word NC1 by using the ECC algorithm described in the embodiment shown in FIG. 3. ECC code The device 131 also reads the 51-bit existing codeword EC1 from the write address. Then, the ECC encoder 131 compares the multiple bits of the new codeword NC1 with the multiple bits of the existing codeword EC1 to determine the number of bits that need to be changed from the existing codeword EC1 to the new codeword NC1. Finally, the ECC encoder 131 flips the bits of the new codeword NC1 including the written data, parity bits, and flipped bits based on the determined number, and converts the new codeword NC1 and the flipped new codeword NC1' One of them is written to the write address. Specifically, the ECC encoder 131 determines whether the determined number exceeds half of the number of codeword bits. If so, the ECC encoder 131 flips all the bits of the new code word NC1 and writes the flipped new code word NC1' including the flipped bits to the write address. If the judgment result is no, the ECC encoder 131 does not perform bit inversion on the new code word NC1, and writes the new code word NC1 to the write address.

On the other hand, FIG. 5 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention. 5, when receiving the written data, the ECC encoder 131 encodes the written data into a 51-bit new code word NC2 by using the ECC algorithm described in the embodiment shown in FIG. 3. The ECC encoder 131 also reads the 51-bit existing codeword EC2 with a predefined data pattern (such as 000000...). Then, the ECC encoder 131 compares the multiple bits of the new codeword NC2 with the multiple bits of the existing codeword EC2 to determine the number of bits that need to be changed from the existing codeword EC2 to the new codeword NC2. Finally, the ECC encoder 131 flips the bits of the new codeword NC2 including the written data, parity bits, and flipped bits based on the determined number, and converts the new codeword NC2 and the flipped new codeword NC2' One of them is written to the write address. Specifically, the ECC encoder 131 determines Whether the number exceeds half of the number of codeword bits. If so, the ECC encoder 131 flips all the bits of the new code word NC2 and writes the flipped new code word NC2' including the flipped bits to the write address. If the judgment result is negative, the ECC encoder 131 does not perform bit inversion on the new code word NC2, and writes the new code word NC2 to the write address.

It should be noted that the parity bits generated by the ECC algorithm (for example, the parity bits p1 to p18 in FIG. 3) always change with the written data (even the one-bit changes) However, it is expected that those parity bits will be frequently written, and then the written data (for example, the written data in FIG. 3) will be written frequently. In this case, even if the number of bits that need to be changed in the parity bit is large, there are fewer bits that need to be changed in the written data (that is, the total number of bits that need to be changed is less than the number of codeword bits. Half of the number), the codeword may not be flipped. Therefore, if the total number of data bits and parity bits is used to determine bit flip, the number of cycles of parity bits cannot be effectively reduced. Therefore, in the following embodiments, the encoding method can determine bit flipping only based on the parity bits that need to be changed from the existing codeword to the new codeword to further improve the bit write durability, but the present invention is not only Limited to this.

For example, FIG. 6 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (51, 33, 7) according to another embodiment of the present invention. 6, when the written data is received, the ECC encoder 131 encodes the written data into a 51-bit new code word NC4 by using the ECC algorithm described in the embodiment shown in FIG. 3. The ECC encoder 131 also reads the 51-bit existing code word EC4 from the write address. Next, the ECC encoder 131 converts the multiple parity bits p1 of the new code word NC4 to p18 is compared with the multiple parity bits p1 to p18 of the existing codeword EC4 to determine the number of parity bits that need to be changed from the existing codeword EC4 to the new codeword NC4. Finally, the ECC encoder 131 flips the bits of the new codeword NC4 based on the determined number, and writes one of the new codeword NC4 and the flipped new codeword NC4' to the write address. Specifically, the ECC encoder 131 determines whether the determined number exceeds half of the number of parity bits. If it is, the ECC encoder 131 flips all the bits of the new code word NC4 and writes the flipped new code word NC4' including the flipped bits to the write address. If the judgment result is negative, the ECC encoder 131 does not perform bit inversion on the new code word NC4, and writes the new code word NC4 to the write address.

In order to further reduce the writing time and power, in some embodiments, multiple flip bits are used to indicate bit flips of different parts of the codeword, and in some embodiments, the flip bits are also included in In the different parts of the codeword, this is not limited in this article. In one embodiment, the flipping bit includes: a first flipping bit included in one of a plurality of even-numbered bits of the codeword for indicating bit flipping of even-numbered bits; and a second flipping bit , Included in one of the odd-numbered bits of the codeword to indicate bit flipping of the odd-numbered bits.

FIG. 7 is a flowchart showing an encoding method used in a memory storage device according to an embodiment of the present invention. The encoding method can be executed by the memory storage device 100 of the embodiment shown in FIG. 1. Therefore, in this embodiment, the encoding method will be explained by referring to the aforementioned memory storage device 100.

Referring to FIG. 7, the memory control circuit 130 receives a write command including a write address and write data (step S702). In response to the received write command, the memory The ECC encoder 131 of the control circuit 130 reads the existing codeword in advance (step S704). In one embodiment, the existing codeword is a codeword pre-stored in the write address, and in another embodiment, the existing codeword has a predefined data pattern (for example, 000000... or FFFFFF...) Codewords, this is not limited in this article.

At the same time, the ECC encoder 131 encodes the written data into a new codeword based on the ECC algorithm without flipping the bits of the new codeword, and loads the new codeword into the write buffer (step S706). Specifically, in step S706, the ECC encoder 131 may add two flipped bits to the written data, calculate the written data and the parity data of the flipped bits based on the ECC algorithm, and convert the parity data , Write data and flip the bit combination to generate a new codeword, and load the new codeword into the write buffer. In this embodiment, the additional flipping bit includes a first flipping bit for indicating bit flipping for even-numbered bits, and a second flipping bit for indicating bit flipping for odd-numbered bits.

Then, the ECC encoder 131 executes steps S708 and S714 in parallel or continuously. It should be noted that in the present invention, the one's complement of the encoded new codeword is also a codeword.

In step S708, the ECC encoder 131 compares the even-numbered bits of the new codeword with the even-numbered bits of the existing codeword to determine what needs to be changed from all even-numbered bits of the existing codeword to all even-numbered bits of the new codeword. The number of bits, and then it is judged whether the determined number exceeds a quarter of the number of codeword bits (step S710). If so, the ECC encoder 131 flips all the even-numbered bits of the codeword, and loads the flipped even-numbered bits into the write buffer (step S712).

Similarly, in step S714, the ECC encoder 131 converts the odd value of the new codeword The digital bits are compared with the odd bits of the existing codeword to determine the number of bits that need to be changed from all the odd bits of the existing codeword to all the odd bits of the new codeword, and then determine whether the determined number exceeds the codeword bits One quarter of the number of yuan (step S716). If so, the ECC encoder 131 flips all the odd-numbered bits of the codeword and loads the flipped odd-numbered bits into the write buffer (step S718).

It should be noted that in steps S710 and S716, if the judgment result is no, the ECC encoder 131 does not perform bit flipping on the codeword (step S720), and therefore, there is no change in the write buffer. It should be noted that in each of the even-numbered bits and the odd-numbered bits, if the number of bits to be changed is the same as the number of bits to be unchanged, the ECC encoder 131 does not perform bit flipping.

Finally, the ECC encoder 131 executes codeword writing to write the codeword written in the buffer to the write address (step S722).

Based on the above content, since the number of bits changed from the existing codeword to the new codeword is reduced by selectively and separately inverting the even and odd bits of the codeword to be written, the writing time and power can be reduced. Further reduction and reliability can be further improved.

For example, FIG. 8 is a schematic diagram showing an encoding method using an ECC algorithm modified by BCH (52, 34, 7) according to another embodiment of the present invention. Referring to FIG. 8, when the written data is received, the ECC encoder 131 encodes the written data into a new 52-bit code word NC3 by using an ECC algorithm similar to the ECC algorithm described in the embodiment shown in FIG. 3 . It should be noted that in this embodiment, the ECC encoder 131 first appends two flip bits to the written data, and encodes the data bits and flip bits. Code into a new 52-bit codeword. In some embodiments, the two inversion bits separately indicate bit inversion for all even data bits and all odd data bits in the codeword. In some embodiments, the two additional flipping bits are set with a first value (ie, logic 1), and the first value indicates that bit flipping is not performed on the codeword. When bit flipping is performed on the even-numbered or odd-numbered bits of the codeword, the corresponding flipped bit is also flipped to a second value (ie, logic 0), and the second value indicates that bit-biting is performed on the codeword Flip.

In some embodiments, in response to receiving the write command, the ECC encoder 131 also reads the existing 52-bit codeword EC3 including two flipped bits.

Then, the ECC encoder 131 compares the even-numbered bits NC3a of the new codeword NC3 with the even-numbered bits EC3a of the existing codeword EC3 to determine that all even-numbered bits change from the existing codeword EC3 to the new codeword NC3 The number of bits that need to be changed. At the same time, the ECC encoder 131 also compares the odd numbered bits NC3b of the new codeword NC3 with the odd numbered bits EC3b of the existing codeword EC3 to determine that all the odd numbered bits change from the existing codeword EC3 to the new codeword. The number of bits that NC3 needs to change. In addition, it should be noted that in the present invention, the one's complement of any part of the encoded new codeword (ie, even-numbered bits or odd-numbered bits) is also a codeword.

Finally, the ECC encoder 131 flips the even bits NC3a of the new codeword NC3 based on the determined number of bits that need to be changed in the even bits, and flips the new codeword NC3 based on the determined number of bits that need to be changed in the odd bits. NC3b, and write the entire new codeword including the two flipped bits to the write address. Specifically, the ECC encoder 131 determines which of the even-numbered bits needs to be changed. Whether the number of location elements exceeds a quarter of the number of codeword bits. If so, the ECC encoder 131 flips all even-numbered bits NC3a of the new codeword NC3 and loads the flipped new codeword NC3a' including the flipped bits into the write buffer. If not, the ECC encoder 131 does not perform bit inversion on the even-numbered bits NC3a of the new code word NC3. Similarly, the ECC encoder 131 determines whether the determined number of bits that need to be changed in the odd-numbered bits exceeds one quarter of the number of codeword bits. If so, the ECC encoder 131 flips all odd bits NC3b of the new codeword NC3 and loads the flipped new codeword NC3b' including the flipped bits into the write buffer. If not, the ECC encoder 131 does not perform bit flipping on the odd bits NC3b of the new codeword NC3. Then, the entire code word including all the even-numbered bits and all the odd-numbered bits in the write buffer is written into the memory array 150.

In the foregoing embodiment, based on the encoding method of the present invention, the even-numbered bits and odd-numbered bits changed from the existing codeword to the encoded codeword are minimized. However, in some embodiments, based on the encoding method provided in the present invention, the changed bits in the parity bits in the first part or the second part are minimized, but the present invention is not limited to this.

In summary, in the encoding method and memory storage device provided in the present invention, an ECC algorithm that uses the BCH ECC algorithm to implement the NVM flip bit write function is introduced, in which one or more flips are used. Bits to indicate the inversion of the codeword bits on different parts of the codeword bits. Therefore, the number of bit changes during writing can be reduced, and the writing time and power can be reduced. In addition, the durability of the memory device is improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make slight changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to those defined by the attached patent scope.

S202~S208‧‧‧Step

Claims (12)

An encoding method for a memory storage device using an error correction code algorithm includes: receiving a write command including a write address and write data; reading an existing codeword; and attaching a flip bit to the write Data; an error correction code encoder based on the error correction code algorithm encodes the written data and the flip bit to generate a plurality of parity bits, and the write data and the A flip bit is appended to the plurality of parity bits to generate a new codeword; the new code is flipped based on the number of bits that need to be changed from the existing codeword to the new codeword in the selected bits Word; and writing one of the new codeword and the flipped new codeword to the write address. The encoding method as described in item 1 of the scope of patent application, wherein if the number of bits to be changed is the same as the number of bits to be unchanged, bit flipping is not performed. The coding method as described in item 1 of the scope of patent application, wherein the one's complement of any one of the existing codeword and the new codeword is also a codeword. The encoding method according to the first item of the scope of patent application, wherein each of the existing codeword and the new codeword includes a first inversion bit and further includes a second A flipped bit, the first flipped bit is included in a first part of the codeword, and the second flipped bit is included in a second part of the codeword. The coding method according to item 4 of the scope of patent application, wherein the one's complement of the first part or the second part of any one of the new codeword and the existing codeword is also a code word. The encoding method as described in item 4 of the scope of patent application, wherein in each of the first part and the second part, if the number of bits to be changed is the same as the number of bits to be unchanged, No bit flip is performed. The encoding method according to the first item of the scope of patent application, wherein the selected bit is the parity bit or the parity bit and the data bit. A memory storage device using an error correction code algorithm includes: a connection interface configured to be coupled to a host system; a memory array; and a memory control circuit coupled to the connection interface and the memory array , And is configured to perform an encoding operation based on the error correction code algorithm in response to receiving a write command including a write address and write data, wherein the encoding operation includes: reading an existing codeword; Bits are appended to the written data; an error correction code encoder based on the error correction code algorithm encodes the written data and the flip bit to generate a plurality of parity bits, and Will be said The written data and the flip bit are appended to the plurality of parity bits to generate a new codeword; based on the number of bits that need to be changed from the existing codeword to the new codeword in the selected bits To flip the new codeword; and write one of the new codeword and the flipped new codeword to the write address. The memory storage device according to item 8 of the scope of patent application, wherein the memory control circuit is configured to: if the number of bits to be changed is the same as the number of bits to be unchanged, no bit is executed Flip. The memory storage device according to claim 8, wherein each of the existing codeword and the new codeword includes a first flip bit and further includes a second flip bit, the The first flip bit is included in the first part of the codeword, and the second flip bit is included in the second part of the codeword. The memory storage device according to claim 10, wherein in each of the first part and the second part, the memory control circuit is configured to: if the bit is changed If the number of bits is the same as the number of bits that will not be changed, no bit flipping is performed. The memory storage device according to claim 8, wherein the selected bit is the parity bit or the parity bit and data bit.

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