TWI698750B - Method for accessing flash memory module and associated flash memory controller and electronic device - Google Patents

Abstract

The present invention provides a method for accessing a flash memory module, wherein the method includes: receiving data and a corresponding metadata from a host; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data includes the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

Description

Method for accessing flash memory module and related flash memory controller and electric Sub-device

The present invention relates to flash memory, in particular to a method of accessing flash memory modules.

When the flash memory controller writes data from a master device to a data page in the flash memory module, it will simultaneously write data corresponding to a spare area of the data page The metadata of the data for subsequent reference. The above metadata can be generated by the flash memory controller or provided by the host device. However, when the metadata is provided by the host device, the metadata may be temporarily stored in the static random access memory (Static Random Access Memory) of the flash memory controller during the process of writing to the data page. Access Memory (SRAM) and external dynamic random access memory (Dynamic Random Access Memory, DRAM). Therefore, at these stages, the metadata of the metadata may be generated incorrectly, which will cause the content to be written to the data page. It is also wrong, which affects the trouble of subsequent data reading.

Therefore, one of the objectives of the present invention is to provide a method for accessing flash memory modules In this way, the metadata of the autonomous device can be protected to avoid the problem of metadata errors caused by static random access memory or dynamic random access memory as described in the prior art.

In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, which includes the following steps: receiving a data and a meta data corresponding to the data from a host device; looping the data The redundancy check operation is performed to generate a cyclic redundancy check code; the metadata and the cyclic redundancy check code are encoded to generate an adjusted check code; the data and the adjusted check code are one And perform an encoding operation to generate an encoded data, where the encoded data includes the data, the adjusted check code, and an error correction code corresponding to the data and the adjusted check code; and the encoded data The data and the metadata are written to a data page in a block of the flash memory module.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes There is a read-only memory, a microprocessor, and multiple codecs, wherein the read-only memory is used to store a program code, and the microprocessor is used to execute the program code to control the flash memory module的Access. In the operation of the flash memory controller, when the flash memory controller receives a piece of data and the unary data corresponding to the piece of data from a host device, the multiple codecs perform cyclic redundancy calibration on the data. Perform a verification operation to generate a cyclic redundancy check code, perform an encoding operation on the metadata and the cyclic redundancy check code to generate an adjusted check code, and perform the data and the adjusted check code together Encoding operation to generate an encoded data, where the encoded data includes the data, the adjusted check code, and an error correction code corresponding to the data and the adjusted check code; and the microprocessor The encoded data and the metadata are written to a data page in a block of the flash memory module.

In another embodiment of the present invention, an electronic device is disclosed, which includes a fast Flash memory module and a flash memory controller. When the flash memory controller receives a data and a metadata corresponding to the data from a host device, the flash memory controller performs a cyclic redundancy check operation on the data to generate a cyclic redundancy check Code, the metadata and the cyclic redundancy check code are encoded to generate an adjusted check code, and the data and the adjusted check code are encoded together to generate an encoded data, wherein The encoded data includes the data, the adjusted check code, and an error correction code corresponding to the data and the adjusted check code; and the flash memory controller includes the encoded data and the metadata Write to a data page in a block of the flash memory module.

100: memory device

110: Flash memory controller

112: Microprocessor

112C: Code

112M: Read only memory

114: Control logic

116: buffer memory

118: Interface logic

120: Flash memory module

130: main device

132: The first codec

134: second codec

136: third codec

200~212, 600~614: steps

D1~D8: Multiple parts of the first data

M1~M4: Multiple parts of metadata

P1~P8, P11~P41: cyclic redundancy check code

P1’~P8’, P11’~P41’: Check code after adjustment

ECC1, ECC2: Error correction code

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention.

FIG. 2 is a flowchart of a method for accessing a flash memory module according to an embodiment of the invention.

Figure 3 is a schematic diagram of the first data and the corresponding metadata.

FIG. 4 is a schematic diagram of cyclic redundancy check operation and mutual exclusion OR operation according to an embodiment of the present invention.

Figure 5 is a schematic diagram of an error correction code block and a sector block according to an embodiment of the invention.

FIG. 6 is a flowchart of a method for reading a flash memory module according to an embodiment of the invention.

FIG. 7 is a schematic diagram of cyclic redundancy check operation and mutual exclusion OR operation according to another embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory (Flash Memory) module 120 and a flash memory The memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. The control logic 114 includes a first codec 132, a second codec 134, and a third codec 136. In this embodiment, the first codec 132 is used for cyclic redundancy check (Cyclic redundancy check, CRC) operation, the second codec 134 is used for exclusive-OR (exclusive-OR, XOR) operation, and the third codec 136 is used for low-density parity check code (Low- density parity-check code, LDPC code) operation, but the present invention is not limited to this.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the controller (for example, through a microprocessor) 112 The flash memory controller 110 that executes the program code 112C) erases the flash memory module 120 and other operations are performed in units of blocks. In addition, a block can record a specific number of pages, where the controller (for example, the memory controller 110 that executes the program code 112C through the microprocessor 112) writes the flash memory module 120 The operation of the data is to write in the data page unit. In this embodiment, the flash memory module 120 is a 3D NAND-type flash.

In practice, the flash memory controller 110, which executes the program code 112C through the microprocessor 112, can use its own internal components to perform many control operations, for example, using the control logic 114 to control the flash memory module 120 Access operations (especially access operations to at least one block or at least one data page), use the buffer memory 116 to perform the required buffer processing, and use the interface logic 118 to communicate with a host The device (Host Device) 130 communicates. The buffer memory 116 may be a static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

In one embodiment, the memory device 100 may be a portable memory device (for example, a memory card that complies with SD/MMC, CF, MS, and XD standards), and the main device 130 is an electronic device that can be connected to the memory device. Such as mobile phones, laptops, desktop computers... etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage that meets Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications. The device may be installed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer. In this case, the main device 130 may be a processor of the electronic device.

FIG. 2 is a flowchart of a method of accessing the flash memory module 120 according to an embodiment of the invention. In step 200, the process starts, and the flash memory controller 110 prepares the autonomous device 130 to receive data and store it in the flash memory module 120. In step 202, the autonomous device 130 of the flash memory controller 110 receives the first data and the metadata corresponding to the first data, where the metadata may include the identification information (ID) and hash data of the first data. (hash data), Quality of Service (QoS) information, or other management information, such as logical address and management information other than the data itself... etc. In this embodiment, referring to Figure 3, the size of the first piece of data is 4 kilobytes (KB), and the metadata is 8 bytes. In the following operations of this embodiment, the first piece of data The data is divided into eight parts D1~D8 with a size of 512 bytes, and the metadata is divided into four parts M1~M4 with a size of 2 bytes.

In step 204, the first codec 132 performs a cyclic redundancy check operation on the first piece of data to generate a cyclic redundancy check code, and in step 206, the second codec 134 compares the metadata with the cyclic redundancy check code. The ring redundancy check code performs an encoding operation to generate an adjusted check code. Specifically, referring to Figure 4, the first codec 132 first performs a cyclic redundancy check operation on the eight parts D1~D8 of the first data respectively to generate multiple cyclic redundancy check codes P1~P8 , The size of each cyclic redundancy check code P1~P8 is 2 bytes; after that, the second codec 134 then compares the cyclic redundancy check code P1~P4 with the four parts M1~ of the metadata respectively. M4 performs mutually exclusive OR operation to generate adjusted check codes P1'~P4' respectively; and the second codec 134 also combines the cyclic redundancy check codes P5~P8 with the four parts M1~M4 of the metadata respectively Perform mutually exclusive OR operations to generate adjusted check codes P5'~P8' respectively.

It should be noted that steps 204 and 206 are performed immediately after the flash memory controller 110 receives the first data and metadata, and at this time the first data and metadata have not been stored in the buffer memory 116. And/or external dynamic random access memory (not shown). The purpose of performing the cyclic redundancy check operation on the first data in step 204 is to avoid subsequent errors in the access process of the buffer memory 116 and/or external dynamic random access memory (that is, to provide point-to-point End to end protection), and in step 206, the cyclic redundancy check code P1~P4 and the four parts M1~M4 of the metadata are mutually exclusive or the purpose is to make the adjusted check code P1 '~P4' can also contain the information content of the metadata, that is, the adjusted check code P1'~P4 can not only protect the first data, but also protect the metadata at the same time.

In step 208, the third codec 136 performs an encoding operation on the first data and the adjusted check code together to generate an encoded data, where the encoded data includes the first data and the adjusted check code And an error correction code corresponding to the first data and the adjusted check code. Specifically, referring to Figure 5, the third codec 136 encodes the four parts D1~D4 of the first data and the corresponding adjusted check codes P1'~P4' together (LDPC encoding) to An error correction code ECC1 is generated, and the four parts D1~D4 of the first data, the adjusted check code P1'~P4' and the error correction code ECC1 constitute An error correction code block (ECC chunk); and the third codec 136 also encodes the other four parts D5~D8 of the first data and the corresponding adjusted check codes P5'~P8' together , To generate an error correction code ECC2, and the four parts D5~D8 of the first data, the adjusted check code P5'~P8' and the error correction code ECC2 constitute another error correction code block.

In step 210, the two error correction code blocks shown in Figure 5 form a sector block, and are temporarily stored in the buffer memory 116 and/or an external dynamic random access memory, wherein the above The section block is used to store in a section of a data page.

In step 212, assuming that the size of a data page is 16 kilobytes, the flash memory controller 110 repeats steps 202 to 210 to receive the second, third, and fourth data and the corresponding metadata with the autonomous device 130 After the corresponding segment block is generated, four segment blocks and 32-byte metadata are written to a data page of a block in the flash memory module 120, where the metadata is stored In a spare area of the data page.

Fig. 6 is a flowchart of a method for reading a flash memory module 120 according to an embodiment of the present invention, wherein the process in Fig. 6 follows the embodiment shown in Figs. 2 to 5, that is, flash The memory controller 110 reads the data page storing the four sector blocks SC1 to SC4 and the 32-byte metadata. At step 600, the process starts. In step 602, the flash memory controller 110 receives a read command from the autonomous device 130. In this embodiment, it is assumed that the read command requires reading the data of the segment block SC1 and the corresponding element. data.

In step 604, the first error correction code block and the second error correction code block in the section block SC1 of the third codec 136 are decoded to generate the first block as shown in Figure 5. Data four One part D1~D4 and adjusted check code P1’~P4’, and the other four parts D5~D8 of the first data and adjusted check code P5’~P8’.

In step 606, the first codec 132 performs a cyclic redundancy check operation on the four parts D1~D4 of the first data generated by decoding to generate another cyclic redundancy check code, and in step 608 Here, the second codec 134 encodes the other cyclic redundancy check code and the metadata read from the data page to generate another adjusted check code. Specifically, referring to Figure 7, the first codec 132 first performs a cyclic redundancy check operation on the four parts D1~D4 of the first data decoded to generate multiple cyclic redundancy checks. Code P11~P41, the size of each cyclic redundancy check code P11~P41 is 2 bytes; after that, the second codec 134 then connects the cyclic redundancy check code P11~P41 with the data page respectively The four parts M1~M4 of the read metadata perform mutually exclusive OR operations to generate adjusted check codes P11'~P41' respectively.

In step 610, the microprocessor 112 determines whether the adjusted check codes P11'~P41' are exactly the same as the adjusted check codes P1'~P4' respectively. If yes, the process goes to step 612; if not, the process goes to step 614.

In step 612, since the adjusted check codes P11'~P41' are exactly the same as the adjusted check codes P1'~P4', the contents of the four parts D1~D4 and the metadata of the first data can be ensured If all are correct, the subsequent microprocessor 112 can transmit the four parts D1 to D4 of the first data and the corresponding metadata to the main device 130. In addition, in one embodiment, since the content of the metadata has been confirmed to be correct, the other four parts D5~D8 of the first data can be directly transmitted to the main device 130 together, without the need to perform steps 606~ 610 operations.

In step 614, since the adjusted check codes P11'~P41' are not exactly the same as the adjusted check codes P1'~P4', it may be that the content of the first data is incorrect or the content of the metadata There is an error, so the microprocessor 112 returns an error message to the main device 130.

To briefly summarize the present invention, in the embodiment of the present invention, when the flash memory controller autonomous device receives a data and corresponding metadata, it will first perform a cyclic redundancy check operation on the data to generate a cyclic redundancy. Check code, and then encode the metadata and cyclic redundancy check code together to generate an adjusted check code with the same number of bits, so that the adjusted check code can not only protect the data point-to-point In addition, metadata can also be protected point-to-point. Through the embodiments of the present invention, there is no need to perform additional cyclic redundancy check operations on metadata, and the amount of data is not increased, so as to save the space of the flash memory as much as possible. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

200~212: steps

Claims (10)

A method for accessing a flash memory module includes: receiving a data and a metadata corresponding to the data from a host device; when the data has not been stored in a buffer memory or a dynamic When randomly accessing the memory, a check code calculation operation is performed on the data to generate a check code to perform end to end protection to avoid subsequent buffer memory or the storage of the dynamic random access memory. Errors in the fetching process; perform a first encoding operation on the metadata and the check code to generate an adjusted check code; perform a second encoding operation on the data and the adjusted check code together to generate A coded data, and store the coded data in the buffer memory or the dynamic random access memory, where the coded data includes the data, the adjusted check code, and the data and the An error correction code of the adjusted check code; and write the encoded data and the metadata to a data page in a block of the flash memory module. For the method described in item 1 of the scope of patent application, the step of performing the first encoding operation on the metadata and the check code to generate the adjusted check code includes: the metadata and the check code Perform exclusive OR (XOR) operation to generate the adjusted check code. For example, the method described in item 1 of the scope of patent application, wherein the data includes multiple parts, and the data is subjected to a check code calculation operation to generate the check code, and the metadata and the check code are performed on the first The step of an encoding operation to generate the adjusted check code includes: performing check code calculation operations on the multiple parts of the data to generate multiple parts of the check code; Dividing the metadata into multiple parts; and performing the first encoding operation on the multiple parts of the metadata and the multiple parts of the check code to respectively generate multiple parts of the adjusted check code . The method described in item 3 of the scope of patent application, wherein the number of bits in each part of the metadata is the same as the number of bits in each part of the check code, and the multiple parts of the metadata are respectively The step of performing the first encoding operation with the multiple parts of the check code to generate the multiple parts of the adjusted check code includes: the multiple parts of the metadata and the check code The multiple parts perform mutually exclusive OR operations to generate the multiple parts of the adjusted check code. For example, the method described in item 1 of the scope of patent application further includes: reading the encoded data and the metadata from the data page in response to a read request from the host device; and decoding the encoded data to Generate the data and the adjusted check code; perform check code calculation operations on the data to generate another check code; encode the other check code with the metadata read from the data page To generate another adjusted check code; and compare the adjusted check code with the another adjusted check code to determine whether the metadata stored in the data page has errors. For example, the method described in item 5 of the scope of patent application further includes: when the content of the adjusted check code is not exactly the same as the content of the other adjusted check code, determine the metadata stored in the data page There is an error, and an error message is returned to the host device; And when the content of the adjusted check code is exactly the same as the content of the other adjusted check code, determine that the metadata stored in the data page is correct, and return the data and the metadata to the host device . Such as the method described in item 1 of the scope of patent application, wherein the metadata includes identification information, hash data, or Quality of Service (QoS) information of the data. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing a Program code; a microprocessor used to execute the program code to control access to the flash memory module; and multiple codecs; wherein when the flash memory controller receives a host device from a Data and metadata corresponding to the data. When the data has not been stored in a buffer memory or a dynamic random access memory, the multiple codecs perform a check code calculation operation on the data A check code is generated to perform end to end protection to avoid errors in the subsequent buffer memory or the access process of the dynamic random access memory; and the metadata and the check code are combined Perform a first encoding operation to generate an adjusted check code, and perform a second encoding operation on the data and the adjusted check code together to generate an encoded data and store it in the buffer memory or the Dynamic random access memory, wherein the encoded data includes the data, the adjusted check code, and an error correction code corresponding to the data and the adjusted check code; and the microprocessor encodes the code The data and the metadata are written to a data page in a block of the flash memory module. The flash memory controller described in item 8 of the patent application, wherein the multiple codecs perform an exclusive OR (XOR) operation on the metadata and the check code to generate the adjusted check code. The flash memory controller described in item 8 of the scope of patent application, wherein the data includes multiple parts, and the multiple codecs respectively perform check code calculation operations on the multiple parts of the data to generate The multiple parts of the check code, and divide the metadata into multiple parts to perform the first encoding operation on the multiple parts of the metadata and the multiple parts of the check code to respectively generate The multiple parts of the adjusted check code.

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