TWI696277B - Display panel, driver circuit and display panel menufacturing method - Google Patents

Abstract

A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array on the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks overlap the first conductor patterns respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks do not overlap the first conductor patterns. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is in a range of 50 micrometers to 3000 micrometers.

Description

Display panel, driving circuit and manufacturing method of display panel

The invention relates to an electronic device, and in particular to a display panel, a driving circuit and a method for manufacturing the display panel.

The liquid crystal display panel may be composed of a counter substrate, an array substrate, and a liquid crystal layer between the two substrates. In order to improve the efficiency of the manufacturing process, most of the current LCD panel manufacturing is to first assemble the array substrate sheet and the counter substrate sheet, and seal the liquid crystal material therebetween to form a motherboard with multiple display panels. After that, the motherboard is cut into multiple independent display panels.

In response to a wide range of product requirements, display panel sizes often have different designs. The manufacture of current liquid crystal display panels requires the development of photomasks for display panels of different sizes, which cannot reduce the manufacturing cost and are not conducive to the customization of special size display panels.

In one embodiment of the present invention, a display panel is provided. The structure of the display panel helps to improve the flexibility of the size of the display panel, improve the disadvantages of the corrosion of the conductive material after the cutting process of the display panel, and avoid different layers or elements of the display panel during the cutting process There is a short circuit problem.

An embodiment of the invention provides a display panel including a substrate, a plurality of standard pixel units and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of masking blocks of a masking pattern layer are arranged in an array on the substrate; each of the standard pixel units includes a first conductor pattern and the masking areas of the first conductor patterns A first masking block in the block, the first masking blocks overlapping the first conductor patterns respectively; each of the dummy pixel units includes a second masking block in the masking blocks, the The second masking blocks do not overlap with the first conductor patterns, wherein a first edge of the substrate and a standard pixel unit in the standard pixel units are adjacent to a first of the dummy pixel units The two edges are separated by a first pitch, and the first pitch is between 50 μm and 3000 μm.

In one embodiment of the present invention, a driving circuit is provided, and its architecture helps to improve the yield of the cutting process of the driving circuit and avoid signal interference problems.

An embodiment of the present invention provides a driving circuit, including a plurality of class circuits and a plurality of class connecting lines. Each of the class circuits includes a plurality of active elements; a first class connecting line located at the edge among the class connecting lines is electrically connected between two class circuits in the class circuits, and one of the first class connecting lines The sections are adjacently arranged in a clear space area, the clear space area is located between two adjacent grade circuits in the class circuits, the active components vacate the clear space area, and the length of the clear space area is between 50 microns and 150 microns The width of the clearance area is between 50 microns and 150 microns.

In one embodiment of the present invention, a driving circuit is provided, and its architecture helps to improve the yield of the cutting process of the driving circuit and avoid signal interference problems.

An embodiment of the present invention provides a driving circuit, including a plurality of class circuits and a plurality of class connecting lines. Each of the class circuits includes a plurality of active components; a first class connection line among the class connections is electrically connected between two class circuits in the class circuits, the first class connection line has a first A section and a second section. The first section is located between two adjacent class circuits in the class circuits. The line width of the first section is smaller than the line width of the second section.

In one embodiment of the present invention, a method for manufacturing a display panel is provided, the structure of which is helpful to improve the flexibility of the size of the display panel, improve the disadvantages of the corrosion of the conductive material after the cutting process of the display panel, and avoid different film layers in the cutting process of the display panel Or the component has a short circuit problem.

An embodiment of the invention provides a method for manufacturing a display panel, which includes providing a substrate material layer, forming a plurality of standard pixel units and a plurality of dummy pixel units, and cutting the substrate material layer along at least one cutting plane. Among them, a plurality of first conductor patterns and a plurality of masking blocks of a masking pattern layer are arranged in an array on the substrate material layer, and each of the standard pixel units includes a first conductor pattern and a plurality of the first conductor patterns A first masking block among the masking blocks, the first masking blocks respectively overlapping the first conductor patterns, and each of the dummy pixel units includes a second masking among the masking blocks In the block, the second shielding blocks do not overlap with the first conductor patterns. A cutting surface of the at least one cutting surface and a standard pixel unit of the standard pixel units are adjacent to a first edge of the dummy pixel units by a first spacing, the first spacing is between Between 50 microns and 3000 microns.

In the display panel of the embodiment of the present invention, since only dummy pixel units lacking specific materials (such as conductive materials) are provided in the pre-cutting area, the edges of the display panel produced by cutting will not be exposed with conductive material, but To avoid the problem of short circuit of different film layers or components in the cutting process of the display panel or the problem of corrosion after the cutting process, thereby ensuring the display quality. In addition, in order to avoid signal interference, the driving circuit is cut after the display panel cutting process to cut off the class connection line. The class connecting line has sections with different widths, or the class connecting line can be disposed away from other components in the pre-cut section to improve the yield of the cutting process of the driving circuit.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Directional terms mentioned in the embodiments, for example, "upper", "lower", "front", "rear", "left", "right", etc., are only directions referring to the drawings. Therefore, the directional terms used are for illustration, not for limiting the present invention. In the drawings, each drawing depicts general features of methods, structures, and/or materials used in particular exemplary embodiments. However, these drawings should not be construed as defining or limiting the scope or nature covered by these exemplary embodiments. For example, for clarity, the relative sizes, thicknesses, and positions of the various film layers, regions, and/or structures may be reduced or enlarged.

In the embodiments, the same or similar elements will use the same or similar reference numerals, and redundant descriptions thereof will be omitted. In addition, the features in the different exemplary embodiments can be combined with each other without conflict, and simple equivalent changes and modifications made in accordance with this specification or the scope of the patent application are still covered by this patent. In addition, the terms "first" and "second" mentioned in this specification or patent application are only used to name discrete components or distinguish different embodiments or ranges, not to limit the number of components. The upper limit or the lower limit is not intended to limit the manufacturing order or setting order of the components.

FIG. 1A is a schematic top view of a display panel 10 according to an embodiment of the present invention, FIG. 1B is a schematic cross-sectional view drawn along section line II′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line II-II′ of FIG. 1A Sectional schematic. Referring to FIG. 1A, the display panel 10 may have a display area AA and a non-display area NAA located around the display area AA, wherein the non-display area NAA may include a driving circuit area DR and a peripheral circuit area B on one side of the driving circuit area DR , Bonding area BD and pre-cutting area C. 1A to 1C together, the display panel 10 may include substrates 100, 190, standard pixel unit SPC, dummy pixel unit DPC, standard class circuit SSC, dummy class circuit DSC, display medium 110, support structure 120, a conductive layer 130, an adhesive layer 140, a planarization layer 150, a masking pattern layer 170, and insulating layers 180, 182, and 185. In other words, the pixel unit can be divided into a standard pixel unit SPC and a dummy pixel unit DPC, and the class circuit can be divided into a standard class circuit SSC and a dummy class circuit DSC. The masking pattern layer 170 can be divided into a plurality of masking blocks 170S, 170D, and each masking block 170S, 170D has a closed opening 172S, 172D, respectively, so that each masking block 170S, 170D is a hollow rectangle. Similarly, the insulating layer 180 can be divided into multiple insulating blocks GI1, the insulating layer 182 can be divided into multiple insulating blocks GI2, and the insulating layer 185 can be divided into multiple insulating blocks PV1.

The difference between the standard pixel unit SPC and the dummy pixel unit DPC is that the components are not exactly the same. The standard pixel unit SPC may include conductor patterns G1, S1, D1, semiconductor patterns SM1, pixel electrodes PE1, color filter patterns 160, masking blocks 170S in the masking pattern layer 170, and insulating blocks GI1 in the insulating layer 180 And the insulating block PV1 in the insulating layer 185. The dummy pixel unit DPC includes a semiconductor pattern SM1, a pixel electrode PE1, a color filter pattern 160, a masking block 170D in the masking pattern layer 170, an insulating block GI1 in the insulating layer 180, and an insulating region in the insulating layer 185 Block PV1, and may optionally include pseudo conductor patterns WG1, WS1. In other words, the dummy pixel unit DPC lacks the conductor patterns G1, S1, and D1, which means that the dummy pixel unit DPC lacks a part of the film layer or element in the standard pixel unit SPC. Among them, the dummy conductor patterns WG1 and WS1 in the dummy pixel unit DPC are the remaining portions of the conductor patterns G1 and D1 in the standard pixel unit SPC, which means that the external dimensions are only partially similar. It is worth noting that although the dummy pixel unit DPC on the left side of FIG. 1B is not exactly the same as the dummy pixel unit DPC on the right side of FIG. 1B, neither of them includes the conductor patterns G1, S1 in the standard pixel unit SPC D1, the functions and functions are similar, and in order to facilitate the explanation and emphasize the difference between the dummy pixel unit DPC and the standard pixel unit SPC, the dummy pixel unit DPC on the left side of FIG. 1B and the dummy image on the right side of FIG. 1B The element cells DPC share the same symbol.

The difference between the standard pixel unit SPC and the dummy pixel unit DPC is that the correspondence between the elements is not exactly the same. The standard pixel unit SPC includes conductor patterns G1, S1, and D1. Therefore, the shielding block 170S (or the color filter pattern 160) in the standard pixel unit SPC may overlap the conductor patterns G1, S1, and D1. The dummy pixel unit DPC does not include the conductor patterns G1, S1, and D1 in the standard pixel unit SPC. Therefore, the dummy pixel unit DPC shielding block 170D (or the color filter pattern 160) does not match the conductor pattern G1. S1 and D1 overlap.

Similarly, the standard class circuit SSC differs from the dummy class circuit DSC in that the components are not identical. The standard class circuit SSC may include the conductor patterns G2, S2, D2, the semiconductor pattern SM2, and the insulating block GI2 in the insulating layer 182. The dummy class circuit DSC includes the semiconductor pattern SM2 and the insulating block GI2 in the insulating layer 182, and may optionally include the pseudo conductor patterns WG2, WS2, and WD2. In other words, the dummy class circuit DSC lacks the conductor patterns G2, S2, D2, which means that the dummy class circuit DSC lacks some of the layers or components in the standard class circuit SSC. Among them, the dummy conductor patterns WG2, WS2, and WD2 in the dummy class circuit DSC are the remaining parts of the conductor patterns G2, S2, and D2 in the standard class circuit SSC, which means that the external dimensions are only partially similar. It is worth noting that although the dummy class circuit DSC on the left side of FIG. 1C is not exactly the same as the dummy class circuit DSC on the right side of FIG. 1C, both of them do not include the conductor patterns G2, S2, and D2 in the standard class circuit SSC. Similar to the function, and to facilitate the explanation and emphasize the difference between the dummy class circuit DSC and the standard class circuit SSC, the dummy class circuit DSC on the left side of FIG. 1C and the dummy class circuit DSC on the right side of FIG. 1C share the same symbol .

The standard pixel unit SPC, the dummy pixel unit DPC, the standard class circuit SSC and the dummy class circuit DSC are set in a specific manner. Specifically, as shown in FIG. 1A, only the standard pixel unit SPC is set in the display area AA; and the standard pixel unit SPC can be selectively set in the non-display area NAA. In addition, the dummy pixel unit DPC and the standard pixel unit SPC are closely arranged to form a matrix. Therefore, the mold layers or components included in the dummy pixel unit DPC and the standard pixel unit SPC are also regularly arranged, for example The color filter patterns 160, the conductor patterns G1, S1, D1, and the shielding blocks 170S, 172D are arranged in an array on the substrate 100. Similarly, the dummy class circuit DSC and the standard class circuit SSC are also arranged in an array. Furthermore, in some embodiments, one standard class circuit SSC may be set corresponding to one or more standard pixel units SPC, and one dummy class circuit DSC may be set corresponding to one or more dummy pixel units DPC. In addition, the adhesive layer 140 can overlap with part of the dummy pixel unit DPC or part of the dummy class circuit DSC, and the adhesion layer 140 can also overlap with part of the standard pixel unit SPC or part of the standard class circuit SSC. For example, in FIG. 1C, the adhesive layer 140 overlaps with one standard class circuit SSC, but the invention is not limited thereto, and the adhesive layer 140 may also overlap with 2 to 4 standard class circuits SSC.

As shown in FIG. 1A, based on the accuracy of the manufacturing process, the display panel 10 reserves a pre-cut area C at its edge to avoid damage to the film layer or elements in the display area AA during the display panel cutting process. In this case, the edge of the pre-cut area C may be aligned with the edge of the portion of the substrate 100 (eg, edge E1). In addition, the pre-cut area C may partially overlap the driving circuit area DR and the peripheral circuit area B, however, the pre-cut area C is separated from the display area AA without overlapping. In other embodiments, the dummy pixel unit DPC and the dummy class circuit DSC are provided in the pre-cut area C of the non-display area NAA, but the standard pixel unit SPC and the standard class circuit SSC are not provided. In other embodiments, the pre-cut area C of the non-display area NAA lacks a film layer or element made of a specific material, such as a film layer or element made of metal or conductive material. In some other embodiments, the dummy pixel unit DPC and dummy class circuit DSC located on the edge of the substrate 100 (such as the edge E1) lack films or elements (such as conductor patterns G1, G2, S1) made of metal or conductive materials , S2, D1, D2), so there is no metal or conductive material exposed on the edge of the display panel 10 produced by cutting, which can avoid short circuit in the display panel cutting process or avoid corrosion problems after the display panel cutting process, thereby ensuring the display quality. Similarly, the overlap between the peripheral circuit area B and the pre-cut area C also lacks a film layer or element made of metal or conductive material. In some embodiments, the edges of the dummy pixel unit DPC and the dummy class circuit DSC at the edge of the substrate 100 (eg, edge E1) are aligned with the edge of the substrate 100 (ie, edge E1).

The width of the pre-cutting area C can be adjusted according to the process accuracy. In some embodiments, the width WTH1 of the pre-cut area C is between 50 microns (micrometer, µm) and 3000 microns. In some embodiments, each section of the pre-cut zone C may have the same width; in other embodiments, different sections of the pre-cut zone C may have different widths. In some embodiments, the edge E1 of the substrate 100 is separated from the edge E2 of the adjacent dummy pixel unit DPC in the standard pixel unit SPC by a distance DIS1, and the distance DIS1 can roughly define the range of the pre-cut area C. In some embodiments, the spacing DIS1 is greater than or equal to 50 microns; in other embodiments, the spacing DIS1 is between 50 microns and 3000 microns. In some other embodiments, the edge E1 of the substrate 100 is separated from the edge E3 of the adjacent dummy class circuit DSC in the standard class circuit SSC by a distance DIS2, and the distance DIS2 may roughly define the range of the pre-cut region C. In some embodiments, the spacing DIS2 is greater than or equal to 50 microns; in other embodiments, the spacing DIS2 is between 50 microns and 3000 microns. It is worth noting that in FIG. 1B, the edges (such as edge E2) of the standard pixel unit SPC and the dummy pixel unit DPC are defined according to the edges of the masking blocks 170S and 170D, respectively; in other embodiments, The edges of the standard pixel unit SPC and the dummy pixel unit DPC can be respectively defined according to the edges of the color filter pattern 160; in other embodiments, the edges of the standard pixel unit SPC can also depend on the edges of the pixel electrode PE1 To define, the dummy pixel unit DPC is similar in size to the standard pixel unit SPC.

In order to improve the flexibility and yield of the size of the display panel 10, the motherboard used to make the display panel 10 can be further designed to cut the display panel 10 of any size in the motherboard while ensuring the display of the display panel 10 quality. Specifically, FIG. 2 is a schematic top view of the motherboard 20 of the display panel 10 according to an embodiment of the present invention. Referring to FIG. 2, the motherboard 20 may have a central region CR, pre-cut regions C1 to C3, a bonding region BD, driving circuit regions DR1 and DR2 located on both sides of the central region CR, and peripheral circuit regions B1 and B2. The pre-cut regions C1~C3 partially overlap the central region CR, the driving circuit regions DR1, DR2, and the peripheral circuit regions B1, B2, respectively. In some embodiments, the pre-cut regions C1-C3 may have the same width; in other embodiments, the pre-cut regions C1-C3 may have different widths. In some embodiments, the width WTH2 of the pre-cut regions C1-C3 is between 50 microns and 3500 microns. The motherboard 20 is used to make the display panel 10, so the upper left corner of FIG. 2 shows the display panel 10 of FIG. 1A. Furthermore, the cutting planes CS1 ˜ CS3 are located in the pre-cutting areas C1 ˜ C3 respectively, wherein the cutting plane CS1 can divide the display panel 10 from the mother board 20. As can be seen from the above, the motherboard 20 includes multiple standard pixel units (not shown in FIG. 2), multiple dummy pixel units (not shown in FIG. 2), and multiple standard class circuits (not shown in FIG. 2). 2) And multiple dummy class circuits (not shown in Figure 2). Among them, the dummy class circuit is mainly arranged in the overlapping region of the driving circuit regions DR1, DR2 and the pre-cut regions C1~C3, and the standard class circuit is mainly arranged in the remaining regions of the driving circuit regions DR1, DR2. The dummy pixel unit is mainly set in the overlapping area of the central area CR and the pre-cutting areas C1~C3, the standard pixel unit is mainly set in the remaining area of the central area CR, and the standard pixel unit, dummy pixel unit, standard Class circuits and dummy class circuits are arranged in an array.

In order to explain the technical content of the motherboard 20 and the display panel 10 in this embodiment in detail, the manufacturing method of the motherboard 20 will be described below with reference to FIGS. 3A to 3I, and the manufacturing method of the display panel 10 will be further described with reference to FIG. 4. 3A to 3I are schematic cross-sectional views of a manufacturing process of a partial motherboard 20 according to an embodiment of the present invention. The cross-sectional positions of FIGS. 3A to 3I are divided into positions corresponding to the cross-sectional line III-III' of FIG. 2.

Referring to FIG. 3A, a substrate material layer 300 is first provided. The substrate material layer 300 may be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate, or may be a flexible substrate, such as a polymer substrate or a plastic substrate. Next, a conductive material layer 301 is continuously formed on the substrate material layer 300. That is to say, in this embodiment, the conductive material layer 301 can be located in the central region CR; however, in other embodiments, the conductive material layer 301 can also be located in the central region CR, the driving circuit regions DR1, DR2 and the peripheral circuit region B1, B2. Based on conductivity considerations, the material of the conductive material layer 301 is generally other conductive materials such as metal materials or alloys, nitrides of metal materials, oxides of metal materials, and oxides of metal materials.

Next, a photoresist layer 302 is formed on the conductive material layer 301 in a comprehensive manner, and the conductive material layer 301 completely overlaps the photoresist layer 302. After forming the photoresist layer 302 on the conductive material layer 301, two exposure processes and one development process are performed. In this embodiment, the first exposure process is to irradiate the photoresist layer 302 through the first photomask 303 with an exposure beam L1 with uniformly distributed illuminance to form a first unexposed region 302H on the photoresist layer 302 With the first exposure area 302E1. The first photomask 303 has at least an opaque photomask pattern 303Q. In this embodiment, the shape of each first unexposed area 302H is the same, and the shape of the first unexposed area 302H is the same as the shape of the conductor pattern G1 in FIG. 1B. In other words, this embodiment is based on the motherboard 20. The central region CR forms first unexposed regions 302H of the same size and arranged in an array, so that the mother board 20 can be cut into a display panel of any size, and the size of the display panel and the pattern of the first photomask 303 (or The first exposure area 302E1) is not relevant.

Referring to FIG. 3B, a second exposure process is performed to form a second exposure area 302E2 on the photoresist layer 302. In this embodiment, the shape and size of the second exposure area 302E2 are completely the same as the shape and size of the pre-cut area C1. In addition, in this embodiment, the second exposure area 302E2 partially or completely overlaps part of the first unexposed area 302H and part of the first exposure area 302E1; in other embodiments, the second exposure area 302E2 and part of The first unexposed area 302H or part of the first exposed area 302E1 partially or completely overlaps. In other words, the motherboard 20 can be cut into a display panel of any size according to the shape of the second exposure area 302E2, and the size of the display panel is related to the pattern of the second exposure area 302E2. In some embodiments, the second exposure process may use the exposure beam L2 provided by the exposure machine to directly illuminate the photoresist layer 302 locally. In other words, the illumination intensity of the exposure beam L2 is concentrated and distributed in the second exposure area 302E2. No need to use an extra mask. However, the present invention is not limited to this. In other embodiments, the exposure beam L1 with uniformly distributed illuminance may be combined with a second mask (not shown) to form the exposure beam L2 and irradiate the photoresist layer 302 to Perform the second exposure process.

Referring to FIG. 3C, a development process is performed on the photoresist layer 302 to form a patterned photoresist layer 302P. Next, referring to FIG. 3D, using the patterned photoresist layer 302P as a mask, an etching process is performed on the conductor material layer 301, and after the etching process is performed to form the conductor pattern G1 and the pseudo-conductor pattern WG1, the patterned photoresist is removed Layer 302P, wherein the method of removing the patterned photoresist layer 302P may include a wet photoresist removal method or a dry photoresist removal method. In this way, the conductive material layer 301 can be patterned according to the first exposure area 302E1 and the second exposure area 302E2 to form the conductor pattern G1 and the pseudo-conductor pattern WG1 in FIG. 1B. The projected shape of the conductor pattern G1 on the substrate material layer 300 is the same as the projected shape of the first unexposed region 302H on the substrate material layer 300, and the projected shape of the pseudo conductor pattern WG1 on the substrate material layer 300 is the same as the first unexposed region In 302H, the projected shape of the remaining area of the second exposure area 302E2 on the substrate material layer 300 is subtracted. In this embodiment, the conductor pattern G1 located in the central region CR of the motherboard 20 is formed by two exposure processes and a development process for the photoresist layer 302; similarly, the driving circuit region DR1 located in the motherboard 20 , The conductor pattern G2 of DR2 or the traces in the peripheral circuit area B can also be formed by two exposure processes and a development process of the photoresist layer, and the conductor patterns G1 and G2 in FIGS. 1B and 1C can be respectively For the gate. Furthermore, in other embodiments, when the conductor pattern G1 is formed, a scan line (not shown) may be formed together, and the conductor pattern G1 may be electrically connected to the scan line; similarly, when the conductor pattern G2 is formed, a In addition, an element connection line (not shown) or an active element connection line (not shown) is formed, and the conductor pattern G2 can be electrically connected to the element connection line or the active element connection line.

Referring to FIG. 3E, an insulating block GI1 covering the conductor pattern G1 and the dummy conductor pattern WG1 is continuously formed on the substrate 100. In this embodiment, the material of the insulating block GI1 may include inorganic materials, organic materials, or a combination thereof. In some embodiments, when the insulating block GI1 is formed in the central region CR of the motherboard 20, it may be combined with the The driving circuit regions DR1 and DR2 form insulating blocks GI2, and the insulating blocks GI1 and GI2 in FIGS. 1B and 1C may be gate insulating layers, respectively.

Next, the semiconductor pattern SM1 overlapping the conductor pattern G1 or the pseudo conductor pattern WG1 is formed on the substrate 100. The material of the semiconductor pattern SM1 may include polysilicon. In this embodiment, the semiconductor pattern SM1 can be formed through a lithography etching process. In some embodiments, when the semiconductor pattern SM1 is formed in the central region CR of the motherboard 20, the semiconductor patterns SM2 may be formed together with the driving circuit regions DR1, DR2 of the motherboard 20, and the semiconductor patterns SM1, SM2 may include source regions, respectively , Drainage area and channel area. In this embodiment, the conductor patterns G1 and G2 are disposed under the semiconductor patterns SM1 and SM2, respectively, and thus will constitute a bottom gate type thin film transistor (bottom gate TFT). However, the present invention is not limited to this. In other embodiments, it can also be designed as a top gate TFT or other suitable type of TFT.

Next, a conductive material layer 304 is continuously formed on the substrate material layer 300. Based on the consideration of conductivity, the material of the conductive material layer 304 is generally a metal material. In other words, the material of the conductive material layer 304 may be similar to the material of the conductive material layer 301. Next, a photoresist layer 305 is formed on the conductive material layer 304 in a comprehensive manner, and the conductive material layer 304 and the photoresist layer 305 completely overlap. After the photoresist layer 305 is formed on the conductive material layer 304, another two exposure processes and a development process are performed. In the present embodiment, the first exposure process is to irradiate the photoresist layer 305 through the first photomask 306 with an exposure beam L1 with uniformly distributed illuminance to form a first unexposed region 305Hs on the photoresist layer 305 , 305Hd and the first exposure areas 305E1a, 305E1b. The first mask 306 has at least opaque mask patterns 306Qs and 306Qd. In this embodiment, the projected shape of each first unexposed region 305Hs on the substrate material layer 300 is the same, and the projected shape of the first unexposed region 305Hs on the substrate material layer 300 is the same as the conductor pattern S1 in FIG. 1B to the substrate 100 The projection shapes of are the same; the shape of each first unexposed area 305Hd is the same, and the shape of the first unexposed area 305Hd is the same as the shape of the conductor pattern D1 in FIG. 1B. In other words, in this embodiment, the first unexposed regions 305Hs and 305Hd in a regular shape and arranged in an array are formed in the central region CR of the mother board 20. In this way, the mother board 20 can be cut into a display panel of any size and display The size of the panel is not related to the pattern of the first photomask 306 (or the first exposure areas 305E1a, 305E1b).

Referring to FIG. 3F, a second exposure process is performed to form a second exposure area 305E2 on the photoresist layer 305. In this embodiment, the projected shapes and sizes of the second exposure regions 302E2 and 305E2 on the substrate material layer 300 are completely the same as the shapes and sizes of the pre-cut area C1. In some embodiments, the projection of the second exposure area 302E2 on the substrate material layer 300 completely overlaps with the projection of the second exposure area 305E2 on the substrate material layer 300; in other embodiments, considering the process accuracy, the second exposure area 302E2 The projection on the substrate material layer 300 is not completely aligned with the projection of the second exposure area 305E2 on the substrate material layer 300, for example, the projection of the second exposure area 302E2 on the substrate material layer 300 is compared to the projection of the second exposure area 305E2 on the substrate material layer 300 The projection has a misalignment of 100 microns. In addition, in this embodiment, the second exposure area 305E2 partially or completely overlaps part of the first unexposed areas 305Hs, 305Hd and part of the first exposure areas 305E1a, 305E1b; in other embodiments, the second exposure area 305E2 partially or completely overlaps part of the first unexposed regions 305Hs, 305Hd or part of the first exposed regions 305E1a, 305E1b. In other words, the motherboard 20 can be cut into a display panel of any size according to the shape of the second exposure area 305E2, and the size of the display panel is related to the projection pattern of the second exposure area 305E2 on the substrate material layer 300. In some embodiments, the second exposure process may use the exposure beam L2 provided by the exposure machine to directly illuminate the photoresist layer 305 locally. In other words, the illumination intensity of the exposure beam L2 is concentrated and distributed in the second exposure area 305E2. No need to use an extra mask. However, the present invention is not limited to this. In other embodiments, the exposure beam L1 with uniformly distributed illuminance may be combined with another second mask (not shown) to form the exposure beam L2 and irradiate the photoresist layer 305. For the second exposure process.

Referring to FIG. 3G, a development process is performed on the photoresist layer 305 to form a patterned photoresist layer 305P. Next, referring to FIG. 3H, using the patterned photoresist layer 305P as a mask, an etching process is performed on the conductive material layer 304, and after the etching process is performed to form the conductor patterns S1, D1 and the pseudo-conductor pattern WS1, the patterning is removed Photoresist layer 305P. In this way, the conductive material layer 304 can be patterned according to the first exposure regions 305E1a, 305E1b and the second exposure region 305E2 to form the conductor patterns S1, D1 and the pseudo-conductor pattern WS1 in FIG. 1B. The projected shapes of the conductor patterns S1 and D1 on the substrate material layer 300 are respectively the same as the projected shapes of the first unexposed regions 305Hs and 305Hd on the substrate material layer 300, and the projected shapes of the pseudo conductor patterns WG1 and WS1 on the substrate material layer 300 are It is the same as the projected shape of the remaining area of the first unexposed areas 305Hs and 305Hd minus the second exposed area 305E2 on the substrate material layer 300. In this embodiment, the conductor patterns S1 and D1 located in the central region CR of the motherboard 20 are formed by two exposure processes and a development process for the photoresist layer 302; similarly, the driving circuit located in the motherboard 20 The conductor patterns S2 and D2 in the regions DR1 and DR2 can also be formed by two exposure processes and a development process for the photoresist layer, and the conductor patterns S1 and S2 in FIGS. 1B and 1C can be the source and the conductor, respectively. The patterns D1 and D2 may be drains, respectively. Furthermore, in other embodiments, when the conductor pattern S1 is formed, a data line (not shown) may be formed together, and the conductor pattern S1 may be electrically connected to the data line; similarly, when the conductor pattern S2 is formed, a In addition, an element connection line (not shown) or an active element connection line (not shown) is formed, and the conductor pattern S2 can be electrically connected to the element connection line or the active element connection line.

Next, referring to FIG. 3I, insulating blocks PV1 covering the conductor patterns S1 and D1 are continuously formed on the substrate 100 to provide a protection function or a planarization function. Moreover, a part of the conductor pattern D1 is exposed from the insulating block PV1 through a lithography etching process. In this embodiment, the material of the insulating block PV1 may include inorganic materials, organic materials, or a combination thereof.

Next, a patterned pixel electrode PE1 is formed on the substrate 100 through a lithography etching process. In this embodiment, the pixel electrode PE1 covers the insulating block PV1, and fills the opening of the insulating block PV1 to be in contact with the conductor pattern D1. In this embodiment, the material of the pixel electrode PE1 may include a transparent metal oxide conductive material, including (but not limited to): indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or Indium germanium zinc oxide. Here, the production of the array substrate plate of the mother board 20 can be completed.

After the production of the counter substrate plate is completed, the array substrate plate and the counter substrate plate can be assembled, and the display medium 110 can be sealed therebetween by the adhesive layer 140, which includes multiple display panels (or multiple standard pictures) Motherboard 20 of multiple pixel units, multiple dummy pixel units, multiple standard class circuits, and multiple dummy class circuits). The opposite substrate sheet may include a substrate 190, a masking pattern layer 170, a color filter pattern 160, a planarization layer 150, and a conductive layer 130. Each masking block 170S, 170D of the masking pattern layer 170 masks the boundary of the color filter pattern 160. The masking pattern layer 170 may be a black matrix (Black Matrix, BM), and the color filter pattern 160 may be, for example, a red filter pattern, green Filter pattern and blue filter pattern. The conductive layer 130 may be selectively a transparent conductive material, such as indium tin oxide. The adhesive layer 140 may be a sealant, and the adhesive layer 140 does not overlap with the cutting surface CS1. In addition, a support structure 120 may be selectively disposed between the array substrate plate and the counter substrate plate, such as but not limited to a photo-spacer to form a cell gap, and the position of the support structure 120 may correspond to The shielding blocks 170S and 170D are arranged to reduce the loss of aperture ratio.

In this embodiment, the display medium 110 may be a liquid crystal material, and the display panel 10 is called a liquid crystal display panel, but the present invention is not limited to this; in other embodiments, the display panel 10 may also be properly adjusted for electrical excitation Optical material display panel or Active Matrix Organic Light-Emitting Diode (AMOLED) display panel. Furthermore, in this embodiment, the array substrate sheet is a substrate sheet with thin film transistors, and the opposite substrate sheet is a color filter substrate sheet with a color filter pattern 160, but the invention is not limited to this; in other In an embodiment, the array substrate sheet may also be a COA substrate sheet incorporating the color filter pattern 160 on the thin film transistor or an AOC substrate sheet incorporating the thin film transistor on the color filter pattern 160. In this case, the opposite No color filter pattern 160 needs to be made on the substrate plate. In other words, the conductor patterns G1, S1, D1, the semiconductor pattern SM1, the pixel electrode PE1, the color filter pattern 160, the shielding block 170S, and the insulating blocks GI1, PV1 are all disposed between the array substrate plate and the counter substrate plate, It means that it is arranged above one of the array substrate plate and the counter substrate plate.

Please refer to FIG. 2, FIG. 3I and FIG. 4 together. FIG. 4 is a schematic top view of the display panel cutting process of the motherboard 20 of the display panel 10 according to an embodiment of the present invention. After the production of the mother board 20 is completed, the mother board 20 is cut along the cutting planes CS1 to CS3 by a mechanical method such as a cutter wheel or a laser to display the display panel to form a plurality of independent display panels, for example, display panels 10 and 42 , 43. The cutting planes CS1~CS3 in FIG. 4 can be located in the second exposure area 302E2 or 305E2 of FIG. 3B or FIG. 3F. Preferably, the cutting planes CS1~CS3 in FIG. 4 are located in the second exposure area of FIG. 3B and FIG. 3F In the overlapping area of 302E2 and 305E2. It can be seen from the above that since the mother board 20 is provided with dummy pixel units DPC or dummy class circuits DSC in the pre-cutting areas C1 to C3, the cut display panels 10, 42, 43 are also on the cutting surfaces CS1 to CS3. The dummy pixel unit DPC or dummy class circuit DSC is installed, and no metal or conductive material is exposed on the cutting planes CS1~CS3. In this way, the cut display panels 10, 42, 43 are tested and shipped The process will not affect the quality due to metal corrosion, and the high temperature and humidity in the display panel cutting process will not cause metal corrosion and cause short circuits. In addition, since the pre-cutting areas C1 to C3 of the motherboard 20 can be further adjusted according to different design considerations and system requirements, the size of the display panel 10 cut from the motherboard 20 can be flexibly adjusted. In addition, after the display panel cutting process, the edges of the dummy pixel unit DPC and the dummy class circuit DSC on the cutting planes CS1~CS3 of the display panels 10, 42, 43 are aligned with the cutting planes CS1~CS3. The display panels 10, 42, and 43 can be connected to external circuits 410, 420, and 430 via bonding areas BD, respectively, wherein the external circuits 410, 420, and 430 are, for example, control circuits or driver chips.

The display panel 10 and the motherboard 20 can be adjusted according to different design considerations. In FIG. 1B, the difference between the standard pixel unit SPC and the dummy pixel unit DPC is that the dummy pixel unit DPC lacks the conductor patterns G1, D1, and S1 in the standard pixel unit SPC to avoid the display panel cutting process Short circuit occurs in the middle or avoids the problem of corrosion after the display panel cutting process. However, the present invention is not limited to this. When the position of the cutting surface CS1 is shifted in the pre-cutting area C1, all the dummy pixel units DPC may not include the conductor patterns G1, D1, S1 and the pseudo conductor patterns WG1, WS1 . On the other hand, the dummy pixel unit DPC may have other component differences than the standard pixel unit SPC. In some embodiments, the dummy pixel unit does not include the pixel electrode PE1 in the standard pixel unit SPC; in some embodiments, the dummy pixel unit does not include the semiconductor pattern SM1 in the standard pixel unit SPC; In some embodiments, the dummy pixel unit does not include the insulating block GI1 or the insulating block PV1 in the standard pixel unit SPC. Similarly, the dummy class circuit DSC may have other component differences compared to the standard class circuit SSC.

For example, please refer to FIG. 5, which is a schematic cross-sectional view of a display panel 50 according to an embodiment of the present invention, wherein the cross-sectional position of FIG. 5 corresponds to the position of the cross-sectional line I-I' of FIG. 1A. The display panel 50 of this embodiment has a similar structure to the display panel 10 of the embodiment described in FIG. 1B. The difference from the embodiment described in FIG. 1B is that the dummy pixel unit DPC5 of the display panel 50 does not include the standard. The conductor pattern G1, the pixel electrode PE1, and the semiconductor pattern SM1 in the pixel unit SPC. In this way, short circuit caused by high temperature and high humidity in the display panel cutting process can be avoided. The pixel electrode PE1 overlaps the opening 172S (and color filter pattern 160) of the masking block 170S; the pixel electrode PE1 does not overlap the opening 172D (and color filter pattern 160) of the masking block 170D. In addition, the semiconductor patterns SM1 overlap with the shielding blocks 170S (or color filter patterns 160) respectively; neither of the semiconductor patterns SM1 overlap with the shielding blocks 170D (or color filter patterns 160). In this case, the pixel electrode PE1 and the semiconductor pattern SM1 may be similar to the manufacturing methods of the conductor patterns G1, G2, S1, S2, D1, and D2 in FIGS. 3A to 3H, and by two exposures to the photoresist layer The process and a development process form a pseudo semiconductor pattern WSM1 (or pseudo pixel electrode). In addition, as shown in FIG. 5, the edge of the dummy pixel unit DPC5 at the edge of the substrate 100 (such as the edge E1) is aligned with the edge of the substrate 100.

Similarly, please refer to FIG. 6, which is a schematic cross-sectional view of a display panel 60 according to an embodiment of the present invention, wherein the cross-sectional position of FIG. 6 corresponds to the position of the cross-sectional line I-I' of FIG. 1A. The display panel 60 of this embodiment is similar in structure to the display panel 10 of the embodiment described in FIG. 1B. The difference from the embodiment described in FIG. 1B is that the dummy pixel unit DPC6 of the display panel 60 does not include the standard. The conductor patterns G1, D1, S1, the pixel electrode PE1, and the semiconductor pattern SM1 in the pixel unit SPC. In this way, short circuit caused by high temperature and high humidity in the display panel cutting process can be avoided. In addition, as shown in FIG. 6, the edge of the dummy pixel unit DPC6 at the edge of the substrate 100 (eg, edge E1) is aligned with the edge of the substrate 100.

Similarly, please refer to FIG. 7, which is a schematic cross-sectional view of a display panel 70 according to an embodiment of the present invention, wherein the cross-sectional position of FIG. 7 corresponds to the position of the cross-sectional line I-I' of FIG. 1A. The display panel 70 of this embodiment has a similar structure to the display panel 10 of the embodiment described in FIG. 1B. The difference from the embodiment described in FIG. 1B is that the dummy pixel unit DPC7 of the display panel 70 does not include the standard. The conductor patterns G1, D1, S1, the pixel electrode PE1, the semiconductor pattern SM1, and the insulating blocks GI1, PV1 in the pixel unit SPC. In this way, short circuit caused by high temperature and high humidity in the display panel cutting process can be avoided. In this case, the insulating blocks GI1 and PV1 can be similar to the manufacturing methods of the conductor patterns G1, G2, S1, S2, D1, and D2 in FIGS. 3A to 3H, and by two exposure processes for the photoresist layer And a development process to form pseudo-insulated blocks WGI1, WPV1. Moreover, the shielding block 170S (or its opening 172S) overlaps with the insulating blocks GI1 and PV1, respectively, while the shielding block 170D (or its opening 172D) does not overlap with the insulating blocks GI1 and PV1. In addition, as shown in FIG. 7, the edge of the dummy pixel unit DPC7 at the edge of the substrate 100 (such as the edge E1) is aligned with the edge of the substrate 100. In some embodiments, the display panel 70 may further include a light-shielding adhesive strip 700. The light-shielding adhesive strip 700 is used to avoid light leakage at the edge. It is disposed in the non-display area NAA, and can be partially connected with the standard pixel unit SPC or partially dummy. The pixel unit DPC7 (or part of the standard class circuit SSC or part of the dummy class circuit DSC) overlaps.

The driving circuit area DR of the display panel 10 can be further adjusted to reduce signal interference. Please refer to FIG. 1A, FIG. 1C, FIG. 8A to FIG. 8D, FIG. 8A is a partial schematic top view of the display panel 10 drawn in FIG. 1A of the present invention, and FIG. 8B to FIG. 8D are the display panel 10 drawn in FIG. 8A of the present invention, respectively Top view schematic diagram of local areas ZM1~ZM3. For ease of explanation, the film layers or elements in FIGS. 1A and 1C are omitted in FIGS. 8A to 8D, and the relative sizes and thicknesses of the film layers, regions, and/or structures may be adaptively reduced or enlarged in FIGS. 8A to 8D. And location. As shown in FIGS. 8A to 8C, in this embodiment, the standard class circuit SSC includes active elements TFT8a, TFT8b, active element connection lines 810S, 810G, 810SM, capacitor CT8, and element connection line 890. The active elements TFT8a and TFT8b include conductor patterns G2, S2, D2 and semiconductor pattern SM2, respectively; the capacitor CT8 includes electrode plates EP1, EP2. As shown in FIGS. 8A and 8D, the dummy class circuit DSC includes pseudo conductor patterns WG2, WS2, WD2, semiconductor patterns SM2, pseudo electrode plates WEP1, WEP2, active component connection lines 810S, 810G, 810SM, and component connection lines 890. From the above, it can be seen again that the difference between the standard class circuit SSC and the dummy class circuit DSC is that the components are not exactly the same.

Specifically, after the display panel 10 is cut out from the motherboard 20, the dummy conductor patterns WG2, WS2, and WD2 of the dummy class circuit DSC may be coupled to the standard class circuit SSC via the class connection lines 800a, 800b, 800c, or 800d , Which can cause signal interference. In order to avoid signal interference, after cutting out the display panel 10 from the mother board 20, the class connection lines 800a to 800d must be further cut along the cutting line CL1, for example, a laser is used to cut the driving circuit. In other embodiments, the driving circuit may be cut before the display panel 10 is cut. As shown in FIG. 8A, in this embodiment, the class connection lines 800a, 800b, 800c, or 800d may be electrically connected between adjacent standard class circuits SSC or between the adjacent standard class circuit SSC and the dummy class Between the circuits DSC, but the invention is not limited to this; in other embodiments, the class connection lines 800a, 800b, 800c or 800d may be electrically connected between non-adjacent standard class circuits SSC or non-adjacent Between the standard class circuit SSC and the dummy class circuit DSC; in other embodiments, the class connection line 800a, 800b, 800c or 800d may be electrically connected only between the two standard class circuits SSC or only electrically connected Between a standard class circuit SSC and a dummy class circuit DSC; in other embodiments, the class connection line 800a, 800b, 800c or 800d can electrically connect the standard class circuit SSC or the dummy class circuit DSC to other Circuit.

Considering the process accuracy, in some embodiments, the pre-cut section 800a at the edge adjacent to the cutting line CL1 should be set away from other components, that is, the clearance area XX is set to facilitate the driving of the class connection lines 800a~800d Circuit cutting process. Specifically, as shown in FIG. 8A, the edge-level connecting line 800a may have a first section 8001 and a second section 8002, where the first section 8001 is a section pre-cut adjacent to the cutting line CL1, and The first section 8001 is disposed adjacent to the clearance area XX. In addition, the first section 8001 may be aligned with the clearance area XX, and further, the upper edge, the right edge, and the lower edge of the first section 8001 may be aligned with the upper edge, the left edge, and the lower edge of the clearance area XX. In some embodiments, the class connection line 800a may be used to provide a specific level of direct current, but the invention is not limited thereto. In order to ensure that the first section 8001 is away from other components, the active components TFT8a, TFT8b, the component connection line 890, the capacitor CT8, or the active component connection lines 810S, 810G, and 810SM are all vacated by the clearance area XX. The element TFT8a, TFT8b, element connection line 890, capacitor CT8 or active element connection line 810S, 810G, 810SM or other signal transmission element. In some embodiments, the length LL of the clearance area XX is between 50 microns and 150 microns, and the width WW of the clearance area XX is between 50 microns and 150 microns. Since the clearance area XX can be located between the adjacent standard class circuit SSC and the dummy class circuit DSC, and the first section 8001 of the class connection line 800a located at the edge is adjacent to the clear space region XX, in this way, when When cutting the class connection lines 800a to 800d with the cutting line CL1, the clearance area XX can avoid damaging components other than the class connection lines 800a to 800d, so the yield of the driving circuit cutting process for the class connection lines 800a to 800d can be improved. It is worth noting that in some embodiments, unimportant elements, such as floating elements, may be provided in the clearance area XX. In addition, as shown in FIG. 8A, the cutting line CL1 is adjacent to the headroom area XX between the adjacent standard class circuit SSC and the dummy class circuit DSC or the headroom between two adjacent standard class circuits SSC. Area XX.

In order to further improve the yield of the cutting process of the driving circuit, the width of any of the class connecting lines 800a to 800d can be further adjusted. For example, as shown in FIG. 8A, the line width W1 of the first section 8001 of the class connection line 800a is smaller than the line width W2 of the second section 8002. In some embodiments, the line width W1 of the first section 8001 is approximately between 8 μm and 10 μm, and the line width W2 of the second section 8002 is approximately between 100 μm and 200 μm. In some embodiments, the ratio between the line width W1 of the first section 8001 and the line width W2 of the second section 8002 is between 0.04 and 1. In some embodiments, the length LN1 of the first section 8001 is between 50 microns and 150 microns. In other embodiments, the class connection lines 800b-800d may also have multiple sections with different widths, so as to facilitate the driving circuit cutting process for the class connection lines 800a-800d.

In addition, as shown in FIGS. 1C and 8A, since the adhesion layer 140 may overlap with part of the standard class circuit SSC or part of the dummy class circuit DSC, the components in the standard class circuit SSC and the dummy class circuit DSC may be further Adjust to ensure the curing of the adhesive layer 140. For example, the electrode plate EP1 in the capacitor CT8 has multiple openings EP1n, and the electrode plate EP2 in the capacitor CT8 also has multiple openings EP2n, and the openings EP1n overlap the openings EP2n, respectively. In other words, the capacitor CT8 has a hollow structure, which can increase the light transmittance of the capacitor CT8 to ensure the curing of the adhesive layer 140. Similarly, the dummy electrode plates WEP1 and WEP2 of the dummy class circuit DSC also have multiple openings, respectively, forming a hollow structure. It is worth noting that in FIG. 8A, the number of openings EP1n and EP2n is 15, respectively, but the present invention is not limited thereto, and the number of openings EP1n and EP2n can be adjusted adaptively according to different requirements.

On the other hand, in some embodiments, the active device TFT8a may be electrically connected by the active device connection line 810S, 810G, or 810SM, wherein the active device connection line 810S and the conductive pattern S2 of the active device TFT8a may form multiple An opening 810Sn, the active device connecting line 810G and the conductive pattern G2 of the active device TFT8a can form a plurality of openings 810Gn, and the active device connecting line 810SM and the semiconductor pattern SM2 of the active device TFT8a can form a plurality of openings 810SMn. In other embodiments, the active element connecting lines 810S, 810G, and 810SM connect two adjacent active element TFTs 8a in parallel. In other embodiments, the line widths Ws, Wg, and Wsm of the active element connection lines 810S, 810G, and 810SM are less than 40 microns, respectively. Similarly, the active device TFTs 8b can be electrically connected by the active device connection line 810G to form an opening 810Gn. In other words, the active devices TFT8a and TFT8b can form a hollow structure with the active device connection lines 810S, 810G or 810SM, which can improve the transmittance of the active devices TFT8a and TFT8b to ensure the curing of the adhesive layer 140. It is worth noting that the number of openings 810Sn, 810Gn, 810SMn can also be adjusted according to different needs. In addition, a plurality of active device connection lines 810G can be formed between the active device TFT8a to form a shunt, thereby increasing the equivalent line width and current resistance, so as to avoid damage to the single active device connection line 810G due to excessive load current; accordingly, A plurality of active element connecting lines 810S or 810SM are provided between the active elements TFT8a. In some embodiments, the active elements TFT8a and TFT8b may be two-finger finger transistors; in other embodiments, the active elements TFT8a and TFT8b may be multi-finger finger transistors. In addition, as shown in FIGS. 1C and 8A to 8C, the edges of the conductor pattern S2 in the active elements TFT8a and TFT8b may be offset from the edges of the semiconductor pattern SM2, but in other embodiments, the edges of the conductor pattern S2 It can be aligned with the edge of the semiconductor pattern SM2 to reduce the load between the gate-source capacitance and the gate-drain capacitance of the active elements TFT8a and TFT8b. Similarly, the dummy conductor patterns WG2, WS2, and semiconductor pattern SM2 of the dummy class circuit DSC can also form a hollow structure with the active device connection lines 810S, 810G, or 810SM.

In order to facilitate the cutting process of the driving circuit, the display panel can be further adjusted. Please refer to FIG. 9, which is a schematic partial top view of a display panel 90 according to an embodiment of the present invention. The display panel 90 of this embodiment has a similar structure to the display panel 10 of the embodiment described in FIG. 8A, and differs from the embodiment described in FIG. 8A in that, in addition to setting the clearance area XX, the adjacent standard in the display panel 90 There may be a gap between the class circuits SSC9, or there may be a gap between the adjacent standard class circuit SSC9 and the dummy class circuit DSC9, and the clearance area XX is located in the gap. The active elements TFT9a, TFT8b, active element connection lines 810S, 810G, 810SM, capacitor CT9, and element connection line 990 of the standard class circuit SSC9 are all free from the clearance area XX; similarly, the dummy conductor patterns WG9, WS9 of the dummy class circuit DSC9 , WD9, semiconductor pattern SM9, pseudo-electrode plates WEP3, WEP4, active component connection lines 810S, 810G, 810SM and component connection lines 990 are all cleared of the clearance area XX. In other words, these gaps substantially expand the range of the clearance area XX, so that the yield of the driving circuit cutting process can be further improved. In addition, in order to reduce the resistance, in this embodiment, the width of the step connection lines 800a-800d may be a fixed value without having a width change.

In order to facilitate the cutting process of the driving circuit, the display panel can be further adjusted. Please refer to FIG. 10, which is a schematic partial top view of a display panel 95 according to an embodiment of the present invention. The display panel 95 of this embodiment has a similar structure to the display panel 90 of the embodiment described in FIG. 9, and differs from the embodiment described in FIG. 9 in that the structure of the step connection line can be further adjusted. For example, as shown in FIG. 10, the class connection line 1000 has a first section 10001 and a second section 10002. The first section 10001 of the class connection line 1000 has branches 10001a to 10001c, and the line width of the branches 10001a to 10001c W3 is smaller than the line width W2 of the second section 10002. In some embodiments, the line width W3 of the branches 10001a-10001c is approximately between 8 microns and 10 microns. In other embodiments, the class connection lines 800b-800d may also have multiple branches to facilitate the driving circuit cutting process. It is worth noting that in FIG. 10, the number of branches 10001a to 10001c of the first section 10001 is three, but the present invention is not limited thereto, and the number of branches of the first section 10001 can be adjusted adaptively according to different requirements.

In order to facilitate the cutting process of the driving circuit, the display panel can be further adjusted. Please refer to FIG. 11. FIG. 11 is a schematic partial top view of a display panel 99 according to an embodiment of the present invention. The display panel 99 of this embodiment is similar to the display panel 90 of the embodiment described in FIG. 9 in structure and functions and functions. Therefore, the same symbol represents the same element. This embodiment differs from the embodiment described in FIG. 9 in that the components in the standard class circuit SSC11 and the dummy class circuit DSC11 of the display panel 99 can be further adjusted. Specifically, the standard class circuit SSC11 may not include the capacitor CT8; similarly, the dummy class circuit DSC11 may not include the pseudo electrode plates WEP1, WEP2. In addition, the shape of the active element TFT11a of the standard class circuit SSC11 is different from the active element TFT9a of the standard class circuit SSC9 in FIG. 9, in this case, the active element TFT11a may also have a capacitance effect. Similarly, the shapes of the dummy conductor patterns WG11 and WS11 of the dummy class circuit DSC11 are different from the dummy conductor patterns WG9 and WS9 of the dummy class circuit DSC9 in FIG. 9.

In summary, the motherboard of the present invention can cut out display panels of any size. In order to avoid damage to the film layer or elements in the display area during the cutting process of the display panel, a pre-cut area is reserved at the edge of the display panel. Since only dummy pixel units or dummy class circuits lacking specific materials (such as conductive materials) are provided in the pre-cutting area, the edge of the display panel produced by cutting will not be exposed with conductive material, which can avoid the display panel cutting process The short circuit problem of different film layers or components or the problem of corrosion after the cutting process is avoided, thereby ensuring the display quality.

In addition, in order to avoid signal interference caused by the dummy class circuit, the driving circuit is cut after the display panel cutting process to cut the class connection line. The class connecting line has sections with different widths, or the class connecting line can be disposed away from other components in the pre-cut section to improve the yield of the cutting process of the driving circuit. Furthermore, since the adhesive layer may be arranged at any position in response to the customization of the display panel, the adhesive layer may overlap with some standard class circuits or dummy class circuits, so the components in the standard class circuit and dummy class circuit It has a hollow structure to improve the light transmittance of the device and ensure the curing of the adhesive layer.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

10, 42, 43, 50, 60, 70, 90, 95: display panel 100, 190: substrate 110: display medium 120: Support structure 130: conductive layer 140: Adhesive layer 150: Flattening layer 160: color filter pattern 170: masking pattern layer 170S, 170D: shadow block 172S, 172D: opening 180, 182, 185: insulating layer 20: Motherboard 300: substrate material layer 301, 304: conductor material layer 302, 305: Photoresist layer 302H, 305Hs, 305Hd: the first unexposed area 302E1, 305E1a, 305E1b: first exposure area 302E2, 305E2: second exposure area 302P, 305P: patterned photoresist layer 303, 306: The first mask 303Q, 306Qs, 306Qd: mask pattern 410, 420, 430: external circuit 700: blackout strip 800a, 800b, 800c, 800d, 900, 1000: class connection line 810S, 810G, 810SM: active component cable 810Sn, 810Gn, 810SMn, EP1n, EP2n: opening 890, 990: component connecting line 8001, 10001: the first section 8002, 10002: the second section 10001a~10001c: branch AA: display area NAA: Non-display area DR, DR1, DR2: drive circuit area B, B1, B2: surrounding line area BD: junction area C, C1~C3: pre-cutting area SPC: Standard pixel unit DPC, DPC5, DPC6, DPC7: virtual pixel unit SSC, SSC9, SSC11: standard class circuit DSC, DSC11: dummy class circuit WTH1, WTH2, WW: width LL, LN1: length DIS1, DIS2: spacing E1, E2, E3: edge GI1, GI2, PV1: insulation block WGI1, WPV1: Insulated block G1, G2, S1, S2, D1, D2: conductor pattern WG1, WG2, WS1, WS2, WD2, WG9, WS9, WD9, WG11, WS11: quasi-conductor pattern WSM1: quasi-semiconductor pattern SM1, SM2, SM9: semiconductor pattern PE1: pixel electrode CR: Central District CS1~CS3: cutting surface L1, L2: exposure beam TFT8a, TFT8b, TFT9a, TFT11a: active components CT8: capacitor EP1, EP2: electrode plate WEP1, WEP2, WEP3, WEP4: pseudo-electrode plate XX: Clearance area W1, W2, W3, Ws, Wg, Wsm: line width CL1: cutting line ZM1~ZM3: area

FIG. 1A is a schematic top view of a display panel according to an embodiment of the invention. FIG. 1B and FIG. 1C are schematic cross-sectional views taken along the lines I-I' and II-II' of FIG. 1A, respectively. 2 is a schematic top view of a motherboard of a display panel according to an embodiment of the present invention. 3A to 3I are schematic cross-sectional views of a manufacturing process of a partial motherboard according to an embodiment of the invention. 4 is a schematic top view of a display panel cutting process of a motherboard according to an embodiment of the invention. 5 to 7 are schematic cross-sectional views of a display panel according to an embodiment of the invention. FIG. 8A is a partial schematic top view of the display panel 10 drawn in FIG. 1A of the present invention. 8B to 8D are schematic top views of the partial area of the display panel drawn in FIG. 8A of the present invention. 9 to 11 are schematic partial top views of a display panel according to an embodiment of the invention.

10: Display panel AA: display area NAA: Non-display area DR: drive circuit area B: surrounding line area C: Pre-cutting area SPC: Standard pixel unit DPC: virtual pixel unit SSC: Standard class circuit DSC: dummy class circuit WTH1: width DIS1, DIS2: spacing E1, E2, E3: edge

Claims (28)

A display panel includes: a substrate, wherein a plurality of first conductor patterns and a plurality of shielding blocks of a shielding pattern layer are arranged in an array on the substrate; a plurality of standard pixel units, each of the standard pixel units includes the A first conductor pattern in the first conductor patterns and a first mask block in the mask blocks, the first mask blocks overlapping the first conductor patterns respectively; and a plurality of dummy pictures Pixel unit, each of the dummy pixel units includes a second masking block among the masking blocks, the second masking blocks do not overlap with the first conductor patterns, wherein a first edge of the substrate The second edges of the dummy pixel units adjacent to a standard pixel unit among the standard pixel units are separated by a first pitch, and the first pitch is between 50 μm and 3000 μm. The display panel as described in item 1 of the patent application scope, wherein each of the standard pixel units further includes a second conductor pattern among the plurality of second conductor patterns, and the first shielding blocks and the second The conductor patterns overlap, the second shielding blocks do not overlap with the second conductor patterns, and each of the first conductor patterns and each of the second conductor patterns is a gate, a drain, or a source, respectively. The display panel as described in item 1 of the patent application scope, wherein each of the standard pixel units further includes a pixel electrode among the plurality of pixel electrodes, each of the first masking block and each of the second masking block It has a first opening and a second opening, the pixel electrodes respectively overlap the first openings of the first masking blocks, and the pixel electrodes do not overlap with the second masking blocks The second openings overlap. The display panel as described in item 1 of the patent application scope, wherein each of the standard pixel units further includes a semiconductor pattern among a plurality of semiconductor patterns, and the first shielding blocks respectively overlap the semiconductor patterns. The second masking block does not overlap with the semiconductor patterns. The display panel as described in item 1 of the patent application scope, wherein each of the standard pixel units further includes an insulating block among a plurality of insulating blocks in an insulating layer, and the first shielding blocks and the The insulating blocks overlap, and the second shielding blocks do not overlap with the insulating blocks. The display panel as described in item 1 of the patent application scope, wherein each of the standard pixel units further includes a first color filter pattern among a plurality of color filter patterns, and each of the dummy pixel units further includes the colors A second color filter pattern in the filter pattern, the first color filter patterns are respectively arranged corresponding to the first conductor patterns, and the second color filter patterns are not arranged corresponding to the first conductor patterns. The display panel as described in item 1 of the patent application scope further includes an adhesive layer which overlaps with some of the standard pixel units. The display panel as described in item 1 of the patent application scope, wherein the plurality of first standard pixel units in the standard pixel units are located in a display area, the dummy pixel units and the standard pixel units The plurality of second standard pixel units are located in a non-display area. The display panel as described in item 1 of the patent application scope further includes: a plurality of standard class circuits, each of which includes a third conductor pattern among a plurality of third conductor patterns, and the standard class circuits correspond to Standard pixel list Element setting; and at least one dummy class circuit, a dummy class circuit in the at least one dummy class circuit corresponds to a dummy pixel unit in the dummy pixel units, wherein the first of the substrate The edge is separated from a third-level circuit of the standard-level circuits by a second interval between a third edge of the at least one dummy-level circuit, and the second interval is between 50 μm and 3000 μm. The display panel as described in item 9 of the patent application scope further includes a plurality of class connecting lines, a first class connecting line located at the edge of the class connecting lines is electrically connected to one of the at least one dummy class circuit Between the dummy class circuit and a standard class circuit among the standard class circuits, a section of the first class connecting line is adjacently disposed in a clear area, and the clear area is disposed in one of the at least one dummy class circuit Between the dummy class circuit and a standard class circuit adjacent to the at least one dummy class circuit among the standard class circuits, each of the standard class circuits includes a plurality of active elements, the active elements vacate the clear area, the The length of the clearance area is between 50 microns and 150 microns, and the width of the clearance area is between 50 microns and 150 microns. The display panel as described in item 9 of the patent application scope further includes a plurality of class connecting lines, a second class connecting line among the class connecting lines is electrically connected to a dummy of the at least one dummy class circuit Between the class circuit and a standard class circuit among the standard class circuits, the second class connecting line has a first section and a second section, the first section is located in the at least one dummy class circuit Virtual order Between the class circuit and a standard class circuit adjacent to the at least one dummy class circuit among the standard class circuits, the line width of the first section is smaller than the line width of the second section. A driving circuit, comprising: a plurality of class circuits, each class circuit including a plurality of active elements; and a plurality of class connecting lines, a first class connecting line located at an edge among the class connecting lines is electrically connected to the classes Between two class circuits in the circuit, a section of the first class connecting line is adjacently arranged in a clear space region, the clear space region is located between two adjacent class circuits in the class circuits, and the active components are empty Out of the clearance area, the length of the clearance area is between 50 microns and 150 microns, and the width of the clearance area is between 50 microns and 150 microns. The driving circuit as described in item 12 of the patent application scope, wherein each of the class circuits further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate has a plurality of first openings, The second electrode plate has a plurality of second openings, and the first openings overlap with the second openings respectively, and the capacitor vacates the clearance area. The driving circuit as described in item 12 of the patent application scope, wherein each of the class circuits further includes a plurality of active element connecting wires, and the active element connecting wires are electrically connected between two active elements in parallel among the active elements To form a plurality of third openings, and the connection lines of the active elements vacate the clearance area. A driving circuit includes: a plurality of class circuits, each class circuit including a plurality of active components; and a plurality of class connecting lines, a first class connecting line among the class connecting lines Is connected between two class circuits in the class circuits, the first class connecting line has a first section and a second section, the first section is located in two adjacent ones of the class circuits Among the class circuits, the line width of the first section is smaller than the line width of the second section. The driving circuit as described in Item 15 of the patent application range, wherein the first section has a plurality of branches, and the line width of each branch is smaller than the line width of the second section. The driving circuit according to item 15 of the patent application scope, wherein each of the class circuits further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate has a plurality of first openings, The second electrode plate has a plurality of second openings, and the first openings respectively overlap the second openings. The driving circuit as described in item 15 of the patent application scope, wherein each of the class circuits further includes a plurality of active element connecting wires, and the active element connecting wires are electrically connected between two active elements in parallel among the active elements To form a plurality of third openings. A manufacturing method of a display panel includes: providing a substrate material layer; forming a plurality of standard pixel units and a plurality of dummy pixel units, wherein a plurality of first conductor patterns and a plurality of masking blocks of a masking pattern layer are formed on the The substrate material layer is arranged in an array, and each of the standard pixel units includes a first conductor pattern in the first conductor patterns and a first masking block in the masking blocks, and the first masking blocks Overlapping with the first conductor patterns respectively, each of the dummy pixel units includes a second masking block among the masking blocks, the second masking blocks are not in contact with the first conductors Patterns overlap; and cutting the substrate material layer along at least one cutting plane, wherein a cutting plane of the at least one cutting plane is adjacent to a standard pixel unit of the standard pixel units of the dummy pixel units A first edge is separated by a first pitch, and the first pitch is between 50 μm and 3000 μm. The method for manufacturing a display panel as described in Item 19 of the patent application range, wherein the steps of forming the standard pixel units and the dummy pixel units include: forming a first conductor material layer on the substrate material layer; forming A first photoresist material layer is formed on the first conductive material layer; a plurality of first unexposed areas and a plurality of first exposure areas are formed on the first photoresist material layer; on the first photoresist material layer Forming at least one second exposure area, wherein the at least one second exposure area partially overlaps the first unexposed areas or the first exposure areas, and the at least one cutting plane is located in the at least one second exposure area, The width of the at least one second exposure area is between 50 μm and 3500 μm; and the first conductive material layer is patterned according to the first exposure areas and the at least one second exposure area to form the first A conductor pattern, the shapes of the first conductor patterns are the same as the shapes of the first unexposed areas. The method for manufacturing a display panel as described in Item 19 of the patent application range, wherein each of the standard pixel units further includes a second conductor pattern among a plurality of second conductor patterns, and the first masking blocks are respectively The second conductor patterns overlap, and these first The two shielding blocks do not overlap with the second conductor patterns, and each of the first conductor patterns and each of the second conductor patterns is a gate, a drain, or a source, respectively. The method for manufacturing a display panel as described in Item 19 of the patent application range, wherein each of the standard pixel units further includes a pixel electrode among the plurality of pixel electrodes, each of the first masking block and each of the second masking area The block has a first opening and a second opening, respectively, the pixel electrodes overlap the first openings of the first shielding blocks, respectively, and the pixel electrodes do not overlap with those of the second shielding blocks The second openings overlap. The method for manufacturing a display panel as described in Item 19 of the patent application range, wherein each of the standard pixel units further includes a semiconductor pattern among a plurality of semiconductor patterns, and the first masking blocks respectively overlap the semiconductor patterns, The second shielding blocks do not overlap with the semiconductor patterns. The method for manufacturing a display panel as described in Item 19 of the patent application range, wherein each of the standard pixel units further includes an insulating block among a plurality of insulating blocks in an insulating layer, and the first shielding blocks are respectively The insulating blocks overlap, and the second shielding blocks do not overlap with the insulating blocks. The method for manufacturing a display panel as described in item 19 of the patent application scope further includes forming an adhesive layer, which overlaps with some of the standard pixel units. The method for manufacturing a display panel as described in Item 19 of the patent application scope, wherein when forming the standard pixel units and the dummy pixel units, a plurality of standard class circuits and at least one dummy class circuit are formed, each of which The standard class circuit includes a third conductor pattern among the plurality of third conductor patterns, the standard class circuits are arranged corresponding to the standard pixel units, and a dummy class in the at least one dummy class circuit The circuit corresponds to a dummy pixel unit in the dummy pixel units, a cutting plane in the at least one cutting plane is adjacent to a standard class circuit in the standard class circuits, and the at least one dummy class circuit A second edge of is separated by a second distance, and the second distance is between 50 microns and 3000 microns. The method for manufacturing a display panel as described in Item 26 of the patent application range, wherein a first class connecting line located at the edge among the plurality of class connecting lines is electrically connected to a dummy class circuit among the at least one dummy class circuit and Between a standard class circuit among the standard class circuits, a section of the first class connecting line is adjacently disposed in a clear space region, and the clear space region is disposed in a dummy class circuit in the at least one dummy class circuit and Among the standard class circuits, a standard class circuit adjacent to the at least one dummy class circuit, each of the standard class circuits includes a plurality of active elements, the active elements vacate the clear area, and the length of the clear area is between Between 50 microns and 150 microns, the clearance area has a width between 50 microns and 150 microns. The method for manufacturing a display panel as described in Item 26 of the patent application range, wherein a second-level connection line among the plurality of level-connection lines is electrically connected to a dummy-level circuit and the ones of the at least one dummy-level circuit Between a standard class circuit in a standard class circuit, the second class connecting line has a first section and a second section, the first section is located in a dummy class in the at least one dummy class circuit Between the circuit and a standard class circuit adjacent to the at least one dummy class circuit among the standard class circuits, the line width of the first section is smaller than the line width of the second section.

Images