TWI696269B - Memory and method of manufacturing integrated circuit - Google Patents

Abstract

An integrated circuit includes a three-dimensional cross-point memory having a plurality of levels of memory cells disposed in cross points of first access lines and second access lines with alternating wide and narrow regions. The manufacturing process of the three-dimensional cross-point memory includes patterning with three patterns: a first pattern to define the memory cells, a second pattern to define the first access lines, and a third pattern to define the second access lines.

Description

Method for manufacturing memory and integrated circuit

The technology described in this article is about an integrated circuit memory technology in a three-dimensional cross-point architecture and a method of manufacturing the device, including the use of programmable programs including phase change materials Resistive memory material technology.

Many three-dimensional (3D) cross-point memory technologies using phase change materials and other programmable resistance materials have been proposed. For example, Li et al. published "Evaluation of SiO ₂ Antifuse in a 3D-OTP Memory" in IEEE Transactions on Device and Materials Reliability Volume 4 Issue 3 in September 2004, describing polycrystalline silicon arranged like memory cells Diode and anti-fuse. Sasago et al. published in the 2009 Symposium on VLSI Technology Digest of Technical Papers ``Cross-Point Phase Change Memory with 4F ² Cell Size Driven by Low-Contact -Resistivity Poly-Si Diode" describes polycrystalline silicon diodes and phase change units arranged like memory cells. Kau et al. published in the 2009 International Electronic Components Conference (IEDM) 09-617, "A Stackable Cross Point Phase Change Memory" on pages 27.1.1~27.1.4, describing a memory post. This memory The body column includes a two-way ovonic threshold switch (OTS) with a phase change unit as an access device. Please also refer to "SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY" described in US Patent No. 6,579,760 on June 17, 2003, and the inventor is Lung.

In a 3D cross-point memory, multiple memory cells are vertically stacked up and down to increase the amount of storage in an area that can be used to store data. The memory cells are arranged at intersections of alternately arranged first access lines (for example, bit lines or word lines) and second access lines (for example, word lines or bit lines).

However, manufacturing difficulties have limited the achievements of 3D crosspoint memory. There are several critical lithography steps in each memory layer. Therefore, the number of key lithography steps required to manufacture this device is multiplied by the number of layers of memory cells, and is implemented in some methods. The execution of key lithography steps is expensive.

Since the demand for ever-increasing memory capacity in integrated circuit memories continues to rise, there is a need to provide a method for manufacturing a three-dimensional cross-point memory with low manufacturing costs and meeting data storage requirements.

One aspect of the technology includes a three-dimensional crosspoint memory having a plurality of first access lines extending in a first direction in a first access line layer and a second access A plurality of second access lines extending in a second direction in the line layer. The first access line and the second access line have alternating wide regions and narrow regions. The wide area in the plurality of second access lines in the second access line layer overlaps the wide area in the plurality of first access lines in the first access line layer overlapping the first access line and the second memory Take the intersection between the lines. An array of memory cells is arranged at the intersection between the first access line and the second access line. If necessary, there may be more layers of memory cell arrays. Each level of the memory cell array includes memory cells disposed at the intersection of the first access line extending in the first direction and the second access line extending in the second direction, where the intersection exists in the first memory Take the line and the second access line in a wide area. In some embodiments, the first access line includes a first conductive material, the second access line includes a second conductive material, and the first conductive material is different from the second conductive material. The memory cell includes a switching unit or a steering device such as a bidirectional fixed limit switch, which is connected in series to a programmable memory element including a phase change material.

Another aspect of the present technology is a method of manufacturing an integrated circuit including the three-dimensional cross-point memory as described above. The method includes forming a first stack of materials, including a layer of a first conductive material and a material layer of a programmable memory cell (layer of materials) and the material layer of the second conductive material. The plurality of first holes are etched through the first stack according to a first pattern. The material layer of the programmable memory cell is laterally etched through the first hole to form a memory cell array. A first insulating fill is then formed in the first hole. A plurality of second holes defined by a second pattern are etched through the first stack. The layer of the first conductive material is laterally etched through the second hole to form a plurality of first access lines. A second insulation filling system is formed in the second hole. Next, the third hole defined by a third pattern is etched through the first stack. The layer of the second conductive material is laterally etched through the third hole to form a plurality of second access lines.

In some embodiments, the first pattern, the second pattern, and the third pattern include an array of holes, and the holes have a length in the first direction and a width in the second direction. The width of the holes in the second pattern is shorter than the width of the holes in the first pattern. In some embodiments, the length of the holes in the third pattern is shorter than the length of the holes in the first pattern. The holes in the second pattern and the third pattern may be oval or oval-like, and the oval-like shape has a long axis and a short axis to a certain extent (including rectangles and other oblong polygons). The long axis of the hole in the second pattern is aligned with the direction of the first access line, and the side of the first access line is defined by the etching circumference of the lateral etching of the first conductive material. The long axis of the hole in the third pattern is aligned with the direction of the second access line, and the side surface of the second access line is defined by the etching circumference of the lateral etching of the second conductive material. The holes in the first pattern may be circular or have other shapes (including squares and other polygons), which have lengths and widths that are nearly equal in the first direction and the second direction.

In some embodiments, three lithography steps may be used to fabricate the three-dimensional cross-point memory described herein: a first lithography step, which defines multiple holes to use the first pattern in multiple layers in the three-dimensional cross-point memory The memory cell is formed by lateral etching; a second lithography step defines a plurality of holes to use the second pattern to form the first access line by lateral etching; and a third lithography step , Multiple holes are defined to form the second access line by lateral etching using the third pattern. As the number of memory cell layers in the three-dimensional cross-point memory increases, the number of lithography steps remains the same. By reducing the number of lithography steps, the average manufacturing cost of each memory cell layer can be reduced.

Other features, aspects, and advantages of the technology described herein can be understood with reference to the following drawings, detailed description, and patent application scope.

100: 3D crosspoint memory

101, 102, 103, 104, 105, 106: first access line

111, 112, 113, 114, 115, 116: second access line

117, 119, 122: wide area

118, 120: narrow area

121: Memory Cell

131: Second access line decoder

133: The first access line decoder

208: programmable memory unit

210: barrier layer

212: Switch unit

300: first stack

302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326: layer

402, 404, 406, 408, 410, 412, 414, 416, 418: first hole 420: length

422: Width

424: first hole pattern

502, 504, 506, 508, 510, 512, 514, 516, 518: holes

600: first memory cell class

602, 604, 606, 608: memory cells

720: First insulation filling

802, 804, 806, 808, 810, 812, 814, 816, 818: second hole

820: Length

822: width

824: Second hole pattern

900: first access line layer

902, 906, 911: narrow area

904, 908: wide area

910, 912: first access line

1020: Second insulation filling

1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118: third hole

1120: Length

1122: Width

1124: Third hole pattern

1200: second access line layer

1202, 1206, 1211: narrow area

1204, 1208: wide area

1210, 1212: second access line

1310: Surface

1410: Dielectric pad

1500: stacked

1501, 1502, 1503: memory cell

1511, 1513: the first access line

1512, 1514: second access line

1521, 1531, 1541: programmable memory unit

1522, 1532, 1542: barrier layer

1523, 1533, 1543: switch unit

1602: The first memory cell class

1604: Second memory cell class

1606: Third memory cell class

1702, 1706: the first access line layer

1704, 1708: wide area

1802, 1806: second access line layer

1804, 1808: wide area

1901~1909: steps

2000: 3D crosspoint memory array

2001: plane and column decoder

2002: character line

2003: Line decoder

2004: bit line

2005, 2007: busbar

2006: square

2008: Supply voltage for bias arrangement

2009: control circuit

2011: data input line

2015: data output line

2050: Integrated circuit

FIG. 1 illustrates a three-dimensional cross-point memory having a first access line and a second access line. The first access line and the second access line have alternating wide areas and narrow areas.

Figure 2 shows an example of a memory cell.

FIGS. 3-14 illustrate stages of a manufacturing process example for manufacturing a three-dimensional cross-point memory having a first access line and a second access line. The first access line and the second access line have alternating wide areas and Narrow area.

FIG. 15 shows an X-Z cross-sectional view of a three-dimensional cross-point memory manufactured using a manufacturing example.

Figures 16-18 show the X-Y layout of the three-dimensional crosspoint memory in Figure 15.

FIG. 19 is a flowchart showing a method of manufacturing a memory having a three-dimensional cross-point memory. The three-dimensional cross-point memory has a first access line and a second access line, and the first access line and the second access The line has alternating wide areas and narrow areas.

FIG. 20 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention.

Detailed descriptions of embodiments of the present invention are provided with reference to FIGS. 1-20.

FIG. 1 shows a three-dimensional cross-point memory 100 having a first access line and a second access line. The first access line and the second access line have alternating wide and narrow areas. regions). The three-dimensional cross-point memory 100 includes a plurality of memory cells, including memory cells 121. The plurality of memory cells are arranged at the intersection of the plurality of first access lines 101, 102, 103, 104, 105, and 106 and the plurality of second access lines 111, 112, 113, 114, 115, and 116. The first The access lines 101, 102, 103, 104, 105, and 106 extend in a first direction (that is, the column direction or the Y direction in FIG. 1), and the second access lines 111, 112, 113, 114, 115, and 116 extends in a second direction (ie, the row direction or the X direction in FIG. 1). The first access line and the second access line have alternating wide areas and narrow areas. For example, the second access line 116 has a wide area 117, a narrow area 118, a wide area 119, a narrow area 120, and a wide area 122 in this order. The first direction and the second direction are orthogonal directions or non-parallel directions, so that an array of cross points is formed between the overlapping wide areas of the first access line and the second access line. Each memory cell is connected to a wide area of a specific first access line and a wide area of a specific second access line. For example, memory The cell 121 is connected to a wide area of the first access line 101 and a wide area of the second access line 111.

The three-dimensional cross-point memory implemented in the configuration of FIG. 1 may have multiple levels of memory cells and multiple first access lines and multiple second access lines in each level to perform The formation of ultra-high density memory. A three-dimensional cross-point memory with multiple levels of memory cells has a plurality of first access line layers and a plurality of second access line layers, the second access line layer and the first access line The layers are staggered. Each first access line layer includes a plurality of first access lines, and each second access line layer includes a plurality of second access lines. The three-dimensional cross-point memory in FIG. 1 includes three memory cell levels, two first access line layers and two second access line layers. The successive memory cell layers share a first access line layer or a second access line layer. The first memory cell hierarchy in the three-dimensional crosspoint memory is inserted in a first access line layer including the first access lines 101, 102 and 103 and a second access line including the second access lines 111, 112 and 113 Between access line layers. The second memory cell hierarchy in the three-dimensional crosspoint memory is inserted between a second access line layer including second access lines 111, 112 and 113 and a first access line including first access lines 104, 105 and 106 Between access line layers. The third memory cell hierarchy in the three-dimensional crosspoint memory is inserted between a first access line layer including first access lines 104, 105, and 106 and a second access line including second access lines 114, 115, and 116. Between access line layers. Other three-dimensional configurations can be realized.

The first access lines 101, 102, 103, 104, 105, and 106 include a first conductive material, and the second access lines 111, 112, 113, 114, 115, and 116 include a second conductive material. The first conductive material and the second conductive material may include various metals, metalloid materials, doped semiconductor access lines or groups thereof Together. Examples of the first conductive material and the second conductive material include tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (tungsten nitride, WN), doped polysilicon (doped polysilicon), cobalt silicide (CoSi), tungsten silicide (WSi), titanium nitride/tungsten/silicon nitride (TiN/W/TiN) and other materials.

In some embodiments, the first conductive material is different from the second conductive material to support a lateral etch process, and the first conductive material and the second conductive material are selectable between the materials. For example, in an embodiment of the three-dimensional cross-point memory of FIG. 1, the first conductive material in the first access line may be tungsten, and the second conductive material in the second access line may be copper. In another exemplary embodiment, the first conductive material in the first access line may be titanium nitride, and the second conductive material in the second access line may be tungsten nitride.

The three-dimensional cross-point array includes access lines that are coupled and electrically communicated with a first access line decoder 133 and a second access line decoder 131, wherein the first access line decoder The second access line decoder may include a driver and a bias voltage selector (bias voltage selector) to apply a bias to the selected first access line and second access line during a write operation or a read operation, Unselected first access line and second access line. In this embodiment, a plurality of first access lines are coupled to a first access line decoder 133, and a plurality of second access lines are coupled to a second access line decoder 131. The sense amplifier (not shown in FIG. 1) can be connected to the first access line or the second access line. In the embodiment of the technology described herein, the sense amplifier is coupled to one of the first access line and the second access line, for example, a current mirror based load circuit Electricity The current source circuit is connected to limit the current during the read operation and the write operation.

FIG. 2 is a close-up view of the example memory cell 121 of FIG. 1. The memory cell 121 has a programmable memory unit 208 that contacts the first access line 101 and a switch unit 212 that contacts the second access line 111. A barrier layer 210 is disposed between the programmable memory unit 208 and the switch unit 212. In the three-dimensional cross-point memory of FIG. 1A, the memory cell is inverted so that the programmable memory unit can contact or be adjacent to a first access line, and the switch unit can be contacted or adjacent to a second access line. In some embodiments, each level may have its own access line layer of the first access line and the second access line. In some embodiments, the memory cell is not inverted so that the switch unit can contact the first access line or the second access line.

The programmable memory cell 208 may include a layer of programmable resistance material. The programmable resistance material may have a first resistance value representing bit "0" and a second resistance value representing bit "1". In some embodiments, more than two resistance values can be used to store multiple bits per cell. In one embodiment, the programmable memory cell 208 includes a layer of phase change memory material used as a programmable resistive material.

Through the application of energy, such as heat or current, the phase change material can be switched between a relatively high resistance state, an amorphous phase, a relatively low resistance state and a crystalline phase. The phase change material of the programmable memory cell 208 may include chalcogenide-based materials and other materials. Chalcogenide alloys include combinations of chalcogenide compounds with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IVA of the periodic table, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include one or more antimony (Sb), gallium (Ga), indium (In), and silver (Ag) combinations. Many phase change based memory materials have been described in the technical literature, including alloys: gallium/antimony (Ga/Sb), indium/antimony (In/Sb), indium/selenium (In/ Se), antimony/tellurium (Sb/Te), germanium/tellurium (Ge/Te), germanium/antimony/tellurium (Ge/Sb/Te), indium/antimony/tellurium (In/Sb/Te), gallium/selenium / Tellurium (Ga/Se/Te), Tin/Antimony/Tellurium (Sn/Sb/Te), Indium/Antimony/Germanium (In/Sb/Ge), Silver/Indium/Antimony/Tellurium (Ag/In/Sb/ Te), germanium/tin/antimony/tellurium (Ge/Sn/Sb/Te), germanium/antimony/selenium/tellurium (Ge/Sb/Se/Te) and tellurium/germanium/antimony/sulfur (Te/Ge/Sb /S). In the family of germanium/antimony/tellurium (Ge/Sb/Te) alloys, various alloy compositions can be used. This composition may be, for example, Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ and GeSb ₄ Te ₇ . More generally, for example, one of chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), transition metal and its mixture or alloy can be combined with germanium/antimony / Tellurium (Ge/Sb/Te) or Gallium/Antimony/Tellurium (Ga/Sb/Te) combined to form a phase change alloy with programmable resistive properties. Specific examples of memory materials are disclosed in US Patent No. 5,687,112, columns 11 to 13, and the inventor is Ovshinsky. The examples can be incorporated by reference into the entire text of this document. Various phase change memory systems are disclosed in US Patent No. 6,579,760, titled "SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY". The contents of this patent case can be incorporated into this article by reference.

In one embodiment, the programmable memory unit 208 may be a resistive random access memory (resistive random access memory) or a ferroelectric random access Memory (ferroelectric random access memory). The programmable resistance material in the programmable memory cell 208 may be a metal oxide, such as hafnium oxide, magnesium oxide, nickel oxide, niobium oxide, and oxide Titanium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide or cobalt oxide. In some embodiments, other resistive memory structures may be implemented, such as metal-oxide resistive memories, magnetic resistive memories, and conductive bridge resistive memories ( conducting-bridge resistive memories) etc.

In some embodiments, the switch unit 212 may be an ovonic threshold switch (OTS) that includes a chalcogenide material. In an embodiment including a bidirectional limit switch, a read operation includes applying a voltage across the first access line and the second access line, which exceeds a threshold of the bidirectional limit switch. In other embodiments, the switch unit may include other types of devices, including directional devices, such as a diode and other bi-directional devices.

In an example, an OTS switch element may include a layer of chalcogenide used as a bidirectional fixed switch, such as arsenic selenide (As ₂ Se ₃ ), telluride Zinc (ZnTe) and germanium selenide (GeSe). The bidirectional fixed limit switch switching unit has a thickness of, for example, about 5 nm to about 25 nm. In some embodiments, the switching unit may include a chalcogenide compound consisting of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S) and One or more elements of the group consisting of antimony (Sb).

The barrier layer 210 includes a material or a combination of multiple materials in order to switch Suitable adhesion is provided between the cell 212 and the programmable memory unit 208. The barrier layer 210 blocks the movement of impurities from the programmable memory cell to the switch cell, and vice versa. The barrier layer may be composed of a conductive material or a semiconductor material having a thickness of about 3 nanometers to about 30 nanometers. Suitable materials for the barrier layer 210 may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (molybdenum) nitride, MoN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN). In addition to metal nitrides, for example, titanium carbide (titanium carbide, TiC), tungsten carbide (WC), graphite (C), other carbon (C) forms, titanium (Ti), molybdenum (Mo), tantalum (Ta ), conductive materials such as titanium silicide (TiSi), tantalum silicide (TaSi) and titanium tungsten (TiW) can be used for the barrier layer 210.

Figures 3 to 14 show an example of a manufacturing process of a three-dimensional cross-point memory having a first access line and a second access line. The first access line and the second access line have similarities as in Figure 1. Alternating wide and narrow areas. The manufacturing process includes three patterns: a first pattern defining memory cells; a second pattern defining first access lines; and a third pattern defining second access lines. The first pattern includes an array of holes having a length in the first direction and a width in the second direction. The holes in the first pattern may have a circular, square, rectangular, elliptical, polygonal, etc. shape. The holes in the first pattern may be circular, or other shapes (including squares and other polygons) having nearly equal lengths and widths in the first direction and the second direction.

Similar to the first pattern, the second pattern and the third pattern include an array of holes, The holes have a length in the first direction and a width in the second direction. The holes in the second pattern and the third pattern may be oval or oval-like, and the oval-like shape has a long axis and a short axis to a certain extent (including rectangles and other rectangular polygons). The long axis of the hole in the second pattern is aligned with the direction of the first access line, and the side of the first access line is defined by the etching circumference of the lateral etching of the first conductive material. The long axis of the hole in the third pattern is aligned with the direction of the second access line, and the side surface of the second access line is defined by the etching circumference of the lateral etching of the second conductive material. In some embodiments, the width of the holes in the second pattern may be shorter than the width of the holes in the first pattern, and the length of the third pattern may be shorter than the length of the first pattern. In these embodiments, the length of the second pattern may be the same as the length of the first pattern, and the width of the third pattern may be the same as the width of the first pattern. In other embodiments, the length of the second pattern may be shorter than the length of the first pattern, and the width of the third pattern is shorter than the width of the first pattern. In these embodiments, the width of the second pattern may be the same as the width of the first pattern, and the length of the second pattern may be the same as the length of the first pattern. FIG. 3 illustrates a stage in the process after forming a first stack 300 with material layers 302-326. The first stack 300 may be formed on an integrated circuit substrate or other type of insulating base. In some embodiments, there may be circuits below the first stack 300. The process of forming the first stack 300 includes depositing a first layer 302 of first conductive material, a first material layer 304 of the programmable memory cell, a first material layer 306 of the barrier layer, and a first layer of the switching unit A material layer 308, a first layer 310 of a second conductive material, a second material layer 312 of the switch unit, a second material layer 314 of the barrier layer, a second material layer of the programmable memory unit 316, a second layer 318 of the first conductive material, a third material layer 320 of the programmable memory cell, A third material layer 322 of the barrier layer, a third material layer 324 of the switch unit, and a second layer 326 of the second conductive material. A 3D cross-point memory cell device with three layers of memory cells can be formed by the first stack 300.

The first conductive material and the second conductive material in the layers 302, 310, 318, and 326 may include a multilayer combination of titanium nitride, tungsten, and titanium nitride as described above. The first conductive material is a phase Different from the second conductive material. Other material combinations can be used. For the first conductive material and the second conductive material, for example, one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (atomic layer deposition) can be used. deposition, ALD) process.

The materials of the switch units in the layers 308, 312, and 324 may include materials of an ovonic threshold switch element, such as the materials mentioned above. In an embodiment where the programmable memory cell includes a phase change material, the material layers 308, 312, and 324 of the switch unit can be formed by physical vapor deposition (PVD), sputtering, or a magnetron sputtering method ( magnetron-sputtering method), for example, magnetron sputtering method is to use argon (Ar), nitrogen (N ₂ ) and/or helium (He) under a pressure of 1 mtorr (mTorr) ~ 100 mtorr Source gas. Alternatively, this layer can also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).

The materials of the barrier layers in the layers 306, 314, and 322 can be selected to include various barrier materials according to programmable resistance memory elements. For a phase change memory unit (phase change memory element), a suitable barrier material may be titanium nitride. Alternate embodiments may include carbon varieties, including carbon nanotubes and graphite. In addition, materials such as silicon carbide and other conductive barrier materials can be used. Such materials for the barrier layer can be, for example, one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) Process for deposition.

The materials of the programmable memory cells in layers 304, 316, and 320 may include various phase change materials. Examples of phase change materials include chalcogenide-based materials, such as gallium/antimony (Ga/Sb), indium/antimony (In/Sb), indium/selenium (In/Se), antimony/tellurium (Sb/Te), Germanium/Tellurium (Ge/Te), Germanium/Antimony/Tellurium (Ge/Sb/Te), Indium/Antimony/Tellurium (In/Sb/Te), Gallium/Selenium/Tellurium (Ga/Se/Te), Tin/ Antimony/Tellurium (Sn/Sb/Te), Indium/Antimony/Germanium (In/Sb/Ge), Silver/Indium/Antimony/Tellurium (Ag/In/Sb/Te), Germanium/Tin/Antimony/Tellurium (Ge /Sn/Sb/Te), germanium/antimony/selenium/tellurium (Ge/Sb/Se/Te) and tellurium/germanium/antimony/sulfur (Te/Ge/Sb/S) alloys. These materials of the programmable memory cell can use, for example, one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD) and atomic layer deposition (atomic layer deposition) , ALD) process for deposition.

FIG. 4A illustrates a manufacturing stage after patterning the first stack 300 to define an array of holes through the stack to the substrate in this embodiment. The hole array includes a plurality of first holes 402, 404, 406, 408, 410, 412, 414, 416, and 418. FIGS. 4B, 4C, and 4D respectively show X-Y layouts of the first layer 302 of the first conductive material, the first material layer 304 of the programmable memory cell, and the first layer 310 of a second conductive material. As shown in FIG. 4B, the hole array uses a first hole pattern (hole pattern) 424 to define a plurality of first holes 402, 404, 406, 408, 410, 412, 414, 416 and 418. The first hole pattern shown in FIG. 4B is a circle. However, other hole patterns such as square or polygonal shapes can also be used. The first pattern has a length 420 in the first direction and a width 422 in the second direction. The first pattern defines a first hole having a length 420 in the first direction and a width 422 in the second direction. In this embodiment, the length 420 in the first direction is approximately equal to the width 422 in the second direction. A lithography process of depositing a photoresist on the first stack can expose a first pattern in the photoresist to remove the exposed photoresist area and the etching is not affected by the photoresist The protected area, and the photoresist is removed after etching to achieve patterning of the plurality of first holes.

During the process of lateral etching through the plurality of first holes (before completion), FIGS. 5A, 5B, and 5C show the first layer 302 of the first conductive material and the programmable memory cell, respectively. The XY layout of the first material layer 304 and a first layer 310 of a second conductive material. This lateral etching selects the first material layer 304 for the programmable memory cell, the second material layer 316 not for the programmable memory cell, and the third material not for the programmable memory cell层320。 Layer 320. The selective etching process does not etch (at least not substantially) the layer of the first conductive material or the layer of the second conductive material. As shown in FIG. 5, compared to the first holes 402, 404, 406, 408, 410, 412, 414, 416, and 418, this etching process is generated in the first material layer 304 of the programmable memory cell Larger holes 502, 504, 506, 508, 510, 512, 514, 516 and 518. A reactive-ion etching process can be used to etch the material layer of the programmable memory cell.

Barrier layer first material layer 306, switch unit first material layer 308, switch unit second material layer 312, barrier layer second material layer 314, barrier layer third material layer 322, switch unit The third material layer 324 and the material layers 304, 316, and 320 of the programmable memory cell are also laterally etched. In some embodiments, the material layer of the programmable memory cell, the material layer of the barrier layer, and the material layer of the switch unit are etched at the same rate. In some embodiments, the material layer of the programmable memory cell, the material layer of the barrier layer, and the material layer of the switch unit are etched at different rates, for example, by using multiple etch chemistries for lateral Etching is used to modify this process. This lateral etching selects the material for the programmable memory cell to ensure that the memory cell has a more or less even side surface.

After the selective lateral etching of the plurality of first holes through the first material layer 304 of the programmable memory cell is completed, the second material layer 316 of the programmable memory cell is not removed, And the third material layer 320 of the non-removable programmable memory cell, FIGS. 6A, 6B, and 6C respectively show the first layer 302 of the first conductive material, the first memory cell layer 600, and a second conductive material. The XY layout of the first layer 310. Once the lateral etching in this stage is completed, the memory cell pillars separated from each other leave the perimeter of the lateral etching. The memory cell column provides a first memory cell hierarchy 600 including memory cells 602, 604, 606, and 608, which is formed by an etching process. Similarly, a second memory cell hierarchy and a third memory cell hierarchy are formed on the second material layer 316 of the programmable memory cell and the third material layer 320 of the programmable memory cell, respectively.

Forming a first insulating fill 720 in the first hole and surrounding the memory cell After the surrounding etched region (etched region), FIGS. 7A, 7B, and 7C respectively show the XY of the first layer 302 of the first conductive material, the first memory cell layer 600, and the first layer 310 of a second conductive material. layout. The insulating fill can be formed by the deposition of silicon oxide or other insulating filling materials suitable for the cross-point structure. Other low-k dielectrics can also be used. The formation of the first insulating fill can be performed by, for example, a spin-on process, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition ( LPCVD) and high density plasma chemical vapor deposition (HDPCVD).

FIGS. 8A, 8B, and 8C illustrate a manufacturing stage after patterning to form a second hole array, the second hole array includes a plurality of second holes 802, 804, 806 aligned with the first hole array , 808, 810, 812, 814, 816 and 818. 8A, 8B, and 8C respectively show the X-Y layout of the first layer 302 of the first conductive material, the first memory cell layer 600, and the first layer 310 of a second conductive material. As shown in FIG. 8A, the second hole array may use a second hole pattern 824 to define a plurality of second holes 802, 804, 806, 808, 810, 812 having an elliptical or oblong shape 814, 816 and 818. The second hole pattern 824 has a length 820 (long axis) in the first direction and a width 822 (short axis) in the second direction. The length 820 is approximately equal to the length and width of the first hole pattern 424 822 is shorter than the width of the first hole pattern 424. The length 820 of the second hole pattern 824 is longer than the width 822 of the second hole pattern 824. The second pattern defines a second hole having a length 820 (long axis) in the first direction and a width 822 (short axis) in the second direction, the length of the second hole being longer than the width of the second hole. The patterning of the plurality of second holes can be completed by a lithography process. As shown in Figure 8B, The second hole is patterned between multiple memory cells.

9A, 9B, and 9C illustrate the selective lateral etching of the layer 302 of the first conductive material passing through the second holes 802, 804, 806, 808, 810, 812, 814, 816, and 818 to form a plurality of first A manufacturing stage after an access line (eg, the first access line 910, 912). 9A, 9B, and 9C illustrate an XY layout of a first access line layer 900, a first memory cell layer 600, and a first layer 310 of a second conductive material. The first access line layer 900 includes A first conductive material layer 302 of an access line is formed. The side surface of the first access line is defined by the perimeter of the selective lateral etching. Since the second conductive material and the material in the memory cell are different from the first conductive material, the selective etching process does not etch the memory cell or the layer of the second conductive material. A reactive ion etching process can be used to etch the material layer 302 of the first conductive material.

As shown in FIG. 9A, when the etching process is performed through the second hole and the length of the second hole in the first direction is longer than the width in the second direction, due to this etching process, it has alternating wide areas and narrow A plurality of first access lines of the area are formed. For example, the first access line layer 900 includes first access lines 910 and 912. The first access line 910 has a narrow area 902, a wide area 904, a narrow area 906, a wide area 908, and a narrow area 911 in sequence.

10A, 10B and 10C illustrate a manufacturing stage after forming a second insulating fill 1020 in the second hole. After forming the second insulating fill 1020 in the second hole and the etched area around the first access line, FIGS. 10A, 10B, and 10C show the first access line layer 900, the first memory cell layer 600, and XY layout of a first layer 310 of a second conductive material. Can be made of silicon oxide or other suitable for cross-point structure The deposition of the insulating filler material forms the second insulating filler. Other low-k dielectrics can also be used. The formation of the second insulating filling can be performed by, for example, a spin-on process, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition ( LPCVD) and high density plasma chemical vapor deposition (HDPCVD).

FIGS. 11A, 11B, and 11C illustrate a manufacturing stage after patterning a third hole array aligned with the first hole array. The third hole array includes a plurality of third holes 1102, 1104, 1106, 1108, 1110 , 1112, 1114, 1116, 1118. FIGS. 11A, 11B, and 11C respectively show X-Y layouts of the first access line layer 900, the first memory cell layer 600, and a first layer 310 of a second conductive material. As shown in FIG. 11A, a third hole pattern 1124 can be used to define a plurality of third holes 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118. The third hole pattern 1124 has a length 1120 (short axis) in the first direction and a width 1122 (long axis) in the second direction. The length 1120 is shorter than the length of the first hole pattern, and the width 1122 is It is approximately equal to the width of the first hole pattern 424. The length 1120 of the third hole pattern 1124 is shorter than the width 1122 of the third hole pattern 1124. The third hole pattern defines a third hole having a length 1120 in the first direction and a width 1122 in the second direction. The length of the second hole (that is, the short axis of the length dimension) is shorter than The width of the second hole (that is, the long axis of the width dimension). The patterning of the plurality of third holes can be achieved by a lithography process. As shown in FIG. 11B, the third hole is patterned between multiple memory cells.

Figures 12A, 12B and 12C show the passing through the third holes 1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118. Selective lateral etching of the second conductive material to form a plurality of second access lines including a plurality of second access lines. The sides of the two access lines are defined by the perimeter of selective lateral etching. FIGS. 12A, 12B, and 12C illustrate an XY layout of a first access line layer 900, a first memory cell layer 600, and a second access line layer 1200. The second access line layer 1200 is made of a second conductive material The first layer 310 is formed. Since the first conductive material and the material in the memory cell are different from the second conductive material, the selective etching process does not etch the memory cell or the first access line. A reactive ion etching process can be used to etch the layer of the second conductive material.

As shown in FIG. 12C, when the etching process is performed by a third array of holes and the length of these holes in the first direction is shorter than the width in the second direction, due to this etching process, it has alternating widths A plurality of second access lines of the area and the narrow area are formed. For example, the second access line layer 1200 includes second access lines 1210 and 1212. The second access line 1210 has a narrow area 1202, a wide area 1204, a narrow area 1206, a wide area 1208, and a narrow area 1211 in sequence.

13A, 13B, and 13C illustrate a manufacturing stage after removing the first insulating filling and the second insulating filling by an etching process. 13A, 13B, and 13C illustrate the X-Y layout of the first access line layer 900, the first memory cell layer 600, and the second access line layer 1200. This removal process exposes multiple surfaces 1310 of the memory cell, the first access line, and the second access line.

After a dielectric material is used to line the exposed surface 1310 to form a dielectric liner 1410, FIGS. 14A, 14B, and 14C illustrate the first access line layer 900, the first An XY layout of a memory cell hierarchy 600 and a second access line layer 1200. The dielectric liner 1410 may include a dielectric material having, for example, a dielectric substance, such as SiO _x , SiN _x , aluminum oxide (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ) , Lanthanum oxide (La ₂ O ₃ ), AlSiO, HfSiO, and ZrSiO, etc., among which are high dielectric constant (high-κ) dielectrics such as SiN _x and hafnium dioxide (HfO ₂ ) in some embodiments It is better. The high dielectric constant dielectric substance has a dielectric constant higher than that of silicon dioxide (SiO ₂ ). In some embodiments, the thickness of the high dielectric constant dielectric liner may be in the range of 0.1 nm to 20 nm. In some embodiments, the thickness in the range of 1 nm to 3 nm is preferred. A dielectric liner can be deposited using highly conforming chemical vapor deposition or atomic layer deposition. Multiple voids may be formed between multiple memory cells in the structure between multiple access lines.

In some embodiments, a layer of dielectric material may be deposited on top of the three-dimensional cross-point memory to protect the memory during subsequent fabrication steps, such as a back end process of line, BEOL) manufacturing steps. In some embodiments, the dielectric pads on top of the top access line layer may be incorporated to form a dielectric layer on top of the three-dimensional cross-point memory.

In some embodiments, after a dielectric material is used to line the exposed surface to form a dielectric liner, a non-high dielectric constant dielectric material may be used to fill multiple voids. An air gap can be formed inside the dielectric material between multiple memory pillars.

In some embodiments, the selection of the second conductive material through the third hole After the lateral etching, a high dielectric constant dielectric material can be used to fill the voids and third holes generated during the lateral etching process.

Figure 15 shows an X-Z cross-sectional view of a stack of memory cells in a three-dimensional cross-point memory. This memory cell stack is manufactured using the manufacturing process examples described in Figures 3-14. For example, a "stack" of memory cells in a 3D cross-point memory array of a stack of 1500 M layers includes M number of memory cells stacked directly on top of each other. The stack 1500 includes memory cells 1501 at the first level and memory cells 1502 at the second level and memory cells 1503 at the third level stacked on top of each other. The memory cell 1501 includes a programmable memory unit 1521, a barrier layer 1522, and a switching unit 1523. The memory cell 1502 of FIG. 15 includes a programmable memory unit 1531, a barrier layer 1532, and a switch unit 1533. The memory cell 1503 in FIG. 15 includes a programmable memory unit 1541, a barrier layer 1542, and a switching unit 1543.

16A, 16B, and 16C show X-Y layouts of the first memory cell hierarchy 1602, the second memory cell hierarchy 1604, and the third memory cell hierarchy 1606 of the memory cell stack 1500 of FIG. 15 respectively. The first memory cell hierarchy 1602 in FIG. 16A includes memory cells 1501 from FIG. 15. The second memory cell hierarchy 1604 of FIG. 16B includes memory cells 1502 from FIG. 15. The third memory cell hierarchy 1606 in FIG. 16C includes the memory cell 1503 from FIG. 15. For clarity, the X-Y layout of the programmable memory cells with only memory cells is shown in Figures 16A, 16B, and 16C.

Please refer to FIG. 15, memory cells 1501, 1502, 1503 are located in two first access line layers (the first access line layer 1702 in FIG. 17A and the first memory in FIG. 17B Line crossing layer 1706) and two second access line layers (second access line layer 1802 in FIG. 18A and second access line layer 1806 in FIG. 18B). The memory cell 1501 at the first level is inserted in the wide area of the first access line 1511 (the wide area 1704 in FIG. 17A) of the first access line layer 1702 in FIG. 17A and the second access in FIG. 18A Between the wide areas of the second access lines 1512 (the wide area 1804 in FIG. 18A) of the line layer 1802. The memory cell 1502 at the second level is inserted in the wide area of the second access line 1512 (the wide area 1804 in FIG. 18A) of the second access line layer 1802 in FIG. 18A and the first access in FIG. 17B Between the wide area of the first access line 1513 (the wide area 1708 in FIG. 17B) of the line layer 1706. The memory cell 1503 at the third level is inserted in the wide area of the first access line 1513 (the wide area 1708 in FIG. 17B) of the first access line layer 1706 in FIG. 17B and the second access in FIG. 18B Between the wide areas of the second access lines 1514 (the wide area 1808 in FIG. 18B) of the line layer 1806.

FIG. 19 is a flowchart showing a method of manufacturing a three-dimensional cross-point memory having a first access line and a second access line. The first access line and the second access line have alternating wide areas and Narrow area. The method includes forming a first material stack in step 1901, including a layer of a first conductive material, a material layer of a programmable memory cell, a material layer of a barrier layer, a material layer of a switching unit, and a second conductive material Material layer (for example, the first stack 300 in FIG. 3). In step 1902, a first hole array including a plurality of first holes (eg, first holes 402, 404, 406, 408, 410, 412, 414, 416, 418 in FIG. 4A) is based on a first hole pattern (Eg, the first hole pattern 424 in FIG. 4B) is etched through the first stack. In step 1903, the material layer of the programmable memory cell, the material layer of the barrier layer, and the material layer of the switch unit are selectively laterally etched through The first hole forms an array of memory cells (e.g., memory cells 602, 604, 606, 608 in FIG. 6B). In step 1904, a first insulating fill (eg, the first insulating fill 720 of FIG. 7A) is formed in the first hole. In step 1905, a plurality of second holes (eg, second holes 802, 804, 806, 808, 810 defined in FIG. 8A) defined by a second hole pattern (eg, second hole pattern 824 in FIG. 8A) are defined , 812, 814, 816, 818) a second hole array is etched through the first stack. In step 1906, the layer of the first conductive material is selectively etched laterally through the second hole to form a plurality of first access lines (such as the first access lines 910 and 912 in FIG. 9A). In step 1907, a second insulating filler (for example, the second insulating filler 1020 in FIG. 10A) is formed in the second hole. In step 1908, a plurality of third holes (such as the third holes 1102, 1104, 1106, 1108, 1110 defined in FIG. 11A) defined by a third hole pattern (such as the third hole pattern 1124 in FIG. 11A) , 1112, 1114, 1116, 1118) a third hole array is etched through the first stack. In step 1909, the layer of the second conductive material is selectively laterally etched through the third hole to form a plurality of second access lines (eg, second access lines 1210, 1212 in FIG. 12C).

The method includes forming a plurality of first access lines extending in a first direction, the first access lines (such as the first access lines 910, 912 of FIG. 9A) have alternating wide areas and narrow areas .

This method includes forming a plurality of second access lines (eg, second access lines 1210, 1212 in FIG. 12C) extending in a second direction. The second access line has alternating wide areas and narrow areas. The wide area in the plurality of second access lines of the plurality of second access lines and the wide area in the plurality of first access lines of the plurality of first access lines overlap on the first access line The intersection with the second access line.

This method includes forming a memory cell array (e.g., memory cells 602, 604, 606, 608 in FIG. 6B) disposed at the intersection (FIG. 15) between the first access line and the second access line.

The method includes forming a first access line of a first conductive material and forming a second access line of a second conductive material. The first conductive material is different from the second conductive material.

The method includes removing the first insulation filling and the second insulation filling, exposing the surfaces of the memory cell, the plurality of first access lines and the plurality of second access lines, and lining at least one of the exposed surfaces with a dielectric material To form a dielectric pad (for example, the dielectric pad 1410 of FIG. 14A).

In some embodiments, the 3D cross-point memory device includes a plurality of conductive layers stacked along the first direction and the second direction, where each conductive layer includes a wire. A plurality of memory elements are located between multiple conductive layers. Each wire extending in a first direction includes at least two inflection points or protrusion portions on the side walls of the wire, the wires along a line orthogonal to the first direction The second direction extends. The memory cells in the three-dimensional cross-point memory device are separated from each other. In some embodiments, the memory unit is a phase change memory material. In some embodiments, each memory cell includes a diamond shape. In some embodiments, each memory cell is a pillar with four side walls. The four turning points are located between the four side walls in the memory element pillar. Turning point shape The shape is defined by the selective laterally etching of the material layer of the programmable memory cell, the material layer of the barrier layer and the material layer of the switch unit passing through the first hole.

Another example of a manufacturing method includes forming a stack of a first dummy layer, a memory layer, and a second temporary layer; forming holes through the stack; and selectively etching to remove portions of the memory layer Region and forming a plurality of memory cells; filling a dielectric material; forming a plurality of first anisotropic through-holes (anisotropic through-hole), each first anisotropic through-hole extending in a first direction; selection Etching to remove part of the first temporary layer to connect the first anisotropic through-openings in the same row and form a plurality of first wires; fill with dielectric material; and form a plurality of second anisotropies Through openings, each second anisotropic through opening extends in a second direction; and selectively etch to remove a portion of the second temporary layer to connect the second anisotropic through openings in the same column , And form a plurality of second wires.

FIG. 20 shows an integrated circuit 2050 including a three-dimensional cross-point memory array 2000. The three-dimensional cross-point memory array 2000 includes memory cells and first and second access lines with alternating wide and narrow areas , Is formed by the three-hole etching process as described herein. A plane and row decoder 2001 is coupled and electrically communicated with a plurality of character lines 2002, and is arranged along the rows in the three-dimensional intersection memory array 2000. A row of decoders 2003 is coupled and electrically communicated on a plurality of bit lines 2004, arranged along the rows in the three-dimensional cross-point memory array 2000 to read data from the memory cells in the three-dimensional cross-point memory array 2000 And write data to the memory cells in the three-dimensional cross-point memory array 2000. The address is from the bus 2005 Supply to plane and column decoder 2001 and row decoder 2003. The sense amplifier, such as pre-charge circuit and other supporting circuits, and the data-in structure in block 2006 are coupled to the row decoder 2003 through the bus 2007 . The data is supplied from the input/output ports on the integrated circuit 2050 or other data sources through the data-in line 2011 to the data input structure in block 2006. Data is supplied from the sense amplifier in block 2006 through the data-out line 2015 to the input/output port on the integrated circuit 2050 or other data destinations inside or outside the integrated circuit 2050 (data destination ). A bias arrangement state machine (bias arrangement state machine) is located in the control circuit (control circuitry) 2009, controls the bias arrangement supply voltage (biasing arrangement supply voltage) 2008 and the sensing circuit (sense circuitry) and data in block 2006 Input structure for reading and writing operations. The control circuit 2009 for performing a read operation, a write operation, and an erase operation can be implemented using a special purpose logic circuit, a general purpose processor, or a combination thereof.

In summary, although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

100: 3D crosspoint memory

101, 102, 103, 104, 105, 106: first access line

111, 112, 113, 114, 115, 116: second access line

117, 119, 122: wide area

118, 120: narrow area

121: Memory Cell

131: Second access line decoder

133: The first access line decoder

Claims (10)

A memory including: a plurality of first access lines extending in a first direction in a first access line layer, the first access lines having alternating A plurality of wide regions and a plurality of narrow regions (alternating wide regions and narrow regions); a plurality of second access lines extending in a second direction in a second access line layer, the second access lines Having a plurality of wide areas and a plurality of narrow areas, the wide areas in the second access lines of the plurality of second access lines and the first stores of the first access lines The wide regions in the fetched lines overlap on the intersections between the first access lines and the second access lines; and an array of memory cells are provided in the At the intersections between the first access line and the second access lines. The memory as recited in item 1 of the patent application range, wherein the plurality of first access lines includes a first conductive material, the plurality of second access lines includes a second conductive material, and the first conductive material is Different from the second conductive material. The memory according to item 1 of the patent application range, wherein each memory cell in the memory cell array includes a switching unit, a barrier layer, and a programmable memory unit in sequence. The memory according to item 3 of the patent application scope, wherein the programmable memory unit includes a phase change material. The memory as described in item 1 of the patent application scope includes: a plurality of third access lines extending in the first direction in a third access line layer, the plurality of third access lines having alternating Wide areas and narrow areas, the wide areas and the second access line layer of the third access lines of the plurality of third access lines in the third access line layer The wide areas in the second access lines of the plurality of second access lines overlap in a plurality of intersections, the intersections are located in the plurality of first access lines in the third access line layer Between the third access lines of the three access lines and the second access lines of the plurality of second access lines in the second access line layer; and a memory cell array disposed on the At the intersections between the third access lines in the third access line layer and the second access lines in the second access line layer. The memory as described in item 1 of the patent application, wherein a plurality of memory cells in the memory cell array are lined with a dielectric material. The memory according to item 6 of the patent application scope, wherein the dielectric material is a high-k material. The memory as described in item 1 of the patent application scope further includes a plurality of voids surrounding the plurality of memory cells in the memory cell array. The memory as described in item 1 of the patent application range, wherein the plurality of memory cells in the memory cell array have four side walls of the pillar. A method for manufacturing an integrated circuit includes: forming a plurality of first access lines extending in a first direction in a first access line layer, the first access lines having alternating wide areas and A plurality of narrow regions; forming a plurality of second access lines extending in a second direction in a second access line layer, the second access lines having alternating multiple wide regions and multiple narrow regions, The wide areas in the second access lines of the plurality of second access lines overlap the wide areas in the first access lines of the first access lines in the first A plurality of intersections between an access line and the second access lines; and forming a memory cell array disposed between the first access lines and the second access lines At the intersection.

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