TWI690913B - Display device and pixel circuit - Google Patents

Display device and pixel circuit Download PDF

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TWI690913B
TWI690913B TW108113048A TW108113048A TWI690913B TW I690913 B TWI690913 B TW I690913B TW 108113048 A TW108113048 A TW 108113048A TW 108113048 A TW108113048 A TW 108113048A TW I690913 B TWI690913 B TW I690913B
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switch
capacitor
gate signal
data voltage
turned
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TW108113048A
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TW202040536A (en
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林志隆
賴柏君
林祐陞
白承丘
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友達光電股份有限公司
國立成功大學
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Priority to CN202010293535.8A priority patent/CN111524481B/en
Publication of TW202040536A publication Critical patent/TW202040536A/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A display device includes: a first switch configured to receive a first gate signal through a first control end, receive a second gate signal through a second control end, and turn on according to the first gate signal and the second gate signal to provide a first data voltage to a first capacitor; a second switch configured to turn on according to the first gate signal to provide a second data voltage to a second capacitor; and a third switch configured to turn on according to the second gate signal to provide a third data voltage to a third capacitor.

Description

顯示裝置及像素電路Display device and pixel circuit

本發明涉及一種電子裝置及一種電路。具體而言，本發明涉及一種顯示裝置及一種像素電路。The invention relates to an electronic device and a circuit. Specifically, the present invention relates to a display device and a pixel circuit.

隨著電子科技的快速進展，顯示裝置已被廣泛地應用在人們的生活當中，諸如行動電話或電腦等。With the rapid development of electronic technology, display devices have been widely used in people's lives, such as mobile phones or computers.

一般而言，顯示裝置可包括閘極驅動電路、源極驅動電路、與像素電路陣列。閘極驅動電路可依序提供複數筆閘極訊號至像素電路，以逐列開啟像素電路的開關電晶體。源極驅動電路可提供複數筆資料電壓至開關電晶體開啟的像素電路，以使像素電路根據資料電壓進行顯示操作。In general, the display device may include a gate driving circuit, a source driving circuit, and a pixel circuit array. The gate driving circuit can sequentially provide a plurality of gate signals to the pixel circuit to turn on the switching transistors of the pixel circuit row by row. The source driving circuit can provide a plurality of data voltages to the pixel circuit turned on by the switching transistor, so that the pixel circuit performs a display operation according to the data voltage.

本發明一實施態樣涉及一種顯示裝置。根據本發明一實施例，顯示裝置包括：一第一開關，用以藉由一第一控制端接收一第一閘極訊號，用以藉由一第二控制端接收一第二閘極訊號，並用以根據該第一閘極訊號及該第二閘極訊號導通，以提供一第一資料電壓至一第一電容；一第二開關，用以根據該第一閘極訊號導通，以提供一第二資料電壓至一第二電容；以及一第三開關，用以根據該第二閘極訊號導通，以提供一第二資料電壓至一第三電容。An embodiment of the present invention relates to a display device. According to an embodiment of the invention, the display device includes: a first switch for receiving a first gate signal through a first control terminal, and a second gate signal for receiving a second control terminal, And used to conduct according to the first gate signal and the second gate signal to provide a first data voltage to a first capacitor; a second switch to conduct according to the first gate signal to provide a The second data voltage is to a second capacitor; and a third switch is used to conduct according to the second gate signal to provide a second data voltage to a third capacitor.

本發明另一實施態樣涉及一種像素電路。根據本發明一實施例，像素電路包括：一第一開關，電性連接於一第一電容與一資料線之間，其中該第一開關的一第一控制端電性連接一第一閘極線，且該第一開關的一第二控制端電性連接一第二閘極線；一第二開關，電性連接於一第二電容與該資料線之間，其中該第二開關的一控制端電性連接該第一閘極線；以及一第三開關，電性連接於一第三電容與該資料線之間，其中該第三開關的一控制端電性連接該第二閘極線。Another embodiment of the present invention relates to a pixel circuit. According to an embodiment of the invention, the pixel circuit includes: a first switch electrically connected between a first capacitor and a data line, wherein a first control terminal of the first switch is electrically connected to a first gate And a second control terminal of the first switch is electrically connected to a second gate line; a second switch is electrically connected between a second capacitor and the data line, wherein one of the second switches The control terminal is electrically connected to the first gate line; and a third switch is electrically connected between a third capacitor and the data line, wherein a control terminal of the third switch is electrically connected to the second gate line line.

藉由應用上述一實施例，即可在不使用多工器的情況下，利用單一資料線提供不同的資料電壓至同一像素電路的不同電容。By applying the above embodiment, a single data line can be used to provide different data voltages to different capacitors of the same pixel circuit without using a multiplexer.

以下將以圖式及詳細敘述清楚說明本揭示內容之精神，任何所屬技術領域中具有通常知識者在瞭解本揭示內容之實施例後，當可由本揭示內容所教示之技術，加以改變及修飾，其並不脫離本揭示內容之精神與範圍。The spirit of this disclosure will be clearly illustrated in the following figures and detailed descriptions. Anyone with ordinary knowledge in the art can understand the embodiments of this disclosure, and they can be changed and modified by the techniques taught in this disclosure. It does not deviate from the spirit and scope of this disclosure.

關於本文中所使用之『第一』、『第二』、…等，並非特別指稱次序或順位的意思，亦非用以限定本發明，其僅為了區別以相同技術用語描述的元件或操作。The terms "first", "second", ..., etc. used in this document do not specifically refer to order or order, nor are they intended to limit the present invention. They are only used to distinguish elements or operations described in the same technical terms.

關於本文中所使用之『電性連接』，可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，而『電性連接』還可指二或多個元件相互操作或動作。With regard to the "electrical connection" used in this article, it can mean that two or more elements directly make physical or electrical contact with each other, or indirectly make physical or electrical contact with each other, and "electrical connection" can also mean two or Multiple elements interoperate or act.

關於本文中所使用之『包含』、『包括』、『具有』、『含有』等等，均為開放性的用語，即意指包含但不限於。The terms "contains", "includes", "has", "contains", etc. used in this article are all open terms, which means including but not limited to.

關於本文中所使用之『及/或』，係包括所述事物的任一或全部組合。As used herein, "and/or" includes any or all combinations of the things described.

關於本文中所使用之用語『大致』、『約』等，係用以修飾任何可些微變化的數量或誤差，但這種些微變化或誤差並不會改變其本質。The terms "approximately" and "approximately" used in this article are used to modify the quantity or error of any slight change, but such slight change or error will not change its essence.

關於本文中所使用之用詞（terms），除有特別註明外，通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論，以提供本領域技術人員在有關本揭露之描述上額外的引導。Regarding the terms used in this article, unless otherwise noted, they usually have the ordinary meaning that each term is used in this field, in the content disclosed here, and in the special content. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of this disclosure.

第1圖為根據本發明實施例所繪示的顯示裝置100的示意圖。顯示裝置100可包括閘極驅動電路110、源極驅動電路120、以及像素陣列102。像素陣列102可包括複數個以矩陣排列的像素電路106。閘極驅動電路110可依序產生並提供複數筆閘極訊號G(1)、…、G(N)給像素陣列102中的像素電路106。源極驅動電路120可產生複數筆資料電壓D(1)、…、D(M)，並透過複數條資料線提供此些資料電壓D(1)、…、D(M)給接收閘極訊號G(1)、…、G(N)的像素電路106，以令像素電路106據以進行資料電壓更新，其中N為自然數，其中M為自然數。FIG. 1 is a schematic diagram of a display device 100 according to an embodiment of the invention. The display device 100 may include a gate driving circuit 110, a source driving circuit 120, and a pixel array 102. The pixel array 102 may include a plurality of pixel circuits 106 arranged in a matrix. The gate driving circuit 110 can sequentially generate and provide a plurality of pen gate signals G(1),..., G(N) to the pixel circuit 106 in the pixel array 102. The source driving circuit 120 can generate a plurality of data voltages D(1), ..., D(M), and provide these data voltages D(1), ..., D(M) to the receiving gate signal through a plurality of data lines The pixel circuits 106 of G(1),..., G(N) enable the pixel circuit 106 to update the data voltage accordingly, where N is a natural number and M is a natural number.

以下段落將搭配第2圖，以兩相鄰像素電路106a、106b為例說明本案細節，然本案不以下述實施例為限。在本實施列中，像素電路106a、106b為前述像素電路106中的相鄰兩者。在本實施列中，像素電路106a用以接收閘極訊號G1(n)、G2(n)及資料電壓Vdata，像素電路106b用以接收閘極訊號G1(n+1)、G2(n+1)及資料電壓Vdata。其中，閘極訊號G1(n)、G2(n)可包含於前述閘極訊號G(1)、…、G(N)中的一者，閘極訊號G1(n+1)、G2(n+1) 可包含於前述閘極訊號G(1)、…、G(N)中的相鄰另一者，且資料電壓Vdata可為前述資料電壓D(1)、…、D(M)中的一者。The following paragraphs will be used in conjunction with FIG. 2 to illustrate the details of this case by taking two adjacent pixel circuits 106a and 106b as examples, but this case is not limited to the following embodiments. In the present embodiment, the pixel circuits 106a and 106b are the adjacent two of the aforementioned pixel circuits 106. In this embodiment, the pixel circuit 106a is used to receive the gate signals G1(n), G2(n) and the data voltage Vdata, and the pixel circuit 106b is used to receive the gate signals G1(n+1), G2(n+1) ) And data voltage Vdata. Among them, the gate signals G1(n), G2(n) may be included in one of the aforementioned gate signals G(1), ..., G(N), the gate signals G1(n+1), G2(n +1) may be included in the adjacent gate signal G(1), ..., G(N), and the data voltage Vdata may be the aforementioned data voltage D(1), ..., D(M) The one.

在一實施列中，像素電路106a包括開關SW11、SW12、SW13、及電容C11、C12、C13。在一實施例中，每一開關SW11、SW12、SW13可用雙閘極電晶體實現，然本案不以此為限。在另外一些實施例中，開關SW11可用兩個以上的電晶體實現，且開關SW12、SW13可分別用一或多電極體實現。在一實施例中，開關SW11、SW12、SW13、及電容C11、C12、C13分別對應不同顏色之顯示。例如，開關SW11及電容C11對應紅色顯示、開關SW12及電容C12對應綠色顯示、且開關SW13及電容C13對應藍色顯示，然本案不以此為限。In one embodiment, the pixel circuit 106a includes switches SW11, SW12, SW13, and capacitors C11, C12, C13. In an embodiment, each switch SW11, SW12, SW13 can be implemented with a double gate transistor, but this case is not limited to this. In some other embodiments, the switch SW11 may be implemented by more than two transistors, and the switches SW12 and SW13 may be implemented by one or more electrode bodies, respectively. In an embodiment, the switches SW11, SW12, SW13, and the capacitors C11, C12, C13 respectively correspond to the display of different colors. For example, the switch SW11 and the capacitor C11 correspond to a red display, the switch SW12 and the capacitor C12 correspond to a green display, and the switch SW13 and the capacitor C13 correspond to a blue display, but this case is not limited to this.

在一實施例中，開關SW11電性連接於電容C11與開關SW12之間，且開關SW11的第一控制端電性連接用以傳遞閘極訊號G1(n)的閘極線，開關SW11的第二控制端電性連接用以傳遞閘極訊號G2(n)的閘極線。在一實施例中，開關SW11用以藉由第一控制端接收閘極訊號G1(n)，用以藉由第二控制端接收閘極訊號G2(n)，並用以根據閘極訊號G1(n)及閘極訊號G2(n) 導通以提供資料電壓Vdata至電容C11。在一實施例中，電容C11電性連接於開關SW11與具有共同電壓VCOM的共同電極之間。In one embodiment, the switch SW11 is electrically connected between the capacitor C11 and the switch SW12, and the first control terminal of the switch SW11 is electrically connected to the gate line for transmitting the gate signal G1(n). The two control terminals are electrically connected to the gate line for transmitting the gate signal G2(n). In one embodiment, the switch SW11 is used to receive the gate signal G1(n) through the first control terminal, to receive the gate signal G2(n) through the second control terminal, and to use the gate signal G1( n) and the gate signal G2(n) is turned on to provide the data voltage Vdata to the capacitor C11. In an embodiment, the capacitor C11 is electrically connected between the switch SW11 and a common electrode having a common voltage VCOM.

在一實施例中，開關SW12電性連接於用以傳遞資料電壓Vdata的資料線與電容C12之間，且開關SW12的第一、第二控制端電性連接用以傳遞閘極訊號G1(n)的閘極線。在一實施例中，開關SW12用以根據閘極訊號G1(n)導通以提供資料電壓Vdata至電容C12。在一實施例中，電容C12電性連接於開關SW12與具有共同電壓VCOM的共同電極之間。In one embodiment, the switch SW12 is electrically connected between the data line for transmitting the data voltage Vdata and the capacitor C12, and the first and second control terminals of the switch SW12 are electrically connected for transmitting the gate signal G1(n ) Gate line. In an embodiment, the switch SW12 is turned on according to the gate signal G1(n) to provide the data voltage Vdata to the capacitor C12. In an embodiment, the capacitor C12 is electrically connected between the switch SW12 and a common electrode having a common voltage VCOM.

在一實施例中，開關SW13電性連接於用以傳遞資料電壓Vdata的資料線與電容C13之間，且開關SW13的第一、第二控制端電性連接用以傳遞閘極訊號G2(n)的閘極線。在一實施例中，開關SW13用以根據閘極訊號G2(n)導通以提供資料電壓Vdata至電容C13。在一實施例中，電容C13電性連接於開關SW13與具有共同電壓VCOM的共同電極之間。In one embodiment, the switch SW13 is electrically connected between the data line for transmitting the data voltage Vdata and the capacitor C13, and the first and second control terminals of the switch SW13 are electrically connected for transmitting the gate signal G2(n ) Gate line. In one embodiment, the switch SW13 is turned on according to the gate signal G2(n) to provide the data voltage Vdata to the capacitor C13. In an embodiment, the capacitor C13 is electrically connected between the switch SW13 and a common electrode having a common voltage VCOM.

在一些實施例中，開關SW12、SW13可為僅具有單一控制端。In some embodiments, the switches SW12 and SW13 may only have a single control terminal.

在一實施列中，像素電路106b包括開關SW21、SW22、SW23、及電容C21、C22、C23。在一實施例中，開關SW21、SW22、SW23、及電容C21、C22、C23具有相似於像素電路106a中開關SW11、SW12、SW13、及電容C11、C12、C13的設置，故相關細節在此不贅述。In one embodiment, the pixel circuit 106b includes switches SW21, SW22, SW23, and capacitors C21, C22, C23. In one embodiment, the switches SW21, SW22, SW23, and the capacitors C21, C22, C23 have settings similar to the switches SW11, SW12, SW13, and the capacitors C11, C12, C13 in the pixel circuit 106a, so the relevant details are not described here Repeat.

在一實施例中，開關SW21的第一控制端電性連接用以傳遞閘極訊號G1(n+1)的閘極線，開關SW21的第二控制端電性連接用以傳遞閘極訊號G2(n+1)的閘極線，開關SW22的第一、第二控制端電性連接用以傳遞閘極訊號G1(n+1)的閘極線，且開關SW23的第一、第二控制端電性連接用以傳遞閘極訊號G2(n+1)的閘極線。In an embodiment, the first control terminal of the switch SW21 is electrically connected to the gate line for transmitting the gate signal G1(n+1), and the second control terminal of the switch SW21 is electrically connected to transmit the gate signal G2 (n+1) gate line, the first and second control terminals of the switch SW22 are electrically connected to the gate line for transmitting the gate signal G1(n+1), and the first and second controls of the switch SW23 The terminal is electrically connected to the gate line for transmitting the gate signal G2(n+1).

藉由應用上述的設置，即可在不使用多工器的情況下，利用單一資料線提供不同的資料電壓至同一像素電路的不同電容。By applying the above configuration, a single data line can be used to provide different data voltages to different capacitors of the same pixel circuit without using a multiplexer.

以下將搭配第3-6圖，以一操作例說明本案實施例中的細節，然本案實施例不以此為限。應注意到，為使說明易於了解，以下操作例僅以像素電路106a為例進行說明，至於像素電路106b的操作當可類推得知。In the following, the details in the embodiment of this case will be described with an operation example in conjunction with FIGS. 3-6, but the embodiment of this case is not limited to this. It should be noted that, in order to make the description easy to understand, the following operation example uses only the pixel circuit 106a as an example for description, and the operation of the pixel circuit 106b can be inferred by analogy.

參照第6圖，在時間點t1-t2間，閘極訊號G1(n)、G2(n)具有第一電壓準位(例如是高電壓準位)。此時，開關SW11、SW12、SW13根據閘極訊號G1(n)、G2(n)導通(如第3圖所示)，而提供具有電壓準位VD1的資料電壓VDATA(於本案中亦稱為第一資料電壓)至電容C11、C12、C13。電壓準位VD1例如可為在此一幀中欲使電容C11所儲存的電壓準位。在此一期間中，開關SW11是經由開關SW12接收具有電壓準位VD1的資料電壓VDATA，而提供至電容C11。Referring to FIG. 6, between time points t1-t2, the gate signals G1(n) and G2(n) have a first voltage level (for example, a high voltage level). At this time, the switches SW11, SW12, SW13 are turned on according to the gate signals G1(n), G2(n) (as shown in FIG. 3), and provide the data voltage VDATA (also referred to in this case as the voltage level VD1) The first data voltage) to the capacitors C11, C12, C13. The voltage level VD1 may be, for example, the voltage level to be stored in the capacitor C11 in this frame. During this period, the switch SW11 receives the data voltage VDATA having the voltage level VD1 through the switch SW12 and provides it to the capacitor C11.

在時間點t2-t3間，閘極訊號G1(n)具有第一電壓準位，且閘極訊號G2(n)具有第二電壓準位(例如是低電壓準位)。此時，如第4圖所示， 開關SW12根據閘極訊號G1(n)導通，而提供具有電壓準位VD2的資料電壓VDATA(於本案中亦稱為第二資料電壓)至電容C12。電壓準位VD2例如可為在此一幀中欲使電容C12所儲存的電壓準位。另一方面，在此期間中，開關SW11、SW13根據具有第二電壓準位的閘極訊號G2(n)而關斷，而未提供具有電壓準位VD2的資料電壓VDATA至電容C11、C13。以另一角度而言，在此期間中，開關SW11、SW13是因未接收到具第一電壓準位的閘極訊號G2(n)而關斷。Between time points t2-t3, the gate signal G1(n) has a first voltage level, and the gate signal G2(n) has a second voltage level (for example, a low voltage level). At this time, as shown in FIG. 4, the switch SW12 is turned on according to the gate signal G1(n), and provides a data voltage VDATA (also referred to as a second data voltage in this case) having a voltage level VD2 to the capacitor C12. The voltage level VD2 may be, for example, the voltage level to be stored in the capacitor C12 in this frame. On the other hand, during this period, the switches SW11 and SW13 are turned off according to the gate signal G2(n) having the second voltage level, and the data voltage VDATA having the voltage level VD2 is not supplied to the capacitors C11 and C13. From another perspective, during this period, the switches SW11 and SW13 are turned off because the gate signal G2(n) with the first voltage level is not received.

在時間點t3-t5間，閘極訊號G1(n)、G2(n)具有第二電壓準位。此時，開關SW11、SW12、SW13根據閘極訊號G1(n)、G2(n)關斷。另一方面，此時，由於閘極訊號G1(n+1)、G2(n+1)具有第一電壓準位，故開關SW21、SW22、SW23根據閘極訊號G1(n+1)、G2(n+1)導通，而對電容C11、C12、C13進行充電(類似於時間點t1-t2間，開關SW11、SW12、SW13的操作)。Between time points t3-t5, the gate signals G1(n) and G2(n) have the second voltage level. At this time, the switches SW11, SW12, SW13 are turned off according to the gate signals G1(n), G2(n). On the other hand, at this time, since the gate signals G1(n+1), G2(n+1) have the first voltage level, the switches SW21, SW22, SW23 are based on the gate signals G1(n+1), G2 (n+1) is turned on, and the capacitors C11, C12, and C13 are charged (similar to the operation of the switches SW11, SW12, and SW13 between time points t1-t2).

在時間點t5-t6間，閘極訊號G1(n)具有第二電壓準位，且閘極訊號G2(n)具有第一電壓準位。此時，如第5圖所示， 開關SW13根據閘極訊號G1(n)導通，而提供具有電壓準位VD3的資料電壓VDATA(於本案中亦稱為第三資料電壓)至電容C13。電壓準位VD3例如可為在此一幀中欲使電容C13所儲存的電壓準位。另一方面，在此期間中，開關SW11、SW12根據具有第二電壓準位的閘極訊號G2(n)而關斷，而未提供具有電壓準位VD3的資料電壓VDATA至電容C11、C12。以另一角度而言，在此期間中，開關SW11、SW12是因未接收到具第一電壓準位的閘極訊號G1(n)而關斷。Between time points t5-t6, the gate signal G1(n) has a second voltage level, and the gate signal G2(n) has a first voltage level. At this time, as shown in FIG. 5, the switch SW13 is turned on according to the gate signal G1(n) to provide a data voltage VDATA (also referred to as a third data voltage in this case) having a voltage level VD3 to the capacitor C13. The voltage level VD3 may be, for example, the voltage level to be stored in the capacitor C13 in this frame. On the other hand, during this period, the switches SW11 and SW12 are turned off according to the gate signal G2(n) having the second voltage level, and the data voltage VDATA having the voltage level VD3 is not supplied to the capacitors C11 and C12. From another perspective, during this period, the switches SW11 and SW12 are turned off because the gate signal G1(n) with the first voltage level is not received.

在時間點t6-t7間，閘極訊號G1(n)、G2(n)具有第二電壓準位。此時，開關SW11、SW12、SW13根據閘極訊號G1(n)、G2(n)關斷。Between time points t6-t7, the gate signals G1(n) and G2(n) have the second voltage level. At this time, the switches SW11, SW12, SW13 are turned off according to the gate signals G1(n), G2(n).

藉由上述的操作，即可在不使用多工器的情況下，提供來自同一資料線的、分別具電壓準位VD1、VD2、VD3的資料電壓Vdata至像素電路106a的不同電容C11、C12、C13。Through the above operation, it is possible to provide the data voltages Vdata with the voltage levels VD1, VD2, and VD3 from the same data line to the different capacitors C11, C12 of the pixel circuit 106a without using the multiplexer. C13.

此外，藉由上述的操作，由於閘極訊號G1(n)、G2(n)具有第一電壓準位的時間皆至少為2倍線時間(line time)，故可避免因閘極訊號G1(n)、G2(n)的轉態所需時間 (如從具有第一電壓準位轉態至具有第二電壓準位所需的時間)而導致的電容C11、C12、C13充電不足問題，而能確保顯示裝置100的顯示品質。In addition, through the above operation, since the time when the gate signals G1(n) and G2(n) have the first voltage level is at least twice the line time, it is possible to avoid the gate signal G1( n), the time required for the transition of G2(n) (such as the time required to transition from having the first voltage level to having the second voltage level) causes insufficient charging of the capacitors C11, C12, and C13, and The display quality of the display device 100 can be ensured.

應注意到，在不同實施例中，電壓準位VD1、VD2、VD3可視實際需求而彼此相同、彼此不同、或彼此部份相同，本案並不以上述實施例為限。It should be noted that in different embodiments, the voltage levels VD1, VD2, and VD3 may be the same as each other, different from each other, or partially the same according to actual needs. This case is not limited to the above embodiment.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

100:顯示裝置100: display device

102:像素陣列102: pixel array

106、106a、106b:像素電路106, 106a, 106b: pixel circuit

110:閘極驅動電路110: Gate drive circuit

120:源極驅動電路120: source drive circuit

G(1)-G(N):閘極訊號G(1)-G(N): gate signal

D(1)-D(M):資料電壓D(1)-D(M): data voltage

G1(n)、G2(n)、G1(n+1)、G2(n+1):閘極訊號G1(n), G2(n), G1(n+1), G2(n+1): gate signal

VDATA:資料電壓VDATA: data voltage

SW11、SW12、SW13、SW21、SW22、SW23:開關SW11, SW12, SW13, SW21, SW22, SW23: switch

C11、C12、C13、C21、C22、C23:電容C11, C12, C13, C21, C22, C23: capacitance

VCOM:共同電壓VCOM: common voltage

t1-t7:時間點t1-t7: time point

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖為根據本發明一實施例所繪示的顯示裝置的示意圖； 第2圖為根據本發明一實施例所繪示的像素電路的示意圖； 第3圖為根據本發明一操作例所繪示的像素電路的示意圖； 第4圖為根據本發明一操作例所繪示的像素電路的示意圖； 第5圖為根據本發明一操作例所繪示的像素電路的示意圖；及 第6圖為根據本發明一操作例所繪示的像素電路的訊號圖。In order to make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the drawings are described as follows: FIG. 1 is a schematic diagram of a display device according to an embodiment of the present invention; 2 is a schematic diagram of a pixel circuit according to an embodiment of the invention; FIG. 3 is a schematic diagram of a pixel circuit according to an operation example of the invention; FIG. 4 is a schematic diagram of an operation example according to the invention FIG. 5 is a schematic diagram of a pixel circuit according to an operation example of the present invention; and FIG. 6 is a signal diagram of the pixel circuit according to an operation example of the present invention.

106a、106b:像素電路 106a, 106b: pixel circuit

G1(n)、G2(n)、G1(n+1)、G2(n+1):閘極訊號 G1(n), G2(n), G1(n+1), G2(n+1): gate signal

VDATA:資料電壓 VDATA: data voltage

SW11、SW12、SW13、SW21、SW22、SW23:開關 SW11, SW12, SW13, SW21, SW22, SW23: switch

C11、C12、C13、C21、C22、C23:電容 C11, C12, C13, C21, C22, C23: capacitance

VCOM:共同電壓 VCOM: common voltage

Claims (10)

一種顯示裝置，包括：一第一開關，用以藉由一第一控制端接收一第一閘極訊號，用以藉由一第二控制端接收一第二閘極訊號，並用以根據該第一閘極訊號及該第二閘極訊號導通，以提供一第一資料電壓至一第一電容；一第二開關，用以根據該第一閘極訊號導通，以提供一第二資料電壓至一第二電容；以及一第三開關，用以根據該第二閘極訊號導通，以提供一第三資料電壓至一第三電容。 A display device includes: a first switch for receiving a first gate signal through a first control terminal, a second gate signal for receiving a second control terminal A gate signal and the second gate signal are turned on to provide a first data voltage to a first capacitor; a second switch is turned on according to the first gate signal to provide a second data voltage to A second capacitor; and a third switch for conducting according to the second gate signal to provide a third data voltage to a third capacitor. 如請求項1所述之顯示裝置，其中在該第一開關導通的期間中，該第二開關導通及/或該第三開關導通。 The display device according to claim 1, wherein the second switch is turned on and/or the third switch is turned on while the first switch is turned on. 如請求項1所述之顯示裝置，其中該第一開關經由該第二開關接收該第一資料電壓。 The display device according to claim 1, wherein the first switch receives the first data voltage via the second switch. 如請求項1所述之顯示裝置，其中在一第一期間中，該第一開關導通以提供該第一資料電壓至該第一電容，該第二開關導通以提供該第一資料電壓至該第二電容，且該第三開關導通以提供該第一資料電壓至該第三電容。 The display device according to claim 1, wherein in a first period, the first switch is turned on to provide the first data voltage to the first capacitor, and the second switch is turned on to provide the first data voltage to the A second capacitor, and the third switch is turned on to provide the first data voltage to the third capacitor. 如請求項1所述之顯示裝置，其中在一第二期間中，該第二開關導通以提供該第二資料電壓至該第二電容，且該第一開關及該第三開關未接收到該第二閘極訊號而關斷。 The display device according to claim 1, wherein in a second period, the second switch is turned on to provide the second data voltage to the second capacitor, and the first switch and the third switch do not receive the The second gate signal is turned off. 如請求項1所述之顯示裝置，其中在一第三期間中，該第三開關導通以提供該第三資料電壓至該第三電容，且該第一開關及該第二開關未接收到該第一閘極訊號而關斷。 The display device according to claim 1, wherein in a third period, the third switch is turned on to provide the third data voltage to the third capacitor, and the first switch and the second switch do not receive the The first gate signal is turned off. 如請求項1至6中任一者所述之顯示裝置，其中該第一資料電壓、該第二資料電壓、及該第三資料電壓來自同一資料線。 The display device according to any one of claims 1 to 6, wherein the first data voltage, the second data voltage, and the third data voltage are from the same data line. 如請求項1至6中任一者所述之顯示裝置，其中該第一開關為一雙閘極電晶體。 The display device according to any one of claims 1 to 6, wherein the first switch is a double gate transistor. 一種像素電路，包括：一第一開關，電性連接於一第一電容與一資料線之間，其中該第一開關的一第一控制端電性連接一第一閘極線，且該第一開關的一第二控制端電性連接一第二閘極線； 一第二開關，電性連接於一第二電容與該資料線之間，其中該第二開關的一控制端電性連接該第一閘極線；以及一第三開關，電性連接於一第三電容與該資料線之間，其中該第三開關的一控制端電性連接該第二閘極線。 A pixel circuit includes: a first switch electrically connected between a first capacitor and a data line, wherein a first control terminal of the first switch is electrically connected to a first gate line, and the first A second control terminal of a switch is electrically connected to a second gate line; A second switch electrically connected between a second capacitor and the data line, wherein a control terminal of the second switch is electrically connected to the first gate line; and a third switch is electrically connected to a Between the third capacitor and the data line, a control terminal of the third switch is electrically connected to the second gate line. 如請求項1所述之像素電路，其中該第一開關經由該第二開關電性連接該資料線。 The pixel circuit according to claim 1, wherein the first switch is electrically connected to the data line via the second switch.
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