TWI688221B - Sending method and receiving device - Google Patents

Abstract

This technology relates to a transmission method and a receiving device that can ensure good communication quality in data transmission using LDPC codes. In group interleaving, an LDPC code with a code length N of 17280 bits is interleaved in units of bit groups 0 to 47 of 360 bits. In group deinterleaving, the arrangement of LDPC codes after group interleaving is restored to the original arrangement. This technical system can be applied to, for example, data transmission using LDPC codes.

Description

Sending method and receiving device

This technology relates to a transmission method and a reception device, and particularly to, for example, a transmission method and a reception device that can ensure good communication quality in data transmission using an LDPC code.

LDPC (Low Density Parity Check) code has a high error correction ability. The transmission method such as ATSC (Advanced Television Systems Committee) 3.0 and other digital broadcasting is widely adopted (for example, refer to Non-Patent Document 1).

LDPC codes, according to research in recent years, have gradually learned that, similar to turbo codes, etc., as the code length becomes longer, the performance closer to the Xuenong limit can be obtained. In addition, LDPC codes have such a property that the minimum distance is proportional to the code length, so as their characteristics, the block error probability characteristic is good, and almost does not occur in the decoding characteristics such as turbo codes. The so-called error gradual phenomenon can also be cited as its advantages. [Prior Technical Literature] [Non-patent literature]

[Non-Patent Document 1] ATSC Standard: Physical Layer Protocol (A/322), 7 September 2016

[Problems to be solved by the invention]

In data transmission using the LDPC code, for example, the LDPC code is regarded as a symbol (or symbolized) of orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), etc. The signal points mapped to the quadrature modulation are sent.

As mentioned above, the data transmission using the LDPC code is gradually extended to the whole world, and is required to ensure good communication (transmission) quality.

This technology was developed in view of this situation, and its purpose is to ensure good communication quality in data transmission using LDPC codes. [Means to solve the problem]

之排列；前記檢查矩陣係含有：以所定值M1、與前記LDPC碼的資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為1440；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

The first transmission method of this technology is a transmission method, which includes: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 3/16 for LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Group i, and the arrangement of bit groups 0 to 47 of the LDPC code of the predecessor 17280 bits is interleaved into bit groups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the bottom of the B matrix; the D matrix adjacent to the NK-M1 row and the NK-M1 column, adjacent to the right of the C matrix, belonging to the identity matrix; the M1 value set in the previous note is 1440; the A matrix And the C matrix is represented by the check matrix initial value table; the preface check matrix initial value table is a table in which the positions of the elements of the preface A matrix and the C matrix 1 are represented every 360 columns, and is:

之排列。前記檢查矩陣係含有：以所定值M1、與前記LDPC碼之資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為1440；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

In the first transmission method of this technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 3/16, the LDPC code will be carried out; Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface inspection matrix contains: the M1 row and K columns represented by the predetermined value M1 and the information length K=N×r of the preface LDPC code, the A matrix at the upper left of the preface inspection matrix; and the M1 row and M1 column, preface The B matrix of the ladder structure adjacent to the right of the A matrix; the Z matrix of the zero matrix adjacent to the right of the M matrix row NK-M1 column, and the previous note of the B matrix; and the A matrix and the A matrix matrix of the K+M1 column of the NK-M1 row Adjacent B matrix below the C matrix; adjacent to the NK-M1 row and NK-M1 column, adjacent to the right of the preceding C matrix is the D matrix belonging to the identity matrix; the M1 value set in the previous note is 1440; the A matrix and C matrix Is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preface A matrix and the C matrix every 360 columns, and is:

之排列；前記檢查矩陣係含有：以所定值M1、與前記LDPC碼的資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為1440；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

The first receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data sent by the sending method; The method includes: an encoding step, based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 3/16, and LDPC encoding; and a group-type interleaving step, which performs the previous LDPC code, Group interleaving in 360-bit bit group units; and the mapping step is to map the previous LDPC code to 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the bottom of the B matrix; the D matrix adjacent to the NK-M1 row and the NK-M1 column, adjacent to the right of the C matrix, belonging to the identity matrix; the M1 value set in the previous note is 1440; the A matrix And the C matrix is represented by the check matrix initial value table; the preface check matrix initial value table is a table in which the positions of the elements of the preface A matrix and the C matrix 1 are represented every 360 columns, and is:

In the first receiving device of the present technology, the previous LDPC code obtained from the data transmitted by the first sending method is decoded.

之排列；前記檢查矩陣係含有：以所定值M1、與前記LDPC碼的資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為720；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

The second transmission method of this technology is a transmission method, which includes: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 5/16 to perform LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Metagroup i, and the arrangement of the bitgroups 0 to 47 of the predecessor 17280-bit LDPC code is interleaved into bitgroups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the B matrix below; the D matrix adjacent to the NK-M1 row and the NK-M1 column, and the D matrix adjacent to the right of the C matrix belonging to the identity matrix; the M1 value set in the previous note is 720; the A matrix before the note And the C matrix is represented by the check matrix initial value table; the preface check matrix initial value table is a table in which the positions of the elements of the preface A matrix and the C matrix 1 are represented every 360 columns, and is:

之排列。前記檢查矩陣係含有：以所定值M1、與前記LDPC碼之資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為720；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

In the second transmission method of the present technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 5/16, LDPC coding will be carried out; Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface inspection matrix contains: the M1 row and K columns represented by the predetermined value M1 and the information length K=N×r of the preface LDPC code, the A matrix at the upper left of the preface inspection matrix; and the M1 row and M1 column, preface The B matrix of the ladder structure adjacent to the right of the A matrix; the Z matrix of the zero matrix adjacent to the right of the M matrix row NK-M1 column, and the previous note of the B matrix; and the A matrix and the A matrix matrix of the K+M1 column of the NK-M1 row Adjacent C matrix below the B matrix; and NK-M1 row NK-M1 column, adjacent to the right of the previous C matrix is the D matrix belonging to the identity matrix; the M1 value set in the previous note is 720; the A matrix and C matrix Is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preface A matrix and the C matrix every 360 columns, and is:

之排列；前記檢查矩陣係含有：以所定值M1、與前記LDPC碼的資訊長度K=N×r而被表示的M1行K列的，前記檢查矩陣之左上的A矩陣；和M1行M1列的，前記A矩陣之右方相鄰的階梯結構之B矩陣；和M1行N-K-M1列的，前記B矩陣之右方相鄰的屬於零矩陣的Z矩陣；和N-K-M1行K+M1列的，前記A矩陣及前記B矩陣之下方相鄰的C矩陣；和N-K-M1行N-K-M1列的，前記C矩陣之右方相鄰的屬於單位矩陣的D矩陣；前記所定值M1係為720；前記A矩陣及C矩陣，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記A矩陣及C矩陣的1之元素的位置每360列地加以表示的表，係為：

The second receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data transmitted by the transmitting method; The method includes: an encoding step, which is based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 5/16, and LDPC encoding; and a group interleaving step, which is to perform the previous LDPC code, Group interleaving in 360-bit bit group units; and the mapping step is to map the previous LDPC code to 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the B matrix below; the D matrix adjacent to the NK-M1 row and the NK-M1 column, and the D matrix adjacent to the right of the C matrix belonging to the identity matrix; the M1 value set in the previous note is 720; the A matrix before the note And the C matrix is represented by the check matrix initial value table; the preface check matrix initial value table is a table in which the positions of the elements of the preface A matrix and the C matrix 1 are represented every 360 columns, and is:

In the second receiving device of the present technology, the previous LDPC code obtained from the data transmitted by the second sending method is decoded.

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The third sending method of this technology is a sending method, which includes: an encoding step, which is based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 7/16, and performs LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Metagroup i, and the arrangement of the bitgroups 0 to 47 of the predecessor 17280-bit LDPC code is interleaved into bitgroups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

之排列。前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

In the third transmission method of the present technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 7/16, LDPC coding will be performed; the previous LDPC code will be Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix portion corresponding to the preface information bits and the parity matrix portion corresponding to the preface parity bits; the preface information matrix portion is checked by inspection The matrix initial value table is shown; the initial check matrix initial value table is a table that shows the position of the element 1 of the preamble information matrix part every 360 columns, and is:

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The third receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data sent by the sending method; The method includes: an encoding step, based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 7/16, and LDPC encoding; and a group interleaving step, which performs the previous LDPC code, Group interleaving in 360-bit bit group units; and the mapping step is to map the previous LDPC code to 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

In the third receiving device of the present technology, the predecessor LDPC code obtained from the data transmitted by the third sending method is decoded.

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The fourth transmission method of the present technology is a transmission method, which includes: an encoding step, which is based on a check matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 9/16, and performs LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Metagroup i, and the arrangement of the bitgroups 0 to 47 of the predecessor 17280-bit LDPC code is interleaved into bitgroups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

之排列。前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

In the fourth transmission method of this technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 9/16, LDPC coding will be performed; the previous LDPC code will be Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix portion corresponding to the preface information bits and the parity matrix portion corresponding to the preface parity bits; the preface information matrix portion is checked by inspection The matrix initial value table is shown; the initial check matrix initial value table is a table that shows the position of the element 1 of the preamble information matrix part every 360 columns, and is:

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The fourth receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data transmitted by the sending method; The method includes: an encoding step, which is based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 9/16, and LDPC encoding; and a group interleaving step, which performs the previous LDPC code, Group interleaving with 360-bit bit group units; and the mapping step is to map the previous LDPC code in 8-bit units to 256 signal points of 256QAM UC (Uniform Constellation) Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

In the fourth receiving device of the present technology, the previous LDPC code obtained from the data transmitted by the fourth sending method is decoded.

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The fifth transmission method of this technology is a transmission method, which includes: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 11/16 to perform LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Metagroup i, and the arrangement of the bitgroups 0 to 47 of the predecessor 17280-bit LDPC code is interleaved into bitgroups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

之排列。前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

In the fifth transmission method of this technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 11/16, LDPC coding will be performed; the previous LDPC code will be Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix portion corresponding to the preface information bits and the parity matrix portion corresponding to the preface parity bits; the preface information matrix portion is checked by inspection The matrix initial value table is shown; the initial check matrix initial value table is a table that shows the position of the element 1 of the preamble information matrix part every 360 columns, and is:

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The fifth receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data sent by the sending method; The method includes: an encoding step, based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 11/16, and LDPC encoding; and a group-type interleaving step, which performs the previous LDPC code, Group interleaving in 360-bit bit group units; and the mapping step is to map the previous LDPC code to 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

In the fifth receiving device of the present technology, the previous LDPC code obtained from the data transmitted by the fifth transmitting method is decoded.

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The sixth transmission method of the present technology is a transmission method, which includes: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 13/16, and LDPC encoding ; And group interleaving step, the group interleaving is to interleave the predecessor LDPC code in 360-bit bit group units; and the mapping step is to interleave the predecessor LDPC code in 8-bit units, Any one of the 256 signal points of UC (Uniform Constellation) mapped to 256QAM; in the group interleaving of the preamble, the i+1th bit group from the beginning of the preamble LDPC code is regarded as a bit Group i, and the arrangement of bit groups 0 to 47 of the LDPC code of the predecessor 17280 bits is interleaved into bit groups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

之排列。前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

In the sixth transmission method of the present technology, based on the check matrix of the LDPC code with a code length N of 17280 bits and an encoding rate r of 13/16, LDPC coding will be performed; the previous LDPC code will be Group interleaving with bit group units interleaved will be performed. Then, the preceding LDPC code is mapped to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units. In the preamble group interleaving, the i+1th bit group from the beginning of the preamble LDPC code is regarded as the bit group i, while the preamble 17280 bit LDPC code bit group 0 to 47 The arrangement will be interleaved into bit groups

Arrangement. The preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix portion corresponding to the preface information bits and the parity matrix portion corresponding to the preface parity bits; the preface information matrix portion is checked by inspection The matrix initial value table is shown; the initial check matrix initial value table is a table that shows the position of the element 1 of the preamble information matrix part every 360 columns, and is:

之排列；前記LDPC碼係含有資訊位元與同位位元；前記檢查矩陣係含有：對應於前記資訊位元的資訊矩陣部及對應於前記同位位元的同位矩陣部；前記資訊矩陣部，係藉由檢查矩陣初期值表而被表示；前記檢查矩陣初期值表係為，將前記資訊矩陣部的1之元素的位置每360列地加以表示的表，係為：

The sixth receiving device of the present technology is a receiving device including: a decoding unit that decodes the LDPC code obtained from the data sent by the sending method; The method includes: an encoding step, which is based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 13/16, and LDPC encoding; and a group interleaving step, which performs the previous LDPC code, Group interleaving with 360-bit bit group units; and the mapping step is to map the previous LDPC code in 8-bit units to 256 signal points of 256QAM UC (Uniform Constellation) Any one of the; in the preamble group interleaving, the i+1 bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the predecessor 17280 bits of the LDPC code The arrangement of bit groups 0 to 47, interleaved into bit groups

The arrangement of the predecessor LDPC code contains information bits and parity bits; the predecessor check matrix contains: the information matrix part corresponding to the predecessor information bits and the parity matrix part corresponding to the predecessor parity bits; the preamble information matrix part It is represented by the check matrix initial value table; the preface check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

In the sixth receiving device of the present technology, the previous LDPC code obtained from the data transmitted by the sixth sending method is decoded.

In addition, the sending device or the receiving device implementing the sending method may be an independent device or an internal block constituting one device. [Effect of the invention]

According to this technology, good data quality can be ensured in data transmission using LDPC codes.

In addition, it is not necessarily limited to the effect described here, and may be any effect described in this disclosure.

The following describes the embodiment of the present technology, but before that, the LDPC code will be described first.

<LDPC code>

In addition, the LDPC code system is a linear code, and does not necessarily need to be 2 yuan, but here is assumed to be 2 yuan for illustration.

The LDPC code defines the parity check matrix of the LDPC code as a sparse matrix, which is its biggest feature. Here, the so-called sparse matrix means that the number of "1" elements of the matrix is a very small matrix (matrix with most elements being 0).

FIG. 1 is a diagram of an example of the check matrix H of the LDPC code.

In the inspection matrix H of FIG. 1, the weight of each column (column weight) (the number of "1") (weight) is "3", and the weight of each row (row weight) is "6".

In the coding (LDPC coding) caused by the LDPC code, for example, a generator matrix G is generated based on the check matrix H, and a codeword (LDPC code is generated by multiplying the generator matrix G by 2 information bits ).

Specifically, the encoding device that performs LDPC encoding first calculates that between the transpose matrix H ^{T of the} check matrix H and the expression GH ^T =0 is the established generation matrix G. Here, if the generator matrix G is a K×N matrix, the encoding device multiplies the generator matrix G by the bit sequence (vector u) of information bits formed by K bits to generate N bits The resulting codeword c (=uG). The code word (LDPC code) generated by the encoding device is received at the receiving side through the predetermined communication path.

The decoding of LDPC codes can be performed by an algorithm called Probabilistic Decoding proposed by Gallager, which consists of variable nodes (also known as message nodes) and check nodes. (check node), the so-called bipartite graph (Tanner graph) is carried out by a message propagation algorithm caused by probability propagation. Here, in the following, the variable node and the inspection node are suitably referred to as nodes.

FIG. 2 is a flowchart illustrating a procedure of decoding LDPC codes.

In addition, in the following, it is appropriate to determine the value of the i-th code bit of the LDPC code (1 codeword) received by the receiving side as a degree of "0", as indicated by the log likelihood ratio. The real value (received LLR) expressed is also called the received value u _0i . Also, let the message output from the check node be u _j and let the message output from the variable node be v _i .

First, in the decoding of the LDPC code, as shown in FIG. 2, in step S11, the LDPC code is received, the message (check node message) u _j is initialized to "0", and at the same time, it will be repeated. The integer variable k of the counter is initialized to "0", and the process proceeds to step S12. In step S12, based on the received value u _0i obtained by receiving the LDPC code, the calculation (variable node calculation) shown in equation (1) is performed to obtain the message (variable node information) v _i , and then, based on the message v _i, for formula (2) calculation (check node calculation) is obtained as shown in the message u _j.

Here, d _v and d _{c in} equations (1) and (2) are respectively the number of "1" indicating the longitudinal direction (column) and lateral direction (row) of the inspection matrix H Arbitrarily selected parameters. For example, in the case of the LDPC code ((3, 6) LDPC code) of the check matrix H shown in FIG. 1 with a column weight of 3 and a row weight of 6, then d _v =3 and d _c =6.

In addition, in the variable node calculus of formula (1) and the check node calculus of (2), the line from the edge (the variable node and the check node connected to the output message) is not separated. ) The input message is regarded as the object of calculation, so the range of calculation is 1 to d _v -1 or 1 to d _c -1. In addition, the check node calculation of formula (2) is actually a table of the function R(v ₁ , v ₂ ) shown in formula (3) defined by outputting ₁ to 2 inputs v ₁ and v ₂ in advance. , Which is used continuously (recursively) as shown in equation (4) and proceeded.

In step S12, the variable k is further increased by "1", and the process proceeds to step S13. In step S13, it is determined whether the variable k is greater than the predetermined number C of repeated decoding. In step S13, if it is determined that the variable k is not greater than C, the procedure returns to step S12, and the same processing is repeated below.

In addition, in step S13, if it is determined that the variable k is greater than C, the process proceeds to step S14, by performing the calculation shown in equation (5), the message v _i as the final output decoding result is obtained and output, and ends LDPC code decoding process.

Here, the calculation of formula (5) is different from the variable node calculation of formula (1), and is performed using the message u _j sent from all branches connected to the variable node.

Fig. 3 is a diagram showing an example of the check matrix H of the (3, 6) LDPC code (encoding rate 1/2, code length 12).

In the inspection matrix H of FIG. 3, as in FIG. 1, the weight of the column is 3, and the weight of the row is 6.

FIG. 4 is a diagram of the bipartite graph of the inspection matrix H of FIG. 3.

Here, in FIG. 4, the system represented by the plus sign “+” is the check node, and the system represented by the equal sign “=" is the variable node. The inspection node and the variable node correspond to the rows and columns of the inspection matrix H, respectively. The connecting line between the check node and the variable node is an edge, which is equivalent to "1" of the elements of the check matrix.

That is, if the element of the j-th row and i-th column of the inspection matrix is 1, in FIG. 4, the i-th variable node (the node of "=") from the top and the j-th inspection node from the top (The "+" node) is connected by branches. The branch system means that the code bits corresponding to the variable nodes have the restriction conditions corresponding to the check nodes.

In the Sum Product Algorithm of the decoding method of the LDPC code, the variable node algorithm and the check node algorithm are repeated.

FIG. 5 is a diagram of the variable node calculation performed in the variable node.

In the variable node, the message v _i corresponding to the branch to be calculated is the messages u ₁ and u ₂ from the remaining branches connected to the variable node, and the received value is used The variable node calculation of equation (1) of u _0i is obtained. The information corresponding to other branches is also obtained in the same way.

FIG. 6 is a diagram of the check node calculation performed in the check node.

Here, the check node calculation of formula (2) can be used a×b=exp{ln(|a|)+ln(|b|)}×sign(a)×sign(b), and rewritten as formula (6). Among them, sign(x) is 1 when x≧0, and -1 when x<0.

When x≧0, if the function ø(x) is defined as the formula ø(x)=ln(tanh(x/2)), then the formula ø ^-1 (x)=2tanh ^-1 (e ^-x ) will be established Therefore, formula (6) can be changed to formula (7).

Among the check nodes, the check node calculation of formula (2) is performed according to formula (7).

That is, in the check node, as shown in FIG. 6, the message u _j corresponding to the branch to be calculated is by using the message v ₁ ,v from the remaining branches connected to the check node ₂ , v ₃ , v ₄ , and v ₅ are calculated by the check node calculation of equation (7). The information corresponding to other branches is also obtained in the same way.

In addition, the function ø(x) of equation (7) can be expressed by the equation ø(x)=ln((e ^x +1)/(e ^x -1)). When x>0, ø(x)= ø ^-1 (x). When the functions ø(x) and ø ^-1 (x) are implemented to the hardware, there are cases where the LUT (Look Up Table) is implemented, but both are the same LUT.

<Configuration example of transmission system to which this technology is applied>

FIG. 7 is an embodiment of a transmission system to which this technology is applied (a so-called system refers to a logical collection of a plurality of devices, as to whether the devices of each structure are located in the same frame, it is not asked) Illustration of a configuration example.

In FIG. 7, the transmission system is composed of the sending device 11 and the receiving device 12.

The transmission device 11 performs transmission (broadcasting) (transmission) of, for example, a program broadcast on television. That is, the transmission device 11 is, for example, to encode the object data that is the object of transmission, such as video data or audio data of the program, into an LDPC code, and pass, for example, a satellite line, or surface wave, cable (wired Line) and other communication channels 13 to send.

The receiving device 12 receives the LDPC code sent from the transmitting device 11 through the communication channel 13, decodes it into object data, and outputs it.

Here, the LDPC code used in the transmission system of FIG. 7 is known to exert extremely high capabilities in the AWGN (Additive White Gaussian Noise) communication path.

On the other hand, in the communication path 13, a burst error or erasure may occur. For example, in particular, when the communication path 13 is a surface wave, in the OFDM (Orthogonal Frequency Division Multiplexing) system, the D/U (Desired to Undesired Ratio) is 0 dB (Undesired=echo power system and Desired=main In a multi-path environment where the power of the paths is equal, the power of certain symbols may sometimes become 0 (erasure) in response to the delay of the echo (paths other than the main path).

Also, in flutter (a communication path with a delay of 0 and an echo that is added to the Doppler frequency will be added), when the D/U is 0dB, with the Doppler frequency, The case where the power of all the OFDM symbols at a specific time becomes zero (erasure).

In addition, with the receiving device 12 side, the wiring of the receiving unit (not shown) such as an antenna that receives signals from the transmitting device 11 to the receiving device 12, or because of the receiving device 12 Instability of the power supply, sometimes burst errors.

On the other hand, in the decoding of the LDPC code, it is in the column of the check matrix H, and even on the variable node corresponding to the code bit of the LDPC code, as shown in FIG. 5, accompanied by the code bit of the LDPC code ( The received signal value u _0i ) is added to perform the variable node calculation of equation (1). Therefore, if the code bits used in the variable node calculation are wrong, the accuracy of the obtained message will decrease.

Then, in the decoding of the LDPC code, it is connected to the check node, and the information obtained from the variable node connected to the check node is used to perform the check node calculation of equation (7), so the plurality of connected The variable nodes (corresponding to the code bits of the LDPC code) that simultaneously have errors (including erasure) in the number of check nodes that increase the decoding performance will degrade.

That is, for example, a check node is that if two or more variable nodes connected to the check node are erased at the same time, all the variable nodes will return a probability of 0 and a probability of 1. It is a message of equal probability. In this case, the check node that sends back the message with equal probability cannot contribute to one decoding process (1 set of variable node calculation and check node calculation). As a result, the number of repetitions of the decoding process needs to be changed In many cases, the decoding performance will be degraded. Furthermore, the power consumption of the receiving device 12 that decodes the LDPC code will increase.

Therefore, in the transmission system of FIG. 7, the performance in the AWGN communication channel (AWGN channel) can be maintained, while the resistance to burst errors or erasure can be improved.

<Configuration example of the transmission device 11>

FIG. 8 is a block diagram of a configuration example of the transmission device 11 of FIG. 7.

In the transmission device 11, one or more input streams (Input Streams) as target data are supplied to a mode adaptation/multiplexer 111.

The mode adaptor/multiplexer 111 performs mode selection and multiplexing of one or more input streams supplied to it according to needs, and supplies data obtained as a result to a padder 112.

The complementer 112 performs necessary zero-filling (null insertion) on the data from the mode adaptation/multiplexer 111, and supplies the resulting data to the BB Scrambler 113.

The BB code mixing device 113 implements BB code mixing (Base-Band Scrambling) on the data from the finisher 112, and supplies the resulting data to the BCH encoder 114.

The BCH encoder 114 performs BCH encoding on the data from the BB encoder 113, and uses the resulting data as LDPC object data that is the object of LDPC encoding, which is supplied to the LDPC encoder 115.

The LDPC encoder 115 (encoding unit) refers to the LDPC object data from the BCH encoder 114, for example, the part corresponding to the co-located bit of the LDPC code, that is, the co-located matrix is a check matrix with a dual diagonal structure. LDPC encoding is performed, and an LDPC code that uses LDPC object data as information bits is output.

That is, the LDPC encoder 115 performs to encode the LDPC object data into, for example, DVB-S.2, or DVB-T.2, DVB-C.2, ATSC3.0, etc. as specified in the specifications LDPC codes of LDPC codes (corresponding to the check matrix) and other LDPC codes are output as LDPC codes obtained as a result.

Here, the LDPC code specified in the specifications of DVB-S.2 or ATSC3.0 is an IRA (Irregular Repeat Accumulate) code. The parity matrix (part or all) of the LDPC code check matrix is It is a stepped structure. The co-location matrix and the ladder structure will be described later. Also, the IRA code system is described in, for example, "Irregular Repeat-Accumulate Codes," H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000.

The LDPC code output by the LDPC encoder 115 is supplied to a bit interleaver 116.

The bit interleaver 116 performs bit interleaving described later on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the bit interleaving to the mapper 117.

The mapper 117 is an LDPC code from the bit interleaver 116, and is mapped to a symbol representing orthogonal modulation by a unit (symbol unit) of one or more code bits of the LDPC code Orthogonal modulation (multi-value modulation).

That is, the mapper 117 maps the LDPC code from the bit interleaver 116, and is defined by the I axis representing the I component in phase with the carrier and the Q axis representing the Q component orthogonal to the carrier The IQ plane is on the constellation, and the orthogonal modulation is performed as the signal point is determined by the modulation method of the orthogonal modulation of the LDPC code.

If the number of signal points of the constellation used in the modulation method of orthogonal modulation performed by the mapper 117 is 2 ^m , then the code bits of the m bits of the LDPC code are used as symbols Element (1 symbol), in the mapper 117, the LDPC code from the bit interleaver 116, which is mapped to 2 ^m signal points in symbol units, represents the signal point of the symbol .

Here, the modulation method as the orthogonal modulation performed by the mapper 117 is, for example, the modulation method specified in the specifications of DVB-S.2 or ATSC3.0, and other modulation methods. That is, for example: BPSK (Binary Phase Shift Keying), or QPSK (Quadrature Phase Shift Keying), 8PSK (Phase-Shift Keying), 16APSK (Amplitude Phase-Shift Keying), 32APSK, 16QAM (Quadrature Amplitude Modulation), 16QAM , 64QAM, 256QAM, 1024QAM, 4096QAM, 4PAM (Pulse Amplitude Modulation), etc. In the mapper 117, which modulation method to perform orthogonal modulation is set in advance according to, for example, the operation of the operator of the transmission device 11.

The data obtained by the processing in the mapper 117 (the mapping result formed by mapping the symbols to the signal points) is supplied to the Time Interleaver 118.

The time interleaver 118 performs time interleaving of symbol units (interleaving in the time direction) on the data from the mapper 117, and supplies the resulting data to the SISO/MISO encoder (SISO/MISO (Single Input Single Output/Multiple Input Single Output) encoder)119.

The SISO/MISO encoder 119 performs time-space encoding on the data from the time interleaver 118 and supplies it to the frequency interleaver 120.

The frequency interleaver 120 performs symbol unit frequency interleaving (interleaving in the frequency direction) on the data from the SISO/MISO encoder 119 and supplies it to the Frame Builder & Resource Allocation 131.

On the other hand, the BCH encoder 121 is supplied with control data (signalling) for transmission control such as Base Band Signaling (BB Header).

The BCH encoder 121 carries out the control data supplied thereto, performs BCH encoding in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.

The LDPC encoder 122 uses the data from the BCH encoder 121 as LDPC target data, performs LDPC encoding in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the mapper 123.

The mapper 123, in the same way as the mapper 117, maps the LDPC code from the LDPC encoder 122 to a unit (symbol unit) of one or more code bits of the LDPC code to indicate positive The signal point of one symbol of the intermodulation is subjected to quadrature modulation, and the resulting data is supplied to the frequency interleaver 124.

The frequency interleaver 124 performs the symbol unit frequency interleaving on the data from the mapper 123 in the same way as the frequency interleaver 120 and supplies it to the frame builder/resource allocation unit 131.

The frame builder/resource allocation unit 131 inserts pilot symbols into the necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and the data (symbols) obtained from the result , A frame (for example, PL (Physical Layer) frame, T2 frame, C2 frame, etc.) composed of a predetermined number of symbols is provided to the OFDM generation unit (OFDM generation) 132.

The OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder/resource allocation unit 131, and transmits it through the communication channel 13 (FIG. 7).

In addition, the transmission device 11 may, for example, not include: a time interleaver 118, a SISO/MISO encoder 119, a frequency interleaver 120, and a frequency interleaver 124, etc., a part of the block shown in FIG. 8 constitute.

<Configuration example of bit interleaver 116>

9 is a block diagram of a configuration example of the bit interleaver 116 of FIG.

The bit interleaver 116 has the function of interleaving data, and is composed of: a parity interleaver 23, a group-wise interleaver 24, and a block interleaver 25 Posed.

The co-located interleaver 23 is a co-located interlace of the co-located bits of the LDPC code from the LDPC encoder 115 to interleave the positions of other co-located bits, and supplies the co-located LDPC code to the group interleaver twenty four.

The group interleaver 24 performs group interleaving on the LDPC code from the co-located interleaver 23, and supplies the group interleaved LDPC code to the block interleaver 25.

Here, in group interleaving, the LDPC code of 1 code is divided from the beginning into 360-bit units equal to the parallel factor P described later, and the 360-bit divided by 1 is regarded as The bit group, the LDPC code from the co-located interleaver 23, is interleaved in units of bit groups.

When group interleaving is performed, the error rate can be improved compared to the case where group interleaving is not performed. As a result, in data transmission, good communication quality can be ensured.

The block interleaver 25 performs block interleaving by inversely multiplexing the LDPC code from the group interleaver 24, for example, symbolizing the LDPC code of 1 code into a map The unit is an m-bit symbol and is supplied to the mapper 117 (FIG. 8).

Here, in block interleaving, for example, in the column The (column) (vertical) direction memorizes the specified number of bits as the column of the memory field, which is the number of bits in the row (horizontal) direction equal to the number of bits m of the symbol In the memory field, there is the LDPC code from the group interleaver 24, which is written in the column direction and read out in the horizontal direction, whereby the LDPC code is symbolized into m-bit symbols yuan.

<Check matrix of LDPC code>

FIG. 10 is a diagram of an example of the check matrix H used for LDPC encoding in the LDPC encoder 115 of FIG. 8.

The check matrix H is of the LDGM (Low-Density Generation Matrix) structure. Among the code bits of the LDPC code, the information matrix H _A corresponding to the information bit and the co-location matrix corresponding to the co-location bits H _T , and can be expressed by the formula H=[H _A |H _T ] (the elements of the information matrix H _A are regarded as the elements on the left and the elements of the homology matrix H _T are regarded as the matrix of the elements on the right).

Here, the number of bits of the information bit and the number of bits of the parity bit among the code bits of the LDPC code of 1 code (1 codeword) are referred to as the information length K and the parity length M, respectively. At the same time, the number of code bits of one (1 codeword) LDPC code is called code length N (=K+M).

The information length K and parity length M of an LDPC code for a certain code length N are determined by the coding rate. In addition, the check matrix H is a matrix in which the rows × columns are M × N (M rows and N columns). Then, the information matrix H _{A is a} matrix of M×K, and the homology matrix H _T is a matrix of M×M.

FIG 11 based LDPC encoder 115 of FIG. 8 are used for parity check matrix H of an LDPC coded matrix H _T of the illustrated example.

As the parity matrix H _T used as the check matrix H used for the LDPC encoding in the LDPC encoder 115, for example, a parity matrix H that is the same as the check matrix H of the LDPC code specified in the specifications such as DVB-T.2 can be used. _T.

The parity matrix H _T of the inspection matrix H of the LDPC code specified in the specifications of DVB-T.2, etc., is shown in FIG. 11, and one element is a matrix of a staircase structure arranged in a so-called staircase ( lower bidiagonal matrix). The row weight of the homeomorphic matrix H _T is 1 for the first row and 2 for all the remaining rows. In addition, the column weight is 1 for the last column and 2 for all the remaining columns.

As described above, the parity matrix H _T of the parity check matrix H is as a stepped structure LDPC code, the parity check matrix H using the system, can be easily generated.

That is, the LDPC code (1 codeword) is expressed as a row vector c, and at the same time, the column vector obtained by transposing the row vector is expressed as c ^T. Furthermore, the LDPC code, which is the portion of the information bits in the row vector c, is represented by the row vector A, and at the same time, the portion of the co-located bits is represented by the row vector T.

In this case, the row vector c is defined by the row vector A as the information bit and the row vector T as the co-located bit, and the expression c = [A|T] (the elements of the row vector A can be regarded as The elements on the left are represented by the elements of the row vector T as the row vector of the elements on the right).

The inspection matrix H and the row vector c=[A|T] as the LDPC code must satisfy the formula Hc ^T =0, and the row vector c=[A|T] satisfying the formula Hc ^T =0 parity bits as the row vector T, based on the parity check matrix _{H = [H a | H T} ] with the bit matrix H _T, is presented a case where the stepped structure shown in FIG. 11, from the formula Hc ^T = 0 From the elements of the first row of the column vector Hc ^T , the elements of each row are sequentially changed to 0 one by one, by which they can be obtained one by one (sequentially).

FIG. 12 is an explanatory diagram of the check matrix H of the LDPC code specified in the specifications such as DVB-T.2.

For the KX column from the first column of the check matrix H of the LDPC code specified in the DVB-T.2 and other specifications, the series weight is X, and for the subsequent K3 column, the series weight is 3. After the M-1 column, the series weight is 2, and for the last column, the series weight is 1.

Here, KX+K3+M-1+1 is equal to the code length N.

13 is a diagram showing the number of columns KX, K3, and M, and the column weight X for each coding rate r of the LDPC code specified in the DVB-T.2 and other specifications.

In the specifications of DVB-T.2, etc., an LDPC code with a code length N of 64800 bits and 16200 bits is specified.

Then, for an LDPC code with a code length N of 64800 bits, there are 11 coding rates (nominal rate) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3 /4, 4/5, 5/6, 8/9, and 9/10, for LDPC codes with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5 , 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9.

Here, in the following, the code length N of 64800 bits is referred to as 64k bits, and the code length N of 16200 bits is referred to as 16k bits.

Regarding the LDPC code, there is a tendency that the error rate of the code bit corresponding to the column with the larger column weight of the check matrix H is lower.

In the inspection matrix H specified in the DVB-T.2 and other specifications shown in FIGS. 12 and 13, the closer the column to the beginning (left side), the greater the column weight tends to be. Therefore, regarding The LDPC code corresponding to the check matrix H has the more code bits at the beginning, the stronger the error (more resistant to errors), and the code bits closer to the end, the weaker the error.

<Co-located>

14 to 16, the co-located interleaving caused by the co-located interleaver 23 of FIG. 9 will be described.

Fig. 14 is a diagram showing an example of a bipartite graph (part of) of the check matrix of the LDPC code.

The inspection node is as shown in FIG. 14. If two complex numbers of variable nodes (corresponding code bits) connected to the inspection node become errors such as erasure at the same time, the inspection node All the variable nodes connected will reply to the message that the probability of 0 and the probability of 1 are equal probabilities. Therefore, if multiple variable nodes connected to the same inspection node become erased at the same time, the performance of decoding will deteriorate.

However, the LDPC code output by the LDPC encoder 115 of FIG. 8 is, for example, the same as the LDPC code specified in the specifications such as DVB-T.2, which is an IRA code, and the parity matrix H _{T of the} check matrix H, As shown in Fig. 11, it has a stepped structure.

FIG. 15 is a diagram showing an example of a bipartite graph of a collocation matrix H _T in a staircase structure and a collocation matrix H _T as shown in FIG. 11.

A line of FIG. 15 showing the same position as a stepped structure matrix H _T of example, B line in FIG. 15 showing the same bits of A of FIG. 15 the matrix H _T of the corresponding bipartite graph.

In the homeostasis matrix H _T in a staircase structure, tied in each row, the elements of 1 are adjacent (except the first row). Thus, in FIG bipartite matrix H _T of the parity, the parity matrix H _T corresponding to the value of a column of two adjacent elements 1, two adjacent variable nodes connected to the same line is a check node.

Therefore, if the parity bits corresponding to the two adjacent variable nodes at the same time become errors at the same time due to cluster errors or erasures, the two corresponding bits of the parity bits that become errors The inspection node connected to the variable node (the variable node that can use the same bit to find the message) will reply the inspection node with the message that the probability of 0 is equal to the probability of 1 The connected variable node, so the decoding performance will be degraded. Then, if the burst length (the number of bits of consecutive bits with errors that occur continuously) becomes larger, the number of check nodes that reply to messages of equal probability will increase, and the performance of decoding will be further deteriorated.

Therefore, the co-located interleaver 23 (FIG. 9) performs co-located interleaving of the co-located bits of the LDPC code from the LDPC encoder 115 to other co-located bits in order to prevent the deterioration of the decoding performance described above. .

Corresponding to the same bits of the LDPC code after parity interleaving lines in FIG. 16 with FIG. 9 bit interleaver 23 for check matrix H _T H matrix is illustrated.

Here, the information matrix H _A of the check matrix H corresponding to the LDPC code output by the LDPC encoder 115 is the information matrix of the check matrix H corresponding to the LDPC code specified in the specifications of DVB-T.2, etc. Similarly, it is a touring structure.

The so-called touring structure refers to a structure in which a certain column is the same as that obtained by cyclically shifting other columns, and also includes, for example: every P column, the position of 1 in each row of the P column is the column P In the first column, a cyclic displacement position is formed in the column direction with a predetermined value such as a value proportional to the value q obtained by dividing the parity length M. Hereinafter, it is appropriate to refer to the P column in the tour structure as a parallel factor.

The LDPC codes specified in the specifications such as DVB-T.2 are as shown in FIGS. 12 and 13, and there are two types of LDPC codes with a code length N of 64800 bits and 16200 bits. For any of the types of LDPC codes, the parallel factor P is defined as one of the factors except 1 and M, which is 360, among the factors of the parity length M.

In addition, the parity length M uses a value q that differs according to the coding rate, and is a value other than the prime number expressed by the formula M=q×P=q×360. Therefore, the value q is also the same as the parallel factor P. Among the factors of the parity length M, the other one of the factors except 1 and M is obtained by dividing the parity length M by the parallel factor P (parity length The factor of M, which is the product of P and q, is the parity length M).

The parity interleaver 23, as described above, makes the information length K, and let the integer above 0 and less than P be x. At the same time, let the integer above 0 and less than q be y. Among the code bits of the N-bit LDPC code, the K+qx+y+1 code bit is interleaved for the position of the K+Py+x+1 code bit.

The K+qx+y+1 code bit and the K+Py+x+1 code bit are all the K+1th and subsequent code bits, so they are co-located bits, therefore, With the co-location interleaving, the position of the co-location bits of the LDPC code will be shifted.

According to such co-located interleaving, the variable nodes (corresponding co-located bits) connected to the same check node will be far away from the parallel factor P, that is, here is far away from 360 bits, so if If the burst length is less than 360 bits, the variable node connected to the same check node can avoid multiple errors at the same time. As a result, the tolerance to burst errors can be improved.

In addition, the LDPC code after the K+qx+y+1 code bit and the K+Py+x+1 code bit are interleaved and co-interleaved is the same as the original check matrix H The K+qx+y+1 column is replaced with the K+Py+x+1 column, and the LDPC code of the check matrix (hereinafter also referred to as conversion check matrix) obtained by performing such column replacement is the same.

In addition, in the parity matrix of the conversion check matrix, as shown in FIG. 16, a pseudo tour structure in units of P columns (360 columns in FIG. 16) appears.

Here, the so-called quasi-tourism structure system means that, except for a part, the rest is a structure that exhibits a tour structure.

For the check matrix of the LDPC code specified in the specifications of DVB-T.2, etc., the conversion check matrix corresponding to the co-located interleaved column replacement is implemented, which is 360 rows × 360 columns in the upper right corner of the conversion check matrix In the part (displacement matrix described later), only one element of 1 (the element that becomes 0) is missing. In this regard, it is not a (complete) tour structure, but a so-called pseudo tour structure.

The conversion check matrix relative to the check matrix of the LDPC code output by the LDPC encoder 115 is, for example, the same as the conversion check matrix relative to the check matrix of the LDPC code specified in the specifications such as DVB-T.2, It is a virtual tour structure.

In addition, the conversion check matrix of FIG. 16 is implemented on the original check matrix H in addition to performing column replacement equivalent to co-located interleaving, and is used to make the conversion check matrix into what is required by the configuration matrix described later. Row replacement (row replacement), the resulting matrix.

FIG. 17 is a flowchart for explaining the processing performed in the LDPC encoder 115, the bit interleaver 116, and the mapper 117 of FIG.

The LDPC encoder 115 waits for the LDPC object data to be supplied from the BCH encoder 114. In step S101, the LDPC object data is encoded into an LDPC code based on the check matrix, and the LDPC code is supplied to the bit interleaver 116. The system proceeds to step S102.

The bit interleaver 116, in step S102, performs bit interleaving on the LDPC code from the LDPC encoder 115, and supplies the symbols obtained by the bit interleaving to the mapper 117. Proceed to step S103.

That is, in step S102, in the bit interleaver 116 (FIG. 9), the co-located interleaver 23 takes the LDPC code from the LDPC encoder 115 as an object, performs co-located interleaving, and interleaves the co-located LDPC code ，送给集团式Interleaver 24.

The group interleaver 24 takes the LDPC code from the co-located interleaver 23 as an object, performs group interleaving, and supplies it to the block interleaver 25.

The block interleaver 25 takes the LDPC code after group interleaving performed by the group interleaver 24 as an object, performs block interleaving, and supplies the resulting m-bit symbols to the mapper 117.

The mapper 117 maps the symbols from the block interleaver 25 to 2 ^m signal points determined by the modulation method of the quadrature modulation performed by the mapper 117 in step S103 Either one performs quadrature modulation, and supplies the data obtained as a result to the time interleaver 118.

As described above, by performing co-located interleaving or group interleaving, the error rate when transmitting a plurality of code bits of the LDPC code as one symbol can be improved.

Here, in FIG. 9, for the convenience of explanation, the block performing the co-interleaving is the co-locating interleaver 23, and the block performing the group-type interlacing is the group-type interleaver 24, drawn individually However, the co-located interleaver 23 and the group interleaver 24 may be integrated.

That is to say, co-located interleaving and group interleaving can be performed by writing and reading out code bits of the memory, and by writing addresses of code bits ( Write address), which is converted into a matrix of addresses (read addresses) for reading out code bits.

Therefore, if the matrix representing the co-located interlace and the matrix obtained by multiplying the matrix representing the group interlace are obtained in advance, the code bits can be converted by these matrices to perform co-located interlace. The result of group interleaving the LDPC code after interleaving the same bit is obtained.

In addition to the co-located interleaver 23 and the group-type interleaver 24, the block interleaver 25 may also be integrally configured.

That is, the block interleaving performed by the block interleaver 25 can also be expressed by converting the write address of the memory storing the LDPC code into a matrix of read addresses.

Therefore, if the matrix obtained by multiplying the matrix representing the interlace interlace, the matrix representing the group interlace, and the matrix representing the block interlace is obtained in advance, then these matrices can be used to perform the interlace interlace and group at a stretch. Group interleaving, and block interleaving.

In addition, one or the amount of co-located interleaving and group interleaving may not be performed.

<Configuration example of LDPC encoder 115>

FIG. 18 is a block diagram of a configuration example of the LDPC encoder 115 of FIG. 8.

In addition, the LDPC encoder 122 of FIG. 8 is also configured in the same manner.

As explained in FIGS. 12 and 13, DVB-T.2 and other specifications are defined as LDPC codes of two code lengths N of 64800 bits and 16200 bits.

Then, for an LDPC code with a code length N of 64800 bits, there are 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 /5, 5/6, 8/9, and 9/10, for LDPC codes with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2 , 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 (Figures 12 and 13).

The LDPC encoder 115 is, for example, an encoding (error correction encoding) caused by such an LDPC code having a code length N of 64800 bits or 16200 bits at each encoding rate, based on each code length N and each code The inspection matrix H prepared at a rate can be carried out.

In addition, the LDPC encoder 115 can be based on a code length N of any code length N other than 17280 bits, and the coding rate is 2/16, 3/16, 4/16, 5/16, 6/16, 7/ LDPC encoding is performed by checking matrix H of LDPC codes of 16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 at other arbitrary encoding rates r.

The LDPC encoder 115 is composed of an encoding processing unit 601 and a storage unit 602.

The encoding processing unit 601 is composed of: an encoding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, an encoding parity calculation unit 615, and a control unit 616 The LDPC code of the LDPC object data supplied to the LDPC encoder 115 is supplied to the bit interleaver 116 (FIG. 8).

That is, the coding rate setting unit 611 sets the code length N or the coding rate r of the LDPC code according to, for example, the operation of the operator, and also has specific information for specifying the LDPC code.

The initial value table reading unit 612 reads the inspection matrix initial value table, which will be described later, from the memory unit 602 to indicate the inspection matrix of the LDPC code specified by the specific information set by the coding rate setting unit 611.

The inspection matrix generation unit 613 generates an inspection matrix H based on the inspection matrix initial value table read by the initial value table reading unit 612, and stores it in the memory unit 602. For example, the check matrix generation unit 613 is the information matrix H _A corresponding to the information length K (= code length N-co-location length M) corresponding to the code length N set by the encoding rate setting unit 611 and the encoding rate r The elements are arranged in the column direction every 360 columns (parallel factor P) to generate a check matrix H, which is stored in the memory unit 602.

The information bit reading unit 614 reads (extracts) information bits of the information length K from the LDPC object data supplied to the LDPC encoder 115.

The coded parity calculation unit 615 reads the inspection matrix H generated by the inspection matrix generation unit 613 from the storage unit 602, and uses the inspection matrix H to target the information bits read by the information bit reading unit 614 The parity bit of is calculated based on the predetermined formula, thereby generating a codeword (LDPC code).

The control unit 616 controls each block constituting the encoding processing unit 601.

The memory section 602 stores, for example, for each code length N of 64800 bits or 16200 bits, the complex value check matrix initial value table corresponding to the complex code rate shown in FIG. 12 and FIG. 13 respectively, or For code length N of 17280 bits, the coding rate is 2/16, 3/16, 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11 The initial check table of the check matrix H of the check matrix initial value table corresponding to /16, 12/16, 13/16, and 14/16, and the check matrix H of the other LDPC codes of any code length N and arbitrary coding rate r. In addition, the memory unit 602 temporarily stores data necessary for processing by the encoding processing unit 601.

FIG. 19 is a flowchart for explaining an example of processing of the LDPC encoder 115 of FIG. 18.

In step S201, the coding rate setting unit 611 sets the code length N and the coding rate r for LDPC coding, and other specific information that specifies the LDPC code.

In step S202, the initial value table reading unit 612 will be specified by the code length N and the coding rate r, etc. of the specific information that has been set by the coding rate setting unit 611, and has been determined in advance. The matrix initial value table is read from the memory unit 602.

In step S203, the inspection matrix generation unit 613 uses the initial value table reading unit 612 to read out the initial value table of the inspection matrix read from the memory unit 602 to obtain (generate) the code set by the coding rate setting unit 611 The check matrix H of the LDPC code of length N and coding rate r is supplied to the storage unit 602 and stored.

In step S204, the information bit reading unit 614, from the LDPC object data supplied to the LDPC encoder 115, the information length corresponding to the code length N and the coding rate r set by the coding rate setting unit 611 The information bits of K (=N×r) are read out, and the check matrix H obtained by the check matrix generating section 613 is read out from the memory section 602 and supplied to the code parity calculation section 615.

In step S205, the coding parity calculation unit 615 uses the information bits from the information bit reading unit 614 and the check matrix H to sequentially calculate the parity bits of the codeword c satisfying the equation (8).

In equation (8), the c system represents a row vector as a codeword (LDPC code), and the c ^T system represents a transposition of the row vector c.

Here, as described above, the portion of the information bit in the row vector c of the LDPC code (1 codeword) is represented by the row vector A, and at the same time, the portion of the co-located bit is represented by the row vector T In the case of, the row vector c can be expressed by the formula c = [A|T] by the row vector A as the information bit and the row vector T as the co-location bit.

The inspection matrix H and the row vector c=[A|T] as the LDPC code must satisfy the formula Hc ^T =0, and the row vector c=[A|T] satisfying the formula Hc ^T =0 parity bits as the row vector T, based on the parity check matrix _{H = [H a | H T} ] with the bit matrix H _T, is presented a case where the stepped structure shown in FIG. 11, from the formula Hc ^T = 0 Starting from the element of the first row of the column vector Hc ^T , the elements of each row are sequentially changed to 0 one by one, which can be obtained one by one.

The coded parity calculation unit 615 finds the parity bit T for the information bit A from the information bit readout unit 614, and the code word c that will be represented by the information bit A and the parity bit T = [A|T] is output as the result of LDPC encoding of information bit A.

Thereafter, in step S206, the control unit 616 determines whether the LDPC encoding has ended. In step S206, if it is determined that the LDPC encoding is not to be ended, that is, for example, if there is LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204), and the following is repeated The processing from step S201 (or step S204) to S206.

In addition, in step S206, if it is determined that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the processing.

For the LDPC encoder 115, it is possible to prepare in advance a table of initial values of inspection matrices (indicating inspection matrices) of various LDPC codes of code length N or coding rate r. In the LDPC encoder 115, it is possible to perform LDPC encoding of various LDPC codes with a code length N or an encoding rate r using the check matrix H generated by the initial value table of the check matrix prepared before the process.

<Example of initial value table of inspection matrix>

The check matrix initial value table is, for example, the check matrix H, the information matrix H corresponding to the information length K corresponding to the code length N and the coding rate r of the LDPC code (LDPC code defined by the check matrix H) The position of the element 1 in _A (Fig. 10) is expressed in 360 columns (parallel factor P). It is prepared in advance for each check matrix H for each code length N and each coding rate r .

That is, the initial value table of the check matrix is to represent at least the position of the element 1 of the information matrix H _A every 360 columns (parallel factor P).

In addition, in the inspection matrix H, all of the homology matrix H _T are inspection matrices in a staircase structure, or a part of the homology matrix H _T is in a ladder structure, and the remaining part is a diagonal matrix (unit matrix) Check the matrix.

Hereinafter, the expression method of the initial value table of the inspection matrix indicating that a part of the co-location matrix H _T has a staircase structure and the remaining portion is a diagonal inspection matrix is also referred to as a type A method. In addition, the expression system of the initial value table of the inspection matrix indicating that all of the co-location matrix H _T is an inspection matrix having a staircase structure is also referred to as a type B system.

In addition, the LDPC code for the check matrix represented by the initial value table of the check matrix of type A method is also called type A code, and the LDPC code for the check matrix represented by the initial value table of the check matrix of type B method is also Called type B code.

The terms "Type A" and "Type B" are based on ATSC 3.0 specifications. For example, in ATSC3.0, both type A code and type B code will be used.

In addition, in DVB-T.2, etc., type B codes are used.

FIG. 20 is a diagram showing an example of the initial value table of the inspection matrix of the type B method.

That is, FIG. 20 illustrates that, as specified in the DVB-T.2 specification, the code length N is 16200 bits, and the coding rate (DVB-T.2 representation coding rate) r is 1 /4 type B code (indicating the check matrix H) check matrix initial value table.

The inspection matrix generation unit 613 (FIG. 18) uses the inspection matrix initial value table of the type B method, and obtains the inspection matrix H as shown below.

FIG. 21 is an explanatory diagram of a method of obtaining the inspection matrix H from the initial value table of the inspection matrix of the type B method.

That is, FIG. 21 illustrates the initial value table of the check matrix of the type B code specified in the DVB-T.2 specification and having a code length N of 16,200 bits and an encoding rate r of 2/3.

The initial value table of the check matrix of the type B method is the position of the total 1 element of the information matrix H _A corresponding to the information length K corresponding to the code length N and the coding rate r of the LDPC code, every 360 rows (parallel factor P) The table represented by the line i is the row number of the element 1 in the 1+360×(i-1) column of the check matrix H (let the row number of the 1st row of the check matrix H) (The row number when it is 0), the number of column weights that the column arranged to reach the 1+360×(i-1) column has.

Here, for the inspection matrix H of the type B method, the co-location matrix H _T (FIG. 10) corresponding to the co-location length M is determined as a staircase structure as shown in FIG. 15, so if the initial value of the inspection matrix can be used Table, and the information matrix H _A (FIG. 10) corresponding to the information length K can be obtained, and the check matrix H can be obtained.

The number of rows k+1 of the initial value table of the check matrix of the type B method varies with the information length K.

The relationship between the information length K and the number of rows k+1 of the initial value table of the check matrix is the relationship of formula (9).

Here, 360 in equation (9) is the parallel factor P described in FIG. 16.

In the initial value table of the inspection matrix in FIG. 21, 13 values are arranged in rows 1 to 3, and in rows 4 to k+1 (line 30 in FIG. 21), There are 3 values in the system.

Therefore, the column weight of the inspection matrix H obtained from the initial value table of the inspection matrix in FIG. 21 is from the first column to the first +360×(3-1)-1 column, and the system is 13; Column 1+360×(3-1), up to column K, is 3.

The first row of the initial value table of the inspection matrix in FIG. 21 is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622. This is shown in the inspection matrix H In the first column, the row number is 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622. The element system of the row is 1 (and the other element systems are 0).

In addition, the second row of the initial value table of the inspection matrix of FIG. 21 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108. Elements in row 361 (=1+360×(2-1)) of matrix H with row numbers 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, and 3108 Department is 1.

As described above, the initial value table of the inspection matrix indicates the position of the element 1 of the information matrix H _A of the inspection matrix H every 360 columns.

The columns other than the 1+360×(i-1) column of the inspection matrix H, that is, the columns from the 2+360×(i-1) column to the 360×i column will be determined by The element 1 in the 1+360×(i-1) column determined by checking the initial value table of the matrix is configured by periodically shifting downward in accordance with the parity length M (downward direction of the column).

That is, for example, the 2+360×(i-1) column is formed by cyclically shifting the 1+360×(i-1) column in the downward direction by M/360 (=q), followed by Column 3+360×(i-1) is formed by cyclically shifting the 1+360×(i-1) column downward by 2×M/360 (=2×q) (the second +360×(i-1) column, made by M/360 (=q) cyclic displacement in the downward direction).

Now, the value of the jth column (jth from the left) of the i-th row (i-th from the top) of the initial value table of the matrix will be checked and expressed as h _i,j . At the same time, the matrix H In the w column, the row number of the element of the jth 1 is represented by H _wj , then the column other than the 1+360×(i-1) column of the check matrix H is the w column, 1 The line number H _{wj of the} element can be obtained by equation (10).

Here, mod(x, y) means that the remainder after dividing x by y.

In addition, the P system is the above-mentioned parallel factor. In the present embodiment, it is, for example, 360 as in the specifications of DVB-T.2 or the like or ATSC3.0. Furthermore, q is the value M/360 obtained by dividing the parity length M by the parallel factor P (=360).

The inspection matrix generation unit 613 (FIG. 18) specifies the row number of the element 1 in the 1+360×(i-1) column of the inspection matrix H by the inspection matrix initial value table.

Then, the check matrix generation unit 613 (FIG. 18) sets the row number H _wj of the element of 1 in the column other than the 1+360×(i-1) column of the check matrix H, which is the w column, according to the formula (10) It is obtained, and a check matrix H with the element of the row number obtained above set to 1 is generated.

22 is a diagram showing the structure of the inspection matrix H of the type A method.

The type A inspection matrix is composed of A matrix, B matrix, C matrix, D matrix, and Z matrix.

The A matrix is a matrix of M1 rows and K columns represented by the predetermined value M1 and the information length K of the LDPC code K=code length N×encoding rate r, and the upper left matrix of the check matrix H.

The B matrix is a matrix of ladder structures adjacent to the right of the A matrix in the M1 row and M1 column.

The C matrix is an N-K-M1 row with K+M1 columns, and an adjacent matrix below the A matrix and the B matrix.

The D matrix is a unit matrix adjacent to the right of the C matrix in rows N-K-M1 and columns N-K-M1.

The Z matrix is a zero matrix (matrix 0) adjacent to the right of the B matrix in M1 rows and N-K-M1 columns.

As in the inspection matrix H of type A composed of the A matrix to the D matrix and the Z matrix above, a part of the A matrix and the C matrix constitute the information matrix; the remaining parts of the B matrix and the C matrix, D The matrix, and the Z matrix, constitute the co-location matrix.

In addition, the B matrix is a matrix with a staircase structure, and the D matrix is an identity matrix. Therefore, a part of the parity matrix of the inspection matrix H of type A (part of the B matrix) is a staircase structure, and the rest (part of the D matrix) ) Is a diagonal matrix (identity matrix).

The A matrix and the C matrix are the same as the information matrix of the inspection matrix H of the type B method, which is a tour structure for each parallel factor P column (such as 360 columns). The initial value table of the inspection matrix of the type A method will be The positions of the 1 elements of the A matrix and the C matrix are shown every 360 columns.

Here, as described above, a part of the A matrix and the C matrix constitute the information matrix, so the initial value table of the type A method inspection matrix is represented by the position of the element 1 of the A matrix and the C matrix every 360 columns. , At least the position of element 1 of the information matrix can be represented every 360 columns.

In addition, the initial value table of the inspection matrix of the type A method represents the position of the element 1 of the A matrix and the C matrix every 360 columns. Therefore, one part of the inspection matrix (the remaining part of the C matrix) can be divided into 1 The position of the element is indicated every 360 columns.

23 is a diagram showing an example of the initial value table of the inspection matrix of the type A method.

That is, FIG. 23 is a diagram showing an example of a check matrix initial value table showing a check matrix H with a code length N of 35 bits and a coding rate r of 2/7.

The initial value table of the inspection matrix of type A method is a table that represents the position of the element 1 of the A matrix and the C matrix every parallel factor P, and in the i-th row, there is the 1+P of the inspection matrix H The row number of the element 1 in the ×(i-1) column (the row number when the row number in the first row of the check matrix H is 0) is arranged up to the row in the first +P×(i-1) column The number of column weights that the column has.

In addition, in order to simplify the description here, the parallel factor P is assumed to be 5, for example.

Regarding the inspection matrix H of the type A method, as parameters, there are M1, M2, Q1, and Q2.

M1 (Figure 22) is a parameter that determines the size of the B matrix and is a value that is a multiple of the parallel factor P. By adjusting M1, the performance of the LDPC code will change, and the decision check matrix H will be adjusted to the predetermined value. Here, as M1, it is assumed that the parallel factor P=15 which is 3 times of 5 is used.

M2 (Fig. 22) is taken from the parity length M and subtracted from M1 to the value M-M1.

Here, the information length K system is N×r=35×2/7=10, and the parity length M system is N-K=35-10=25, so the M2 system is M-M1=25-15=10.

Q1 is obtained according to the formula Q1=M1/P, and represents the displacement number (row number) of the cyclic displacement in the A matrix.

That is, columns other than the 1+P×(i-1) column of the A matrix of the inspection matrix H of the type A method, that is, from the 2+P×(i-1) column to the P×i column Each column up to this point is to periodically shift the element of the 1 in the 1+P×(i-1) column determined by checking the matrix initial value table in the downward direction (downward direction of the column) Configured, Q1 represents the displacement number of the cyclic displacement in the A matrix.

Q2 is obtained according to the formula Q2=M2/P, and represents the displacement number (row number) of the cyclic displacement in the C matrix.

That is, columns other than the 1+P×(i-1) column of the C matrix of the inspection matrix H of the type A method, that is, from the 2+P×(i-1) column to the P×i column Each column up to this point is to periodically shift the element of the 1 in the 1+P×(i-1) column determined by checking the matrix initial value table in the downward direction (downward direction of the column) Configured, Q2 represents the displacement number of the cyclic displacement in the C matrix.

Here, for the Q1 system, M1/P=15/5=3, and for the Q2 system, M2/P=10/5=2.

In the initial value table of the inspection matrix of FIG. 23, in the first and second rows, three values are arranged, and in the third to fifth rows, one value is arranged. For the arrangement of the numerical values, the column weights of the A matrix and the C matrix of the inspection matrix H obtained from the initial value table of the inspection matrix in FIG. 23 are from the first column = 1 + 5 × (1-1) to It is 3 until the 10th column = 5 × 2 columns; it is 1 from the 11th column = 1 + 5 × (3-1) to the 25th column = 5 × 5 columns.

That is, the first row of the initial value table of the inspection matrix of FIG. 23 is 2, 6, 18, which means that in the first column of the inspection matrix H, the row numbers are 2, 6, 18 The element system is 1 (and the other element systems are 0).

Here, in the current situation, the A matrix (Figure 22) is a matrix of 15 rows and 10 columns (M1 row and K columns), and the C matrix (Figure 22) is a matrix of 10 rows and 25 columns (NK-M1 row K+M1 Column) matrix, therefore, the row of the check matrix H with row numbers 0 to 14 is the row of the A matrix, and the row of the check matrix H with row numbers 15 to 24 is the row of the C matrix.

Therefore, among the rows with row numbers 2, 6, and 18 (hereinafter described as rows #2, #6, and #18), rows #2 and #6 are the rows of the A matrix, and row #18 is the C The rows of the matrix.

The second row of the initial value table of the inspection matrix in FIG. 23 is 2, 10, and 19, which is shown in the sixth (=1+5×(2-1)) column of the inspection matrix H, row # 2. The element system of #10 and #19 is 1.

Here, in the sixth (=1+5×(2-1)) column of the inspection matrix H, among the rows #2, #10, and #19, rows #2 and #10 are the rows of the A matrix , Row #19, is the row of the C matrix.

The third row of the initial value table of the inspection matrix of FIG. 23 is 22, which shows that in the 11th (=1+5×(3-1)) column of the inspection matrix H, the element system of row #22 Is 1.

Here, in the 11th (=1+5×(3-1)) column of the inspection matrix H, row #22 is the row of the C matrix.

Similarly in the following, 19 in the 4th row of the initial value table of the inspection matrix of FIG. 23 indicates that the element system of row #19 is 1 in the 16th (=1+5×(4-1)) column of the inspection matrix H 15 in the fifth row of the initial value table of the inspection matrix of FIG. 23 indicates that the element system of row #15 is 1 in the 21st (=1+5×(5-1)) column of the inspection matrix H.

As described above, the initial value table of the inspection matrix shows the positions of the elements of the A matrix and the C matrix 1 of the inspection matrix H for every parallel factor P=5 columns.

Check the columns other than the 1+5×(i-1) column of the A matrix and C matrix of the check matrix H, that is, the columns from the 2+5×(i-1) column to the 5×i column The column is the element of column 1+5×(i-1) determined by checking the initial value table of the matrix, according to the parameters Q1 and Q2, it is directed downward (downward direction of the column), periodically Cyclic displacement is configured.

That is, for example, the 2+5×(i-1) column of the A matrix is formed by cyclically shifting the 1+5×(i-1) column downward by Q1 (=3), and then Column 3+5×(i-1) is formed by cyclically shifting the 1+5×(i-1) column downward by 2×Q1 (=2×3) (the 2+ Column 5×(i-1), made by cyclic displacement of Q1 in the downward direction).

Also, for example, the 2+5×(i-1) column of the C matrix is obtained by cyclically shifting the 1+5×(i-1) column downward by Q2 (=2), followed by Column 3+5×(i-1) is formed by cyclically shifting the 1+5×(i-1) column downward by 2×Q2 (=2×2) (the 2+5 Column ×(i-1), made by cyclic displacement of Q2 in the downward direction).

FIG. 24 is a diagram of the A matrix generated from the initial value table of the inspection matrix of FIG. 23.

In the A matrix of FIG. 24, according to the first row of the initial value table of the inspection matrix of FIG. 23, the element system of rows #2 and #6 in the first (=1+5×(1-1)) column is 1.

Then, from the 2nd column (=2+5×(1-1)) to the 5th column (=5+5×(1-1)), the previous column is Q1=3. Cyclic displacement in the downward direction.

Then, in the A matrix of FIG. 24, according to the second row of the initial value table of the check matrix of FIG. 23, the elements of rows #2 and #10 in the sixth (=1+5×(2-1)) column are: 1.

Then, from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column, the previous column is Q1=3. Cyclic displacement in the downward direction.

Fig. 25 is a diagram showing the co-interleaving of the B matrix.

The inspection matrix generating unit 613 (FIG. 18) generates an A matrix using the initial value table of the inspection matrix, and arranges the B matrix in a staircase structure to the right of the A matrix. Then, the check matrix generating section 613 regards the B matrix as a co-occurrence matrix, so that the adjacent 1 elements of the B-matrix of the staircase structure will be co-interleaved in a row direction away from the parallel factor P=5 .

FIG. 25 is a diagram illustrating the A matrix and the B matrix of the B matrix of FIG. 24 after being co-interleaved.

FIG. 26 is a diagram of the C matrix generated from the check matrix initial value table of FIG. 23.

In the C matrix of FIG. 26, according to the first row of the initial value table of the inspection matrix of FIG. 23, the element system of row #18 of the first (=1+5×(1-1)) column of the inspection matrix H is 1 .

Then, from the 2nd (=2+5×(1-1)) column to the 5th (=5+5×(1-1)) column of the C matrix, the previous column is taken as Q2= 2 cyclic displacement of the downward direction.

Then, in the C matrix of FIG. 26, according to the second row to the fifth row of the initial value table of the inspection matrix of FIG. 23, the row #6 (=1+5×(2-1)) of the matrix H is checked. 19. Row #22 in the 11th (=1+5×(3-1)) column, row #19 in the 16th (=1+5×(4-1)) column, and 21st (=1+5 The element system of row #15 in the ×(5-1)) column is 1.

Then, from the 7th (=2+5×(2-1)) column to the 10th (=5+5×(2-1)) column, the 12th (=2+5×(3) -1)) to the 15th column (=5+5×(3-1)), from the 17th (=2+5×(4-1)) column to the 20th (=5+5 ×(4-1)) columns and columns from the 22nd (=2+5×(5-1)) column to the 25th (=5+5×(5-1)) column , Which is formed by circularly displacing the previous column in the downward direction with Q2=2.

The inspection matrix generation unit 613 (FIG. 18) uses the initial value table of the inspection matrix to generate the C matrix, and arranges the C matrix under the A matrix and the B matrix (after the same-position interleaving).

Then, the inspection matrix generation unit 613 arranges the Z matrix to the right of the B matrix, and at the same time, arranges the D matrix to the right of the C matrix to generate the inspection matrix H shown in FIG. 26.

Fig. 27 is a diagram showing the co-interleaving of the D matrix.

The inspection matrix generating section 613, after generating the inspection matrix H of FIG. 26, regards the D matrix as a homo-location matrix, so that the odd-numbered row of the D matrix of the identity matrix and the element 1 of the next even-numbered row will be in the row direction , Away from the way of parallelism factor P=5, the same-position interleaving (only for D matrix) is performed.

FIG. 27 illustrates the inspection matrix H after the parity interleaving of the D matrix is performed on the inspection matrix H of FIG. 26.

The LDPC encoder 115 (the coding parity calculation unit 615 (FIG. 18 )) performs LDPC coding (generation of LDPC code) using the check matrix H of FIG. 27, for example.

Here, the LDPC code generated using the check matrix H of FIG. 27 is an LDPC code that has been co-interleaved. Therefore, the LDPC code generated using the check matrix H of FIG. 27 is tied to the co-located interleaver 23 In (Figure 9), there is no need to perform interleaving. That is, the LDPC code generated using the check matrix H after performing the co-interleaving of the D matrix becomes the LDPC code having undergone the co-interleaving. Therefore, regarding the LDPC code, the co-locating interleaving in the co-locating interleaver 23, The department was skipped.

FIG. 28 is a part of the B matrix and the C matrix of the inspection matrix H of FIG. 27 (the part arranged under the B matrix among the C matrix), and the D matrix, which are restored as the interlaced An illustration of the check matrix H formed by column permutation of the same-position deinterleaved columns.

In the LDPC encoder 115, by using the check matrix H of FIG. 28, LDPC encoding (generation of LDPC codes) can be performed.

When the LDPC coding is performed using the check matrix H of FIG. 28, according to the LDPC coding, an LDPC code that is not co-interleaved can be obtained. Therefore, when LDPC encoding is performed using the check matrix H of FIG. 28, the co-located interleaver 23 (FIG. 9) performs co-located interleaving.

FIG. 29 is a diagram of the conversion inspection matrix H obtained by performing row permutation on the inspection matrix H of FIG. 27.

The conversion check matrix, as described later, is obtained by using: an identity matrix of P×P, one or more quasi-identity matrices that become 0 among the ones of the identity matrix, and a cyclic shift of the identity matrix or quasi-identity matrix A matrix represented by a combination of a displacement matrix, an identity matrix, a quasi-unit matrix, or a sum matrix of two or more of the displacement matrix and a P×P zero matrix.

The conversion check matrix is used to decode the LDPC code. In the decoding of the LDPC code, as will be described later, it is possible to adopt an architecture in which the check node calculation and the variable node calculation are performed simultaneously.

<New LDPC code>

In data transmission using LDPC codes, as a method of ensuring good communication quality, there is a method of using LDPC codes with good performance.

The following describes a new LDPC code with good performance (hereinafter also referred to as a new LDPC code).

As the new LDPC code system, for example, the parallel factor P is the same 360 as DVB-T.2 or ATSC3.0, and the type A code or type B code corresponding to the inspection matrix H of the tour structure.

LDPC encoder 115 (Figures 8 and 18), the code length N can be longer than 64k bits, for example 69120 bits, and the coding rate r is for example 2/16, 3/16, 4/16, New LDPC code for any of 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16 The initial value table of the check matrix (the check matrix H obtained from it) is used to perform LDPC encoding to the LDPC code.

Also, the LDPC encoder 115, as shown below, can be based on the code length N being shorter than 64k bits, for example, 17280 bits (17k bits), and the coding rate r is, for example, 2/16, 3/16 , 4/16, 5/16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, or 14/16 The initial value table of the check matrix of the new LDPC code (the check matrix H obtained from it) is used to perform LDPC encoding to the new LDPC code.

When LDPC encoding is performed on a new LDPC code having a code length N of 17280 bits, the memory 602 of the LDPC encoder 115 (FIG. 8) stores the check matrix initial value table of the new LDPC code.

FIG. 30 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=2/16) whose code length N is 17280 bits and code rate r is 2/16 as a new LDPC code A diagram showing an example of the initial value table of the inspection matrix (of type A method).

FIG. 31 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=3/16) that has a code length N of 17280 bits and an encoding rate r of 3/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 32 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=4/16) that has a code length N of 17280 bits and an encoding rate r of 4/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 33 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=5/16) that has a code length N of 17280 bits and an encoding rate r of 5/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 34 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=6/16) that has a code length N of 17280 bits and an encoding rate r of 6/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 35 is a check matrix H of a type A code (hereinafter also referred to as a type A code with r=7/16) that has a code length N of 17280 bits and an encoding rate r of 7/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 36 is a check matrix H of a type B code (hereinafter also referred to as a type B code of r=7/16) with a code length N of 17280 bits and a coding rate r of 7/16 as a new LDPC code A diagram showing an example of the initial value table of the inspection matrix (of type B method).

FIG. 37 is a check matrix H of a type B code (hereinafter also referred to as a type B code with r=8/16) that has a code length N of 17280 bits and an encoding rate r of 8/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 38 is a check matrix H of a type B code (hereinafter also referred to as a type B code with r=9/16) as a new LDPC code with a code length N of 17280 bits and an encoding rate r of 9/16 An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 39 is a check matrix H for a type B code (hereinafter also referred to as a type B code with r=10/16) that has a code length N of 17280 bits and an encoding rate r of 10/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 40 is a check matrix H for a type B code (hereinafter also referred to as a type B code with r=11/16) as a new LDPC code with a code length N of 17280 bits and an encoding rate r of 11/16 An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 41 is a check matrix H of a type B code (hereinafter also referred to as a type B code with r=12/16) as a new LDPC code with a code length N of 17280 bits and an encoding rate r of 12/16 An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 42 is a check matrix H for a type B code (hereinafter also referred to as a type B code with r=13/16) that has a code length N of 17280 bits and an encoding rate r of 13/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

FIG. 43 is a check matrix H of a type B code (hereinafter also referred to as a type B code with r=14/16) that has a code length N of 17280 bits and an encoding rate r of 14/16 as a new LDPC code An illustration of an example of the initial value table of the inspection matrix shown.

The new LDPC code is an LDPC code with good performance.

Here, the LDPC code with good performance is an LDPC code obtained from an appropriate check matrix H.

The so-called appropriate check matrix H system is, for example, when the LDPC code obtained from the check matrix H is transmitted at a low E _s /N ₀ or E _b /N _o (signal power per one bit to noise power ratio) To make the BER (bit error rate) (and FER (frame error rate)) smaller, and the check matrix that meets the specified conditions.

The appropriate inspection matrix H can be obtained by, for example, measuring LDPC codes obtained from various inspection matrices that satisfy the specified conditions and BER simulation when transmitting at a low E _s /N _o Out.

The predetermined conditions that should be satisfied as the appropriate check matrix H are, for example: the analytical result obtained by the analytical method of the performance of a code called density evolution (Density Evolution) is good, and the other is called cycle 4. The loop system of the element of 1 is absent.

Here, in the information matrix H _A , it is known that if the elements of 1 are densely distributed like the cycle 4, the decoding performance of the LDPC code will be degraded. Therefore, it is preferable that the cycle 4 does not exist in the inspection matrix H system.

In the inspection matrix H, the minimum value of the loop length (loop length) composed of the elements of 1 is called the girth. Cycle 4 does not exist, which means the girth is greater than 4.

In addition, the predetermined conditions that the appropriate inspection matrix H should satisfy can be appropriately determined from the viewpoint of improvement of the decoding performance of the LDPC code or ease of decoding processing of the LDPC code (simplification).

FIGS. 44 and 45 are explanatory diagrams of density evolution obtained as an analysis result of a predetermined condition that the appropriate inspection matrix H should satisfy.

The so-called density evolution is a code analysis method that calculates the expected value of the error probability of the entire LDPC code (ensemble) whose code length N, which is a feature of a degree sequence described later, is ∞.

For example, on the AWGN channel, if the dispersion value of the noise is gradually increased from 0, the expected value of the overall error probability, although initially 0, but once the dispersion value of the noise reaches a certain threshold (threshold) Above, it is no longer 0.

According to the density evolution, the overall performance can be determined by comparing the expected value of the error probability to a value other than 0, and the threshold of the dispersion value of the noise (hereinafter also referred to as the performance threshold). ) Good or bad.

In addition, for a specific LDPC code, the overall performance of the LDPC code can be predicted by determining the entirety to which the LDPC code belongs and performing density evolution on the entirety.

Therefore, if the LDPC code with good performance can be found in the whole with good performance, it can be found from the LDPC code to which the whole belongs.

Here, the so-called frequency sequence system indicates the ratio of the variable node or the check node having the weight of each value to the code length N of the LDPC code.

For example, the regular(3,6) LDPC code system with a coding rate of 1/2 is subordinated to it. The weight of all variable nodes (column weight) is 3, and the weight of all inspection nodes (row weight) is 6. The whole feature is given by this one-degree sequence.

Fig. 44 illustrates such an overall biner graph (Tanner graph).

In the bipartite graph of FIG. 44, there are N variable nodes indicated by the circle marks (○ marks) in the figure, which are exactly equal to the code length N, and there are check nodes shown by squares (□ marks) in the figure. It is exactly equal to N/2 of the multiplied value obtained by multiplying the code length N by the coding rate 1/2.

On each variable node, the system is connected with three branches equal to the column weights. Therefore, all the branches connected to the N variable nodes only have 3N branches.

In addition, at each inspection node, the system is connected with 6 branches equal to the row weight. Therefore, for the branches connected to the N/2 inspection nodes, there are only 3N branches.

Then, in the bipartite graph of FIG. 44, there is one interleaver.

The interleaver randomly sorts the 3N branches connected to the N variable nodes, and connects the sorted branches to the 3N branches connected to the N/2 check nodes. Any one.

The sorting pattern in the interleaver that sorts the 3N branches connected to the N variable nodes is (3N)! (=(3N)×(3N-1)×・・・×1) Species. Therefore, the totality of features given by such a degree sequence in which the weight of all variable nodes is 3 and the weight of all check nodes is 6 is a set of (3N)! LDPC codes.

In the simulation for obtaining a good performance LDPC code (suitable check matrix), it is used in the evolution of density, and the entire multi-edge type is used.

In the multi-branch type, the branch connected to the variable node and the branch connected to the branch connected to the check node are divided into multiple edges, by which the overall characteristics are given Can be carried out more rigorously.

Fig. 45 is a diagram illustrating an example of a bipartite graph of the entire multi-branched type.

In the bipartite graph of FIG. 45, there are two interleavers including a first interleaver and a second interleaver.

Also, in the bipartite graph of FIG. 45, there are only one variable node system with one branch connected to the first interleaver and zero branch connected to the second interleaver, and the first interleaved The number of branches connected to the interleaver is one, and the number of branches connected to the second interleaver is two. There are only v2 variable nodes. The number of branches connected to the first interleaver is zero, and the number of branches 2 The variable node system with two branches connected to the interleaver has only v3, and exists separately.

Then, in the bipartite graph of FIG. 45, there are only two inspection nodes connected to the first interleaver and two branches connected to the second interleaver, and there are only c1 inspection nodes, and the first interleaver There are only two branches connected to the branch on the second interleaver, and there are only c2 inspection nodes connected to the branch on the second interleaver. There are 0 branches connected to the first interleaver and the second interleaved There are only three c3 inspection nodes connected to the device, which exist separately.

Here, regarding the evolution of density and the actual work, it was revealed, for example: "On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit", SYChung, GDForney, TJ Richardson, R. Urbanke, IEEE Communications Leggers, VOL.5, NO.2, Feb 2001.

In the simulation of finding a new LDPC code (check matrix), the density evolution of the multi-branch type is used to find the E _b /N ₀ (signal power per 1 bit vs. noise) at which the BER begins to fade (it gradually decreases) Power ratio), that is, the whole whose performance threshold becomes below a predetermined value, from the LDPC codes to which the whole belongs, select the LDPC code whose BER becomes smaller when using orthogonal modulation of 1 or more such as QPSK, and select it as performance Good LDPC code.

The new LDPC code (table of initial values of the check matrix representing the check matrix) is obtained by the above simulation.

Therefore, if the new LDPC code is used, good communication quality can be ensured during data transmission.

FIG. 46 is an explanatory diagram of the column weight of the check matrix H as the type A code of the new LDPC code.

Regarding the check matrix H of the type A code, as shown in FIG. 46, the column weights of the first column to the K1 column of the A matrix and the C matrix are expressed as X1, and the subsequent K2 column of the A matrix and the C matrix The weight is expressed as X2, the column weight of the subsequent K3 column of the A matrix and the C matrix is expressed as X3, and the column weight of the subsequent M1 column of the C matrix is expressed as XM1.

In addition, K1+K2+K3 is equal to the information length K, and M1+M2 is equal to the parity length M. Therefore, K1+K2+K3+M1+M2 is equal to the code length N=17280 bits.

Further, regarding the check matrix H of the type A code, the column weight system of the first column to the M1-1 column of the B matrix is 2, and the column weight system of the M1 column (the last column) of the B matrix is 1. Furthermore, the column weight system of the D matrix is 1, and the column weight system of the Z matrix is 0.

Fig. 47 is a diagram showing the parameters of the inspection matrix H of the type A code (shown in the initial value table of the inspection matrix) of Figs. 30 to 35.

r=2/16, 3/16, 4/16, 5/16, 6/16, 7/16 Type A code check matrix H as parameters K, X1, K1, X2, K2, X3, K3 , XM1, M1, M2, as shown in Figure 47.

The parameters X1, K1, X2, K2, X3, K3, XM1, M1 (or M2) are set so that the performance (such as error rate, etc.) of the LDPC code will be more improved.

FIG. 48 is an explanatory diagram of the column weights of the check matrix H as the type B code of the new LDPC code.

Regarding the check matrix H of the type B code, as shown in FIG. 48, the column weights from the first column to the KX1 column are represented as X1, the column weights of the subsequent KX2 column are represented as X2, and the subsequent KX3 column The column weight is expressed as X3, the column weight of the subsequent KX4 column is expressed as X4, and the column weight of the subsequent KY1 column is expressed as Y1.

In addition, KX1+KX2+KX3+KX4+KY1 is equal to the information length K, and KX1+KX2+KX3+KX4+KY1+M is equal to the code length N=17280 bits.

As for the check matrix H of the type B code, among the last M columns, the column weight of the M-1 column other than the last column is 2 and the column weight of the last column is 1.

FIG. 49 is a diagram showing the parameters of the inspection matrix H of the type B code (shown in the initial value table of the inspection matrix) of FIGS. 36 to 43.

r=7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16 Type K code check matrix H as parameters K, X1, KX1 , X2, KX2, X3, KX3, X4, KX4, Y1, KY1, M, as shown in Figure 49.

The parameters X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1 are set so that the performance of the LDPC code will be further improved.

According to the new LDPC code, in addition to a good BER/FER, a capacity close to the limit of Xuenong (communication path capacity) can also be achieved.

50 to 53 are explanatory diagrams of other examples of new LDPC codes.

That is, FIG. 50 is a type A code provided by the Japan Broadcasting Association (hereinafter also referred to as r=4) with a code length N of 17280 bits and an encoding rate r of 4/16 as a new LDPC code. / New type A code of 16) is an illustration of an example of the initial value table of the inspection matrix represented by the inspection matrix H.

FIG. 51 is a diagram showing the parameters of the check matrix H of the new type A code of r=7/16 provided by the Japan Broadcasting Association.

The parameters K, X1, K1, X2, K2, X3, K3, XM1, M1, M2 are the parameters described in Figure 46, and the parameters K, X1 of the check matrix H of the new type A code for r=4/16 , K1, X2, K2, X3, K3, XM1, M1, M2, as shown in Figure 51.

Fig. 52 is a type B code provided by the Japan Broadcasting Association (hereinafter also referred to as r=9/16) with a code length N of 17280 bits and an encoding rate r of 9/16 as a new LDPC code A diagram of an example of the initial value table of the inspection matrix represented by the inspection matrix H of the new type B code).

FIG. 53 is a diagram showing the parameters of the check matrix H of the new type B code of r=9/16 provided by the Japan Broadcasting Association.

The parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, M are the parameters described in Figure 48, and the inspection matrix H of the new type B code with r=9/16 The parameters K, X1, KX1, X2, KX2, X3, KX3, X4, KX4, Y1, KY1, M are as shown in Figure 52.

<Constellation>

54 to 78 are diagrams of examples of constellations that can be used in the transmission system of FIG. 7.

In the transmission system of FIG. 7, for example, for a combination of modulation method (MODulation) and LDPC code (CODe), that is, MODCOD, the constellation used in the MODCOD can be set.

For one MODCOD, more than one constellation can be set.

In the constellation, there are uniform UC (Uniform Constellation) and non-uniform NUC (Non Uniform Constellation).

In addition, NUC includes, for example, a constellation called 1D-NUC (1-dimensional (M ² -QAM) non-uniform constellation) or a 2D-NUC (2-dimensional (QQAM) non-uniform constellation) ) Constellation, etc.

Generally speaking, the BER of 1D-NUC is better than that of UC; moreover, the BER of 2D-NUC is better than that of 1D-NUC.

The modulation method is the constellation of QPSK, which becomes UC. As a constellation with a modulation method of 16QAM, or 64QAM, 256QAM, etc., for example, UC or 2D-NUC can be used, and as a constellation with a modulation method of 1024QAM or 4096QAM, for example, UC or 1D-NUC can be used.

In the transmission system of FIG. 7, for example, constellations specified in ATSC3.0 or DVB-C.2, etc. can be used, and other constellations that can make the error rate good can be used.

That is, when the modulation method is QPSK, for each coding rate r of the LDPC code, for example, the same UC can be used.

In addition, when the modulation method is 16QAM, 64QAM, or 256QAM, for each coding rate r of the LDPC code, for example, the same UC can be used. Furthermore, in the case where the modulation method is 16QAM, 64QAM, or 256QAM, for example, different 2D-NUC may be used with each coding rate r of the LDPC code.

In addition, when the modulation method is 1024QAM or 4096QAM, for each coding rate r of the LDPC code, for example, the same UC can be used. In addition, when the modulation method is 1024QAM or 4096QAM, for example, different 1D-NUC may be used according to each coding rate r of the LDPC code.

Here, the UC of QPSK is also described as QPSK-UC, and the UC of 2 ^m QAM is also described as 2 ^m QAM-UC. Further, a 2 ^m QAM will also 1D-NUC and 2D-NUC, respectively, according to a 2 ^m QAM-1D-NUC and 2 ^m QAM-2D-NUC.

The following explains several constellations specified in ATSC3.0.

Fig. 54 is a diagram showing the coordinates of the signal points of QPSK-UC used for all the coding rates of the LDPC codes specified in ATSC3.0 when the modulation method is QPSK.

In Figure 54, "Input Data cell y" represents the 2-bit symbol mapped on QPSK-UC, and "Constellation point z _s " represents the coordinate of the signal point z _s . In addition, the index signal point z _s s (described later point signal index _q q likewise Z), represented by symbol-based discrete-time (the time between a symbol and the next symbol interval).

In FIG. 54, the coordinates of the signal point z _s are expressed in the form of complex numbers, and j is the imaginary unit (√(-1)).

Figure 55 shows that when the modulation method is 16QAM, the coding rate r(CR) for the LDPC code specified in ATSC3.0 is 2/15, 3/15, 4/15, 5/15, 6/15 , 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, 13/15 are used to show the coordinates of the signal points of 16QAM-2D-NUC.

In FIG. 55, as in FIG. 54, the coordinates of the signal point z _s are expressed in the form of complex numbers, and j is the imaginary unit.

In FIG. 55, w#k represents the coordinates of the signal point of the first quadrant of the constellation.

In 2D-NUC, the signal points of the second quadrant of the constellation are arranged at the position where the signal points of the first quadrant are symmetrically moved about the Q axis, and the signal points of the third quadrant of the constellation are arranged at, The signal point of the first quadrant is symmetrically moved to the origin. Then, the signal point of the fourth quadrant of the constellation is arranged at a position where the signal point of the first quadrant is moved symmetrically to the I axis.

Here, when the modulation method is 2 ^m QAM, m bits are regarded as one symbol, and the one symbol is mapped to the signal point corresponding to the symbol.

The m-bit symbol can be represented by an integer value such as 0 to 2 ^m -1, but now assuming b = 2 ^m /4, the symbol y represented by the integer value of 0 to 2 ^m -1 (0), y(1), ..., y(2 ^m -1) can be classified into symbols y(0) to y(b-1), y(b) to y(2b-1) , Y(2b) to y(3b-1), and y(3b) to y(4b-1).

In FIG. 55, the suffix k of w#k is an integer value in the range of 0 to b-1, and w#k is the symbol element in the range of symbol elements y(0) to y(b-1) The coordinates of the signal point corresponding to y(k).

Then, the coordinates of the signal point corresponding to the symbol y(k+b) in the range of symbol y(b) to y(2b-1) are represented by -conj(w#k), symbol y The coordinates of the signal point corresponding to the symbol y(k+2b) in the range of (2b) to y(3b-1) are represented by conj(w#k). In addition, the coordinates of the signal points corresponding to the symbols y(k+3b) in the range of symbols y(3b) to y(4b-1) are represented by -w#k.

Here, the conj(w#k) system represents the conjugate complex number of w#k.

For example, when the modulation method is 16QAM, m=4-bit symbols y(0), y(1), ..., y(15) are regarded as b=2 ⁴ /4=4, and It is classified into four types: symbol elements y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15).

Then, for example, the symbol element y(12) among the symbol elements y(0) to y(15) is the symbol element y(k+3b) in the range of symbol elements y(3b) to y(4b-1) =y(0+3×4), since k=0, the coordinate of the signal point corresponding to the symbol y(12) is -w#k=-w0.

Now, assuming that the coding rate r(CR) of the LDPC code is 9/15, for example, according to FIG. 55, the modulation method is 16QAM, and w0 when the coding rate r is 9/15 is 0.2386+j0.5296 Therefore, the coordinate -w0 of the signal point corresponding to the symbol y(12) is -(0.2386+j0.5296).

Fig. 56 is the modulation rate r(CR) = 2/15, 3/15, 4/15, 5/15, 6/15 for the LDPC code specified in ATSC3.0 when the modulation method is 1024QAM , 7/15, 8/15, 9/15, 10/15, 11/15, 12/15, and 13/15 are examples of the coordinates of the signal point of 1024QAM-1D-NUC used.

In Figure 56, u#k represents the real part Re(z _s ) and the imaginary part Im(z _s ) of the complex number of 1D-NUC as the coordinate of the signal point z _s , which is a kind of so-called The vector u=(u0, u1,..., u#V-1) component of the position vector. The quantity V of the component u#k of the position vector u is given by the formula V=√(2 ^m )/2.

FIG. 57 is a diagram showing the relationship between the symbol y of 1024QAM and the position vector u (component u#k).

Now, suppose that the 10-bit symbol y of 1024QAM, from its beginning bit (the highest bit), is expressed as y _0,s , y _1,s , y _2,s , y _3,s , y _4,s , y _5,s , y _6,s , y _7,s , y _8,s , y _9,s .

The A-line of Fig. 57 shows that the even-numbered 5-bit y _1,s , y _3,s , y _5,s , y _7,s , y _9,s of the symbol y, and the symbol y Correspondence relationship of u#k represented by the real part Re(z _s ) of the corresponding signal point z _s (of the coordinates).

The B system of FIG. 57 shows that the odd-numbered 5-bit y _0,s , y _2,s , y _4,s , y _6,s , y _8,s of the symbol y, and the symbol y The corresponding relationship of u#k is represented by the imaginary part Im(z _s ) of the corresponding signal point z _s .

In the 1024QAM 10-bit symbol y = (y _{0, s} , y _{1, s} , y _{2, s} , y _{3, s} , y _{4, s} , y _{5, s} , y _{6, s} , y _{7, s} , y _{8, s} , y _{9, s} ) is for example (0, 0, 1, 0, 0, _{1, 1} , _1, 0, 0), then the odd-numbered 5-bit (y _{0, s} , y _{2, s} , y _{4, s} , y _{6, s} , y _{8, s} ), the system is (0, _{1, 0, 1,} 0), the even-numbered 5-bit (y _{1, s} , y _{3, s} , y _{5, s} , y _{7, s} , y _{9, s} ), the system is (0, _{0, 1} , 1, 0).

In A of Fig. 57, the even-numbered 5-bits (0, 0, 1, 1, 0) correspond to u11, so the symbol y = (0, 0, 1, 0, 0, 1 , 1, 1, 0, 0) the real part Re(z _s ) of the signal point z _s is u11.

In B of Fig. 57, the odd-numbered 5-bit (0, 1, 0, 1, 0) corresponds to u3, therefore, the symbol y = (0, 0, 1, 0, 0, 1 , 1, 1, 0, 0) The imaginary part Im(z _s ) of the signal point z _s is u3.

On the other hand, assuming that the coding rate r of the LDPC code is 6/15, for example, according to FIG. 56 above, the modulation method is 1024QAM, and the coding rate r(CR) of the LDPC code = 6/15. The 1D-NUC used is 0.1295 for the u3 system and 0.7196 for the u11 system.

Therefore, the real part Re(z _s ) of the signal point z _s corresponding to the symbol y = (0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u11 = 0.7196, the imaginary part Im(z _s ) system is u3 = 0.1295. As a result, the coordinate of the signal point z _s corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is expressed as 0.7196+j0.1295.

In addition, the signal points of the 1D-NUC are tied in a constellation and arranged in a lattice on a line parallel to the I axis or a line parallel to the Q axis. However, the distance between the signal points is not constant. In addition, the average power of the signal points on the constellation can be normalized when transmitting the signal points (the data mapped on it). Normalization, assuming that based on the squared average of all signal points (the coordinates) on the absolute values of the constellation represented as P _ave, then the reciprocal square root of the squared average √P _ave 1 P _ave / ( √P _ave ), multiplying each signal point z _s on the constellation, which can be carried out.

It can be used in the transmission system of FIG. 7, such as the constellation specified in ATSC3.0 above.

Figures 58 to 69 are diagrams of the coordinates of the signal points of UC specified in DVB-C.2.

That is, FIG. 58 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of QPSK-UC (UC of QPSK) defined in DVB-C.2. Fig. 59 is an illustration of the imaginary part Im(z _q ) of the coordinate z _q of the signal point of QPSK-UC defined in DVB-C.2.

FIG. 60 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of 16QAM-UC (UC of 16QAM) specified in DVB-C.2. Fig. 61 is an illustration of the imaginary part Im(z _q ) of the coordinate z _q of the signal point of 16QAM-UC specified in DVB-C.2.

Fig. 62 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of 64QAM-UC (64QAM UC) specified in DVB-C.2. Fig. 63 is an illustration of the imaginary part Im(z _q ) of the coordinate z _q of the signal point of 64QAM-UC specified in DVB-C.2.

FIG. 64 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of 256QAM-UC (UC of 256QAM) specified in DVB-C.2. Fig. 65 is an illustration of the imaginary part Im(z _q ) of the coordinate z _q of the signal point of 256QAM-UC specified in DVB-C.2.

FIG. 66 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of 1024QAM-UC (UC of 1024QAM) specified in DVB-C.2. Fig. 67 is an illustration of the imaginary part Im(z _q ) of the coordinate z _q of the signal point of 1024QAM-UC specified in DVB-C.2.

FIG. 68 is a diagram of the real part Re(z _q ) of the coordinate z _q of the signal point of 4096QAM-UC (4096QAM UC) specified in DVB-C.2. Fig. 69 is a diagram of the imaginary part Im(z _q ) of the coordinate z _q of the signal point 4096QAM-UC specified in DVB-C.2.

In addition, in FIGS. 58 to 69, y _i,q represents the i+1 bit from the beginning of the symbol of m bits of 2 ^m QAM (for example, 2 bits in QPSK). In addition, the average power of the signal points on the constellation can be normalized when sending signals from UC signal points (data mapped on the UC). Normalization, assuming that based on the squared average of all signal points (the coordinates) on the absolute values of the constellation represented as P _ave, then the reciprocal square root of the squared average √P _ave 1 P _ave / ( √P _ave ), by multiplying each signal point z _q on the constellation, which can be carried out.

It can be used in the transmission system of FIG. 7, such as the UC specified in DVB-C.2 above.

That is, regarding FIGS. 30 to 43, 50, and 52, the code length N is 17280 bits, and the coding rate r is 2/16, 3/16, 4/16, 5/16, 6/16 , 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 respectively (corresponding to the check matrix initial value table) new LDPC codes, The UC shown in FIGS. 58 to 69 can be used.

Figures 70 to 78 are for Figures 30 to 43, 50, and 52, the code length N is 17280 bits, and the coding rate r is 2/16, 3/16, 4/16, 5/ NUC signals that can be used with the new LDPC codes of 16, 6/16, 7/16, 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, and 14/16 Illustration of examples of point coordinates.

That is, FIG. 70 is a diagram showing an example of the coordinates of the signal point of 16QAM-2D-NUC that can be used for the new LDPC code.

Fig. 71 is a diagram showing an example of the coordinates of the 64QAM-2D-NUC signal point that can be used for the new LDPC code.

72 and 73 are diagrams showing examples of the coordinates of the 256QAM-2D-NUC signal point that can be used for the new LDPC code.

In addition, FIG. 73 is a figure continued from FIG. 72.

In FIGS. 70 to 73, the coordinates of the signal point z _s are represented in the form of a complex number as in FIG. 55, and j represents an imaginary unit.

In FIGS. 70 to 73, w#k is the coordinate of the signal point representing the first quadrant of the constellation, as in FIG. 55.

Here, as illustrated in FIG. 55, the m-bit symbol is expressed as an integer value of 0 to 2 ^m -1. If b=2 ^m /4 is assumed, the integer value of 0 to 2 ^m -1 is used. The represented symbols y(0), y(1), ..., y(2 ^m -1) can be classified into symbols y(0) to y(b-1), y(b) There are 4 types from y(2b-1), y(2b) to y(3b-1), and y(3b) to y(4b-1).

In FIGS. 70 to 73, the same as in FIG. 55, the suffix k of w#k takes an integer value in the range of 0 to b-1, and w#k represents the symbol element y(0) to y The coordinates of the signal point corresponding to the symbol y(k) in the range of (b-1).

That is, in FIGS. 70 to 73, as in FIG. 55, the coordinates of the signal point corresponding to the symbol element y(k+3b) in the range of symbol elements y(3b) to y(4b-1), It is represented by -w#k.

However, in FIG. 55, the coordinates of the signal point corresponding to the symbol y(k+b) in the range of symbols y(b) to y(2b-1) are treated as -conj(w#k) Indicates that the coordinate of the signal point corresponding to the symbol y(k+2b) in the range of symbol y(2b) to y(3b-1) is represented by conj(w#k), but it is shown in Figure 70 In Fig. 73, the symbol system of conj is reversed.

That is, in Figures 70 to 73, the coordinates of the signal points corresponding to the symbols y(k+b) in the range of symbols y(b) to y(2b-1) are conj(w#k ) Is expressed, the coordinates of the signal point corresponding to the symbol element y(k+2b) in the range of symbol elements y(2b) to y(3b-1) are represented by -conj(w#k).

Fig. 74 is a diagram showing an example of the coordinates of the signal point of 1024QAM-1D-NUC that can be used for the new LDPC code.

That is, Fig. 74 is the real part Re(z _s ) and the imaginary part Im(z _s ) of the complex number of 1024QAM-1D-NUC as the coordinate of the signal point z _s , and the position vector u( Illustration of the relationship of components u#k).

FIG. 75 is a diagram showing the relationship between the symbol y of 1024QAM and the position vector u (component u#k) of FIG. 74.

That is, now, suppose that the 10-bit symbol y of 1024QAM is represented as y _{0, s} , y _{1, s} , y _{2, s} , y ₃ from the beginning bit (the highest bit) _{, s} , y _{4, s} , y _{5, s} , y _{6, s} , y _{7, s} , y _{8, s} , y _{9, s} .

The A system in FIG. 75 shows that the odd-numbered 5-bit y _0,s , y _2,s , y _4,s , y _6,s , y _{8, of the} 10-bit symbol y (from the beginning) _s corresponds to the position vector u#k of the real part Re(z _s ) of the signal point z _s (coordinates) corresponding to the symbol y.

The B system in FIG. 75 shows that the even-numbered 5-bit y _1,s , y _3,s , y _5,s , y _7,s , y _{9,s of the} 10-bit symbol y, and the The correspondence relationship of the position vector u#k represented by the imaginary part Im(z _s ) of the signal point z _s corresponding to the symbol y.

When the 10-bit symbol y of 1024QAM is mapped to the signal point z _s of 1024QAM-1D-NUC as specified in Fig. 74 and Fig. 75, the method of finding the coordinates of the signal point z _s is shown in Fig. 56 and The situation explained in FIG. 57 is the same, so the explanation is omitted.

Fig. 76 is a diagram showing an example of the coordinates of the 4096QAM-1D-NUC signal point that can be used for the new LDPC code.

That is, Figure 76 shows the real part Re(z _s ) and the imaginary part Im(z _s ) of the complex number of 4096QAM-1D-NUC as the coordinate of the signal point z _s , and the position vector u(u #k) illustration of the relationship.

77 and 78 are diagrams showing the relationship between the symbol y of 4096QAM and the position vector u (component u#k) of FIG. 76.

That is, now, suppose that the 12-bit symbol y of 4096QAM is represented as y _{0, s} , y _{1, s} , y _{2, s} , y ₃ from the beginning bit (the highest bit) _,s ,y _4,s ,y _5,s ,y _6,s ,y _7,s ,y _8,s ,y _9,s ,y _10,s ,y _11,s .

Figure 77 shows that the odd-numbered 6-bit y _0,s , y _2,s , y _4,s , y _6,s , y _8,s , y _{10,s of the} 12th symbol y , Corresponding to the position vector u#k representing the real part Re(z _s ) of the signal point z _s corresponding to the symbol y.

Figure 78 shows that the even-numbered 6-bit y _1,s , y _3,s , y _5,s , y _7,s , y _9,s , y _{11,s of the} 12th symbol y , Corresponding to the position vector u#k representing the imaginary part Im(z _s ) of the signal point z _s corresponding to the symbol y.

When the 12-bit symbol y of 4096QAM is mapped to the signal point z _s of the 4096QAM-1D-NUC specified in FIGS. 76 to 78, the method of finding the coordinates of the signal point z _s is shown in FIG. 56 and The situation explained in FIG. 57 is the same, so the explanation is omitted.

In addition, when transmitting the signal points of NUC in Figs. 70 to 78 (data mapped on the above), the average power of the signal points on the constellation can be normalized. Normalization, assuming that based on the squared average of all signal points (the coordinates) on the absolute values of the constellation represented as P _ave, then the reciprocal square root of the squared average √P _ave 1 P _ave / ( √P _ave ), multiplying each signal point z _s on the constellation, which can be carried out. In addition, in the above-mentioned FIG. 57, the odd-numbered bit of the symbol y is associated with the position vector u#k representing the imaginary part Im(z _s ) of the signal point z _s , and at the same time, the even-number of the symbol y The one bit corresponds to the position vector u#k representing the real part Re(z _s ) of the signal point z _s , but in FIG. 75, and FIG. 77 and FIG. 78, on the contrary, the odd number of the symbol y bytes is in association with the real part Re (z _s) of the position vector represents the signal point z _s u # k, while the even-numbered symbol bit y is the imaginary part of the signal representing the point z _s Im ( The position vector u#k of z _s ) establishes a correspondence.

<Block Interleaver 25>

FIG. 79 is an explanatory diagram of block interleaving performed by the block interleaver 25 of FIG. 9.

Block interleaving is performed by dividing the LDPC code of 1 codeword from the beginning into a part called part 1 (part 1) and a part called part 2 (part 2).

If the length of part 1 (number of bits) is expressed as Npart1, and at the same time, the length of part 2 is expressed as Npart2, then Npart1+Npart2 is equal to the code length N.

Conceptually, in block interleaving, the column as a memory area that stores Npart1/m bits in the column (vertical) direction of one direction is orthogonal to the column direction. In the horizontal direction, the arrangement reaches a number m equal to the number of bits m of the symbol, and each column is cut from top to bottom to be parallel factor P, which is a small unit of 360 bits. The small units in this column are also called column units.

In block interleaving, as shown in FIG. 79, part 1 of the LDPC code of 1 codeword is written into the first column unit of the column from top to bottom (column direction) Things are carried out in a column from left to right.

Then, once the writing to the first column of the right column is completed, as shown in FIG. 79, it returns to the column at the left end, and from the top to the bottom of the second column of columns The writing is performed in a column from left to right. In the same manner below, the writing of part 1 of the LDPC code of 1 codeword will be performed.

Once the writing of Part 1 of the LDPC code of 1 codeword is completed, as shown in FIG. 79, from the first row of all m vertical columns, in the horizontal row direction, the LDPC code is read in units of m bits Part 1.

The m-bit unit of this part 1 is used as an m-bit symbol, and is supplied from the block interleaver 25 to the mapper 117 (FIG. 8).

The reading of part 1 in m-bit units is carried out in sequence toward the lower row of m columns. Once the reading of part 1 is finished, part 2 is divided into m from the beginning The bit unit, which is an m-bit symbol, is supplied from the block interleaver 25 to the mapper 117.

Therefore, the part 1 system is interleaved on one side and symbolized on the other side, and the part 2 system is not interleaved, but is sequentially cut into m bits and symbolized.

The length of the column is Npart1/m, which is the parallel factor P, which is a multiple of 360. In such a way that Npart1/m is a multiple of 360, the LDPC code of 1 codeword is divided into part 1 and part 2 .

Fig. 80 is a diagram showing an example of part 1 and part 2 of an LDPC code having a code length N of 17280 bits in the case where the modulation schemes are QPSK, 16QAM, 64QAM, and 256QAM.

When the modulation method is QPSK, 16QAM, 64QAM, and 256QAM, in any case, part 1 series is 17280 bits, and part 2 series is 0 bits.

<Group Interlace>

FIG. 81 is an explanatory diagram of group interleaving performed in the group interleaver 24 of FIG. 9.

In group interleaving, as shown in FIG. 81, the LDPC code of 1 codeword is divided from the beginning into 360-bit units equal to the parallel factor P, and the 360-bit divided by 1 is regarded as The bit group, an LDPC code of 1 codeword, is interleaved in units of bit groups according to a predetermined pattern (hereinafter also referred to as GW pattern).

Here, when the LDPC code of 1 codeword is divided into bit groups, the i+1th bit group from the beginning is also described as bit group i below.

When the parallel factor P is 360, for example, an LDPC code with a code length N of 1800 bits is divided into 5 (=1800/360) bits of the bit group 0,1,2,3,4 Group. Furthermore, for example, an LDPC code with a code length N of 69120 bits is divided into 192 (=69120/360) bit groups of bit groups 0, 1, ..., 191. Also, for example, an LDPC code with a code length N of 17280 bits is divided into 48 (=17280/360) bit groups of bit groups 0, 1, ..., 47.

The following assumes that the GW pattern is represented by the arrangement of numbers representing bit groups. For example, regarding the LDPC code of 5 bit groups 0,1,2,3,4 with a code length N of 1800 bits, for example, the GW pattern of 4,2,0,3,1 means that the bit The arrangement of groups 0,1,2,3,4 is interleaved (sorted) into the arrangement of bit groups 4,2,0,3,1. In addition, regarding the arrangement of bit groups or GW patterns, in addition to the comma-separated arrangement (for example, 4,2,0,3,1) indicating the number of bit groups, the expression bits are also used The number of metagroups is represented by a space-separated arrangement (for example, 4 2 0 3 1).

For example, for the LDPC code whose code length N is 1800 bits, the i+1th code bit from the beginning is represented by x _i .

In this case, if group interleaving based on the GW pattern of ₄ , ₂ , ₀ , ₃ , ₁ , the 1800-bit LDPC code {x ₀ , x ₁ ,..., x ₁₇₉₉ } is interleaved into { x ₁₄₄₀ ,x ₁₄₄₁ ,...,x ₁₇₉₉ }, {x ₇₂₀ ,x ₇₂₁ ,...,x ₁₀₇₉ }, {x ₀ ,x ₁ ,...,x ₃₅₉ }, {x ₁₀₈₀ ,x ₁₀₈₁ ,...,x ₁₄₃₉ }, {x ₃₆₀ ,x ₃₆₁ ,...,x ₇₁₉ }.

The GW pattern can vary with each code length N of the LDPC code, or each coding rate r, each modulation method, each constellation, and even with the code length N, coding rate r, modulation method, and constellation Each combination of 2 or more is used for setting.

<Example of GW pattern for LDPC code>

Fig. 82 is a diagram showing the first example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 82, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 83 is a diagram showing a second example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 83, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 84 is a diagram showing a third example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 84, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 85 is a diagram showing a fourth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 85, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 86 is a diagram showing a fifth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 86, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 87 is a diagram showing a sixth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 87, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 88 is a diagram showing a seventh example of the GW pattern of an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 88, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 89 is a diagram showing an eighth example of the GW pattern for an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 89, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 90 is a diagram showing a ninth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 90, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 91 is a diagram showing a tenth example of the GW pattern of an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 91, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 92 is a diagram showing an eleventh example of the GW pattern of an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 92, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 93 is a diagram showing a twelfth example of the GW pattern for an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 93, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 94 is a diagram showing a thirteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 94, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 95 is a diagram showing a 14th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 95, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 96 is a diagram showing a fifteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 96, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 97 is a diagram showing the 16th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 97, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 98 is a diagram showing the 17th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 98, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 99 is a diagram showing an eighteenth example of the GW pattern for an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 99, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 100 is a diagram showing a nineteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 100, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 101 is a diagram of the twentieth example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 101, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 102 is a diagram showing a twenty-first example of the GW pattern of an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 102, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 103 is a diagram showing the 22nd example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 103, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 104 is a diagram showing the 23rd example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 104, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 105 is a diagram showing the 24th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 105, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 106 is a diagram showing the 25th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 106, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 107 is a diagram showing the 26th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 107, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 108 is a diagram showing the 27th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 108, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 109 is a diagram of the 28th example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 109, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 110 is a diagram showing the 29th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 110, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 111 is a diagram of the 30th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 111, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 112 is a diagram showing the 31st example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 112, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 113 is a diagram of the 32nd example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 113, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 114 is a diagram of the 33rd example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 114, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 115 is a diagram of the 34th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 115, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 116 is a diagram showing the 35th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 116, the arrangement of bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 117 is a diagram of the 36th example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 117, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 118 is a diagram showing a 37th example of the GW pattern for an LDPC code having a code length N of 17280 bits.

之排列。According to the GW pattern of FIG. 118, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 119 is a diagram showing the 38th example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 119, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 120 is a diagram showing the 39th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 120, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

FIG. 121 is a diagram of the 40th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 121, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 122 is a diagram showing the 41st example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 122, the arrangement of the bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

Fig. 123 is a diagram showing the 42nd example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 123, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

Fig. 124 is a diagram showing the 43rd example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 124, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 125 is a diagram showing the 44th example of the GW pattern of the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 125, the arrangement of the bit groups 0 to 47 of the 17280-bit LDPC code is interleaved into bit groups

Arrangement.

FIG. 126 is a diagram of the 45th example of the GW pattern for the LDPC code whose code length N is 17280 bits.

之排列。According to the GW pattern of FIG. 126, the arrangement of bit groups 0 to 47 of the LDPC code of 17280 bits is interleaved into bit groups

Arrangement.

The first to 45th examples of the GW pattern of the LDPC code with a code length N of 17280 bits are the LDPC codes with an arbitrary coding rate r and arbitrary modulation methods for the code length N with 17280 bits. Any combination of constellations can be applied.

However, the group interleaving can be set by setting the applicable GW pattern according to each combination of the code length N of the LDPC code, the coding rate r of the LDPC code, the modulation method, and the constellation. For each combination, the error rate is more improved.

The GW pattern of FIG. 82 is, for example, by combining the type A code of FIG. 31 (corresponding to the initial value table of the check matrix) with r=3/16, QPSK, and QPSK-UC of FIGS. 58 and 59. If applicable, a particularly good error rate can be achieved.

The GW pattern of FIG. 83 is, for example, by applying a combination of type A code of r=5/16 of FIG. 33, QPSK, and QPSK-UC of FIGS. 58 and 59, a particularly good error rate can be achieved .

The GW pattern of FIG. 84 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=7/16 of FIG. 36, QPSK, and QPSK-UC of FIGS. 58 and 59. .

The GW pattern of FIG. 85 is, for example, a particularly good error can be achieved by applying a combination of the new type B code of r=9/16 of FIG. 52, QPSK, and QPSK-UC of FIGS. 58 and 59. rate.

The GW pattern of FIG. 86 is, for example, a particularly good error rate can be achieved by applying the combination of the type B code of r=11/16 of FIG. 40, QPSK, and QPSK-UC of FIGS. 58 and 59. .

The GW pattern of FIG. 87 is, for example, by applying a combination of type B code of r=13/16 of FIG. 42, QPSK, and QPSK-UC of FIGS. 58 and 59, a particularly good error rate can be achieved .

The GW type pattern of FIG. 88 is, for example, a particularly good error rate can be achieved by applying the combination of type A code of r=3/16 of FIG. 31, 16QAM, and 16QAM-UC of FIGS. 60 and 61. .

The GW pattern of FIG. 89 is, for example, a particularly good error rate can be achieved by applying the combination of type A code of r=5/16 of FIG. 33, 16QAM, and 16QAM-UC of FIGS. 60 and 61. .

The GW pattern of FIG. 90 is, for example, by applying a combination of type B code of r=7/16 of FIG. 36, 16QAM, and 16QAM-UC of FIGS. 60 and 61, a particularly good error rate can be achieved .

The GW pattern of FIG. 91 is, for example, a particularly good error can be achieved by applying the combination of the new type B code of r=9/16 of FIG. 52, 16QAM, and 16QAM-UC of FIGS. 60 and 61. rate.

The GW pattern of FIG. 92 is, for example, a particularly good error rate can be achieved by applying the combination of the type B code of r=11/16 of FIG. 40, 16QAM, and 16QAM-UC of FIGS. 60 and 61. .

The GW pattern of FIG. 93 is, for example, a particularly good error rate can be achieved by applying the combination of the type B code of r=13/16 of FIG. 42, 16QAM, and 16QAM-UC of FIGS. 60 and 61. .

The GW pattern of FIG. 94 is, for example, suitable for the combination of the type A code of r=2/16 of FIG. 30, 16QAM, and 16QAM-2D-NUC of FIG. 70 to achieve a particularly good error rate.

The GW pattern of FIG. 95 is, for example, a particularly good error rate can be achieved by applying a combination of the new type A code of r=4/16 of FIG. 50, 16QAM, and 16QAM-2D-NUC of FIG. 70. .

The GW pattern of FIG. 96 is, for example, suitable for the combination of the type A code of r=6/16 of FIG. 34, 16QAM, and 16QAM-2D-NUC of FIG. 70 to achieve a particularly good error rate.

The GW pattern of FIG. 97 is, for example, suitable for the combination of the type B code of r=8/16 of FIG. 37, 16QAM, and 16QAM-2D-NUC of FIG. 70 to achieve a particularly good error rate.

The GW pattern of FIG. 98 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=10/16 of FIG. 39, 16QAM, and 16QAM-2D-NUC of FIG. 70.

The GW pattern of FIG. 99 is, for example, suitable for the combination of the type B code of r=12/16 of FIG. 41, 16QAM, and 16QAM-2D-NUC of FIG. 70 to achieve a particularly good error rate.

The GW pattern of FIG. 100 is, for example, suitable for the combination of the type B code of r=14/16 of FIG. 43, 16QAM, and 16QAM-2D-NUC of FIG. 70 to achieve a particularly good error rate.

The GW type pattern of FIG. 101 is, for example, a particularly good error rate can be achieved by applying a combination of type A code of r=2/16 of FIG. 30, 64QAM, and 64QAM-UC of FIGS. 62 and 63. .

The GW pattern of FIG. 102 is, for example, a particularly good error can be achieved by applying a combination of the new type A code of r=4/16 of FIG. 50, 64QAM, and 64QAM-UC of FIGS. 62 and 63. rate.

The GW pattern of FIG. 103 is, for example, a particularly good error rate can be achieved by applying a combination of type A code of r=6/16 of FIG. 34, 64QAM, and 64QAM-UC of FIGS. 62 and 63. .

The GW pattern of FIG. 104 is, for example, a particularly good error rate can be achieved by applying the combination of type B code of r=8/16 of FIG. 37, 64QAM, and 64QAM-UC of FIGS. 62 and 63. .

The GW pattern of FIG. 105 is, for example, by applying a combination of type B code of r=10/16 of FIG. 39, 64QAM, and 64QAM-UC of FIGS. 62 and 63, a particularly good error rate can be achieved .

The GW pattern of FIG. 106 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=12/16 of FIG. 41, 64QAM, and 64QAM-UC of FIGS. 62 and 63. .

The GW pattern of FIG. 107 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=14/16 of FIG. 43, 64QAM, and 64QAM-UC of FIGS. 62 and 63. .

The GW pattern of FIG. 108 is, for example, suitable for the combination of type A code with r=3/16 of FIG. 31, 64QAM, and 64QAM-2D-NUC of FIG. 71 to achieve a particularly good error rate.

The GW pattern of FIG. 109 is, for example, suitable for the combination of the type A code with r=5/16 of FIG. 33, 64QAM, and 64QAM-2D-NUC of FIG. 71 to achieve a particularly good error rate.

The GW pattern of FIG. 110 is, for example, suitable for the combination of the type B code of r=7/16 of FIG. 36, 64QAM, and 64QAM-2D-NUC of FIG. 71 to achieve a particularly good error rate.

The GW pattern of FIG. 111 is, for example, by applying the combination of the new type B code of r=9/16 of FIG. 52, 64QAM, and 64QAM-2D-NUC of FIG. 71, a particularly good error rate can be achieved .

The GW pattern of FIG. 112 is, for example, suitable for the combination of the type B code of r=11/16 of FIG. 40, 64QAM, and 64QAM-2D-NUC of FIG. 71 to achieve a particularly good error rate.

The GW pattern of FIG. 113 is, for example, suitable for the combination of the type B code of r=13/16 of FIG. 42, 64QAM, and 64QAM-2D-NUC of FIG. 71 to achieve a particularly good error rate.

The GW pattern of FIG. 114 is, for example, a particularly good error rate can be achieved by applying the combination of the type A code of r=3/16 of FIG. 31, 256QAM, and 256QAM-UC of FIGS. 64 and 65. .

The GW pattern of FIG. 115 is, for example, a particularly good error rate can be achieved by applying a combination of type A code of r=5/16 of FIG. 33, 256QAM, and 256QAM-UC of FIGS. 64 and 65. .

The GW pattern of FIG. 116 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=7/16 of FIG. 36, 256QAM, and 256QAM-UC of FIGS. 64 and 65. .

The GW pattern of FIG. 117 is, for example, a particularly good error can be achieved by applying a combination of the new type B code of r=9/16 of FIG. 52, 256QAM, and 256QAM-UC of FIGS. 64 and 65. rate.

The GW pattern of FIG. 118 is, for example, a particularly good error rate can be achieved by applying the combination of the type B code of r=11/16 of FIG. 40, 256QAM, and 256QAM-UC of FIGS. 64 and 65. .

The GW pattern of FIG. 119 is, for example, a particularly good error rate can be achieved by applying a combination of type B code of r=13/16 of FIG. 42, 256QAM, and 256QAM-UC of FIGS. 64 and 65. .

The GW pattern of FIG. 120 is, for example, suitable for the combination of the type A code with r=2/16 of FIG. 30, 256QAM, and the 256QAM-2D-NUC of FIGS. 72 and 73, to achieve particularly good Error rate.

The GW-type pattern of FIG. 121 is, for example, suitable for a combination of the new type A code of r=4/16 of FIG. 50, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, which is particularly good Error rate.

The GW pattern of FIG. 122 is, for example, by applying a combination of type A code of r=6/16 of FIG. 34, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, a particularly good result can be achieved Error rate.

The GW pattern of FIG. 123 is, for example, suitable for the combination of the type B code of r=8/16 of FIG. 37, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, and particularly good Error rate.

The GW pattern of FIG. 124 is, for example, by applying a combination of the type B code of r=10/16 of FIG. 39, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, particularly good Error rate.

The GW pattern of FIG. 125 is, for example, suitable for the combination of the type B code of r=12/16 of FIG. 41, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, to achieve particularly good Error rate.

The GW-type pattern of FIG. 126 is, for example, suitable for the combination of the type B code of r=14/16 of FIG. 43, 256QAM, and 256QAM-2D-NUC of FIGS. 72 and 73, to achieve particularly good Error rate.

<Configuration example of the receiving device 12>

FIG. 127 is a block diagram of a configuration example of the receiving device 12 of FIG. 7.

The OFDM operation unit (OFDM operation) 151 receives the OFDM signal from the transmission device 11 (FIG. 7) and performs signal processing of the OFDM signal. The data obtained by the signal processing by the OFDM processing unit 151 is supplied to the frame management unit (Frame Management) 152.

The frame management unit 152 performs the processing (frame interpretation) of the frame composed of the data supplied from the OFDM processing unit 151, and the signal of the object data obtained from the result, and the signal of the control data, They are supplied to Frequency Deinterleaver 161 and 153, respectively.

The frequency deinterleaver 153 performs frequency deinterleaving in symbol units on the data from the frame management unit 152 and supplies it to the Demapper 154.

The de-emitter 154 decodes the data from the frequency deinterleaver 153 (data on the constellation) based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the side of the transmitting device 11 Map (signal point configuration decoding) and perform quadrature demodulation, and supply the resulting data (LDPC code (likelihood)) to LDPC decoder (LDPC decoder) 155.

The LDPC decoder 155 (decoding unit) performs LDPC decoding of the LDPC code from the de-encoder 154, and supplies the resulting LDPC object data (here BCH code) to the BCH decoder (BCH decoder) 156.

The BCH decoder 156 performs BCH decoding of the LDPC object data from the LDPC decoder 155, and outputs the control data (signal) obtained as a result.

On the other hand, the frequency deinterleaver 161 performs frequency deinterleaving in symbol units on the data from the frame management unit 152 and supplies it to the SISO/MISO decoder 162.

The SISO/MISO decoder 162 performs time-space decoding of the data from the frequency deinterleaver 161 and supplies it to the time deinterleaver 163.

The time deinterleaver 163 performs time deinterleaving in symbol units on the data from the SISO/MISO decoder 162 and supplies it to the Demapper 164.

The de-emitter 164 decodes the data from the time deinterleaver 163 (data on the constellation) based on the signal point arrangement (constellation) determined by the orthogonal modulation performed on the side of the transmitting device 11 Map (signal point configuration decoding) and perform quadrature demodulation, and supply the resulting data to the Bit Deinterleaver 165.

The bit deinterleaver 165 performs bit deinterleaving of the data from the demapper 164, and the data after the bit deinterleaving, that is, the LDPC code (likelihood), is supplied to the LDPC decoder 166.

The LDPC decoder 166 performs LDPC decoding of the LDPC code from the bit deinterleaver 165, and supplies the resulting LDPC object data (here, BCH code) to the BCH decoder 167.

The BCH decoder 167 performs BCH decoding of the LDPC object data from the LDPC decoder 155, and supplies the resulting data to the BB DeScrambler 168.

The BB descrambling code 168 implements the BB descrambling code on the data from the BCH decoder 167, and supplies the resulting data to the Null Deletion 169.

The null value deletion unit 169 deletes the Null inserted in the patcher 112 of FIG. 8 from the data from the BB descrambler 168 and supplies it to the demultiplexer 170.

The demultiplexer 170 separates one or more streams (object data) multiplexed from the data from the null deletion unit 169, and performs necessary processing as an output stream (Output stream) It is output.

In addition, the receiving device 12 may be configured without a part of the block shown in FIG. 127. That is, for example, when the transmitting device 11 (FIG. 8) is configured without the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124, the receiver The device 12 may not include the time interleaver 118, the SISO/MISO encoder 119, the frequency interleaver 120, and the frequency interleaver 124 of the transmission device 11, respectively, namely the time deinterleaver 163, SISO/MISO The decoder 162, the frequency deinterleaver 161, and the frequency deinterleaver 153 are configured.

<Configuration example of bit deinterleaver 165>

FIG. 128 is a block diagram of a configuration example of the bit deinterleaver 165 of FIG. 127.

The bit deinterleaver 165 is composed of a block deinterleaver 54 and a group deinterleaver 55. The data from the demapper 164 (FIG. 127) is the symbol bit of the symbol. (Bit) Deinterlace.

That is, the block deinterleaver 54 takes the symbol bits from the symbols of the demapper 164 as the object, and performs the block deblocking corresponding to the block interleaving by the block interleaver 25 of FIG. 9 Interleaving (inverse processing of block interleaving), that is, deblocking the block where the position of the code bits (likelihood) of the LDPC code ordered by block interleaving is restored to the original position, The LDPC code obtained as a result is supplied to the group deinterleaver 55.

The group deinterleaver 55 takes the LDPC code from the block deinterleaver 54 as an object, and performs the group deinterleaving (group Inverse processing of group interleaving), that is, for example, the code bits of the LDPC code that has been arranged in units of bit groups that have been changed by the group interleaving illustrated in FIG. 81 are grouped by bit Units are sorted in order to restore the original arrangement of the group to deinterlace.

Here, for the LDPC code supplied from the de-emitter 164 to the bit deinterleaver 165, there may be cases where co-located interleaving, group interleaving, and block interleaving have been performed. In the system, it is possible to perform co-located de-interlacing corresponding to co-located interleaving (inverse processing of co-located interlacing, that is, to restore the code bits of the LDPC code whose arrangement has been changed by co-located interlace to the original co-located de-interlacing), All of the block deinterleaving corresponding to block interleaving and the group deinterleaving corresponding to group interleaving.

However, in the bit deinterleaver 165 of FIG. 128, there is a block deinterleaver 54 for performing block deinterleaving corresponding to block interleaving, and a group deinterleaving corresponding to performing group interleaving. Group deinterleaver 55, but the co-located de-interlacing block corresponding to co-located interleaving may not be set without co-located de-interlacing.

Therefore, the bit deinterleaver 165 (group deinterleaver 55) is supplied to the LDPC decoder 166, there are block deinterleaving and group deinterleaving, and there is no parity deinterleaving LDPC code.

The LDPC decoder 166 decodes the LDPC code of the LDPC code from the bit deinterleaver 165, based on: at least performing the check matrix H of the type B scheme used by the LDPC encoder 115 of FIG. 8 in LDPC encoding, at least equivalent to The conversion check matrix obtained by the column replacement of the same-position interleaved column, or the conversion check matrix obtained by performing row replacement on the check matrix of the type A method (Figure 27), and the data obtained by the result is regarded as the object of LDPC The decoding result of the data is output.

FIG. 129 is a flowchart for explaining the processing performed by the de-emitter 164, bit deinterleaver 165, and LDPC decoder 166 of FIG. 128. FIG.

In step S111, the de-enumerator 164 de-maps the data from the time deinterleaver 163 (the data on the constellation that has been mapped to the signal point) and performs quadrature demodulation to supply the bit With the deinterleaver 165, the process proceeds to step S112.

In step S112, the bit deinterleaver 165 performs deinterleaving of the data from the demapper 164 (bit deinterleaving), and the process proceeds to step S113.

That is, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 takes the data (symbols) from the demapper 164 as the object, performs block deinterleaving, and The resulting code bits of the LDPC code are supplied to the group deinterleaver 55.

The group deinterleaver 55 takes the LDPC code from the block deinterleaver 54 as an object, performs group deinterleaving, and supplies the resulting LDPC code (likelihood) to the LDPC decoder 166 .

In step S113, the LDPC decoder 166 decodes the LDPC code of the LDPC code from the group deinterleaver 55 based on the check matrix H used by the LDPC encoder 115 of FIG. 8 in the LDPC encoding. That is, for example, based on the conversion check matrix obtained from the check matrix H, the data obtained as a result is output to the BCH decoder 167 as the decoding result of the LDPC target data.

In addition, in FIG. 128, as in the case of FIG. 9, for descriptive convenience, the block deinterleaver 54 that performs block deinterleaving and the group deinterleaver 55 that performs group deinterleaving will be used. It is drawn as a separate structure, but the block deinterleaver 54 and the group deinterleaver 55 can also be integrated.

In addition, in the case where the transmitting device 11 does not perform group-type interleaving, the receiving device 12 may be configured without a group-type deinterleaver 55 that performs group-type deinterleaving.

<LDPC decoding>

The LDPC decoding performed by the LDPC decoder 166 of FIG. 127 will be described again.

In the LDPC decoder 166 of FIG. 127, as described above, there are LDPC codes from the group-type deinterleaver 55 that have been subjected to block de-interleaving and group-type de-interleaving, and are not subjected to co-located de-interleaving. The decoding is to use: for the check matrix H of the type B method used by the LDPC encoder 115 of FIG. 8 in the LDPC encoding, at least perform a conversion check matrix obtained by column replacement equivalent to the interleaved columns, or check the type A method The matrix (FIG. 27) is subjected to the conversion check matrix (FIG. 29) obtained by row replacement.

Here, the LDPC decoding is performed by using a conversion check matrix to suppress the circuit scale, and at the same time, the LDPC decoding that can suppress the operating frequency within a sufficiently achievable range has been previously proposed (for example, refer to Japanese Patent No. 4224777 number).

Therefore, first, referring to FIGS. 130 to 133, the LDPC decoding using the conversion check matrix proposed earlier will be described.

FIG. 130 is a diagram of an example of a check matrix H of an LDPC code having a code length N of 90 and an encoding rate of 2/3.

In addition, in FIG. 130 (the same applies to FIGS. 131 and 132 described later), 0 is expressed as an English period (.).

In the inspection matrix H of FIG. 130, the parity matrix has a staircase structure.

FIG. 131 is a diagram of the inspection matrix H′ obtained by performing the row replacement of equation (11) and the column replacement of equation (12) on the inspection matrix H of FIG. 130.

Line replacement: line 6s+t+1→line 5t+s+1 ・・・(11)

Column replacement: column 6x+y+61 → column 5y+x+61 ・・・(12)

In equations (11) and (12), s, t, x, and y are integers in the range of 0≦s<5, 0≦t<6, 0≦x<5, 0≦t<6, respectively. .

If the line replacement according to equation (11) is performed, the first, seventh, thirteenth, nineteenth, and twenty-fifth lines with the remainder divided by six being 1 will be replaced with the first, second, third, fourth, and fifth lines, respectively. Lines 2, 8, 14, 20, and 26 with a remainder of 2 divided by 6 are replaced with lines 6, 7, 8, 9, and 10, respectively.

Also, if the column replacement according to equation (12) is performed, the 61st, 67th, 73rd, 79th, and 85th columns with the remainder divided by 6 as 1 and the 61st column (collocation matrix) are replaced by the Columns 61, 62, 63, 64, and 65, replace the 62nd, 68th, 74th, 80th, and 86th columns with the remainder divided by 6 as the 66th, 67th, 68th, 69th, and 70th columns, respectively. Way of replacement.

In this way, the inspection matrix H shown in FIG. 130 is a matrix obtained by permuting rows and columns, which is the inspection matrix H′ shown in FIG. 131.

Here, even if the row replacement of the check matrix H is performed, the arrangement of the code bits of the LDPC code is not affected.

In addition, the column permutation system of equation (12) is equivalent to the above-mentioned K+qx+y+1 code bit, interleaved to the position of the K+Py+x+1 code bit, and interleaved , Let the information length K be 60, let the parallel factor P be 5, and let the factor q (=M/P) of the parity length M (here 30) be 6 when the parity is interleaved.

Therefore, the inspection matrix H′ of FIG. 131 is at least the inspection matrix H of FIG. 130 (hereinafter appropriately referred to as the original inspection matrix) H, and the K+qx+y+1 column is replaced with the K+Py +x+1 column replacement, resulting conversion check matrix.

Regarding the conversion check matrix H′ of FIG. 131, if the original LDPC code of the check matrix H of FIG. 130 is multiplied by the same replacement as in equation (12), a 0 vector is output. That is, if the row vector c of the original inspection matrix H as the LDPC code (1 codeword) is subjected to column replacement of equation (12) and expressed as c′, then according to the nature of the inspection matrix, Hc ^{The T} system is a 0 vector, so H'c' ^T is of course a 0 vector.

Based on the above, the conversion check matrix H′ of FIG. 131 is the check matrix of the LDPC code c′ obtained by performing column replacement of equation (12) on the original LDPC code c of the check matrix H.

Therefore, the original LDPC code c of the check matrix H is subjected to column replacement of equation (12), and the LDPC code c′ after the column replacement is decoded using the conversion check matrix H′ of FIG. 131 (LDPC decoding). By performing the inverse replacement of the column replacement of equation (12) on this decoding result, the same decoding result as when the original LDPC code of the check matrix H is decoded using the check matrix H can be obtained.

FIG. 132 is a diagram of the conversion check matrix H′ of FIG. 131 with intervals in units of 5×5 matrices.

In FIG. 132, the conversion check matrix H'is used: the unit size P is a unit matrix of 5×5 (=P×P), and more than one of the unit matrix 1 becomes a matrix of 0 (the following is suitable (Referred to as a quasi-unit matrix), a matrix obtained by using the unit matrix or the quasi-unit matrix as a cyclic shift (hereinafter referred to as a displacement matrix), an identity matrix, a quasi-unit matrix, or a displacement matrix The combination of the sum (hereinafter referred to as a sum matrix as appropriate) and the 5×5 of 0 matrix are shown.

The conversion check matrix H'of FIG. 132 can be composed of: a 5×5 unit matrix, a quasi-unit matrix, a displacement matrix, a sum matrix, and a 0 matrix. Therefore, the 5×5 matrices (unit matrix, quasi-unit matrix, displacement matrix, sum matrix, and 0 matrix) that constitute the conversion check matrix H′ are hereinafter appropriately referred to as constituent matrices.

The decoding of the LDPC code of the inspection matrix represented by the P×P composition matrix can adopt an architecture in which the inspection node calculation and variable node calculation are performed simultaneously.

FIG. 133 is a block diagram of a configuration example of a decoding device that performs such decoding.

That is, FIG. 133 illustrates a decoding apparatus for decoding an LDPC code using the original check matrix H of FIG. 130 and at least the conversion check matrix H′ of FIG. 132 obtained by column replacement of equation (12). Examples of the structure.

FIG decoding apparatus 133, the line: into the reservoir 6 as a FIFO300 ₁ to 300 ₆ by branched data memory 300, which will be selected FIFO300 ₁ to 300 ₆ the selector 301, a check node calculation section 302,2 Cyclic shift circuits 303 and 308, a branch data storage memory 304 made up of 18 FIFOs 304 ₁ to 304 ₁₈ , a selector 305 for selecting FIFOs 304 ₁ to 304 ₁₈ , and reception data for storing reception data It is composed of a memory 306, a variable node calculation unit 307, a decoded word calculation unit 309, a received data sorting unit 310, and a decoded data sorting unit 311.

First, the method of storing data in the branches 300 and 304 for data storage will be described.

The memory 300 for branch data storage is obtained by dividing the number of rows 30 of the conversion check matrix H'of FIG. 132 by the number of rows (parallel factor P) constituting the matrix, that is, 6 FIFOs 300 ₁ to 300 ₆ Composition. FIFO300 _y (y=1, 2, ..., 6), which is composed of the memory area of the complex number of segments, regarding the memory area of each segment, the number of rows and columns constituting the matrix (parallel factor P ) That is, the information corresponding to the 5 branches is read and written simultaneously. In addition, the number of segments in the memory area of FIFO 300 _y is the maximum number of 1s in the row direction of the conversion check matrix of FIG. 132 (weight of Han people), which is 9.

In the FIFO300 ₁ , the data corresponding to the position 1 of the first row to the fifth row of the conversion check matrix H'of FIG. 132 (message from the variable node v _i ) is the horizontal direction in each row The close form (in the form of ignoring 0) is stored. That is, if the jth row and the ith column are represented as (j,i), in the memory area of the first segment of the FIFO 300 ₁ , the (1,1) to (5,5) of the check matrix H'are converted The data corresponding to the position 1 of the 5×5 unit matrix is stored. In the memory field of the second paragraph, the displacement matrix of (1,21) to (5,25) of the inspection matrix H'is converted (the 5×5 unit matrix is shifted by three cyclic shifts to the right The data corresponding to the position of 1 in the displacement matrix is stored. The memory areas of paragraphs 3 to 8 are also similar, storing data in correspondence with the conversion check matrix H'. Then, in the memory area of the ninth paragraph, convert the displacement matrix (1,86) to (5,90) of the check matrix H'(replace the 1 in the first row of the 5×5 unit matrix with 0 And the data corresponding to the 1 position of the displacement matrix formed by one cyclic displacement to the left are stored.

In the FIFO 300 ₂ , the data corresponding to the positions of 1 in the 6th row to the 10th row of the conversion check matrix H′ of FIG. 132 are stored. That is, in the memory area of the first segment of FIFO300 ₂ , the sum matrix of (6,1) to (10,5) of the conversion check matrix H'(the unit matrix of 5×5 is made to the right) The data corresponding to the position of 1 of the first displacement matrix formed by the cyclic displacement of the first displacement matrix and the second displacement matrix obtained by making two cyclic displacements to the right is the sum matrix) Be saved. In addition, in the memory area of the second paragraph, the data corresponding to the position 1 of the second displacement matrix composed of the sum matrix of (6,1) to (10,5) of the conversion check matrix H'is store.

That is, for a constituent matrix with a weight of 2 or more, one or more of the constituent matrix, the P×P unit matrix with a weight of 1, and the quasi-unit matrix with 1 or more of the elements of the unit matrix becoming 0, or When the unit matrix or the quasi-unit matrix is cyclically shifted and expressed in the form of the sum of complex numbers in the displacement matrix, the position of the unit matrix, quasi-unit matrix, or displacement matrix with a weight of 1 corresponds to the position of 1. The data (information corresponding to the branch in the identity matrix, quasi-identity matrix, or displacement matrix) is stored at the same address (the same FIFO in FIFO 300 ₁ to 300 ₆ ).

In the following, the memory areas of paragraphs 3 to 9 are also stored in correspondence with the conversion check matrix H'.

The FIFOs 300 ₃ to 300 ₆ are similarly stored in correspondence with the conversion check matrix H′.

The memory 304 for branch data storage is composed of 18 FIFOs 304 ₁ to 304 ₁₈ obtained by dividing the number of columns of the conversion check matrix H′ by 90 and dividing the number of columns (parallel factor P) constituting the matrix, that is, 5 . FIFO304 _x (x=1, 2, ..., 18), which is composed of the memory area of the complex number of segments, regarding the memory area of each segment, the number of rows and columns constituting the matrix (parallel factor P ) That is, the information corresponding to the 5 branches is read and written simultaneously.

In the FIFO304 ₁ , the data corresponding to the position 1 from the first column to the fifth column of the conversion check matrix H'of FIG. 132 (the message u _j from the check node) is that each column is oriented in the vertical direction The close form (in the form of ignoring 0) is stored. That is, in the memory area of the first segment of FIFO304 ₁ , the data corresponding to the position 1 of the 5×5 unit matrix of (1,1) to (5,5) of the check matrix H'is converted to store. In the memory field of the second paragraph, the sum matrix (6,1) to (10,5) of the conversion check matrix H'(the 5×5 unit matrix is shifted to the right by 1 cyclic shift 1 The displacement matrix and the sum of the second displacement matrix made by performing two cyclic displacements to the right, that is, the sum matrix, are the data corresponding to the position of the first displacement matrix 1 which is formed. In addition, in the memory area of the third paragraph, the data corresponding to the position 1 of the second displacement matrix composed of the sum matrix of (6,1) to (10,5) of the conversion check matrix H'is treated as store.

That is, for a constituent matrix with a weight of 2 or more, one or more of the constituent matrix, the P×P unit matrix with a weight of 1, and the quasi-unit matrix with 1 or more of the elements of the unit matrix becoming 0, or When the unit matrix or the quasi-unit matrix is cyclically shifted and expressed in the form of the sum of complex numbers in the displacement matrix, the position of the unit matrix, quasi-unit matrix, or displacement matrix with a weight of 1 corresponds to the position of 1. Data (messages corresponding to the branches in the identity matrix, quasi-identity matrix, or displacement matrix) are stored at the same address (the same FIFO in FIFO304 ₁ to 304 ₁₈ ).

In the following, the memory areas of the fourth and fifth paragraphs are also stored in correspondence with the conversion check matrix H'. The number of segments in the memory area of the FIFO 304 ₁ is the maximum number of 1s in the row direction (weight of the Han people) in the first to fifth columns of the conversion check matrix H', which is 5.

The FIFOs 304 ₂ and 304 ₃ also store data in correspondence with the conversion check matrix H′, and their respective lengths (number of segments) are both 5. The FIFOs 304 ₄ to 304 ₁₂ are similarly stored in correspondence with the conversion check matrix H′, and their respective lengths are all 3. The FIFOs 304 ₁₃ to 304 ₁₈ are similarly stored in correspondence with the conversion check matrix H′, and their respective lengths are all 2.

Next, the operation of the decoding device of FIG. 133 will be described.

The memory 300 for branch data storage is made up of 6 FIFOs 300 ₁ to 300 _6. According to the 5 messages D311 supplied from the previous-stage cyclic shift circuit 308, it belongs to the conversion check matrix H'of FIG. 132 Which line of information (Matrix data) D312, the FIFO that stores the data is selected from FIFO300 ₁ to 300 ₆ , and the 5 messages D311 batches are sequentially stored one by one to the selected FIFO. In addition, the branch data storage memory 300 reads five messages D300 ₁ from the FIFO 300 ₁ in sequence at the time of data reading, and supplies them to the selector 301 of the next stage. Data storage branch 300, line after the message from the read out FIFO300 _1, from ₃₀₀₆ to FIFO300 ₂ are sequentially read out messages to the selector 301 is supplied with a memory.

The selector 301 selects five messages from the FIFO that is currently reading data among the FIFO 300 ₁ to 300 ₆ according to the selection signal D301, and supplies them to the inspection node calculation unit 302 as the message D302.

Check node calculation section 302, a line 5 to a check node calculators ₃₀₂₁ to _3025, using messages through the selector 301 is supplied D302 (D302 ₁ to D302 ₅₎ (messages v formula (7) _i) In accordance with equation (7), the check node calculation is performed, and five messages D303 (D303 ₁ to D303 ₅ ) (the message u _{j of} formula (7)) obtained by the result of the check node calculation are supplied to the circular displacement circuit 303.

The cyclic shift circuit 303 divides the five messages D303 ₁ to D303 ₅ obtained in the check node calculation unit 302 according to the corresponding branch into the original unit matrix (or quasi-unit) in the conversion check matrix H′ (Matrix) The information (Matrix data) D305 obtained by performing several cyclic displacements is cyclically displaced, and the result is supplied as a message D304 to the memory 304 for branch data storage.

The branch data storage memory 304 is made up of 18 FIFOs 304 ₁ to 304 ₁₈ , and according to the 5 messages D304 supplied from the previous-stage cyclic shift circuit 303, which row of information belongs to the conversion check matrix H' D305, and the FIFO for storing data is selected from FIFO304 ₁ to 304 ₁₈ , and 5 messages D304 batches are sequentially stored one by one to the selected FIFO. In addition, the branch data storage memory 304 reads five messages D306 ₁ from the FIFO 304 ₁ sequentially when data is read, and supplies them to the selector 305 of the next stage. M. data storage 304, based on the information read from the end of the FIFO304 ₁ out from FIFO304 ₂ to ₃₀₄₁₈ are sequentially read out messages to the selector 305 is supplied with a memory.

The selector 305 selects five messages from the FIFO that is currently reading data among the FIFOs 304 ₁ to 304 ₁₈ according to the selection signal D307, and supplies them as variable D308 to the variable node calculation unit 307 and decoding Word calculation unit 309.

On the other hand, the received data sorting unit 310 sorts the LDPC codes D313 corresponding to the check matrix H of FIG. 130 received through the communication channel 13 by performing column replacement of equation (12) and sorts them as received The data D314 is supplied to the memory 306 for receiving data. The received data memory 306 calculates the received LLR (log likelihood ratio) based on the received data D314 supplied from the received data sorting unit 310 and memorizes the received LLR every 5 places It is aggregated and supplied as the received value D309 to the variable node calculation unit 307 and the decoded word calculation unit 309.

The variable node calculation section 307, a line 5 to a variable node calculators 307 ₁ to _3075, the use of messages through the selector 305 is supplied D308 (D308 ₁ to D308 ₅₎ (Formula (1) message u _j ), and five received values D309 (received value u _0i of formula (1)) supplied from the memory 306 for received data, perform variable node calculation according to formula (1), and perform the calculation The message D310 (D310 ₁ to D310 ₅ ) obtained by the result (the message v _{i of} equation (1)) is supplied to the cyclic shift circuit 308.

The cyclic shift circuit 308 divides the information D310 ₁ to D310 ₅ calculated in the variable node calculation unit 307 into the original unit matrix (or quasi unit) in the conversion check matrix H′ according to the corresponding branch (Matrix) The information obtained by performing several cyclic displacements is cyclically displaced, and the result is supplied as a message D311 to the branch data storage memory 300.

By performing the above operations for one round, the LDPC code can be decoded once (variable node calculation and check node calculation). The decoding device of FIG. 133 performs the decoding of the LDPC code a predetermined number of times, and then obtains and outputs the final decoding result in the decoded word calculation unit 309 and the decoded data sorting unit 311.

That is, the decoded word calculation unit 309 is composed of five decoded word calculators 309 ₁ to 309 ₅ and uses the five messages D308 (D308 ₁ to D308 ₅ ) (the message of formula (5)) output by the selector 305 u _j ), and five received values D309 (received value u _{0i of} formula (5)) supplied from the memory 306 for received data, as the final segment of the multiple decoding, based on formula (5) Then, the decoding result (decoded word) is calculated, and the decoded data D315 obtained by the result is supplied to the decoded data sorting unit 311.

The decoded data sorting unit 311 takes the decoded data D315 supplied from the decoded word calculation unit 309 as an object, performs the inverse replacement of the column replacement of equation (12), and sorts the order as the final decoding result D316. To be output.

As described above, for the inspection matrix (original inspection matrix), one or both of row replacement and column replacement are performed and converted into a unit matrix of P×P, and more than one of its elements becomes 0. The sum of the identity matrix, the displacement matrix that made the identity matrix or the quasi-unit matrix cyclically shifted, the identity matrix, the quasi-unit matrix, or the complex number of the displacement matrix is the combination of the matrix and the P×P 0 matrix, and That is, a check matrix (conversion check matrix) that can be represented by a combination of constituent matrices, whereby the decoding system of the LDPC code can be adopted, and P numbers that are smaller than the number of rows or columns of the check matrix can be simultaneously performed Check the architecture of node calculus and variable node calculus. In the case of adopting an architecture that can simultaneously perform a number of P node calculations (inspection node calculation and variable node calculation) that are smaller than the number of rows or columns of the inspection matrix, it is possible to simultaneously perform rows equal to the inspection matrix The calculation of the number of nodes or the number of columns can suppress the operating frequency within the achievable range, and can perform most repeated decoding.

The LDPC decoder 166 configured with the receiving device 12 of FIG. 127 is, for example, similar to the decoding device of FIG. 133, by simultaneously performing P check node calculations and variable node calculations, LDPC decoding is performed.

That is, for the sake of simplifying the description, it is assumed that the check matrix of the LDPC code output by the LDPC encoder 115 composed of the transmission device 11 of FIG. 8 is, for example, if it is as shown in FIG. Check matrix H, in the parity interleaver 23 of the sending device 11, the K+qx+y+1 code bit is interleaved for the position of the K+Py+x+1 code bit Interleaving is performed by setting the information length K to 60, the parallel factor P to 5, and the factor q (=M/P) of the parity length M to 6.

This co-located interleaving corresponds to the column replacement of equation (12) as described above. Therefore, the LDPC decoder 166 does not need to perform the column replacement of equation (12).

Therefore, in the receiving device 12 of FIG. 127, as described above, the group-type deinterleaver 55 supplies the LDPC decoder 166 with the LDPC code that has not undergone co-bit deinterleaving, that is, the 12) The LDPC code in the state of column replacement is processed by the LDPC decoder 166 except that the column replacement of equation (12) is not performed, and the decoding device of FIG. 133 is the same.

That is, FIG. 134 is a diagram of a configuration example of the LDPC decoder 166 of FIG. 127.

In FIG. 134, the LDPC decoder 166 is constructed in the same manner as the decoding device of FIG. 133 except that the reception data sorting unit 310 of FIG. 133 is not provided, except that the column replacement of equation (12) is not performed Except for this point, the rest performs the same processing as the decoding device of FIG. 133, and therefore the description thereof is omitted.

As described above, the LDPC decoder 166 can be configured without the reception data sorting unit 310, so the scale can be reduced compared to the decoding device of FIG. 133.

In addition, in FIGS. 130 to 134, in order to simplify the description, the code length N of the LDPC code is set to 90, the information length K is set to 60, and the parallel factor (the number of rows and columns constituting the matrix) P is set to 5. Set the factor q (=M/P) of the parity length M to 6, but each of the code length N, the information length K, the parallel factor P, and the factor q (=M/P) is not limited to The above value.

That is, in the transmission device 11 of FIG. 8, the output of the LDPC encoder 115 is, for example, the code length N is set to 64800, or 16200, 69120, 17280, etc., and the information length K is set to N-Pq( = NM), the parallel factor P is set to 360, and the factor q is set to the LDPC code of M/P. However, the LDPC decoder 166 of FIG. 134 can be applied to such LDPC codes by performing simultaneously P check node calculus and variable node calculus to perform LDPC decoding.

In addition, after decoding the LDPC code in the LDPC decoder 166, the parity part of the decoding result is unnecessary, and only the information bit of the decoding result is output, there is no need to decode the data sorting unit 311, This constitutes the LDPC decoder 166.

<Configuration example of block deinterleaver 54>

FIG. 135 is an explanatory diagram of block deinterleaving performed by the block deinterleaver 54 of FIG. 128. FIG.

In the block deinterleaving, by performing the reverse processing of the block interleaving of the block interleaver 25 described in FIG. 79, the arrangement of the code bits of the LDPC code will be restored to the original arrangement (recovered).

That is, in block deinterleaving, for example, in the same way as block interleaving, for m columns equal to the number of bits of symbols m, the LDPC code is written and read, and the code bits of the LDPC code The arrangement will be restored to the original arrangement.

However, in block deinterleaving, the LDPC code is written in accordance with the order in which the LDPC code is read in block interleaving. Furthermore, in block deinterleaving, the reading of the LDPC code is performed in accordance with the order in which the LDPC code is written in the block interleaving.

That is, as shown in FIG. 135, the part 1 of the LDPC code is written from the first row of all m columns to the horizontal direction, and the part 1 of the LDPC code that has become the symbol unit of m bits is written . That is, the code bits of the LDPC code that has become symbols of m bits are written in the horizontal direction.

The writing of the part 1 in m-bit units is performed sequentially in the row below the m columns. Once the writing of the part 1 is completed, as shown in FIG. 135, the first in the column The reading of the part 1 from the top to the bottom of each column unit is performed in the column from the left to the right.

Once the reading up to the right column is completed, as shown in FIG. 135, return to the left column and read the part 1 from the top to the bottom of the second column of the column Is carried out in a column from left to right, and in the same manner below, the reading of part 1 of the LDPC code of 1 codeword is performed.

Once the reading of part 1 of the LDPC code of 1 code word is completed, for part 2 that has become an m-bit symbol unit, its m-bit symbol unit will be sequentially connected after part 1, With this, the symbol unit LDPC code is restored to the original code bit arrangement of the LDPC code (LDCP code before block interleaving) of 1 codeword.

<Other configuration examples of bit deinterleaver 165>

FIG. 136 is a block diagram of another configuration example of the bit deinterleaver 165 of FIG. 127.

In addition, in the figure, the part corresponding to FIG. 128 is denoted by the same symbol, and the description thereof is appropriately omitted below.

That is, the bit deinterleaver 165 of FIG. 136 is constructed in the same manner as FIG. 128 except that the co-position deinterleaver 1011 is newly added.

In FIG. 136, the bit deinterleaver 165 is composed of a block deinterleaver 54, a group deinterleaver 55, and a parity deinterleaver 1011, and performs the code of the LDPC code from the demapper 164 Bit-by-bit deinterleaving.

That is, the block deinterleaver 54 takes the LDPC code from the de-encoder 164 as an object, and performs block deinterleaving corresponding to the block interleaving performed by the block interleaver 25 of the transmission device 11 (region Inverse processing of block interleaving), that is, deinterleaving the blocks where the positions of code bits replaced by block interleaving are restored to their original positions, and the resulting LDPC code is supplied to the group type Deinterleaver 55.

The group-type deinterleaver 55 is a group corresponding to the group-type interleaving performed by the group-type interleaver 24 of the transmission device 11 as a sorting process, taking the LDPC code from the block deinterleaver 54 as an object. Group deinterlacing.

The LDPC code obtained as a result of group deinterleaving is supplied from group deinterleaver 55 to co-located deinterleaver 1011.

The parity deinterleaver 1011 uses the grouped deinterleaved code bits in the group deinterleaver 55 as the object to perform the parity corresponding to the parity interleaving performed by the parity interleaver 23 of the transmitting device 11 Deinterleaving (inverse processing of co-located interlace), that is, the code bits of the LDPC code whose arrangement is changed by co-located interlace are restored to the original co-located de-interlacing.

The LDPC code obtained as a result of co-located deinterleaving is supplied from the co-located deinterleaver 1011 to the LDPC decoder 166.

Therefore, in the bit deinterleaver 165 of FIG. 136, the LDPC decoder 166 is supplied with LDPC codes that have undergone block deinterleaving, group deinterleaving, and co-located deinterleaving, that is, according to the check matrix H LDPC code obtained by LDPC encoding.

The LDPC decoder 166 decodes the LDPC code of the LDPC code from the bit deinterleaver 165 using the check matrix H used by the LDPC encoder 115 of the transmission device 11 in the LDPC encoding.

That is, the LDPC decoder 166 decodes the LDPC code of the LDPC code from the bit deinterleaver 165 for the type B method, and uses the LDPC encoder 115 of the transmission device 11 used in the LDPC encoding (type B method ) The inspection matrix H itself, or a conversion inspection matrix obtained by performing at least the same-column column replacement on the inspection matrix H is performed. In addition, the LDPC decoder 166 decodes the LDPC code of the LDPC code from the bit deinterleaver 165 for the type A method, and uses the (type A method) used by the LDPC encoder 115 of the transmission device 11 during LDPC encoding. Of) the inspection matrix (FIG. 27), the inspection matrix (FIG. 28) obtained by performing column replacement, or the conversion inspection matrix (FIG. 29) obtained by performing row replacement on the inspection matrix used in the LDPC encoding (FIG. 27), to Proceed.

Here, in FIG. 136, from the bit deinterleaver 165 (co-located deinterleaver 1011) to the LDPC decoder 166, the LDPC code obtained by LDPC encoding according to the check matrix H is supplied, so this The LDPC decoding of the LDPC code uses the type B method check matrix H itself used by the LDPC encoder 115 of the sending device 11 in LDPC encoding, or the type A method check matrix used in LDPC encoding (Figure 27) In the case of performing a check matrix (FIG. 28) obtained by performing column replacement, the LDPC decoder 166 can be operated by, for example, performing calculation of messages (check node messages, variable node messages) for 1 node at a time The LDPC decoding device caused by the full serial decoding method in sequence, or the full parallel decoding method that performs the calculation of the message for all nodes simultaneously (parallel) The result is a LDPC decoding device.

In addition, the LDPC decoder 166 decodes the LDPC code of the LDPC code and uses: for the type B method check matrix H used by the LDPC encoder 115 of the transmission device 11 in the LDPC encoding, at least the same bit interleaving is performed. If the conversion check matrix obtained by column replacement or the type A check matrix used for LDPC encoding (Figure 27) is replaced by a row check matrix (Figure 29), then The LDPC decoder 166 is a decoding device with a structure that simultaneously performs P (or a factor other than 1 of P) check node calculation and variable node calculation, and is obtained by implementing and using the LDPC code The column replacement required for the conversion check matrix (collocation interleaving) is the same as the column replacement, and is composed of a decoding device (FIG. 133) of the received data sorting section 310 that sorts the symbols of the LDPC code.

In addition, in FIG. 136, for convenience of description, the block deinterleaver 54 that performs block deinterleaving, the group deinterleaver 55 that performs group deinterleaving, and the parity deinterleaving that performs parity deinterleaving The interleaver 1011 is drawn separately, but the block deinterleaver 54, the group deinterleaver 55, and the co-located de-interleaver 1011 are more than two, which can be co-located with the transmitter 11 23. The group interleaver 24 and the block interleaver 25 are also integrally constructed.

<Configuration example of the receiving system>

FIG. 137 is a block diagram of a first configuration example of a receiving system to which the receiving device 12 can be applied.

In FIG. 137, the receiving system is composed of an acquisition unit 1101, a transmission path decoding processing unit 1102, and an information source decoding processing unit 1103.

The acquisition unit 1101 is a signal containing at least LDPC coded LDPC object data such as video data or audio data of a program, for example, through surface digital broadcasting, satellite digital broadcasting, CATV network, Internet or A transmission channel (communication channel) not shown in another network or the like is acquired and supplied to the transmission channel decoding processing unit 1102.

Here, if the signal acquired by the acquisition unit 1101 is broadcast from a broadcasting station through surface waves, or satellite waves, or a CATV (Cable Television) network, etc., the acquisition unit 1101 is controlled by a channel selector or STB (Set Top Box), etc. In addition, when the signal acquired by the acquisition unit 1101 is transmitted from a web server by a multicast method such as IPTV (Internet Protocol Television), for example, the acquisition unit 1101 is generated by, for example, NIC (Network Interface Card) It is composed of network I/F (Inter face).

The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission channel decoding processing unit 1102 implements transmission channel decoding processing including at least the process of correcting the error occurred in the transmission channel for the signal acquired by the acquisition unit 1101 through the transmission channel, and supplies the resulting signal to the Information source decoding processing unit 1103.

That is, the signal acquired by the acquisition unit 1101 through the transmission channel is a signal obtained by at least performing error correction coding required to correct errors occurring in the transmission channel, and the transmission channel decoding processing unit 1102 is The signal performs transmission channel decoding processing such as error correction processing.

Here, the error correction coding system includes, for example, LDPC coding, BCH coding, or the like. Here, as error correction coding, at least LDPC coding is performed.

In addition, the decoding process of the transmission path may include demodulation of the modulation signal.

The information source decoding processing unit 1103 performs information source decoding processing that includes at least the processing of decompressing the compressed information into the original information on the signal that has been subjected to the transmission path decoding processing.

That is, sometimes, for the signal acquired by the acquisition unit 1101 through the transmission path, in order to reduce the amount of data such as image or sound as information, compression encoding is performed to compress the information. At this time, the information source decodes The processing unit 1103 performs information source decoding processing such as processing (decompression processing) for decompressing the compressed information into the original information on the signal that has been subjected to the transmission channel decoding processing.

In addition, if the signal acquired by the acquisition unit 1101 through the transmission path has not been compression-encoded, the information source decoding processing unit 1103 does not decompress the compressed information into the original information. .

Here, as the decompression processing system, there is, for example, MPEG decoding. In addition, in the decoding process of the transmission path, in addition to understanding the compression process, it may sometimes include a descrambling code.

In the receiving system configured as described above, in the acquisition unit 1101, for example, data such as video or audio is subjected to compression encoding such as MPEG encoding, and then, after error correction encoding such as LDPC encoding is performed The signal is acquired through the transmission channel and supplied to the transmission channel decoding processing unit 1102.

In the transmission channel decoding processing unit 1102, the signal from the acquisition unit 1101, for example, the same processing as that performed by the receiving device 12, is implemented as a transmission channel decoding process, and the resulting signal, The system is supplied to the information source decoding processing unit 1103.

The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the transmission path decoding processing unit 1102, and the resulting video or audio is output.

The receiving system of FIG. 137 as described above can be applied to, for example, a TV tuner that receives a TV broadcast as a digital broadcast.

In addition, the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be implemented as a separate device (hardware (IC (Integrated Circuit), etc.)) or software module, respectively And make up.

Further, regarding the acquisition unit 1101, the transmission channel decoding processing unit 1102, and the information source decoding processing unit 1103, the collection unit 1101 and the transmission channel decoding processing unit 1102 may be combined, or the transmission channel decoding processing unit 1102 and the information source decoding process The set of the unit 1103, the acquisition unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 are configured as a single device.

FIG. 138 is a block diagram of a second configuration example of a receiving system to which the receiving device 12 can be applied.

In addition, in the figure, the part corresponding to FIG. 137 is denoted by the same symbol, and its description is appropriately omitted below.

The receiving system of FIG. 138 is the same as that of FIG. 137 in that it has the acquisition unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, and that the output unit 1111 is newly installed Is different from Figure 137.

The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs audio, and outputs an image or audio that is a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays video or outputs audio.

The reception system as shown in FIG. 138 above can be applied to, for example, a TV (television receiver) that receives a television broadcast as a digital broadcast, or a radio receiver that receives a radio broadcast.

In addition, when the signal acquired by the acquisition unit 1101 is not compression-encoded, the signal output by the transmission channel decoding processing unit 1102 is supplied to the output unit 1111.

FIG. 139 is a block diagram of a third configuration example of the receiving system to which the receiving device 12 can be applied.

In addition, in the figure, the part corresponding to FIG. 137 is denoted by the same symbol, and its description is appropriately omitted below.

The receiving system of FIG. 139 is the same as FIG. 137 in that it has an acquisition unit 1101 and a transmission path decoding processing unit 1102.

However, the receiving system of FIG. 139 is different from FIG. 137 in that the information source decoding processing unit 1103 is not provided, and the recording unit 1121 is newly provided.

The recording unit 1121 records (memorizes) the signal output by the transmission path decoding processing unit 1102 (for example, TS packet of MPEG TS) on a disc, hard disk (disk), flash memory, etc. (memory) ) In the media.

The receiving system as shown in Fig. 139 above can be applied to a video recorder that broadcasts a TV for recording.

In addition, in FIG. 139, the receiving system is configured with an information source decoding processing section 1103. In the information source decoding processing section 1103, the signal after the information source decoding processing is performed, that is, the decoding result The video or sound is recorded by the recording unit 1121.

<An embodiment of a computer>

Secondly, the above series of processing can be performed by hardware or software. When a series of processing is performed by software, the program constituting the software can be installed on a general-purpose computer, etc.

Here, FIG. 140 illustrates a configuration example of an embodiment of a computer on which a program that executes the above-mentioned series of processing is installed.

The program is a hard disk 705 or ROM 703 which can be recorded in advance in a computer as a recording medium.

Alternatively, the program system can be temporarily or permanently pre-stored (recorded) on a floppy disk, CD-ROM (Compact Disc Read Only Memory), MO (Magneto Optical) disk, DVD (Digital Versatile Disc), magnetic disk, semiconductor A removable recording medium 711 such as a memory. Such a removable recording medium 711 can be provided as so-called package software.

In addition to installing the program from the removable recording medium 711 to the computer as described above, the program can also be downloaded from a download site, digital satellite broadcasting artificial satellite, wirelessly transmitted to the computer, or via LAN (Local Area Network) , The Internet and other networks are transmitted to the computer in a wired manner. In the computer, the program thus transmitted is received by the communication unit 708 and can be installed in the built-in hard disk 705.

The computer department has a built-in CPU (Central Processing Unit) 702 . The CPU 702 is connected to the I/O interface 710 through the bus 701. Once the CPU 702 passes through the I/O interface 710, the user performs an input unit composed of a keyboard, mouse, microphone, etc. If the command is input after the operation of 707, etc., the program stored in the ROM (Read Only Memory) 703 will be executed. Or, the CPU 702 is a program stored in the hard disk 705, transmitted from a satellite or a network, received by the communication unit 708 and installed in the hard disk 705, or installed from the drive 709 The program on which the removable recording medium 711 is read and installed on the hard disk 705 is loaded into the RAM (Random Access Memory) 704 and executed. In this way, the CPU 702 performs the processing according to the above-mentioned flowchart or the processing performed by the above-mentioned block diagram. Then, the CPU 702 outputs the processing result as needed, for example, through the output interface 710 to output from the output unit 706 composed of an LCD (Liquid Crystal Display) or a speaker, etc., or sends the signal from the communication unit 708, or Even recorded in the hard disk 705 medium.

Here, in this specification, the processing steps described by the program used to allow the computer to perform various processes do not necessarily need to be processed in time series in the order described in the flowchart, but also include parallel Or individual processing (such as parallel processing or processing caused by objects).

In addition, the program system can be processed by one computer or distributed by multiple computers. Even, the program system can be transferred to a remote computer and executed.

In addition, the embodiment of the present technology is not limited to the above-mentioned embodiment, and various changes can be made without departing from the gist of the present technology.

For example, the above-mentioned new LDPC code (check matrix initial value table) or GW pattern is applicable to satellite lines, surface waves, cables (wire lines), and other communication paths 13 (FIG. 7). Even the new LDPC code or GW type system can be used for data transmission other than digital broadcasting.

In this specification, for ease of understanding, it is assumed that the LDPC encoder 115 (FIG. 8) encodes the LDPC code based on the check matrix, but the check matrix is equivalent to the check matrix initial value table. The information, therefore, the encoding of the LDPC code based on the check matrix includes the encoding of the LDPC code based on the check matrix initial value table. Similarly, in the LDPC decoder 166 (FIG. 127), the decoding of the LDPC code based on the check matrix includes the decoding of the LDPC code based on the check matrix initial value table.

In addition, the effects described in this specification are only examples and are not limited, and may have other effects.

11‧‧‧Sending device 12‧‧‧Receiving device 23‧‧‧ Parity interleaver 24‧‧‧Group interleaver 25‧‧‧ block interleaver 54‧‧‧block deinterleaver 55‧‧‧Group deinterleaver 111‧‧‧Mode adaptation/multiplexer 112‧‧‧Finisher 113‧‧‧BB code mixer 114‧‧‧BCH encoder 115‧‧‧LDPC encoder 116‧‧‧bit interleaver 117‧‧‧Antipode 118‧‧‧Interleaver 119‧‧‧SISO/MISO encoder 120‧‧‧ Frequency interleaver 121‧‧‧BCH encoder 122‧‧‧LDPC encoder 123‧‧‧Antipode 124‧‧‧ Frequency interleaver 131‧‧‧Frame Builder/Resource Allocation Department 132‧‧‧OFDM generation 151‧‧‧OFDM Processing Department 152‧‧‧ Frame Management Department 153‧‧‧ frequency deinterleaver 154‧‧‧De-emitter 155‧‧‧LDPC decoder 156‧‧‧BCH decoder 161‧‧‧ frequency deinterleaver 162‧‧‧SISO/MISO decoder 163‧‧‧Deinterleaver 164‧‧‧De-emitter 165‧‧‧bit deinterleaver 166‧‧‧LDPC decoder 167‧‧‧BCH decoder 168‧‧‧BB demixer 169‧‧‧Deletion of null value 170‧‧‧Demultiplexer 300‧‧‧Memory for branch data storage 301‧‧‧selector 302‧‧‧ Check Node Computing Department 303‧‧‧Circulation displacement circuit 304‧‧‧Memory for branch data storage 305‧‧‧selector 306‧‧‧Memory for receiving data 307‧‧‧ Variable Node Computing Department 308‧‧‧Circulation displacement circuit 309‧‧‧Decoded word calculation department 310‧‧‧Receiving data sorting department 311‧‧‧Decoding data sorting department 601‧‧‧Encoding Processing Department 602‧‧‧ Memory Department 611‧‧‧ coding rate setting section 612‧‧‧ Initial value table reading section 613‧‧‧Check matrix generation section 614‧‧‧ Information bit readout department 615‧‧‧Coincidence Calculation Department 616‧‧‧Control Department 701‧‧‧Bus 702‧‧‧CPU 703‧‧‧ROM 704‧‧‧RAM 705‧‧‧Hard Disk 706‧‧‧ Output 707‧‧‧ Input 708‧‧‧Ministry of Communications 709‧‧‧Drive 710‧‧‧I/O interface 711‧‧‧removable recording media 1001‧‧‧Reverse Sorting Department 1002‧‧‧Memory 1011‧‧‧Parallel deinterleaver 1101‧‧‧ Acquisition Department 1102‧‧‧Transmission Decoding Processing Department 1103‧‧‧ Information Source Decoding Processing Department 1111‧‧‧ Output 1121‧‧‧Recording Department

[Fig. 1] An explanatory diagram of the check matrix H of the LDPC code. [Figure 2] A flowchart for explaining the decoding procedure of the LDPC code. [Fig. 3] An illustration of an example of the check matrix of the LDPC code. [Fig. 4] An illustration of an example of a bipartite graph of a check matrix. [FIG. 5] An illustration of an example of a variable node. [Fig. 6] An illustration of an example of a check node. [Fig. 7] A diagram showing a configuration example of an embodiment of a transmission system to which the present technology is applied. [Fig. 8] A block diagram of a configuration example of the transmission device 11. [Fig. 9] A block diagram of a configuration example of the bit interleaver 116. [Fig. 10] A diagram of an example of a check matrix. [Fig. 11] A diagram of an example of a parity matrix. [Fig. 12] An explanatory diagram of the check matrix of the LDPC code specified in the DVB-T.2 specification. [Fig. 13] An explanatory diagram of the check matrix of the LDPC code specified in the DVB-T.2 specification. [Fig. 14] An illustration of an example of a bipartite graph for decoding of LDPC codes. [15] a staircase structure as a parity matrix H _T, and corresponding to the example of the parity matrix H _T of the bipartite graph of illustration. [16] with the LDPC code after interleaving of bits corresponding to the parity check matrix H is a matrix H _T of the illustrated example. [Fig. 17] A flowchart for explaining an example of processing performed by the bit interleaver 116 and the mapper 117. [Fig. 18] A block diagram of a configuration example of the LDPC encoder 115. [Fig. 19] A flowchart for explaining an example of processing of the LDPC encoder 115. [FIG. 20] An illustration of an example of the check matrix initial value table with a coding rate of 1/4 and a code length of 16,200. [Fig. 21] An explanatory diagram of a method of obtaining the inspection matrix H from the initial value table of the inspection matrix. [Fig. 22] A diagram of the structure of the inspection matrix. [Fig. 23] A diagram showing an example of the initial value table of the inspection matrix. [Fig. 24] An explanatory diagram of the A matrix generated from the initial value table of the inspection matrix. [Fig. 25] An explanatory diagram of co-interleaving of the B matrix. [Fig. 26] An explanatory diagram of the C matrix generated from the initial value table of the inspection matrix. [Fig. 27] An explanatory diagram of the co-interleaving of the D matrix. [Fig. 28] A diagram of an inspection matrix obtained by performing column permutation as a column permutation of an in-situ de-interleaving that restores an in-situ interleaving. [Fig. 29] A diagram of a conversion inspection matrix obtained by performing row permutation on the inspection matrix. [Fig. 30] A diagram of an example of an initial value table of a check matrix of a type A code with N=17280 bits and r=2/16. [FIG. 31] An illustration of an example of the initial value table of the check matrix of the type A code of N=17280 bits and r=3/16. [FIG. 32] A diagram of an example of an initial value table of a check matrix of a type A code with N=17280 bits and r=4/16. [FIG. 33] An illustration of an example of the initial value table of the check matrix of the type A code with N=17280 bits and r=5/16. [FIG. 34] A diagram of an example of an initial value table of a check matrix of a type A code with N=17280 bits and r=6/16. [FIG. 35] A diagram of an example of an initial value table of a check matrix of a type A code with N=17280 bits and r=7/16. [FIG. 36] A diagram of an example of an initial value table of a check matrix of a type B code with N=17280 bits and r=7/16. [Fig. 37] A diagram of an example of an initial value table of a check matrix of a type B code of N=17280 bits and r=8/16. [Fig. 38] A diagram of an example of an initial value table of a check matrix of a type B code of N=17280 bits and r=9/16. [Fig. 39] A diagram of an example of an initial value table of a check matrix of a type B code of N=17280 bits and r=10/16. [Fig. 40] A diagram of an example of an initial value table of a check matrix of a type B code of N=17280 bits and r=11/16. [FIG. 41] A diagram of an example of an initial value table of a check matrix of a type B code with N=17280 bits and r=12/16. [FIG. 42] A diagram of an example of an initial value table of a check matrix of a type B code with N=17280 bits and r=13/16. [Fig. 43] A diagram of an example of an initial value table of a check matrix for a type B code of N=17280 bits and r=14/16. [Fig. 44] An illustration of an example of an overall bipartite graph of a degree sequence with a column weight of 3 and a row weight of 6. [Fig. 45] An illustration of an example of an overall bipartite graph of multiple branch types. [Fig. 46] An explanatory diagram of the inspection matrix of the type A method. [Fig. 47] An explanatory diagram of the inspection matrix of the type A method. [Fig. 48] An explanatory diagram of the inspection matrix of the type B method. [Fig. 49] An explanatory diagram of the inspection matrix of the type B method. [FIG. 50] A diagram of an example of an initial value table of a check matrix of a new type A code of N=17280 bits and r=4/16. [Figure 51] A diagram of the parameters of the check matrix H of the new type A code with r=4/16. [FIG. 52] A diagram of an example of an initial value table of a check matrix of a new type B code of N=17280 bits and r=9/16. [Figure 53] A diagram of the parameters of the check matrix H of the new type B code with r=9/16. [FIG. 54] An illustration of an example of the coordinate of the signal point of UC when the modulation method is QPSK. [FIG. 55] An illustration of an example of the coordinates of the 2D-NUC signal point when the modulation method is 16QAM. [Fig. 56] An illustration of an example of the coordinate of the 1D-NUC signal point when the modulation method is 1024QAM. [Fig. 57] A diagram of the relationship between the symbol y of 1024QAM and the position vector u. [Figure 58] An illustration of an example of the coordinate z _q of the signal point of QPSK-UC. [Figure 59] An illustration of an example of the coordinate z _q of the signal point of QPSK-UC. [Fig. 60] An illustration of an example of the coordinate z _q of the signal point of 16QAM-UC. [Fig. 61] An illustration of an example of the coordinate z _q of the signal point of 16QAM-UC. [Fig. 62] An illustration of an example of the coordinate z _q of the signal point of 64QAM-UC. [Figure 63] An illustration of an example of the coordinate z _q of the signal point of 64QAM-UC. [Fig. 64] An illustration of an example of the coordinate z _q of the signal point of 256QAM-UC. [Figure 65] An illustration of an example of the coordinate z _q of the signal point of 256QAM-UC. [Figure 66] An illustration of an example of the coordinate z _q of the signal point of 1024QAM-UC. [Figure 67] An illustration of an example of the coordinate z _q of the signal point of 1024QAM-UC. [Figure 68] An illustration of an example of the coordinate z _q of the signal point of 4096QAM-UC. [Figure 69] An illustration of an example of the coordinate z _q of the signal point of 4096QAM-UC. [Figure 70] An illustration of an example of the coordinate z _s of the signal point of 16QAM-2D-NUC. [Figure 71] An illustration of an example of the coordinate z _s of the signal point of 64QAM-2D-NUC. [Figure 72] An illustration of an example of the coordinate z _s of the signal point of 256QAM-2D-NUC. [Figure 73] An illustration of an example of the coordinate z _s of the signal point of 256QAM-2D-NUC. [Figure 74] An illustration of an example of the coordinate z _s of the signal point of 1024QAM-1D-NUC. [Fig. 75] A diagram of the relationship between the symbol y of 1024QAM and the position vector u. [Fig. 76] An illustration of an example of the coordinate z _s of the signal point of 4096QAM-1D-NUC. [Fig. 77] A diagram of the relationship between the symbol y of 4096QAM and the position vector u. [Fig. 78] A diagram of the relationship between the symbol y of 4096QAM and the position vector u. [Fig. 79] An explanatory diagram of block interleaving performed by the block interleaver 25. [Fig. 80] An explanatory diagram of block interleaving performed by the block interleaver 25. [Fig. 81] An explanatory diagram of group interleaving performed in the group interleaver 24. [Fig. 82] A diagram showing a first example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 83] A diagram showing a second example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 84] A diagram showing a third example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 85] A diagram showing a fourth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 86] A diagram showing a fifth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 87] A diagram showing a sixth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 88] A diagram showing a seventh example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 89] An illustration of an eighth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 90] A diagram showing a ninth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 91] An illustration of a tenth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 92] An illustration of an eleventh example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 93] An illustration of a twelfth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 94] A diagram showing a thirteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 95] A diagram showing a 14th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 96] A diagram showing a fifteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 97] An illustration of a 16th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 98] A diagram showing a 17th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 99] An illustration of an eighteenth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 100] A diagram showing a nineteenth example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 101] An illustration of a twentieth example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 102] An illustration of a twenty-first example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 103] A diagram showing a 22nd example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 104] An illustration of a 23rd example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 105] A diagram showing a 24th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 106] An illustration of a 25th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 107] An illustration of a 26th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 108] An illustration of a 27th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 109] A diagram showing a 28th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 110] An illustration of the 29th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 111] An illustration of the 30th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 112] An illustration of the 31st example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 113] An illustration of the 32nd example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 114] An illustration of the 33rd example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 115] An illustration of the 34th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 116] An illustration of the 35th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [FIG. 117] A diagram showing a 36th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 118] An illustration of the 37th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 119] An illustration of a 38th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 120] An illustration of the 39th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 121] An illustration of the 40th example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 122] An illustration of a 41st example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 123] A diagram showing a 42nd example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 124] An illustration of the 43rd example of the GW pattern of the LDPC code whose code length N is 17280 bits. [Fig. 125] An illustration of a 44th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [Fig. 126] An illustration of a 45th example of the GW pattern of an LDPC code whose code length N is 17280 bits. [FIG. 127] A block diagram of a configuration example of the receiving device 12. [Fig. 128] A block diagram of a configuration example of a bit deinterleaver 165. [Fig. 129] A flowchart for explaining an example of processing performed by the mapper 164, the bit deinterleaver 165, and the LDPC decoder 166. [Fig. 130] An illustration of an example of the check matrix of the LDPC code. [Fig. 131] A diagram showing an example of a matrix (transition check matrix) obtained by performing row replacement and column replacement on an inspection matrix. [FIG. 132] An illustration of an example of a conversion check matrix divided into 5×5 units. [FIG. 133] A block diagram of a configuration example of a decoding device in which P node calculations are performed in batches. [FIG. 134] A block diagram of a configuration example of the LDPC decoder 166. [FIG. [Fig. 135] An explanatory diagram of block deinterleaving performed by the block deinterleaver 54. [FIG. 136] A block diagram of another configuration example of the bit deinterleaver 165. [FIG. [FIG. 137] A block diagram of a first configuration example of a receiving system to which the receiving device 12 can be applied. [FIG. 138] A block diagram of a second configuration example of a receiving system to which the receiving device 12 can be applied. [FIG. 139] A block diagram of a third configuration example of a receiving system to which the receiving device 12 can be applied. [Fig. 140] A block diagram of a configuration example of one embodiment of a computer to which this technology is applied.

Claims (12)

A method of sending messages, which includes: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 3/16, and LDPC encoding; and a group interleaving step, which performs The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column The A matrix and the C matrix adjacent to the B matrix below; the D matrix adjacent to the NK-M1 row and the NK-M1 column, and the D matrix adjacent to the right of the C matrix belonging to the identity matrix; the M1 value set in the foregoing note is 1440; And the C matrix is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the positions of the elements of the preamble A matrix and the C matrix 1 every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 3/16, and LDPC coding is performed; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units. Interleaved group-type interleaving; and the mapping step, which maps the predecessor LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column The A matrix and the C matrix adjacent to the B matrix below; the D matrix adjacent to the NK-M1 row and the NK-M1 column, and the D matrix adjacent to the right of the C matrix belonging to the identity matrix; the M1 value set in the foregoing note is 1440; And the C matrix is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the positions of the elements of the preamble A matrix and the C matrix 1 every 360 columns, and is:

A method of sending messages, including: an encoding step based on a check matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 5/16, and LDPC encoding; and a group interleaving step, which involves The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of the bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the bottom of the predecessor B matrix; the D matrix adjacent to the NK-M1 row and NK-M1 column, adjacent to the right of the predecessor C matrix belonging to the identity matrix; the M1 value set in the preamble is 720; And the C matrix is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the positions of the elements of the preamble A matrix and the C matrix 1 every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 5/16, and performs LDPC coding; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units Interleaved group interleaving; and the mapping step is to map the previous LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the foreword check matrix contains: the M1 row and K column represented by the predetermined value M1 and the information length K=N×r of the foreword LDPC code, the A matrix at the upper left of the foreword check matrix; and the M1 row M1 column , The matrix B of the ladder structure adjacent to the right of the preceding A matrix; and the matrix Z of the zero matrix adjacent to the right of the M matrix row NK-M1; and the Z matrix of the NK-M1 row K+M1 column, the preceding note The A matrix and the C matrix adjacent to the bottom of the predecessor B matrix; the D matrix adjacent to the NK-M1 row and NK-M1 column, adjacent to the right of the predecessor C matrix belonging to the identity matrix; the M1 value set in the preamble is 720; And the C matrix is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the positions of the elements of the preamble A matrix and the C matrix 1 every 360 columns, and is:

A method of sending messages, including: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 7/16; and LDPC encoding; and a group interleaving step The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of the bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 7/16, and performs LDPC coding; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units Interleaved group interleaving; and the mapping step is to map the previous LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A method for sending messages, including: an encoding step, which is based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 9/16, and LDPC encoding; and a group interleaving step, which performs The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of the bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 9/16, and LDPC coding is performed; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units. Interleaved group interleaving; and the mapping step is to map the previous LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A method of sending messages, including: an encoding step based on an inspection matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 11/16; and an LDPC encoding; and a group interleaving step The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 11/16, and performs LDPC coding; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units Interleaved group-type interleaving; and the mapping step, which maps the predecessor LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A method for sending messages, including: an encoding step based on a check matrix of an LDPC code with a code length N of 17280 bits and an encoding rate r of 13/16; and LDPC encoding; and a group interleaving step The predecessor LDPC code is interleaved in groups of 360-bit bit groups; and the mapping step is to map the predecessor LDPC code to 256QAM UC (Uniform Constellation) in 8-bit units Any one of the 256 signal points; In the preamble group interleaving, the i+1th bit group from the beginning of the predecessor LDPC code is regarded as the bit group i, and the preamble is 17280 bits The arrangement of the bit groups 0 to 47 of the LDPC code is interleaved into bit groups

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

A receiving device, comprising: a decoding unit, which decodes the LDPC code obtained from the data sent by the sending method; wherein the preceding sending method contains: an encoding step, based on the code length N is the inspection matrix of the LDPC code of 17280 bits and the coding rate r is 13/16, and performs LDPC coding; and the group interleaving step is to carry out the previous LDPC code in 360-bit bit group units. Interleaved group-type interleaving; and the mapping step, which maps the predecessor LDPC code to any of the 256 signal points of 256QAM UC (Uniform Constellation) in 8-bit units; In interleaving, the i+1th bit group from the beginning of the previous LDPC code is regarded as bit group i, and the bit groups 0 to 47 of the predecessor 17280-bit LDPC code are arranged to interleave Bit group

The arrangement of the preface LDPC code contains information bits and parity bits; the preface inspection matrix contains: the information matrix part corresponding to the preface information bits and the parity matrix part corresponding to the preface parity bits; the preface information matrix part It is represented by the check matrix initial value table; the preamble check matrix initial value table is a table that represents the position of the element 1 of the preamble information matrix section every 360 columns, and is:

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