TWI687914B - Pulse signal control module, synchronous pulse signal generation method, source driver and display device - Google Patents

Abstract

A pulse signal control module for a source driver has: a channel mode detection circuit for detecting a channel mode; a DIO signal generation circuit for generating a control signal according to the channel mode to determine a The settling time and width of the first pulse signal of one of the buffer output stages, where the first pulse signal is used to notify the next source driver; a buffer input stage is used for the previous source The first pulse signal of the driver is buffered to generate a second pulse signal; a pulse width detection circuit to detect the width of the second pulse signal to generate a synchronization control signal; and a clock synchronization circuit to use A delay time is determined according to the synchronization control signal, and the second pulse signal is delayed according to the delay time to generate a third pulse signal.

Description

Pulse signal control module, synchronous pulse signal generation method, source driver and display device

The present invention relates to a method for enabling multiple source drivers to operate sequentially in a synchronous mode, in particular, a method for determining different synchronization pulse signal widths according to different channel modes, and determining different synchronization pulse signal widths according to different synchronization pulse signal widths The method of output pulse signal establishment time.

With the development of technology, most electronic products used by people in daily life have display screens. In the display screen, each pixel unit is charged through the source driver and the gate driver to achieve the display effect. The source driver includes a shift register, a data register, a data latch, a voltage level booster, a digital analog converter, and an output buffer.

FIG. 1a is a schematic diagram of a DIO (digital input output) buffer structure of an existing source driver. As shown in FIG. 1a, a first IC (integrated circuit) 10 buffers an internal signal S _IN by an inverter 11 and a buffer output stage 12 to generate a first pulse signal S1, in which the buffer outputs The output of stage 12 is coupled to a parasitic capacitor 30; and a second IC 20 buffers the first pulse signal S1 by a buffer input stage 21 to generate a second pulse signal S2, and by a synchronization circuit 22 Perform a delay operation on the second pulse signal S2 to generate a third pulse signal S3 after a predetermined time.

Please refer to FIG. 1b, which is a schematic diagram of a working timing of the DIO buffer architecture of FIG. 1a. As shown in FIG. 1b, the DIO buffer architecture uses a synchronous clock CLK3 (which is a clock obtained by dividing a basic clock by a frequency divided by 3, and the period of the basic clock is T); In channel mode CM1 (for example, in a case where there are 966 pixel data channels in a display), the second pulse signal S2 will be established 3T after the rising edge of the first pulse signal S1, and the synchronization circuit 22 enables The three-pulse signal S3 is established 9T after the rising edge of the second pulse signal S2, and the third pulse signal S3 can be synchronized with the start channel clock of the synchronization clock CLK3; and in the second channel mode CM2 (for example, In the case of a display with 960 pixel data channels), the second pulse signal S2 will be established 3T after the rising edge of the first pulse signal S1, and the third pulse signal S3 will be in the second due to the synchronization circuit 22 The pulse signal S2 is established 9T after the rising edge, so the third pulse signal S3 can be synchronized with the end channel clock of the synchronization clock CLK3.

However, when the frequency of the synchronization clock changes, the DIO buffer architecture of FIG. 1a cannot ensure that the third pulse signal S3 has the correct settling time in the first channel mode CM1 and in the second channel mode CM2. Please refer to FIG. 1c, which is another schematic diagram of the working timing of the DIO buffer architecture of FIG. 1a. As shown in FIG. 1c, when the DIO buffer architecture uses a synchronous clock CLK6 (which is a clock obtained by dividing a basic clock by a frequency divided by 6, the period of the basic clock is T), because In the first channel mode CM1, the second pulse signal S2 will be established 6T after the rising edge of the first pulse signal S1. In order to synchronize the third pulse signal S3 with the start channel clock of the synchronization clock CLK3, the synchronization The circuit 22 needs to make the third pulse signal S3 established 6T after the rising edge of the second pulse signal S2. However, since the second pulse signal S2 is generated on the rising edge of the synchronous clock CLK6, in the first channel mode CM1, the second pulse signal S2 is generated 6T after the rising edge of the first pulse signal S1, and In the second channel mode CM2, the second pulse signal S2 is established 3T after the rising edge of the first pulse signal S1. Therefore, when the third pulse signal S3 is set to be established at 6T after the rising edge of the second pulse signal S2, the establishment time will be the channel clock before the end of the synchronization clock CLK3, and the synchronization clock The clock of the last channel of CLK3 is not synchronized, resulting in data transmission errors.

In order to solve the above problems, a novel pulse driver control module of the source driver is urgently needed in the art.

Under the condition that the chip application conditions, chip frequency, and DIO load capacitance are unknown, traditional DIO buffers often have excessive design, and excessive design will consume too much area and power consumption, and in order to improve the driving ability, the excessive design The peak current specification will cause the DIO buffer to draw too much current from the power supply voltage (VDD), causing the power supply voltage to drop too much, which affects chip performance. Therefore, the present invention provides a pulse signal control module used in a source driver, which can extend the DIO buffer setup time from the traditional 3 basic cycles (ie 3T) to 6 basic cycles (ie 6T), And correspondingly provide different delay times in different channel modes, so that an output pulse signal can have the correct settling time in different channel modes, thereby ensuring that the source driver can operate synchronously with a gate driver, At the same time, the area occupied by the DIO buffer, the required peak current and the resulting voltage drop of the power supply voltage are greatly reduced.

Another object of the present invention is to provide a method for generating a synchronous pulse signal of a source driver, which can correspondingly provide different delay times in different channel modes, so that an output pulse signal can be provided in different channel modes The correct settling time ensures that a source driver can operate synchronously with a gate driver.

Another object of the present invention is to provide a source driver that can provide different delay times correspondingly in different channel modes, so that an output pulse signal can have a correct settling time in different channel modes, thereby Ensure that the source driver can operate synchronously with a gate driver.

In order to achieve the above purpose, a pulse signal control module for a source driver is proposed, which has: a channel pattern detection circuit for detecting a channel pattern; 　　 a DIO signal generation circuit for The channel mode generates a control signal to determine the settling time and width of a first pulse signal of a buffer output stage, wherein the first pulse signal is used to notify the next source driver; a buffer input stage, Used to buffer the first pulse signal of the previous source driver to generate a second pulse signal; a pulse width detection circuit to detect the width of the second pulse signal to generate a synchronous control A signal; and a clock synchronization circuit for determining a delay time according to the synchronization control signal, and delaying the second pulse signal according to the delay time to generate a third pulse signal.

In one embodiment, under different channel modes, the first pulse signal has different widths.

To achieve the above object, the present invention further discloses a method for generating a synchronous pulse signal of a source driver, which includes the following steps: 　　using a channel pattern detection circuit to detect a channel pattern; using a DIO signal generation circuit to determine a The establishment time and width of the first pulse signal of one of the buffer output stages, wherein the first pulse signal is used to notify the next of the source driver; 　　 uses a buffer input stage for the previous one of the source driver The first pulse signal is buffered to generate a second pulse signal; using a pulse width detection circuit to detect the width of the second pulse signal to generate a synchronization control signal; and using a clock synchronization circuit to follow the synchronization control signal A delay time is determined, and the second pulse signal is delayed according to the delay time to generate a third pulse signal.

In one embodiment, under different channel modes, the first pulse signal has different widths.

To achieve the above objective, the present invention further discloses a source driver, which has a multi-drop connection (multi-drop) interface and a pulse signal control module to ensure that the source driver can be synchronized with a gate driver, and more The source driver can cooperatively drive a display panel through the multi-point connection interface. The pulse signal control module has: a channel pattern detection circuit for detecting a channel pattern; 　　 a DIO signal generation circuit , Used to generate a control signal according to the channel mode to determine the settling time and width of a first pulse signal of a buffer output stage, wherein the first pulse signal is used to notify the next source driver; a The buffer input stage is used to buffer the first pulse signal of the previous source driver to generate a second pulse signal; a pulse width detection circuit for detecting the width of the second pulse signal To generate a synchronization control signal; and a clock synchronization circuit for determining a delay time according to the synchronization control signal, and delaying the second pulse signal according to the delay time to generate a third pulse signal.

In one embodiment, under different channel modes, the first pulse signal has different widths.

In a possible embodiment, the multi-point connection interface may be a mini-low voltage differential signal (mini-LVDS) interface or a low-swing differential signal (Reduced Swing Differential Signaling; RSDS) interface.

To achieve the above objective, the present invention further provides a display device having a display panel and at least one source driver as described above for driving the display panel.

In a possible embodiment, the multi-point connection interface may be a mini low voltage differential signal interface or a low swing differential signal interface.

In order to enable your review committee to further understand the structure, features and purpose of the present invention, the drawings and detailed description of the preferred embodiments are attached as follows.

Please refer to FIG. 2, which illustrates a block diagram of an embodiment of a pulse signal control module for a source driver of the present invention. As shown in FIG. 2, a source driver 100 includes a pulse signal control module composed of a first buffer unit 110 and a second buffer unit 120, wherein the previous source driver 100 is composed of the first buffer unit 110 Output a first pulse signal S1 to the second buffer unit 120 of the next source driver 100, and the second buffer unit 120 of the next source driver 100 is established at a corresponding time according to the width of the first pulse signal S1 A third pulse signal S3.

The first buffer unit 110 includes an inverter 111, a buffer output stage 112, a channel mode detection circuit 113, and a DIO signal generation circuit 114.

The inverter 111 has an input terminal and an output terminal. The input terminal is used for coupling with an internal pulse signal S _IN , and the output terminal is coupled with the buffer output stage 112.

The buffer output stage 112 generates the first pulse signal S1 according to the internal pulse signal S _IN , and determines the settling time and width of the first pulse signal S1 under the control of the DIO signal generation circuit 114. In addition, the output terminal of the buffer output stage 112 is coupled to a parasitic capacitor 130.

The channel mode detection circuit 113 is used to detect a channel mode, for example, by detecting a status signal to know whether the channel mode is the first channel mode (a display has a total of 966 pixel data channels) or the second channel Mode (a display has a total of 960 pixel data channels).

The DIO signal generation circuit 114 controls the buffer output stage 112 according to the detection result of the channel pattern detection circuit 113 to determine the setup time and width of the first pulse signal S1.

The second buffer unit 120 includes a buffer input stage 121, a clock synchronization circuit 122, and a pulse width detection circuit 123.

The buffer input stage 121 is used to buffer the first pulse signal S1 of the previous source driver according to the control of a clock signal CK to generate a second pulse signal S2, wherein the clock signal CK is performed on a basic clock A clock obtained by frequency division operation, the period of the basic clock is T, and the time when the second pulse signal S2 lags the first pulse signal S1 is equal to one cycle of the clock signal CK (= nT, n is an integer greater than 1 ).

The clock synchronization circuit 122 is used to generate the third pulse signal S3 according to the second pulse signal S2, and determines the setup time of the third pulse signal S3 according to a control signal CNTL provided by the pulse width detection circuit 123.

The pulse width detection circuit 123 is used to detect the width of the second pulse signal S2 and generate a control signal CNTL according to the width of the second pulse signal S2 to control the clock synchronization circuit 122 to determine the establishment time of the third pulse signal S3 .

In addition, in the specific channel mode of the pulse signal control module of the present invention, the establishment time of the first pulse signal S1 may be earlier or later than a reference time point.

Please refer to FIG. 3, which is a working timing diagram of a pulse signal control module of the present invention, in which the settling time of the first pulse signal S1 in the second channel mode CM2 is 3T earlier than a reference time point.

As shown in FIG. 3, in the first channel mode CM1, the first pulse signal S1 is established at the rising edge of the second cycle of the clock CLK6 with a width of 6T; the second pulse signal S2 rises at the first pulse signal S1 It is generated at 6T after the edge and its width is 6T; and the third pulse signal S3 is generated at 6T from the falling edge of the second pulse signal S2. According to this timing, the third pulse signal S3 can be synchronized with the start channel clock of the clock CLK3.

In the second channel mode CM2, the first pulse signal S1 is established 3T in advance and has a width of 9T; the second pulse signal S2 is generated 6T after the rising edge of the first pulse signal S1 and its width is 9T; and the third The pulse signal S3 is generated at 6T from the falling edge of the second pulse signal S2. According to this timing, the third pulse signal S3 can be synchronized with the end channel clock of the clock CLK3.

Please refer to FIG. 4, which is another working timing diagram of the pulse signal control module of the present invention, in which the settling time of the first pulse signal S1 in the second channel mode CM2 is delayed by 3T from a reference time point.

As shown in FIG. 4, in the first channel mode CM1, the first pulse signal S1 is established at the rising edge of the second cycle of the clock CLK6, and the width is 6T; the second pulse signal S2 rises at the first pulse signal S1 It is generated at 6T after the edge and its width is 6T; and the third pulse signal S3 is generated at 6T from the falling edge of the second pulse signal S2. According to this timing, the third pulse signal S3 can be synchronized with the start channel clock of the clock CLK3.

In the second channel mode CM2, the first pulse signal S1 is established after 3T and has a width of 9T; the second pulse signal S2 is generated 6T after the rising edge of the first pulse signal S1 and has a width of 9T; and The three-pulse signal S3 is generated at the falling edge from the second pulse signal S2. According to this timing, the third pulse signal S3 can be synchronized with the end channel clock of the clock CLK3.

According to the above principle, the present invention further provides a method for generating a synchronous pulse signal of the source driver. Please refer to FIG. 5, which is a flowchart of an embodiment of a method for generating a synchronous pulse signal of a source driver of the present invention. As shown in FIG. 5, the method includes the following steps: detecting a channel pattern in the first IC (S501); determining the settling time and width of a first pulse signal in the first IC according to the channel pattern (S501) S502); performing a buffer operation on the first pulse signal in the second IC to generate a second pulse signal (S503); and detecting the width of the second pulse signal in the second IC, and The establishment time of a third pulse signal is determined according to the width (S504).

That is to say, the synchronization pulse signal generation method of FIG. 5 mainly includes: using a channel pattern detection circuit 113 to detect a channel pattern; using a DIO signal generation circuit 114 to determine the first of a buffer output stage 112 according to the channel pattern Settling time and width of a pulse signal S1, wherein, in different channel modes, the first pulse signal S1 has a different width, and the first pulse signal S1 is used to notify the next source driver 100; using a buffer The input stage 121 buffers the first pulse signal S1 of the previous source driver 100 to generate a second pulse signal S2; a pulse width detection circuit 123 detects the width of the second pulse signal S2 to generate a The synchronization control signal CNTL; and a clock synchronization circuit 122 determines a delay time according to the synchronization control signal CNTL, and delays the second pulse signal S2 according to the delay time to generate a third pulse signal S3.

According to the above description, the present invention further provides a source driver, which has a multi-drop connection (multi-drop) interface and a pulse signal control module to ensure that the source driver can be synchronized with a gate driver, and more The source driver can cooperatively drive a display panel through the multi-point connection interface. The pulse signal control module has: a channel mode detection circuit for detecting a channel mode; a DIO signal generation circuit For generating a control signal according to the channel mode to determine the settling time and width of a first pulse signal of a buffer output stage, wherein, in different channel modes, the first pulse signal has different Width to inform the next source driver; a buffer input stage to buffer the first pulse signal of the previous source driver to generate a second pulse signal; a pulse width detection circuit To detect the width of the second pulse signal to generate a synchronization control signal; and a clock synchronization circuit to determine a delay time according to the synchronization control signal and delay the second pulse signal according to the delay time to generate A third pulse signal.

In a possible embodiment, the multi-point connection interface may be a mini-low voltage differential signal (mini-LVDS) interface or a low-swing differential signal (Reduced Swing Differential Signaling; RSDS) interface.

Based on the above principle, the present invention further provides a display device having a display panel and at least one source driver as described above for driving the display panel, and the multi-point connection interface may be a mini low voltage difference Dynamic signal interface or a low-swing differential signal interface.

With the design disclosed above, the present invention has the following advantages:

1. The pulse signal control module used in a source driver of the present invention can correspondingly provide different delay times in different channel modes, so that an output pulse signal can have correct delay in different channel modes Settling time to ensure that the source driver can operate synchronously with a gate driver.

2. The synchronous pulse signal generation method of the source driver of the present invention can correspondingly provide different delay times in different channel modes, so that an output pulse signal can have a correct settling time in different channel modes, thereby Ensure that a source driver can operate synchronously with a gate driver.

3. The source driver of the present invention can correspondingly provide different delay times in different channel modes, so that an output pulse signal can have the correct settling time in different channel modes, thereby ensuring that the source driver can Synchronous operation with a gate driver.

The case disclosed in this case is a preferred embodiment, and any part of the modification or modification that originates from the technical idea of this case and can be easily inferred by those skilled in the art, does not deviate from the patent scope of this case.

In summary, regardless of the purpose, means or effectiveness of this case, it shows that it is very different from the conventional technology, and its first invention is practical and practical, and it does meet the patent requirements of the invention. Society is for supreme prayer.

10: First IC

11: Inverter

12: buffer output stage

20: Second IC

21: Buffer input stage

22: Synchronous circuit

30: Parasitic capacitance

100: source driver

110: first buffer unit

111: Inverter 111

112: buffer output stage

113: Channel mode detection circuit

114: DIO signal generation circuit

120: second buffer unit

121: Buffer input stage

122: Clock synchronization circuit

123: Pulse width detection circuit

130: Parasitic capacitance

S501: Detect a channel mode in the first IC

S502: Determine the setup time and width of a first pulse signal in the first IC according to the channel mode

S503: Perform a buffer operation on the first pulse signal in the second IC to generate a second pulse signal

S504: Detect the width of the second pulse signal in the second IC, and determine the establishment time of a third pulse signal according to the width

FIG. 1a is a schematic diagram of a DIO buffer structure of an existing source driver. FIG. 1b is a schematic diagram of a working timing of the DIO buffer architecture of FIG. 1a. FIG. 1c is another schematic diagram of the working timing of the DIO buffer architecture of FIG. 1a. 2 is a block diagram of an embodiment of a pulse signal control module for a source driver of the present invention. FIG. 3 is a working timing diagram of one of the pulse signal control modules of the present invention. FIG. 4 is another working timing diagram of the pulse signal control module of the present invention. 5 is a flowchart of an embodiment of a method for generating a synchronous pulse signal of a source driver of the present invention

100: source driver

110: first buffer unit

111: Inverter 111

112: buffer output stage

113: Channel mode detection circuit

114: DIO signal generation circuit

120: second buffer unit

121: Buffer input stage

122: Clock synchronization circuit

123: Pulse width detection circuit

130: Parasitic capacitance

Claims (9)

A pulse signal control module for a source driver includes: a channel pattern detection circuit for detecting a channel pattern; and a digital input/output signal generation circuit for generating a control signal according to the channel pattern To determine the settling time and width of a first pulse signal of a buffer output stage, wherein the first pulse signal is used to notify the next source driver; a buffer input stage is used to The first pulse signal of the source driver is buffered to generate a second pulse signal; a pulse width detection circuit for detecting the width of the second pulse signal to generate a synchronization control signal; and a clock synchronization The circuit is used to determine a delay time according to the synchronization control signal, and delay the second pulse signal according to the delay time to generate a third pulse signal. The pulse signal control module according to claim 1, wherein the first pulse signal has different widths in different channel modes. A method for generating a synchronous pulse signal of a source driver includes the following steps: a channel pattern detection circuit is used to detect a channel pattern; a digital input/output signal generation circuit is used to determine the first output of a buffer output stage according to the channel pattern Settling time and width of a pulse signal, wherein the first pulse signal is used to notify the next source driver; a buffer input stage is used to perform the first pulse signal of the previous source driver Buffering to generate a second pulse signal; using a pulse width detection circuit to detect the width of the second pulse signal to generate a synchronization control signal; and using a clock synchronization circuit to determine a delay time according to the synchronization control signal, and according to The delay time delays the second pulse signal to generate a third pulse signal. The method for generating a synchronous pulse signal according to claim 3, wherein the first pulse signal has different widths in different channel modes. A source driver with a multi-point connection interface and a pulse signal control module to ensure that the source driver can operate synchronously with a gate driver, and a plurality of the source drivers can pass the multi-point The connection interface cooperatively drives a display panel. The pulse signal control module has: a channel mode detection circuit for detecting a channel mode; and a digital input/output signal generation circuit for generating a control signal according to the channel mode Determines the settling time and width of a first pulse signal of a buffer output stage, where the first pulse signal is used to notify the next of the source driver; a buffer input stage is used for the previous one The first pulse signal of the source driver is buffered to generate a second pulse signal; a pulse width detection circuit for detecting the width of the second pulse signal to generate a synchronization control signal; and a clock synchronization circuit To determine a delay time according to the synchronization control signal, and delay the second pulse signal according to the delay time to generate a third pulse signal. The source driver according to claim 5, wherein the first pulse signal has different widths in different channel modes. The source driver according to claim 5, wherein the multi-point connection interface is a mini low voltage differential signal interface or a low swing differential signal interface. A display device has a display panel and at least one source driver according to claim 5 for driving the display panel. The display device according to claim 8, wherein the multi-point connection interface is a mini low voltage differential signal interface or a low swing differential signal interface.

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