TWI686786B - display system - Google Patents

Abstract

The invention provides a display system and a method for forming an output buffer of a source driver. The display system includes a plurality of pixels coupled to a plurality of gate lines and a plurality of source lines. A gate driver generates a plurality of gate signals to the plurality of gate lines. A source driver generates a plurality of image signals to the plurality of source lines. The source driver includes an output buffer. The output buffer is one of a native transistor device, a depletion transistor device or a low threshold transistor device

Description

display system

The present invention relates to a display system, and particularly to a source driver architecture for a display system.

Flat panel display technology occupies a pivotal position in the consumer entertainment electronics industry. Conventional flat panel displays, such as liquid crystal displays, display images by driving the chipset to change the arrangement direction of liquid crystal molecules by output voltage, and the display screen is formed by the light transmittance of each pixel. The driving chip mainly includes a source driver and a gate driver. When a pixel displays colors, a thin film transistor switch needs to be controlled by the gate driver, and the source driver inputs three primary color signals of R, G, and B, respectively. The gate driver is responsible for the switching of the signals in each column of the display. When the display performs a scanning operation row by row, the gate driver turns on a whole row of switches to allow the source driver to perform signal input. The source driver is responsible for the input action of the pixel signals of each row of the display. When the gate driver turns on a whole row of switches, the source driver immediately inputs the data voltage of the row of pixels to provide the signal required for displaying the picture. When the display gradually improves the resolution, brightness and response speed, the more the driver chip needs to develop toward the direction of high frequency and high voltage, in order to meet the needs of high-speed scanning frequency and fast driving.

Therefore, in this technical field, a new source driver circuit composition is needed to improve the display quality and response time of flat panel displays.

Some embodiments of the present invention provide a display system. The above display system includes a plurality of pixels, coupled to a plurality of gate lines and a plurality of source lines. A gate driver generates a plurality of gate signals to the above-mentioned equal gate lines. A source driver generates a complex image signal to the above-mentioned source lines. The source driver includes an output buffer, wherein the output buffer includes a transistor element, the transistor element is an initial conduction transistor element, a One of a depletion type transistor element or a low threshold voltage transistor element.

Some embodiments of the present invention provide a method of forming an output buffer of a source driver. The above method of forming the output buffer of the source driver includes providing a P-type substrate. A high-pressure P-type well area and two high-pressure N-type well areas adjacent to the two sides of the high-pressure P-type well area adjacent to the high-pressure P-type well area are formed in the P-type substrate. A gate structure is formed on the P-type substrate, wherein the gate structure completely covers the high-voltage P-type well region and partially covers the high-voltage N-type well regions. A first device threshold voltage adjustment doping process is performed on a part of the high-voltage P-type well region close to a surface of the P-type substrate. A second device threshold voltage adjustment doping process is performed on a portion of the high-voltage P-type well region close to the surface of the P-type substrate, so that the threshold voltage of the output buffer is equal to or less than 0.5 volt (V).

100‧‧‧Display system

102‧‧‧LCD display panel

104‧‧‧Gate driver

106‧‧‧ Timing controller

110‧‧‧thin film transistor

112‧‧‧ pixels

114‧‧‧storage capacitor

200‧‧‧ source driver

208: digital to analog converter

210: output buffer

212: Operational amplifier

VDD: source drive voltage

VSS: gate drive voltage

VCOM: common voltage

G1~Gi: gate line

D1, Dk: source line

DATA: digital image signal string

GC: gate control signal string

SC: source control signal string

SW: switch

P: output pad

IN: input

OUT: output

Vin: analog signal

Vout: output voltage

300: P-type substrate

301: Isolation

302: High-pressure P-type well area

303: Surface

304: High-pressure N-type well area

306: Gate structure

308: N-type heavily doped region

310: P-type heavily doped region

312: High voltage N-type diffusion drain region

314: High-pressure P-type diffusion drain region

322: Deep N-type well area

410, 440: doping process for adjusting the critical voltage of high-voltage devices

420: N-type metal oxide semiconductor field effect transistor device threshold voltage adjustment doping process

430: P-type metal oxide semiconductor field effect transistor device threshold voltage adjustment doping process

462: opening

470, 480: line

500a~500d: transistor element

Figure 1 shows a block diagram of a display system according to some embodiments of the invention.

Figure 2 shows a block diagram of a source driver according to some embodiments of the invention.

FIG. 3 shows a schematic circuit diagram of an output buffer according to some embodiments of the invention.

FIGS. 4A-4D show schematic cross-sectional views of transistor elements of output buffers according to some embodiments of the present invention.

FIGS. 5A to 5C show cross-sectional schematic diagrams of transistor elements of an output buffer according to some embodiments of the present invention, which show the adjustment steps of the device threshold voltage when the output buffer is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS) .

FIG. 6 shows a voltage-time (V-T) graph of the output buffer of some embodiments of the present invention and the output buffer of the conventional technology, which shows the comparison of the driving capabilities of the two.

In order to make the purpose, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments and the accompanying drawings for detailed description. The description of the present invention provides different examples to illustrate the technical features of different embodiments of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes, and is not intended to limit the present invention. In addition, the reference numerals in the embodiments are repeated for the purpose of simplifying the description, and do not mean the correlation between different embodiments.

Figure 1 shows a block diagram of a display system 100 according to some embodiments of the invention. As shown in FIG. 1, in some embodiments of the present invention, the display system 100 includes a liquid crystal display (LCD) device. The above-mentioned liquid crystal display device includes a liquid crystal display panel (LCD panel) 102, a plurality of gate drivers 104, a plurality of source drivers 200, and a timing controller 106.

In some embodiments of the present invention, the liquid crystal display panel (LCD panel) 102 may include a thin film transistor substrate (TFT substrate), a color filter substrate (not shown), and a liquid crystal layer (LC) layer) (not shown). The thin film transistor substrate has a thin film transistor array (TFT array) disposed therein, the filter substrate is disposed facing the thin film transistor substrate, and the liquid crystal layer is disposed between the thin film transistor substrate and the filter substrate. For convenience of display, in FIG. 1, the position of the thin film transistor substrate may be the same as the position of the liquid crystal display panel 102.

In some embodiments of the present invention, the thin film transistor substrate of the liquid crystal display panel 102 may include a plurality of gate lines G1~Gi and a plurality of source lines (data lines) D1~Dk. The gate lines G1~Gi and the source lines D1~Dk intersect each other and define a plurality of pixels 112. Therefore, the pixel 112 is electrically coupled to the gate lines G1~Gi and the source lines D1~Dk. Each pixel 112 has a thin film transistor (TFT) 110 and a storage capacitor 114. The gate lines G1~Gi are electrically coupled to the gates of the thin film transistors 110 in their corresponding pixels 112, respectively, and the source lines D1~Dk are electrically coupled to the corresponding pixels in their corresponding pixels 112, respectively. The source of the thin film transistor 110. The storage capacitor 114 in each pixel 112 is electrically coupled to the drain of its corresponding thin film transistor 110. The storage capacitor 114 of the embodiment shown in FIG. 1 is electrically coupled to the drain of the thin film transistor 110 in the same pixel 112.

In some embodiments of the present invention, the gate driver 104 of the display system 100 is electrically coupled to the gate lines G1~Gi, and is used to sequentially activate the gate lines G1~Gi of the LCD panel 102. The source driver 200 of the display system 100 is electrically coupled to the source lines D1~Dk, and is used to apply an analog signal to the source lines D1~Dk of the liquid crystal display panel 102. The timing controller 106 of the display system 100 is electrically coupled to the gate driver 104 and the source driver 200, and is used to control the operation timing of the source driver 110 and the gate driver 130 and provide images required by the liquid crystal display panel 102 Signal and supply voltage to the storage capacitor 114 of the liquid crystal display panel 102.

The timing controller 106 may receive image signals and control signals input from the outside. The control signals may be horizontal synchronization signals, vertical synchronization signals, main clock signals, and data enable signals. In addition, the timing controller 106 can process the image signals according to the operating conditions of the liquid crystal display panel 102 to generate a digital image signal string DATA and a source control signal string SC to transmit to the source driver 200 and generate a gate control signal string GC Transmission to the gate driver 104. In some embodiments of the present invention, the above-mentioned source control signal string SC may include an output control signal for indicating that the analog signal is applied to the corresponding source line, and a clock signal. In some embodiments of the present invention, the gate control signal string GC may include a vertical start signal for indicating the start of the gate-on voltage of the pixel 112, a gate clock signal, and a gate-control voltage The output enable signal of the duration. In some embodiments of the present invention, the timing controller 106 provides a common voltage VCOM to the storage capacitor 114 of the liquid crystal display panel 102.

The gate driver 104 receives and processes the gate control signal string GC from the timing controller 106 to generate a plurality of gate signals for the gate lines G1~Gi. The source driver 200 receives and processes the digital image signal string DATA and the source control signal string SC from the timing controller 106 to generate complex image signals to the source lines D1 to Dk.

FIG. 2 shows a block diagram of the source driver 200 according to some embodiments of the present invention. In some embodiments of the present invention, the source driver 200 may include a shift register 202, a data latch 204, a level shifter 206, and a digital A digital to analog converter (DAC) 206 and an output buffer 210. In some embodiments of the present invention, the shift register 202 and the data latch 204 are used to receive digital data, and the digital-to-analog converter 208 and the output buffer 210 are used to output analog signals.

In some embodiments of the present invention, the shift register 202 of the source driver 200 receives and processes the externally applied digital image signal string DATA to generate a complex shift signal. In detail, the shift register 202 responds to a control signal string SC such as a clock signal and a horizontal start signal to control the received digital image signal string DATA, and outputs a complex shift signal to be generated and stored in the data in chronological order The latch 204.

In some embodiments of the present invention, the data latch 204 of the source driver 200 receives and processes the aforementioned multiple shift signals to generate a plurality of latch signals. In detail, the data latch 204 receives and stores the image signal string DATA in response to the shift signal, and outputs a complex latch signal in response to the control signal string SC such as a clock signal.

In some embodiments of the present invention, the level converter 206 of the source driver 200 receives and processes the multiple latch signals to generate a complex conversion signal. In detail, the level converter 206 converts the latch signal output by the data latch 204 from a low voltage range to a high voltage range and outputs a conversion signal of the high voltage range.

In some embodiments of the present invention, the digital-to-analog converter 208 of the source driver 200 receives and processes the above-mentioned multiple converted signals to generate a complex analog signal. In detail, the digital-to-analog converter 208 receives the digital conversion signal output by the level converter 206 in the high voltage range to convert the received digital-conversion signal to an analog signal to drive the corresponding source line.

In some embodiments of the present invention, the output buffer 210 of the source driver 200 receives and processes the aforementioned multiple analog signals to generate complex image signals for the corresponding source lines D1~Dk (Figure 1). The output buffer 210 can be used to isolate the signal input terminal and the output terminal, to avoid the signal input terminal being affected by the load, and to provide sufficient driving capacity to cope with the corresponding source line load (data line) and output to meet the requirements of the display system specifications Analog video signal.

FIG. 3 shows a schematic circuit diagram of the output buffer 210 according to some embodiments of the invention. FIG. 3 is a schematic circuit diagram of an output buffer corresponding to each source line (for example, the source lines D1 to Dk in FIG. 1). In some embodiments of the present invention, the output buffer 210 may include an operational amplifier 212, a switch SW, and an output pad P. The operational amplifier 212 includes an input terminal IN and an output terminal OUT. As shown in FIG. 3, the input terminal IN of the operational amplifier 212 receives the analog signal Vin described above. The switch SW of the output buffer 210 is electrically connected to the output terminal OUT of the operational amplifier 212 and the output pad P, and serves as an electrical transmission path electrically connected to the corresponding source line of the output pad P. The operational amplifier 212 can generate the output voltage Vout corresponding to the voltage level to the output terminal OUT according to the analog signal Vin received at the input terminal IN. When the switch SW is turned on, the output terminal OUT of the operational amplifier 212 is electrically connected to the source line of the output pad P of the source driver 200 (for example, one of the source lines D1 to Dk), and the source line The voltage is driven to a certain voltage level.

In some embodiments of the present invention, the switch SW of the output buffer 210 may include a transistor device, the transistor device is an initial conduction transistor device (native transistor device), a depletion transistor device (depletion transistor device) Or one of a low threshold transistor device. In some embodiments of the present invention, when the above transistor element is a low threshold voltage transistor element, the threshold voltage of the transistor element is equal to or less than 0.5 volts (V). In some embodiments of the present invention, when the above transistor element is an initially on transistor element or a depletion transistor element, the critical voltage of the transistor element is equal to or less than 0 volts (V).

FIGS. 4A-4D show schematic cross-sectional views of transistor elements 500a-500d of the output buffer of a display system according to some embodiments of the present invention. In some embodiments of the present invention, the transistor element of the output buffer may include an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS). In some embodiments of the present invention, the transistor element of the output buffer may include a laterally diffused metal oxide semiconductor field effect transistor (LDMOS) or a double diffused drain metal oxide semiconductor field effect transistor (DDDMOS).

As shown in FIG. 4A, in some embodiments of the present invention, the transistor element 500a may be a laterally diffused N-type metal oxide semiconductor field effect transistor (may be referred to as LDNMOS for short). Therefore, the transistor element 500a may be referred to as LDNMOS 500a. LDNMOS 500a includes a P-type substrate 300, a high-voltage P-type well (HVPW) 302, a high-voltage N-type well (HVNW) 304, a gate structure 306, an N-type heavily doped region (N+) 308, and a P-type heavily doped区(P+)310. In some embodiments of the present invention, the P-type substrate 300 is, for example, a P-type epitaxial substrate. A plurality of high-pressure P-type well regions (HVPW) 302 and a plurality of high-pressure N-type well regions (HVNW) 304 are alternately arranged on the P-type substrate 300. Therefore, two opposite sides of each high-pressure P-type well area (HVPW) 302 adjoin a different high-pressure N-type well area (HVNW) 304. Moreover, two opposite sides of each high-pressure N-type well area (HVNW) 304 are adjacent to different high-pressure P-type well areas (HVPW) 302.

As shown in FIG. 4A, the LDNMOS 500a may include one or more spacers 301 extending from the top surface of the P-type substrate 300 into a portion of the P-type substrate 300 to define an N-type heavily doped region (N+) 308 and The formation position of the P-type heavily doped region (P+) 310. The insulator 301 may be, for example, a shallow trench insulator (STI) or a local oxide of silicon (LOCOS).

As shown in FIG. 4A, the gate structure 306 of the LDNMOS 500a is disposed on the surface of the P-type substrate 300 and completely covers a high-voltage P-type well region (HVPW) 302, and partially covers the adjacent high-voltage P-type well region (HVPW) ) Two high-pressure N-type well areas (HVNW) 304 on opposite sides of 302. In addition, the gate structure 306 completely covers the insulation 301 located in the high-voltage N-type well area (HVNW) 304 respectively. A part of the high-voltage P-type well region (HVPW) 302 completely covered by the gate structure 306 and close to the gate structure 306 can be regarded as a channel region of the LDNMOS 500a, while the adjacent high-voltage P-type well region (HVPW) 302 The two high-voltage N-type well regions (HVNW) 304 on opposite sides can be regarded as the source/drain regions (S/D regions) of the LDNMOS 500a.

As shown in FIG. 4A, a plurality of N-type heavily doped regions (N+) 308 of the LDNMOS 500a are respectively disposed in a high-voltage N-type well region (HVNW) 304, and a plurality of P-type heavily doped regions (P+) of the LDNMOS 500a 310 are respectively arranged in a plurality of high-pressure P-type well areas (HVPW) 302. Moreover, the N-type heavily doped region (N+) 308 and the P-type heavily doped region (P+) 310 are surrounded by the insulation 301, respectively. The N-type heavily doped region (N+) 308 of the LDNMOS 500a can be regarded as a source/drain region doped region (S/D pick-up region). The P-type heavily doped region (P+) 310 of the LDNMOS 500a can be regarded as a bulk pick-up region.

As shown in FIG. 4B, in some embodiments of the present invention, the transistor element 500b may be a laterally diffused P-type metal oxide semiconductor field effect transistor (may be referred to as LDPMOS for short). Therefore, the switching element 500b may also be referred to as LDPMOS 500b. LDPMOS 500b includes a P-type substrate 300, a deep N-type well (DNW) 322, a high-voltage P-type well (HVPW) 302, a high-voltage N-type well (HVNW) 304, a gate structure 306, and an N-type heavily doped region (N+) 308 and P-type heavily doped region (P+) 310. If the elements in the above drawings are the same as or similar to those shown in FIG. 4A, you can refer to the previous related descriptions, and no repeated description is given here.

As shown in FIG. 4B, the deep N-type well region (DNW) 322 of the LDPMOS 500b is disposed on the P-type substrate 300. The high-pressure P-type well area (HVPW) 302 and the high-pressure N-type well area (HVNW) 304 of the LDPMOS 500b are alternately arranged on the deep N-type well area (DNW) 322.

The gate structure 306 of the LDPMOS 500b completely covers one high-voltage N-type well region (HVNW) 304, and partially covers two high-voltage P-type well regions (HVPW) adjacent to opposite sides of the above-mentioned high-voltage N-type well region (HVNW) 304. 302. In addition, the gate structure 306 completely covers the insulation 301 located in the two high-voltage P-type wells (HVPW) 302 respectively. The high-voltage N-type well region (HVNW) 304 completely covered by the gate structure 306 and close to the gate structure 306 can be regarded as the channel region of the LDPMOS 500b, and adjacent to the above-mentioned high-voltage N-type well region (HVNW) 304 The two high-voltage P-type well regions (HVPW) 302 on opposite sides of the can be regarded as the source/drain regions (S/D regions) of the LDPMOS 500b.

As shown in FIG. 4B, the plural N-type heavily doped regions (N+) 308 of the LDPMOS 500b are respectively disposed in the plural high-voltage N-type well regions (HVNW) 304, and the plural P-type heavily doped regions of the LDNMOS 500b ( P+) 310 are respectively arranged in a plurality of high-pressure P-type well areas (HVPW) 302. Moreover, the N-type heavily doped region (N+) 308 and the P-type heavily doped region (P+) 310 are surrounded by the insulation 301, respectively. The P-type heavily doped region (P+) 310 of the LDPMOS 500b may be regarded as a source/drain region doped region (S/D pick-up region). The N-type heavily doped region (N+) 308 of the LDPMOS 500b can be regarded as a bulk pick-up region.

The transistor element 500c shown in FIG. 4C may be a double-diffusion drain N-type metal oxide semiconductor field effect transistor (may be referred to as DDDNMOS for short). If the components in the above drawings are the same as or similar to those shown in FIGS. 4A to 4B, you can refer to the previous related descriptions, and they will not be repeated here.

As shown in FIG. 4C, DDDNMOS 500c includes a P-type substrate 300, a high-voltage P-type well region (HVPW) 302, a high-voltage N-type diffused drain region (HVNDD) 312, a gate structure 306, and an N-type heavily doped region ( N+) 308 and P-type heavily doped region (P+) 310.

As shown in FIG. 4C, the high-voltage P-type well area (HVPW) 302 of the DDDNMOS 500c is disposed on the P-type substrate 300. DDDNMOS 500c has two high-voltage N-type diffusion drain regions (HVNDD) 312, which are respectively disposed on high-voltage P-type well regions (HVPW) 302. The gate structure 306 of the DDDNMOS 500c is disposed on the high-voltage P-type well region (HVPW) 302, and the opposite sides of the gate structure 306 partially overlap the two high-voltage N-type diffusion drain regions (HVNDD) 312, respectively. Therefore, the high-voltage N-type diffused drain region (HVNDD) 312 can be regarded as the source/drain region of the DDDNMOS 500c, located directly below the gate structure 306 and between the high-voltage N-type diffused drain region (HVNDD) 312, and close to The high-voltage P-type well region (HVPW) 302 of a portion of the gate structure 306 can be regarded as a channel region of the DDDNMOS 500c.

The DDDNMOS 500c has two N-type heavily doped regions (N+) 308, which are respectively disposed on two high-voltage N-type diffusion drain regions (HVNDD) 312, and are adjacent to opposite sides of the gate structure 306. Therefore, the N-type heavily doped region (N+) 308 can be regarded as the source/drain region wiring doped region of the DDDNMOS 500c. In addition, DDDNMOS 500c has two P-type heavily doped regions (P+) 310, which are respectively disposed on high-voltage P-type well regions (HVPW) 302 outside two high-voltage N-type diffusion drain regions (HVNDD) 312, and by The spacer 301 is separated from the N-type heavily doped region (N+) 308. Therefore, the P-type heavily doped region (P+) 310 can be regarded as the body wiring doped region of the DDDNMOS 500c.

The transistor element 500d shown in FIG. 4D may be a double-diffused drain P-type metal oxide semiconductor field effect transistor (may be referred to as DDDPMOS for short). If there are any parts in the above drawings that are the same as or similar to those shown in FIGS. 4A to 4C, you can refer to the previous related descriptions, and they will not be repeated here.

As shown in FIG. 4D, DDDPMOS 500d includes a P-type substrate 300, a high-voltage P-type well region (HVPW) 302, a high-voltage N-type well region (HVNW) 304, a high-voltage P-type diffusion drain region (HVPDD) 314, a gate Structure 306, N-type heavily doped region (N+) 308 and P-type heavily doped region (P+) 310.

As shown in FIG. 4D, the high-voltage P-type well region (HVPW) 302 of the DDDPMOS 500d is disposed on the P-type substrate 300, and the high-voltage N-type well region (HVNW) 304 is disposed on the high-voltage P-type well region (HVPW) 302. The DDDPMOS 500d has two high-voltage P-type diffusion drain regions (HVPDD) 314, which are respectively disposed on the high-voltage N-type well region (HVNW) 304. The gate structure 306 of the DDDPMOS 500d is disposed on the high-voltage N-type well region (HVNW) 304, and opposite sides of the gate structure 306 partially overlap the two high-voltage P-type diffusion drain regions (HVPDD) 314, respectively. Therefore, the high-voltage P-type diffused drain region (HVPDD) 314 can be regarded as the source/drain region of the DDDPMOS 500d, located directly under the gate structure 306 and between the high-voltage P-type diffused drain region (HVPDD) 314, and close to Part of the high-voltage N-type well region (HVNW) 304 of the gate structure 306 can be regarded as the channel region of the DDDPMOS 500d.

The two P-type heavily doped regions (P+) 310 of the DDDPMOS 500d are respectively disposed on the two high-voltage P-type diffused drain regions (HVPDD) 314, and are adjacent to opposite sides of the gate structure 306. Therefore, the P-type heavily doped region (P+) 310 can be regarded as the source/drain region wiring doped region of the DDDPMOS 500d. In addition, the two N-type heavily doped regions (N+) 308 of DDDPMOS 500d are respectively disposed on the high-voltage N-type well regions (HVNW) 304 outside the two P-type diffusion drain regions (HVPDD) 314, and are isolated by The object 301 is separated from the P-type heavily doped region (P+) 310. Therefore, the N-type heavily doped region (N+) 308 can be regarded as the body wiring doped region of the DDDPMOS 500d.

FIGS. 5A to 6C are schematic cross-sectional views of the transistor elements of the output buffer of a display system according to some embodiments of the present invention, which show the adjustment steps of the device threshold voltage when the transistor elements of the output buffer are LDNMOS 500a.

As shown in FIG. 5A, first, a P-type substrate 300 is provided, and an isolation region 301 is formed on the substrate 300, followed by several doping processes to form a plurality of well regions in the P-type substrate 300, including staggered arrangement A plurality of high-pressure P-type well areas (HVPW) 302 and a plurality of high-pressure N-type well areas (HVNW) 304. Next, a gate structure 306 is formed on the surface of the P-type substrate 300. The gate structure 306 completely covers a high-voltage P-type well region (HVPW) 302, and partially covers the opposite of the adjacent high-voltage P-type well region (HVPW) 302. Two high-voltage N-type well areas (HVNW) 304 on both sides and the insulation 301 located in the above-mentioned high-voltage N-type well area (HVNW) 304.

Next, as shown in FIG. 5A, in order to reduce the threshold voltage of the LDNMOS 500a to be one of the initially turned on transistor element, the depletion type transistor element, or a low threshold voltage transistor element, it may choose not to proceed (or skip (skip)) The doping process of the high-voltage device critical voltage adjustment for the channel region of LDNMOS 500a (the high-voltage P-type well region (HVPW) 302 located directly under the gate structure 306 and close to a surface 303 of the P-type substrate 300) (HVNMOS Vt implant process) 410.

After that, several doping processes may be performed to form a plurality of N-type heavily doped regions (N+) 308 in the plurality of high-voltage N-type well regions (HVNW) 304, and in a plurality of high-pressure P-type well regions, respectively In (HVPW) 302, a plurality of P-type heavily doped regions (P+) 310 are formed. Through the above process, the LDNMOS 500a of the output buffer of the display system according to some embodiments of the present invention is formed.

FIG. 5B shows the steps of adjusting the device threshold voltage of the output buffer (LDNMOS 500a) according to some embodiments of the present invention. If the forming steps of each element in the above drawings are the same as or similar to those shown in FIG. 5A, the relevant descriptions above can be referred to, and no repeated description will be given here.

As shown in FIG. 5B, in some embodiments of the present invention, after forming the gate structure 306, the channel region of the LDNMOS 500a (the portion directly below the gate structure 306 and close to the surface 303 of the P-type substrate 300 High voltage P-type well region (HVPW) 302) for N-type metal oxide semiconductor field effect transistor (NMOS) device critical voltage adjustment doping process 420 and P-type metal oxide semiconductor field effect transistor (PMOS) device critical voltage adjustment doping In the process 430, the threshold voltage of the LDNMOS 500a is close to 0V or equal to or less than 0V. For example, after performing the NMOS threshold voltage adjustment doping process 420 and the PMOS threshold voltage adjustment doping process 430, the conductivity type of the channel region of the LDNMOS 500a can be changed to N-type, and can be regarded as a depletion type transistor device. In some embodiments of the invention, the N-type metal oxide semiconductor field effect transistor (NMOS) device threshold voltage adjustment doping process 420 is a high-voltage N-type metal oxide semiconductor field effect transistor device threshold voltage adjustment doping process (HVNMOS Vt implant process), and the P-type metal oxide semiconductor field effect transistor (PMOS) device threshold voltage adjustment doping process 430 is a high-voltage P-type metal oxide semiconductor field effect transistor device threshold voltage adjustment doping process (HVPMOS Vt implant process). In some embodiments of the present invention, the dopants implanted in the channel region of the NMOS threshold voltage adjustment doping process 420 and the PMOS threshold voltage adjustment doping process 430 have opposite conductivity types.

After the NMOS threshold voltage adjustment doping process 420 and the PMOS threshold voltage adjustment doping process 430, several doping processes may be performed to form a plurality of N-type heavy layers in the plurality of high-voltage N-type well regions (HVNW) 304, respectively. Doped regions (N+) 308, and a plurality of P-type heavily doped regions (P+) 310 are formed in the plurality of high-pressure P-type well regions (HVPW) 302, respectively. Through the above process, an LDNMOS 500b of an output buffer of a display system according to some embodiments of the present invention is formed.

FIG. 5C shows the steps of adjusting the device threshold voltage of the output buffer (LDNMOS 500a) according to some embodiments of the present invention. If the forming steps of each element in the above drawings are the same as or similar to those shown in FIG. 5A, the relevant descriptions above can be referred to, and no repeated description will be given here.

As shown in FIG. 5C, in some embodiments of the present invention, after forming the gate structure 306 and performing the HVNMOS Vt implant process 410 shown in FIG. 5A, the LDNMOS 500a process may be performed A photomask 460 is added to it, which has an opening 462 that exposes only the channel region of the LDNMOS 500a. Therefore, the above photomask 460 can perform another high-voltage device criticality on the channel region of the LDNMOS 500a (the high-voltage P-type well region (HVPW) 302 located directly under the gate structure 306 and close to the surface 303 of the P-type substrate 300) The voltage adjustment doping process 440 makes the critical voltage of the LDNMOS 500a close to 0V, or equal to or less than 0V. In some embodiments of the present invention, the high-voltage device threshold voltage adjustment doping process 410 and the high-voltage device threshold voltage adjustment doping process 440 may implant dopants of the same conductivity type or opposite conductivity types in the channel region.

After the high-voltage device threshold voltage adjustment doping process 410 and the high-voltage device threshold voltage adjustment doping process 440, several doping processes may be performed to form a plurality of N in the plurality of high-voltage N-type well regions (HVNW) 304, respectively Type heavily doped region (N+) 308, and a plurality of P type heavily doped regions (P+) 310 are formed in a plurality of high-pressure P-type well regions (HVPW) 302, respectively. Through the above process, an LDNMOS 500c of an output buffer of a display system according to some embodiments of the present invention is formed.

In other embodiments of the present invention, when the transistor component of the output buffer is LVPMOS 500b (Figure 4B), an additional device threshold voltage adjustment doping process may be performed on the channel region, or the channel region may not be subjected to the original The process has a high-voltage device threshold voltage adjustment doping process to make the LVPMOS 500b threshold voltage close to 0V, or equal to or less than 0V. For example, after the above-mentioned device threshold voltage adjustment doping process, the channel region of the LVPMOS 500b can be transformed into a P-type, and can be regarded as a depletion-type transistor device.

FIG. 6 shows a voltage-time (V-T) graph of the output buffer of some embodiments of the present invention and the output buffer of the conventional technology, which shows the comparison of the driving capabilities of the two.

In FIG. 6, line 470 is the voltage-time curve of the output buffer of the prior art, and line 480 is the voltage-time curve of the output buffer of some embodiments of the present invention. Since the conventional technology uses an enhanced metal oxide semiconductor field effect transistor (enhancement MOS) as the transistor element of the output buffer, the driving capacity and performance (switching frequency) of the conventional output buffer will be affected by the on-resistance of the device itself (Ron), gate charge (Qg), gate-drain charge (Qgd), or gate-source charge (Qgs) cannot be effectively improved. Compared with the output buffer (line 470) of the conventional technology, the (switching) element (line 480) of the output buffer of some embodiments of the present invention uses an initial conduction transistor element, a depletion transistor element, or a low threshold voltage One of the transistor elements. The threshold voltage of the above element is close to 0V (for example, equal to or less than 0.5V), or equal to or less than 0V, so the operating frequency (switching speed) of the element can be increased, and the pixel can be reached in a shorter time. The analog voltage required by 112 improves the drive capacity and performance of the output buffer, and further improves the image display quality and image response time of the display system.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the scope of the attached patent application.

210‧‧‧Output buffer

212‧‧‧Operational amplifier

D1, Dk‧‧‧ source line

SW‧‧‧switch

P‧‧‧ Output pad

IN‧‧‧input

OUT‧‧‧Output

Vin‧‧‧Analog signal

Vout‧‧‧Output voltage

Claims (7)

A display system includes: complex pixels, coupled to complex gate lines and complex source lines; a gate driver to generate complex gate signals to the gate lines; and a source driver to generate complex image signals to For the source lines, the source driver includes: an output buffer, wherein the output buffer includes an operational amplifier and a switch, wherein the switch includes a transistor element, and the transistor element is an initial One of a transistor transistor (native transistor device), a depletion transistor device (depletion transistor device) or a low threshold voltage transistor device (low threshold transistor device), wherein the operation is performed when the switch is turned on The amplifier is electrically connected to the source lines; a shift register receives and processes an image signal to generate a complex shift signal; a data latch receives and processes the shift signals to Generate complex latch signals; a level converter, receive and process the latch signals to generate complex conversion signals; and a digital analog converter, receive and process the conversion signals to generate complex analog signals; The output buffer receives and processes the analog signals to generate the image signals. The display system as described in item 1 of the patent application scope, wherein the transistor element The critical voltage is equal to or less than 0.5 volts (V). The display system as described in item 1 of the patent application range, wherein the critical voltage of the transistor element is equal to or less than 0 volts (V). The display system as described in item 1 of the patent application scope, wherein the transistor element comprises an N-type metal oxide semiconductor field effect transistor (NMOS) or a P-type metal oxide semiconductor field effect transistor (PMOS). The display system as described in item 1 of the patent application scope, wherein the transistor element comprises a laterally diffused metal oxide semiconductor field effect transistor (LDMOS) or a double diffusion drain metal oxide semiconductor field effect transistor (DDDMOS). The display system as described in item 4 of the patent application scope, wherein the N-type metal oxide semiconductor field effect transistor includes a channel region, and the channel region is N-type. The display system as described in item 4 of the patent application scope, wherein the P-type metal oxide semiconductor field effect transistor includes a channel region, and the channel region is P-type.

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