TWI685830B - DC power supply circuit with high power rejection ratio and display device including the same - Google Patents

Abstract

A DC power supply circuit with high power rejection ratio, including: a front-stage low-dropout voltage stabilizing unit, used to generate a front-stage output voltage according to a second reference voltage under the supply of a system voltage; an internal system voltage is enabled Unit for selecting the system voltage or the output voltage of the previous stage according to the control of a selection signal to provide an internal system voltage at an internal system voltage output terminal; a bandgap reference voltage generating unit for generating according to the internal system voltage A bandgap reference voltage; a buffer circuit unit for generating a first reference voltage, the second reference voltage and a third reference voltage according to the bandgap reference voltage under the supply of the internal system voltage; a boost conversion A unit for performing a boost conversion operation according to the first reference voltage to boost the system voltage to an output stage supply voltage; and an output stage low dropout voltage stabilizing unit for the internal system voltage and the output Under the power supply of the level supply voltage, a voltage stabilization operation is performed according to the third reference voltage to provide an output voltage.

Description

DC power supply circuit with high power rejection ratio and display device including the same

The invention relates to a DC power supply circuit, in particular to a DC power supply circuit with a high power rejection ratio and a display device including the same.

，其中，V _DD為一輸入電源的電壓，Ripple(V _DD)代表該輸入電源的漣波電壓大小，V _out為一直流穩壓電源電路的輸出電壓，及Ripple(V _out)代表該輸出電壓的漣波電壓大小。 The DC stabilized power supply circuit is an essential component of general electronic products, and the Power Supply Rejection Ratio (PSRR) is an important item for evaluating the performance of the DC stabilized power supply circuit. The power supply rejection refers to the ratio of the input power variation of the DC power supply circuit to the output power variation, and is used to describe the ability of the DC power supply circuit to suppress noise carried by an input power supply. The formula for calculating PSRR is

, Where V _DD is the voltage of an input power supply, Ripple(V _DD ) represents the ripple voltage of the input power supply, V _out is the output voltage of a DC power supply circuit, and Ripple(V _out ) represents the output voltage The magnitude of the ripple voltage.

For example, when an AMOLED (Active-matrix organic light-emitting diode) panel is powered by a DC power supply circuit, if the fluctuation of an input power supply voltage (VDD) exceeds 500mV, then The change of the output voltage (Vout) of the DC stabilized power supply circuit cannot exceed 4mV. Once the output voltage of the DC stabilized power supply circuit changes by more than 4mV, the display screen of the AMOLED panel will show a significant light-dark change phenomenon, which is called water ripple in the industry.

FIG. 1 shows an architecture diagram of a conventional voltage-stabilized power supply circuit. As shown in FIG. 1, a regulated power supply circuit 1'includes: a bandgap reference voltage generating unit 11', a boost converter 12' and a low-dropout regulator (LDO) 13', The bandgap reference voltage generating unit 11' is used to generate a bandgap reference voltage VBG according to a system voltage VDD, and provide the bandgap reference voltage VBG to the low dropout linear regulator 13'; the boost converter 12' is A bias power supply VREG for converting the system voltage VDD to a low-dropout linear regulator 13'. On the other hand, the low-dropout linear regulator 13' includes: an error amplifier 131', a pass element (Pass element) 132', a first P-type field effect transistor 133' and a second P-type field effect A current mirror composed of a transistor 134', a voltage dividing resistor composed of a first resistor 135' and a second resistor 136', and a load capacitor 137'. In the low-dropout linear regulator 13', the current mirror provides a certain current, and the constant current and the voltage-dividing resistor determine the voltage value of the output voltage VLDO of the low-dropout linear regulator 13'.

It is worth noting that the error amplifier 131', the transfer element 132' and the voltage dividing resistor constitute a negative feedback system. When the output voltage VLDO rises, the value of a feedback voltage VFB transmitted to the negative input terminal of the error amplifier 131' through the voltage-dividing resistor also increases; at this time, the output voltage VN of the error amplifier 131' will decrease. The gate voltage VG of one P-type field effect transistor 133' and the second P-type field effect transistor 134' will increase to reduce the current value of the constant current provided by the current mirror, thereby making the low dropout linear regulator The output voltage VLDO at 13' drops to maintain the stability of the output voltage VLDO.

At present, the regulated power supply circuit 1 ′ shown in FIG. 1 has been widely used in the driving power circuit of the AMOLED panel, which can output a range of 5V according to the system voltage VDD ranging from 2V to 4.5V Output voltage VLDO between 4.5V. It is worth noting that the boost converter 12' is used to perform a boost process on the system voltage VDD, but the bias power supply VREG output by the boost converter 12' is determined by its internal power switch. Frequency switching with noise ripple (Ripple). Therefore, the low-dropout linear regulator 13' is used to eliminate the noise ripple while providing a stable output voltage VLDO.

=41.94dB 。但是，圖1所示的穩壓供電電路1’並非僅包含低壓降線性穩壓器13’，其還同時包含帶隙參考電壓電路11’與升壓變換器12’。在這種情況下，假設穩壓供電電路1’的理想的PSRR=

=40dB且系統電壓V _DD的變化量為A，則可使用下式(1)與式(2)推算理想的輸出電壓V _LDO的變動量。 As mentioned in the foregoing description, if the fluctuation of the system voltage V _DD exceeds 500 mV, it must be ensured that the change in the output voltage V _LDO of the low-dropout linear regulator 13 ′ cannot exceed 4 mV; that is, in an ideal situation, The PSRR of the low dropout linear regulator 13' must be greater than

=41.94dB. However, the stabilized power supply circuit 1 ′ shown in FIG. 1 does not only include the low-dropout linear regulator 13 ′, but also includes the bandgap reference voltage circuit 11 ′ and the boost converter 12 ′. In this case, assume that the ideal PSRR of the regulated power supply circuit 1'=

=40dB and the variation of the system voltage V _DD is A, then the following equations (1) and (2) can be used to estimate the ideal output voltage V _LDO variation.

=

…………………..(1)

=

…………………..(1)

……………………..(2) =

……………………..(2)

、

、

、

、A

代入上式(1)與式(2)，可算出 =30.315 ；其中，R1與R2分別為第一電阻135’ 的電阻值與第二電阻136’的電阻值。顯然，在系統電壓V _DD的波動為500mV的情況下，因受到帶隙參考電壓電路11’與升壓變換器12’的影響，穩壓供電電路1’中的低壓降線性穩壓器13’的輸出電壓V _LDO的變化量為30.315 mV，其遠超過規定上限的4mV。亦即，穩壓供電電路1’的真正的PSRR=

=24dB。可想而知，若以圖1所示的穩壓供電電路1’提供直流電源以驅動一AMOLED面板，則該AMOLED面板的顯示幕必然會顯示出水波紋。 To

,

,

,

, A

Substitute the above formula (1) and formula (2), can be calculated =30.315 ; Where R1 and R2 are the resistance value of the first resistor 135' and the resistance value of the second resistor 136', respectively; Obviously, when the fluctuation of the system voltage V _DD is 500 mV, the low-dropout linear regulator 13 ′ in the regulated power supply circuit 1 ′ is affected by the bandgap reference voltage circuit 11 ′ and the boost converter 12 ′ The amount of change in the output voltage V _LDO is 30.315 mV, which far exceeds the specified upper limit of 4mV. That is, the true PSRR of the regulated power supply circuit 1'=

=24dB. It is conceivable that if the stabilized power supply circuit 1 ′ shown in FIG. 1 is used to provide DC power to drive an AMOLED panel, the display screen of the AMOLED panel will inevitably show water ripples.

Therefore, there is an urgent need in the art for a novel DC power supply circuit.

An object of the present invention is to provide a DC power supply circuit with a high power rejection ratio, which can provide a PSRR of 64.4 dB under a system voltage fluctuation of 500 mV.

Another object of the present invention is to provide a display device which can minimize the water ripple of a display screen under a system voltage fluctuation of 500 mV.

In order to achieve the above purpose, a DC power supply circuit with a high power rejection ratio is proposed, which includes:

A pre-stage low-dropout voltage stabilizing unit is used to generate a pre-stage output voltage according to a second reference voltage under the supply of a system voltage;

An internal system voltage enable unit for selecting the system voltage or the output voltage of the previous stage according to the control of a selection signal to provide an internal system voltage at an internal system voltage output terminal;

A band gap reference voltage generating unit for generating a band gap reference voltage according to the internal system voltage;

A buffer circuit unit for generating a first reference voltage, the second reference voltage and a third reference voltage according to the bandgap reference voltage under the supply of the internal system voltage;

A boost conversion unit for performing a boost conversion operation according to the first reference voltage to boost the system voltage to an output stage supply voltage; and

An output-stage low-dropout voltage stabilizing unit is used to perform a voltage-stabilizing operation according to the third reference voltage to provide an output voltage under the supply of the internal system voltage and the supply voltage of the output stage.

In an embodiment, the pre-stage low dropout voltage stabilizing unit includes:

A first error amplifier, powered by the system voltage, has a positive input terminal for coupling the second reference voltage, a negative input terminal for coupling a first feedback voltage, and an output terminal for providing a first Regulate voltage

A first N-type field effect transistor having a gate to couple the first regulated voltage, a drain to couple the system voltage, and a source to provide the output voltage of the previous stage; and

A first voltage dividing resistor and a first filter capacitor connected in parallel therewith, the first voltage dividing resistor is used to generate the first feedback voltage according to a ratio of the output voltage of the previous stage.

In an embodiment, the internal system voltage enabling unit includes:

An inverter for generating an inverted signal of a selection signal;

A first P-type field effect transistor with a gate to couple the selection signal, a source to couple the system voltage, and a drain to couple to the internal system voltage output; and

A second P-type field effect transistor having a gate to be coupled to an output of the inverter, a source to be coupled to the output voltage of the previous stage, and a drain to be coupled to the internal system voltage Output.

In an embodiment, the buffer circuit unit includes:

A first buffer for generating the first reference voltage according to the bandgap reference voltage under the supply of the internal system voltage;

A second buffer for generating the second reference voltage according to the bandgap reference voltage under the supply of the internal system voltage; and

A third buffer is used to generate the third reference voltage according to the bandgap reference voltage under the supply of the internal system voltage.

In one embodiment, the first buffer, the second buffer, and the third buffer all include a voltage follower.

In an embodiment, the output stage low-dropout voltage regulator unit includes:

A second error amplifier for amplifying the difference between the third reference voltage and a second feedback voltage to generate a second regulated voltage under the supply of the internal system voltage;

A second N-type field effect transistor for controlling the magnitude of a channel current according to the second regulation voltage;

A third P-type field effect transistor and a fourth P-type field effect transistor are used to form a current mirror to enable the channel of the fourth P-type field effect transistor under the power supply of the output stage supply voltage The current is proportional to the channel current of the third P-type field effect transistor; and

A second voltage divider resistor and a second filter capacitor connected in parallel with it are coupled to a drain of the fourth P-type field effect transistor to generate the output voltage, and the second voltage divider resistor It is used to generate the second feedback voltage according to a ratio of the output voltage.

In addition, the present invention further provides a display device, including:

A display panel;

A data drive unit, electrically connected to the display panel;

A scanning drive unit, electrically connected to the display panel;

A controller unit electrically connected to the data driving unit and the scanning driving unit; and

A DC power supply circuit with a high power rejection ratio as described above provides the output voltage to the display panel.

In one embodiment, the display panel is a touch display panel.

In a possible embodiment, the display panel may be an organic light emitting display panel or an active matrix organic light emitting display panel.

In order to enable your review committee to further understand the structure, features, objectives, and extreme advantages of the present invention, the drawings and the detailed description of the preferred embodiments are attached as follows.

Please refer to FIG. 2 and FIG. 3 together. FIG. 2 shows a block diagram of an embodiment of a DC power supply circuit with a high power rejection ratio according to the present invention; and FIG. 3 shows a diagram for implementing the architecture shown in FIG. 2. Circuit diagram of an embodiment of each block function. As shown in FIGS. 2 and 3, a high power rejection ratio DC power supply circuit 1 (hereinafter referred to as "power supply circuit 1") includes a front-stage low-dropout voltage stabilizing unit 11, an internal system voltage enabling unit 12, and a band gap The reference voltage generating unit 13, a buffer circuit unit 14, a boost conversion unit 15 and an output stage low dropout voltage stabilizing unit 16 generate an output voltage VLDO according to a system voltage VDD.

The front-stage low-dropout voltage stabilizing unit 11 is used to generate a front-stage output voltage VBUF according to a second reference voltage VREF2 under the power supply of the system voltage VDD. As can be seen from FIG. 3, the front-stage low-dropout regulator unit 11 is a low-dropout regulator (LDO), which includes: a first error amplifier 111 and a first N-type field effect transistor 112 1. A first voltage dividing resistor composed of a first resistor 113 and a second resistor 114, and a first filter capacitor 115.

In operation, the first error amplifier 111 is powered by the system voltage VDD, a positive input terminal receives the second reference voltage VREF2 provided by the buffer circuit unit 14, and a negative input terminal receives a first feedback voltage VFB1, and An output terminal provides a first regulated voltage VN1; the first N-type field effect transistor 112 as a pass element is electrically connected to the output terminal of the first error amplifier 111 with a gate, and a drain The system voltage VDD is coupled, and the front-stage output voltage VBUF is provided to the internal system voltage enabling unit 12 with a source. On the other hand, the negative input terminal of the first error amplifier 111 is electrically connected between the first resistor 113 and the second resistor 114, and the first filter capacitor 115 is connected in parallel with the first voltage dividing resistor. During operation, the first error amplifier 111, the first N-type field effect transistor 112 and the voltage dividing resistor form a negative feedback system to maintain the output stability of the previous stage output voltage VBUF, wherein, when the first regulated voltage When VN1 rises, the voltage value of the first feedback voltage VFB1 will also increase. At this time, the first regulation voltage VN1 of the first error amplifier 111 will decrease to make the channel current value of the first N-type field effect transistor 112 Decreases, thereby reducing the voltage value of the output voltage VBUF of the previous stage; and when the first regulation voltage VN1 decreases, the voltage value of the first feedback voltage VFB1 will also decrease. At this time, the first regulation of the first error amplifier 111 The voltage VN1 will rise to increase the channel current value of the first N-type field effect transistor 112, thereby increasing the voltage value of the previous stage output voltage VBUF.

The internal system voltage enabling unit 12 is a multiplexer switch circuit for selecting the system voltage VDD or the previous stage output voltage VBUF according to the control of a selection signal CS_VDD-BG to provide an internal system voltage VDD_inn at an internal system voltage output terminal. As can be seen from FIG. 3, the internal system voltage enabling unit 12 includes: an inverter 121, a first P-type field effect transistor 122 and a second P-type field effect transistor 123, wherein the inverter 121 is used to Generate the inverted signal of the selection signal CS_VDD-BG; the gate of the first P-type field effect transistor 122 is coupled to the selection signal CS_VDD-BG, the source is coupled to the system voltage VDD, and the drain is coupled to the internal system voltage output; The gate of the second P-type field effect transistor 123 is coupled to the output of the inverter 121, the source is coupled to the previous stage output voltage VBUF, and the drain is coupled to the internal system voltage output. During operation, when the signal CS_VDD-BG is selected as a low-level signal, the first P-type field effect transistor 122 and the second P-type field effect transistor 123 will be in the on state and the off state, respectively. The system voltage VDD is coupled to the internal system voltage output through the channel of the first P-type field effect transistor 122 to provide the internal system voltage VDD_inn; when the selection signal CS_VDD-BG is a high-level signal, the first P-type field The effect transistor 122 and the second P-type field effect transistor 123 will be in the off state and the on state respectively. At this time, the output voltage VBUF of the previous stage will be output through the channel of the second P-type field effect transistor 123 and the internal system voltage. The terminal is coupled to provide the internal system voltage VDD_inn.

The bandgap reference voltage generating unit 13 generates a bandgap reference voltage VBG according to the internal system voltage VDD_inn.

The buffer circuit unit 14 has a first voltage follower 141, a second voltage follower 142, and a third voltage follower 143, which are used to supply the internal system voltage VDD_inn according to the bandgap reference voltage VBG generates a first reference voltage VREF1, a second reference voltage VREF2 and a third reference voltage VREF3, wherein the first voltage follower 141, the second voltage follower 142 and the third voltage follower 143 all have a The output terminal is electrically connected to a negative input terminal, and a positive input terminal is coupled to the bandgap reference voltage VBG. It should be explained here that although the buffer circuit unit 14 shown in FIG. 3 is implemented with three voltage followers, it is not intended to limit the implementation state of the buffer circuit unit 14. In fact, the voltage follower is an output buffer used to increase the output driving force, so other circuit units with the same characteristics can be used to implement the buffer circuit unit 14. That is to say, in a broad sense, the buffer circuit unit 14 includes a first buffer for generating the first reference voltage VREF1 according to the bandgap reference voltage VBG under the power supply of the internal system voltage VDD_inn to provide to the boost converter unit 15; a second buffer for generating the second reference voltage VREF2 according to the bandgap reference voltage VBG under the power supply of the internal system voltage VDD_inn to provide to the previous stage low dropout voltage stabilizing unit 11; and a third buffer, It is used to generate the third reference voltage VREF3 according to the bandgap reference voltage VBG under the power supply of the internal system voltage VDD_inn to provide to the output stage low dropout voltage stabilizing unit 16.

The boost conversion unit 15 performs a boost conversion operation according to the first reference voltage VREF1 to boost the system voltage VDD to an output stage supply voltage VREG.

The output stage low dropout voltage regulator unit 16 is electrically connected to the internal system voltage enable unit 12, the buffer circuit unit 14 and the boost converter unit 15 simultaneously, so as to be powered by the internal system voltage VDD_inn and the output stage supply voltage VREG, according to the third reference The voltage VREF2 performs a voltage stabilization operation to provide the output voltage VLDO. As shown in FIG. 3, the output stage low-dropout regulator unit 16 includes a second error amplifier 161, a second N-type field effect transistor 162, a third P-type field effect transistor 163, and a fourth P-type field The effect transistor 164, a second voltage divider resistor (composed of a third resistor 165 and a fourth resistor 166 connected in series), and a second filter capacitor 167.

During operation, the second error amplifier 161 is powered by the internal system voltage VDD_inn, and amplifies the difference between the third reference voltage VREF3 and a second feedback voltage VFB2 to generate a second regulated voltage VN2; the second N The field effect transistor 162 is used to control the magnitude of a channel current according to the second regulation voltage VN2; the third P type field effect transistor 163 and the fourth P type field effect transistor 164 are used to form a current mirror, Under the power supply of the output stage supply voltage VREG, a voltage VG is generated at the gates of the third P-type field effect transistor 163 and the fourth P-type field effect transistor 164 according to the channel current of the second N-type field effect transistor 162 To determine the channel current of the fourth P-type field effect transistor 164 to generate the output voltage VLDO on the second voltage-dividing resistor; and at steady state, the second circuit provided by the second voltage-dividing resistor The grant voltage VFB2 will be equal to the third reference voltage VREF3, that is, the output voltage VLDO will be equal to a multiple of the third reference voltage VREF3. In addition, as can be seen from FIG. 3, the third resistor 165 and the fourth resistor 166 connected in series constitute the second voltage-dividing resistor, and a negative input terminal of the second error amplifier 161 is electrically connected to the third resistor 165 and the third resistor The four resistors 166 are coupled to the second feedback voltage VFB2. Furthermore, the second filter capacitor 167 is connected in parallel with the second voltage dividing resistor.

In more detail, the output stage low dropout voltage regulator unit 16 utilizes a negative feedback mechanism to provide a stable, low ripple output voltage VLDO, wherein when the output voltage VLDO rises, the voltage of the second feedback voltage VFB2 Will rise accordingly, and the second regulated voltage VN2 of the second error amplifier 161 will drop to increase the gate voltage VG of the third P-type field effect transistor 163 and the fourth P-type field effect transistor 164, thereby making the fourth The channel current value of the P-type field effect transistor 164 decreases to reduce the output voltage VLDO; and when the output voltage VLDO decreases, the voltage of the second feedback voltage VFB2 decreases accordingly, and the second regulated voltage of the second error amplifier 161 VN2 will rise to lower the gate voltage VG of the third P-type field effect transistor 163 and the fourth P-type field effect transistor 164, thereby increasing the channel current value of the fourth P-type field effect transistor 164 to pull up Output voltage VLDO.

=41.94dB 。在這種情況下，假設電源電路1的理想的PSRR=

=40dB且系統電壓V _DD的變化量為A，則可使用下式(3)與式(4)推算理想的輸出電壓V _LDO的變動量。 In this way, the above description has completely and clearly introduced the circuit composition and working principle of the high power rejection ratio DC power supply circuit 1 of the present invention. It must be explained again that if the fluctuation of the system voltage V _DD exceeds 500 mV, it must be noted that the change of the output voltage V _LDO of the power circuit 1 of the present invention cannot exceed 4 mV; that is, in an ideal situation, the power circuit The PSRR of 1 must be greater than

=41.94dB. In this case, assume that the ideal PSRR of the power supply circuit 1 =

=40dB and the variation of the system voltage V _DD is A, the following equations (3) and (4) can be used to estimate the ideal output voltage V _LDO variation.

=

…………………..(3)

=

………………….. (3)

………………………..(4) =

……………………….. (4)

、

、

、

、A

代入上式(3)與式(4)，可算出 =0.303 ；其中，R1與R2分別為該第三電阻165 的值與該第四電阻166的值。顯然，在系統電壓V _DD的波動為500mV的情況下，本發明之電源電路1仍舊可以提供變化量僅為0.303 mV的輸出電壓V _LDO至後端的顯示器，遠低於規定上限的4mV。亦即，本發明之電源電路1的確具有

=41.9dB的優秀的電源拒斥比(PSRR)之表現。 To

,

,

,

, A

Substitute into the above formula (3) and formula (4) to calculate =0.303 ; Where R1 and R2 are the value of the third resistor 165 and the value of the fourth resistor 166, respectively; Obviously, in the case where the fluctuation of the system voltage V _DD is 500 mV, the power supply circuit 1 of the present invention can still provide the output voltage V _LDO with a variation of only 0.303 mV to the rear-end display, which is far below the specified upper limit of 4 mV. That is, the power circuit 1 of the present invention does have

= 41.9dB excellent power supply rejection ratio (PSRR) performance.

As can be seen from the above description, the power supply circuit 1 of the present invention is very suitable for replacing the power supply circuit in the existing organic light emitting display because of its excellent PSRR performance. In view of this, the present invention also proposes a display device of the DC power supply circuit 1 having the high power rejection ratio. 4 is a block diagram showing an embodiment of the display device of the present invention, wherein a display device 3 includes a display panel 31, a data drive unit 32, a scan drive unit 33, a controller unit 34, and 3 and FIG. 4 shows the high power rejection ratio DC power circuit 1 of the present invention; wherein, the display panel 31 may be an active organic light emitting display panel (Active Matrix Organic Light Emitting Display, AMOLED) or an organic light emitting Display Panel (Organic Light Emitting Display, OLED). As mentioned above, the high power rejection ratio DC power supply circuit 1 of the present invention is used to receive a system voltage VDD provided by a power supply device 2 and then provide a stable output voltage VLDO to the display panel 31 with minimal Ripples of water on a display screen. As shown in FIG. 4, the stable output voltage VLDO is input to the display panel 31 in the form of a positive voltage ELVDD and a negative voltage ELVSS. In addition, the power supply device 2 referred to herein refers to a rechargeable battery whose output voltage changes according to the amount of stored power, such as a lithium battery. In addition, the display panel 31 can also be a touch display panel.

So far, the above has completely and clearly explained the high power rejection ratio DC power supply circuit of the present invention and the display device including the same; and, through the above, the present invention has the following advantages:

(1) The high power rejection ratio DC power supply circuit of the present invention can provide a PSRR of 64.4 dB in the case where the fluctuation of a system voltage is 500 mV.

(2) The display device of the present invention can minimize the water ripple of a display screen when the system voltage fluctuation is 500mV.

It must be emphasized that the aforementioned disclosure in this case is a preferred embodiment, and any part of the modification or modification that originates from the technical idea of this case and is easily inferred by those who are familiar with the art, does not deviate from the patent of this case. Power category.

In summary, regardless of the purpose, means and effects of this case, it shows that it is very different from the conventional technology, and its first invention is practical and practical, and it does meet the patent requirements of the invention. I urge your review committee to investigate and give the patent to the AirPlus as soon as possible. Society is for supreme prayer.

<The present invention>

1‧‧‧High power rejection ratio DC power supply circuit

11‧‧‧Pre-stage low dropout voltage stabilizing unit

12‧‧‧Internal system voltage enable unit

13‧‧‧ Bandgap reference voltage generating unit

14‧‧‧buffer circuit unit

15‧‧‧ Boost converter unit

16‧‧‧Output stage low voltage drop regulator unit

111‧‧‧First error amplifier

112‧‧‧First N-type field effect transistor

113‧‧‧ First resistance

114‧‧‧Second resistance

115‧‧‧ First filter capacitor

121‧‧‧Inverter

12‧‧‧First P-type field effect transistor

123‧‧‧Second P-type field effect transistor

141‧‧‧ First voltage follower

142‧‧‧Second voltage follower

143‧‧‧ third voltage follower

161‧‧‧Second Error Amplifier

162‧‧‧Second N-type field effect transistor

163‧‧‧The third P-type field effect transistor

164‧‧‧P-type field effect transistor

165‧‧‧The third resistance

166‧‧‧ Fourth resistance

167‧‧‧Second filter capacitor

2‧‧‧Power supply device

3‧‧‧Display device

31‧‧‧Display panel

32‧‧‧Data drive unit

33‧‧‧ Scan drive unit

34‧‧‧Controller unit

<Xizhi>

1’‧‧‧Regulated power supply circuit

11’‧‧‧Multiplexer

12’‧‧‧ Boost converter

13’‧‧‧Low Drop Linear Regulator

131’‧‧‧ error amplifier

132’‧‧‧Transmission element

133’‧‧‧First P-type field effect transistor

134’‧‧‧Second P-type field effect transistor

135’‧‧‧ First resistance

136’‧‧‧Second resistance

137’‧‧‧load capacitance

FIG. 1 shows a conventional architecture diagram of a regulated power supply circuit; FIG. 2 shows a circuit block diagram of a high power rejection ratio DC power supply circuit of the present invention; FIG. 3 shows a high power rejection ratio DC power supply of the present invention Circuit architecture diagram of the circuit; and FIG. 4 shows an architecture diagram of a display device of the present invention.

1‧‧‧High power rejection ratio DC power supply circuit

11‧‧‧Pre-stage low dropout voltage stabilizing unit

12‧‧‧Internal system voltage enable unit

13‧‧‧ Bandgap reference voltage generating unit

14‧‧‧buffer circuit unit

15‧‧‧ Boost converter unit

16‧‧‧Output stage low voltage drop regulator unit

Claims (9)

A high-power rejection ratio DC power supply circuit, which includes: a front-stage low-dropout voltage stabilizing unit for generating a front-stage output voltage according to a second reference voltage under a system voltage supply; an internal system voltage The enabling unit is used to select the system voltage or the pre-stage output voltage according to the control of a selection signal to provide an internal system voltage at an internal system voltage output terminal; Generate a bandgap reference voltage; a buffer circuit unit for generating a first reference voltage, the second reference voltage, and a third reference voltage according to the bandgap reference voltage under the supply of the internal system voltage; a boost A conversion unit for performing a step-up conversion operation according to the first reference voltage to boost the system voltage to an output stage supply voltage; and an output stage low-dropout voltage stabilization unit for the internal system voltage and the Under the power supply of the output stage supply voltage, a voltage stabilization operation is performed according to the third reference voltage to provide an output voltage. The DC power supply circuit with a high power rejection ratio as described in item 1 of the patent scope, wherein the pre-stage low dropout voltage stabilizing unit includes: a first error amplifier, which is powered by the system voltage and has a positive input To couple the second reference voltage, a negative input terminal is coupled to a first feedback voltage, and an output terminal is provided to provide a first regulated voltage; a first N-type field effect transistor has a gate Coupled to the first regulated voltage, a drain to couple the system voltage, and a source to provide the output voltage of the previous stage; and a first voltage-dividing resistor and a first filter capacitor connected in parallel with the first A voltage dividing resistor is used to generate the first feedback voltage according to a ratio of the output voltage of the previous stage. The high power rejection ratio DC power supply circuit as described in item 1 of the patent scope, wherein the internal system voltage enable unit includes: an inverter for generating an inverted signal of the selection signal; a first The P-type field effect transistor has a gate to couple the selection signal, a source to couple the system voltage, and a drain to couple to the internal system voltage output; and a second P-type field effect The transistor has a gate to be coupled to an output of the inverter, a source to be coupled to the output voltage of the previous stage, and a drain to be coupled to the output of the internal system voltage. The DC power supply circuit with a high power rejection ratio as described in item 1 of the patent application scope, wherein the buffer circuit unit includes: a first buffer for reference by the band gap under the supply of the internal system voltage The voltage generates the first reference voltage; a second buffer is used to generate the second reference voltage according to the bandgap reference voltage under the supply of the internal system voltage; and a third buffer is used in the internal Under the supply of the system voltage, the third reference voltage is generated according to the bandgap reference voltage. The high-power rejection ratio DC power supply circuit as described in item 4 of the patent application scope, wherein the first buffer, the second buffer, and the third buffer all include a voltage follower. The high-power rejection ratio DC power supply circuit as described in item 1 of the patent application scope, wherein the output stage low-dropout voltage stabilizing unit includes: a second error amplifier used to The difference between the third reference voltage and a second feedback voltage is amplified to generate a second regulated voltage; a second N-type field effect transistor is used to control the magnitude of a channel current according to the second regulated voltage; A third P-type field effect transistor and a fourth P-type field effect transistor are used to form a current mirror to enable the channel of the fourth P-type field effect transistor under the power supply of the output stage supply voltage The current is proportional to the channel current of the third P-type field effect transistor; and a second voltage divider resistor and a second filter capacitor connected in parallel therewith are the drain of one of the fourth P-type field effect transistor It is coupled to generate the output voltage, and the second voltage divider resistor is used to generate the second feedback voltage according to a ratio of the output voltage. A display device includes: a display panel; a data drive unit electrically connected to the display panel; a scan drive unit electrically connected to the display panel; a controller unit electrically connected the data drive unit and the A scanning drive unit; and a DC power supply circuit with a high power rejection ratio as described in any one of claims 1 to 6 to provide the output voltage to the display panel. The display device as described in item 7 of the patent application scope, wherein the display panel is a touch display panel. The display device as described in item 7 of the patent application range, wherein the display panel is an organic light emitting display panel or an active matrix organic light emitting display panel.

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