TWI684968B - Input stage circuit, driver and display device - Google Patents

Abstract

An input stage circuit has: an input terminal for receiving a first pulse signal of an output stage circuit; an output terminal for providing a second pulse signal; a counting control unit which counts according to a clock signal And determine the state of a switching signal after a count value reaches a predetermined value; a switching unit has a signal input terminal, a control terminal, a first signal output terminal and a second signal output terminal, the signal input terminal Is coupled to the first pulse signal, the control terminal is coupled to the switching signal, and the switching unit determines to electrically connect the signal input terminal to the first signal output terminal or the first signal according to the switching signal Two signal output terminals; a first sub-circuit that determines a first logic level conversion operation according to a first threshold voltage, which has a first input terminal to couple with the first signal output terminal, and a first The output terminal is coupled to the output terminal; and a second sub-circuit determines a second logic level conversion operation according to a second threshold voltage, and has a second input terminal to be coupled to the second signal output terminal , And a second output terminal to be coupled to the output terminal, wherein the second threshold voltage is lower than the first threshold voltage.

Description

Input stage circuit, driver and display device

The invention relates to an input stage circuit, in particular to an input stage circuit of a buffer capable of controlling voltage conversion.

With the development of technology, most electronic products used in daily life have display screens, and the general display screen charges each pixel unit through at least one source driver and at least one gate driver to To achieve the screen display effect. The current source driver (gate driver IC) and gate driver (gate driver IC) mostly use multi-drop connection (multi-drop) as the interface, for example: mini low voltage differential signal (mini Low Voltage Differential Signaling; mini-LVDS ) Interface, or low swing amplitude differential signal (Reduced Swing Differential Signaling; RSDS) interface, and use a synchronous buffer output stage circuit when communicating between chips.

In addition, please refer to FIG. 1, which shows a waveform diagram of the output voltage of an existing buffer output stage circuit and the input voltage of an existing buffer input stage circuit. As shown in FIG. 1, the intersection voltage V _SW of the voltage DIO-OUT of a buffer output stage circuit and the voltage DIO-IN of a buffer input stage circuit is generally defined as a conversion voltage. Generally speaking, V _SW =1/2VDD, that is, the voltage of the buffer input stage circuit is logic high only when the voltage DIO-OUT of the buffer output stage circuit is lower than 1/2VDD. In addition, the transition time of the buffer input stage circuit voltage DIO-IN from logic low to logic high is defined as T _SW .

Circuit design can usually reduce V _SW to increase the conversion rate. However, when V _{SW is} very low, the noise immunity of the circuit will decrease, especially when the voltage DIO-OUT of the buffer output stage circuit has noise higher than V _SW , it will cause the logic level of the buffer input stage circuit. Turning over will make the circuit less robust.

In order to solve the above-mentioned problems, there is an urgent need in the art for a synchronous signal buffer input stage circuit with controllable switching voltage.

An object of the present invention is to provide a controllable buffer input stage circuit, which determines two voltage level conversion methods through a counting control unit.

Another object of the present invention is to provide a controllable buffer input stage circuit, which can enable a plurality of serially connected display drivers to perform voltage level conversion in a separately controlled manner or in a unified control manner.

To achieve the above purpose, the present invention discloses a controllable input stage circuit, which has: an input terminal for receiving a first pulse signal of an output stage circuit; an output terminal for providing a second pulse signal A counting control unit counts according to a clock signal, and determines the state of a switching signal after the count value reaches a predetermined value; a switching unit has a signal input terminal, a control terminal, and a first signal output terminal And a second signal output terminal, the signal input terminal is coupled to the first pulse signal, the control terminal is coupled to the switching signal, and the switching unit determines to electrically connect the signal input terminal according to the switching signal To the first signal output terminal or the second signal output terminal; a first sub-circuit that determines a first logic level conversion operation according to a first threshold voltage, and has a first input terminal The first signal output terminal is coupled, and a first output terminal is coupled to the output terminal; and a second sub-circuit determines a second logic level conversion operation according to a second threshold voltage, which has a first Two input terminals are coupled to the second signal output terminal, and a second output terminal is coupled to the output terminal, wherein the second threshold voltage is lower than the first threshold voltage.

In one embodiment, the second sub-circuit includes a current source and an NMOS transistor connected in series with the current source.

In an embodiment, when the counting control unit determines that the input terminal has not received the pulse signal according to the count value, the switching signal assumes a first state so that the switching unit electrically connects the signal input terminal to all The first signal output terminal.

In an embodiment, when the counting control unit determines that the input terminal has received the pulse signal according to the count value, the switching signal assumes a second state so that the switching unit electrically connects the signal input terminal to all The second signal output terminal.

To achieve the above objective, the present invention further provides a driver having a multi-point connection interface and an input stage circuit as described above, and a plurality of the drivers can cooperatively drive a display panel through the multi-point connection interface.

In a possible embodiment, the multi-point connection interface may be a mini low voltage differential signal interface or a low swing differential signal interface.

In a possible embodiment, the driver may be a source driver or a gate driver or a source-gate integrated driver.

To achieve the above objective, the present invention further provides a display device having a display panel and at least one driver as described above for driving the display panel.

In a possible embodiment, the driver may be a source driver or a gate driver or a source-gate integrated driver.

In a possible embodiment, the multi-point connection interface may be a mini low voltage differential signal interface or a low swing differential signal interface.

In order to enable your review committee to further understand the structure, features and purpose of the present invention, the drawings and detailed description of the preferred embodiments are attached as follows.

Please refer to FIG. 2, which illustrates a schematic diagram of an embodiment of the input stage circuit of the present invention, wherein the input stage circuit can be applied to a source driver or a gate driver, and the source driver or the gate driver is Multi-drop connection (multi-drop) as the interface, for example: mini low voltage differential signal (mini Low Voltage Differential Signaling; mini-LVDS) interface, or low swing amplitude differential signal (Reduced Swing Differential Signaling; RSDS) interface.

As shown in FIG. 2, an input stage circuit 100 is a controllable input stage circuit, which includes an input terminal, an output terminal, a counting control unit 101, a switching unit 102, a first sub-circuit 103 and a first Two sub-circuits 104, wherein the first sub-circuit 103 is an ordinary input circuit, and the second sub-circuit 104 is a low conversion voltage circuit.

The input terminal is used to receive a first pulse signal DIO-OUT of an output stage circuit, and the output terminal is used to provide a second pulse signal OUT.

The counting control unit 101 counts according to a clock signal CLK, and determines the state of a switching signal SEL after the count value reaches a predetermined value to control the internal connection configuration of the switching unit 102, thereby connecting the first pulse signal DIO-OUT To the first sub-circuit 103 or the second sub-circuit 104.

Please refer to FIG. 3, which is a schematic diagram of an embodiment of the second sub-circuit 104. As shown in FIG. 3, the second sub-circuit 104 includes a current source 104a and an NMOS transistor 104b. During operation, as long as the input voltage IN is higher than the threshold voltage V _{TH of the} NMOS transistor 104b, the logic level of the second pulse signal OUT will be reversed, that is, by making the second sub-circuit 104 V _SW = V _TH can greatly reduce V _SW to increase the conversion rate of the logic level.

Please refer to FIG. 4, which is a schematic diagram of an application example of the input stage circuit of the present invention. As shown in FIG. 4, the wafer IC1, the wafer IC2, and the wafer IC3 all have the input stage circuit 100 of the present invention; the wafer IC1 outputs the pulse signal SIG1 to the wafer IC2, and the wafer IC2 outputs the pulse signal SIG2 to the wafer IC3, and in this application example Each of the input stage circuits uses individually controlled working methods. Specifically, at time t1, the counting control unit of the chip IC2 completes a counting procedure for the clock signal CLK and records a first count value when the pulse signal SIG1 arrives; and at time t2, the counting of the chip IC3 The control unit completes a counting procedure for the clock signal CLK and records a second count value when the pulse signal SIG2 arrives.

The first count value corresponds to a first duty cycle. In this embodiment, the first duty cycle includes t1-t3 phase and t3-t5 phase. In the t1-t3 phase, the period is a predetermined value, the chip IC2 will connect the chip IC1 to the first sub-circuit 103 of the chip IC2; and in the t3-t5 phase, the chip IC2 will connect the chip IC1 to the chip IC2 Second subcircuit 104.

The second count value corresponds to a second duty cycle. In this embodiment, the second duty cycle includes t2-t6 stage and t6-t8 stage. In the t2-t6 stage, the period is a predetermined value, the chip IC3 will connect the chip IC2 to the first sub-circuit 103 of the chip IC3; and in the t6-t8 stage, the chip IC3 will connect the chip IC2 to the chip IC3 Second subcircuit 104.

In this way, the chip IC2 can periodically select the first sub-circuit 103 and the second sub-circuit 104 sequentially according to the first count value, and the chip IC3 can periodically select the first sub-circuit 103 sequentially according to the second count value A sub-circuit 103 and a second sub-circuit 104, so as to realize the control mode of each chip separately.

In addition, in the operation sequence of FIG. 4, since each wafer records a count value of the clock signal CLK when the pulse signal first arrives, it is switched from the first sub-circuit 103 to the second sub-circuit after a period of time 104, so this method is more suitable for the case where the pulse time of the pulse signal SIG1 and the pulse signal SIG2 is relatively large.

Please refer to FIG. 5, which is a schematic diagram of another application example of the input stage circuit of the present invention. As shown in FIG. 5, the wafer IC1, the wafer IC2, and the wafer IC3 all have the input stage circuit 100 of the present invention; the wafer IC1 outputs the pulse signal SIG1 to the wafer IC2, and the wafer IC2 outputs the pulse signal SIG2 to the wafer IC3, and in this application example Each input stage circuit uses a unified control working mode. Specifically, at time t1, the counting control units of wafer IC2 and wafer IC3 both complete a counting procedure for clock signal CLK and record a count value when pulse signal SIG1 arrives.

The count value corresponds to a unified duty cycle. In this embodiment, the unified working cycle includes t1-t4 and t4-t5 stages. In the t1-t4 stage, the period is a predetermined value, the chip IC2 will immediately connect the chip IC1 to the second sub-circuit 104 of the chip IC2, and the chip IC3 will immediately connect the chip IC2 to the second sub-circuit of the chip IC3 104; In the t4-t5 stage, the wafer IC2 will connect the wafer IC1 to the first sub-circuit 103 of the wafer IC2, and the wafer IC3 will connect the wafer IC2 to the first sub-circuit 103 of the wafer IC3.

In addition, in the operation sequence of FIG. 5, each chip selects the second sub-circuit 104 immediately except for recording the count value of the clock signal CLK when the pulse signal first arrives, so this method is suitable for The pulse signal SIG1 and the pulse signal SIG2 have a small pulse time interval.

Based on the above, the input stage circuit 100 of the present invention is connected to the first sub-circuit 103 (that is, the ordinary input circuit) before the pulse signal SIG1 arrives. At this time, V _{SW is} about 1/2VDD, which ensures the robustness of the circuit And, when the clock signal SIG1 is about to arrive, connect the second sub-circuit 104 (that is, the low switching voltage circuit) to increase the conversion rate of the logic level.

In addition, according to the above principle, the present invention further provides a driver having a multi-point connection interface and an input stage circuit as described above, and a plurality of the drivers can cooperatively drive a multi-point connection interface through the multi-point connection interface. Display panel.

In a possible embodiment, the multi-point connection interface may be a mini low voltage differential signal interface or a low swing differential signal interface.

In a possible embodiment, the driver may be a source driver or a gate driver or a source-gate integrated driver.

Based on the above principle, the present invention further provides a display device having a display panel and at least one driver as described above for driving the display panel. The driver may be a source driver or a gate driver or a A source-gate integrated driver, and the multi-point connection interface may be a mini low voltage differential signal interface or a low swing differential signal interface.

With the design disclosed above, the present invention has the following advantages:

1. An input stage circuit can be dynamically determined by a counting control unit using a common input circuit or a low switching voltage circuit.

2. Each input stage circuit of a plurality of chips connected in series can decide to use a common input circuit or a low conversion voltage circuit.

3. Each input stage circuit of a plurality of chips connected in series can uniformly decide to adopt a common input circuit or a low-switching voltage circuit.

The case disclosed in this case is a preferred embodiment, and any part of the modification or modification that originates from the technical idea of this case and can be easily inferred by those skilled in the art, does not deviate from the patent scope of this case.

In summary, regardless of the purpose, means and effects of this case, it shows that it is very different from the conventional technology, and its first invention is practical and practical, and it does meet the patent requirements of the invention. I urge your review committee to investigate and give the patent to the AirPlus as soon as possible. Society is for supreme prayer.

100‧‧‧ input stage circuit

101‧‧‧Counter control unit

102‧‧‧Switching unit

103‧‧‧The first sub-circuit

104‧‧‧Second subcircuit

104a‧‧‧Current source

104b‧‧‧NMOS transistor

FIG. 1 is a waveform diagram showing the output voltage of an existing buffer output stage circuit and the input voltage of an existing buffer input stage circuit. 2 is a schematic diagram of an embodiment of the input stage circuit of the present invention. FIG. 3 is a schematic diagram of an embodiment of a second sub-circuit of the input stage circuit of the figure. FIG. 4 is a schematic diagram of an application example of the input stage circuit of the present invention. FIG. 5 is a schematic diagram of another application example of the input stage circuit of the present invention.

100‧‧‧ input stage circuit

101‧‧‧Counter control unit

102‧‧‧Switching unit

103‧‧‧The first sub-circuit

104‧‧‧Second subcircuit

Claims (9)

An input stage circuit has: an input terminal for receiving a first pulse signal of an output stage circuit; an output terminal for providing a second pulse signal; a counting control unit which counts according to a clock signal And determine the state of a switching signal after a count value reaches a predetermined value; a switching unit has a signal input terminal, a control terminal, a first signal output terminal and a second signal output terminal, the signal input terminal Is coupled to the first pulse signal, the control terminal is coupled to the switching signal, and the switching unit determines to electrically connect the signal input terminal to the first signal output terminal or the first signal according to the switching signal Two signal output terminals; a first sub-circuit that determines a first logic level conversion operation according to a first threshold voltage, which has a first input terminal to couple with the first signal output terminal, and a first The output terminal is coupled to the output terminal; and a second sub-circuit determines a second logic level conversion operation according to a second threshold voltage, and has a second input terminal to couple with the second signal output terminal And a second output terminal to be coupled to the output terminal, wherein the second threshold voltage is lower than the first threshold voltage; wherein the counting control unit judges that the input terminal has not received the pulse signal according to the counting value So that the switching signal assumes a first state so that the switching unit electrically connects the signal input terminal to the first signal output terminal. The input stage circuit of claim 1, wherein the second sub-circuit includes a current source and an NMOS transistor connected in series with the current source. The input stage circuit according to claim 1, wherein when the counting control unit judges that the input terminal has received the pulse signal according to the count value, the switching signal assumes a second state to enable the switching unit to apply the signal The input terminal is electrically connected to the second signal output terminal. A driver has a multi-point connection interface and an input stage circuit as described in any one of claims 1-3, and a plurality of the drivers can cooperatively drive a display panel through the multi-point connection interface. The driver according to claim 4, wherein the multi-point connection interface is a mini low voltage differential signal interface or a low swing differential signal interface. The driver according to claim 4, which is a source driver or a gate driver or a source-gate integrated driver. A display device has a display panel and at least one driver according to claim 4 for driving the display panel. The display device according to claim 7, wherein the driver is a source driver or a gate driver or a source-gate integrated driver. The display device according to claim 7, wherein the multi-point connection interface is a mini low-voltage differential signal interface or a low-swing differential signal interface.

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