TWI682388B - Semiconductor device - Google Patents

Abstract

An array of variable resistance cells based on a programmable threshold transistor and a resistor connected in parallel is described, including 3D and split gate variations. An input voltage applied to the transistor, and the programmable threshold of the transistor, can represent variables of sum-of-products operations. Programmable threshold transistors in the variable resistance cells comprise charge trapping memory transistors, such as floating gate transistors or dielectric charge trapping transistors. The resistor in the variable resistance cells can comprise a buried implant resistor connecting the current-carrying terminals (e.g. source and drain) of the programmable threshold transistor. A voltage sensing sense amplifier is configured to sense the voltage generated by the variable resistance cells as a function of an applied current and the resistance of the variable resistance cells.

Description

Semiconductor components

The present invention relates to a circuit that can be used to perform or support a product-sum operation.

In neuromorphic computing systems, machine learning systems, and some types of computational circuits based on linear algebra, product sum functions can be important components. The function can be expressed as follows:

In this expression, the variable input of each product term is the product of X _i and the weighting W _i. The weight W _i may vary between terms, corresponding to, for example, the coefficient of the variable input X _i .

The product-sum function can be implemented in circuit operations using a cross-point array architecture, where the electrical characteristics of the array unit incur this function.

For high-speed implementations, it is desirable to have a very large array, so that many operations can be performed in parallel, or a very large product and series can be performed. In the system, there are a very large number of inputs and outputs, so that the total current consumption may be very large.

The present invention is expected to provide a structure suitable for products and functions implemented in a large array, and can be more effective in energy saving.

The present invention describes an apparatus including an array of variable resistance cells, in which a variable resistance cell includes a programmable threshold transistor and a parallel resistor. The device is operable so that the input voltage applied to the transistor and the programmable threshold of the transistor can represent changes in the product and operation. In the embodiments described herein, the variable resistance of each variable resistance cell is a function of the voltage and resistance applied to the control gate of a programmable threshold transistor in the cell.

In some embodiments, the device includes a voltage sensing sense amplifier for sensing the voltage generated by the variable resistance unit as a function of the applied current and the resistance of the variable resistance unit. In this way, the product sum of the magnitude of current generation can be limited or fixed, and reduce power consumption.

The array of cells composed of a transistor and a resistor (1T-1R) can be implemented in two-dimensional (2D) and three-dimensional (3D) arrays. In addition, the embodiments described herein can implement the resistor as a buried implant resistor with a layout coverage of a single variable threshold transistor, in effect fabricating an array of transistor (1T) cells to be configured with voltage sensing The very compact layout of the product sum operation.

The present invention describes an embodiment in which the variable resistance unit in the array is arranged on a plurality of strings in series with the variable resistance unit. A plurality of word lines may be coupled to the string lines of the serial variable resistance unit string lines. The word line driver is connected to multiple word lines to apply a variable gate voltage to a programmable threshold transistor in the variable resistance unit.

The embodiments of the present invention describe that the programmable threshold transistor in the variable resistance unit includes a charge trapping storage transistor, such as a floating gate transistor or a dielectric charge trapping transistor.

Embodiments of the present invention describe a buried resistance of a resistor in a variable resistance unit including a current-carrying terminal of a programmable threshold transistor connected in series; the current-carrying terminal is, for example, a source electrode and a drain electrode.

The present invention provides an apparatus for generating product and data. The apparatus includes an array of variable resistance units, each variable resistance unit in the array, each unit includes a programmable threshold transistor and a resistor in parallel, the array includes a series The n-row unit and m-column unit of the unit string circuit. A control and bias circuit is coupled to the array. The control and bias circuit includes logic for programming a programmable threshold transistor in the array with a threshold corresponding to the weighting factor value W _mn of the corresponding cell. The input driver is coupled to the corresponding column of m column units, and the input driver selectively applies input X _m to m columns. The row driver is configured to apply a current I _n to a corresponding row of n row units. The voltage sensing circuit is operatively coupled to the row unit.

The present invention describes a system including a memory array and a product and accelerator array interconnected using a data path controller. The product and accelerator array includes a programmable resistance cell array. Memory arrays can be used in coordination with product and accelerator arrays for configuration and product and function operations.

A method for operating a variable resistance cell array to produce a sum of product data, including programming a programmable threshold transistor in the array with a threshold value corresponding to the weighting factor value of the corresponding cell; selectively applying input to a column in the array Cells, applying current to corresponding rows of row cells in the array; and sensing voltages on one or more row cells of the row cells in the array.

In order to have a better understanding of the above and other aspects of the present invention, the following examples are specifically described in conjunction with the accompanying drawings as follows:

12,35,3635‧‧‧Programmable threshold transistor

14, 36, 3636‧‧‧ resistance

21, 22, 23, 24 ‧‧‧ current source

26‧‧‧Ground

30、3630‧‧‧First current carrying node

31、3631‧‧‧second current carrying node

32、3632‧‧‧Control terminal

100, 200, 300, 3105‧‧‧ substrate

101、201‧‧‧Source terminal

102、202‧‧‧ Jiji

103‧‧‧ Floating gate polysilicon layer

104、204‧‧‧Control gate polysilicon layer

105, 205‧‧‧ Gate dielectric layer

106‧‧‧Inner polysilicon dielectric

107, 108, 207, 208

109, 209‧‧‧ contact layer

110, 210, 304, 451

112, 114, 212, 214‧‧‧ current path

113, 213‧‧‧ p-type channel area

203‧‧‧dielectric charge trapping layer

206‧‧‧Block dielectric layer

301,302‧‧‧Shallow trench isolation structure

303‧‧‧Border

310‧‧‧Source area

311‧‧‧ Drainage area

315‧‧‧floating gate

316‧‧‧Control gate

320‧‧‧Side wall

321‧‧‧Etching stop layer

322‧‧‧Interconnect dielectric

325, 326‧‧‧ Internal connection contacts

400‧‧‧series connection of variable resistance unit

401, 402‧‧‧ string selected character line

410, 411, 412, 413, 414, 415‧‧‧‧ character line gate stack

420,421,422,423,424,425,426,427 n-type implants

450‧‧‧p-type protective layer

502‧‧‧bit line contact

503‧‧‧Source line contact

504, 505‧‧‧ Active area

600, 601‧‧‧ current-carrying node

602‧‧‧ input node

650‧‧‧Sense amplifier

651‧‧‧Buffer

652, 656, 965, 975‧‧‧

655‧‧‧ Reference voltage circuit

660‧‧‧register

661‧‧‧ arithmetic logic unit

665‧‧‧ Reference line

666‧‧‧Resistance voltage divider

667‧‧‧selector

680, 690, 700 ‧‧‧ operation string circuit

681‧‧‧ line reference string line

691, 701, 702

692‧‧‧ Reference area

703‧‧‧Array area

901‧‧‧Integrated circuit

905‧‧‧Data bus

910‧‧‧Control logic

920, 3410‧‧‧ block

930‧‧‧Bus

940‧‧‧ character line driver

945, 3006, 3108, 3205, 3405a, 3405b ‧‧‧ character line

960‧‧‧ neuromorphic memory array

970‧‧‧line decoder

980‧‧‧buffer circuit

985‧‧‧Second data cable

990‧‧‧Data buffer

991‧‧‧ input/output circuit

993‧‧‧Data path

1000‧‧‧System

1001‧‧‧ Product and accelerator array

1002‧‧‧Memory array

1003‧‧‧Data path controller

2700‧‧‧U-shaped vertical NAND string circuit

2800‧‧‧The first NAND string circuit

2801‧‧‧Second NAND string circuit

2901, 3201‧‧‧ First pattern metal layer

2902, 3202‧‧‧Second pattern metal layer

2903, 3106, 3208

2904, 3107, 3203‧‧‧Ground selected line

2905、3005a、3005b、3103‧‧‧Vertical channel structure

2906‧‧‧ auxiliary gate structure

3001, 3101, 3401‧‧‧bit line

3002, 3402‧‧‧ source line

3003, 3004, 3403, 3404 ‧‧‧ selected gate

3007‧‧‧ Rear gate

3102‧‧‧ Internal connection

3104‧‧‧Common source line diffusion

3109‧‧‧dielectric layer

3110, 3206‧‧‧ charge trapping layer

3111‧‧‧semiconductor material film

3112‧‧‧doped polysilicon

3204‧‧‧Auxiliary gate line

3207‧‧‧thin film channel layer

3209‧‧‧Insulation

3406‧‧‧ shared floating gate structure

3407‧‧‧polysilicon dielectric layer

3408‧‧‧Tunnel dielectric layer

3409‧‧‧doped semiconductor core

Figure 1 is a functional diagram showing the product-sum operation. The product-sum operation may be a basic element of a neuromorphic operation system known in the prior art.

FIG. 2 is a partial diagram of a variable resistance cell array disposed in a product-sum operation.

FIG. 3 is a schematic diagram of a variable resistance unit according to embodiments described herein.

FIG. 4 shows a simplified cross-sectional view of a variable resistance unit including floating gate storage transistors and buried implant resistors.

FIG. 5 shows a simplified cross-sectional view of a variable resistance unit including dielectric charge trapping storage transistors and buried implant resistors.

FIGS. 6-9 illustrate a manufacturing flowchart of the variable resistance unit according to the embodiments described herein.

FIGS. 10A and 10B are a cross-sectional view and a layout view showing that variable resistance units are arranged in series in a NAND-like (NAND-Like) structure.

11A and 11B are diagrams illustrating exemplary operation of the variable resistance unit.

FIG. 12 illustrates a string line (String) of variable resistance units configured for product-sum operation.

FIG. 13 is a simplified block diagram of a sensing circuit that can be used in a product-sum operation together with a variable resistance cell array.

FIG. 13A is an enlightening diagram showing the purpose of the sensing operation using the circuit of FIG. 13.

Figure 14 shows a simplified diagram of a reference voltage circuit that can be used with the sensing circuit as shown in Figure 13.

FIG. 15 illustrates the configuration of a variable resistance cell array including a reference string (String).

FIG. 16 shows another configuration diagram of a variable resistance cell array including a reference string and unused cells.

FIG. 17 shows another configuration diagram of a variable resistance cell array including two reference strings and unused cells.

Figures 18-22 are functional diagrams of variable resistance units configured to use multiple bit weights to implement product and operation terms.

Figure 23 is a simplified block diagram of a device including variable resistance cell array applications, for example, for neuromorphic memory.

Figures 24-26 show the system including the product accelerator array and its different operations.

Fig. 27 is a schematic circuit diagram of a vertical U-shaped NAND string circuit of a variable resistance unit.

Fig. 28 is a schematic circuit diagram of an alternative vertical NAND-like string circuit of a variable resistance unit.

FIG. 29 is a perspective view of a 3D array of vertical U-shaped NAND string circuits of variable resistance units.

FIG. 30 is a cross-sectional view of a single vertical U-shaped NAND series string variable resistance cell string line of the variable resistance cell, which can be implemented in the array as shown in FIG. 29.

FIG. 31 also illustrates another type of 3D array of vertical U-shaped NAND-like string lines of variable resistance cells as described herein.

FIG. 32 shows a vertical channel single gate structure of a vertical U-shaped NAND string circuit including a variable resistance unit of another embodiment.

Figure 33 is a close-up view of the variable resistance unit of the array of Figure 32.

FIG. 34 is a vertical cross-sectional view of a floating gate type NAND-like structure including variable resistance cells as described herein.

Figure 35 is a close-up view of the shared floating gate type NAND variable resistance cell string circuit of Figure 34.

FIG. 36 is a schematic diagram of a split gate variable resistance unit according to embodiments described herein.

Figures 1-36 provide a detailed description of embodiments of the present invention.

Figure 1 is a product sum operation diagram, where the sum term is the product of the input X _i and the weight W _i , in this example, where i is from 1 to 7. The weight W _i may be different from the sum term. In operation, the weights can be specified as a set of coefficients and then applied to the input that calculates the change in the sum as a variable input. In addition, in the algorithm that performs the learning process, the weights that change over time are used as the learning process to change the coefficients, and the learning results in the sum of the available results.

In the illustrated example, the output of the summation is applied to the sigmoid function to generate a non-linear method to produce an output between the minimum and maximum values, such as between 0 and 1. This is a common model used for synaptic layers in neuromorphic operations. Other activation functions can also be used, such as logical operations. The product-sum operation can also be applied to non-neuromorphic configurations or neurological model considerations.

Figure 2 is a schematic diagram of a variable resistance cell array, where each cell in the array includes a programmable threshold transistor 12 and a resistor 14 in parallel. In this diagram, the array includes four string variable resistance units, where each string includes four variable resistance units connected in series between the sum nodes SUM ₁ to SUM ₄ and a reference line, for example是 ground wire 26. The four word lines WL1 to WL4 are coupled to the control terminals of the variable resistance units in each string. As shown, there can be any number of row and sum nodes connected to SUM _n and any number of word lines WL _m . variable resistance unit n rows and m columns with weight W _nm as a unit of programmable threshold Vt, the resistor R _nm and a function of the current I _n of the row unit.

The voltage applied to the word line corresponds to the variable inputs X ₁ to X ₄ ,... X _m . In this method, the variable resistance of each variable resistance cell in the string line is the voltage applied on the word line to the control gate of the cell, the threshold of the programmable threshold transistor in the cell, the current and resistance in the cell Function.

Sum nodes SUM ₁ to SUM ₄ ,... SUM _{n are} coupled to a voltage sensing sense amplifier to generate signals representing the product and output of each string line. In a representative example, during the sensing operation, current sources 21-24 are coupled to each string line to apply a fixed current to each string line.

Figure 3 is a schematic diagram of a variable resistance unit, for example for the array of Figure 2. The variable resistance unit includes a first current carrying node 30, a second current carrying node 31, and a control terminal 32. The programmable threshold transistor 35 and the resistor 36 are connected in parallel to the first current-carrying node and the second current-carrying node. The programmable threshold transistor has a gate connected to the control terminal 32.

The voltage VG on the control terminal 32 can be regarded as the gate voltage of the programmable threshold transistor 35. The control terminal 32 may correspond to the word line of the array in FIG. 2. The voltage V _S on the first current-carrying node 30 can be regarded as the source voltage of the cell. The voltage V _D on the second current-carrying node 31 can be regarded as the drain voltage of the cell.

In this example, the cell current I _C applied to the carrier having a second node designed or adjustable amplitude of the current 31, to establish a voltage drop depending on the voltage range of the resistance value of the resistor element 36 in the voltage of the sense amplifier in the unit . The current amplitude can be adjusted according to the specific array embodiment, so that a useful voltage range can be generated on the string line to be supplied to the sum node. In addition, the resistance size of the resistor and the configuration of the programmable threshold transistor can be designed to operate with a selected current level and a specified sensing range.

The programmable threshold transistor 35 can use floating gate memory cells, split gate floating gate memory cells, and dielectric charge trapping memory cells, such as SONOS devices or other known types of dielectric charge trapping memory cells such as BE-SONOS and TANOS, and separation gate. Other programmable memory cell technologies can also be used, such as phase change memory, metal oxide memory, etc.

Furthermore, in embodiments of the present technology, the resistor 36 may be implemented as a buried implant resistor between the source and drain terminals of the programmable threshold transistor 35.

Figure 36 is a schematic diagram of a separate gate variable resistance unit, which can be used in a modified version of the array of Figure 2, for example. The variable resistance unit includes a first current carrying node 3630, a second current carrying node 3631, and a control terminal 3632. The control terminal covers part of the channel length by the charge trapping layer and is separated from the channel by the gate dielectric without charge trapping for data storage in channel length balancing. The programmable threshold transistor 3635 and the resistor 3636 are connected in parallel to the first current-carrying node and the second current-carrying node. The programmable threshold transistor has a gate connected to the control terminal 3632.

The voltage V _G at the control terminal 3632 can be regarded as the gate voltage of the programmable threshold transistor 3635. The control terminal 3632 may correspond to the word line in the array shown in FIG. 2. The voltage on the first current carrying node 3630 can be regarded as the voltage source of the cell. The voltage V _D on the second current-carrying node 3631 can be regarded as the drain voltage of the cell.

FIG. 4 is a simplified cross-sectional view of a floating gate device having a resistor connected in parallel to a channel, and the resistor is implemented using ion implantation to create a buried implant resistor 110.

In this example, the device is implemented on a substrate 100, which may be a p-type substrate. The source terminal 101 and the drain terminal 102 are implemented by n-type ion implantation in the substrate 100. The source terminal 101 and the drain terminal 102 have their formed contacts 107, 108, coupled to a source node having a voltage V _S and a drain node having a voltage V _D. The p-type channel region 113 is provided between the buried implant resistor 110 and the gate dielectric layer 105 (channel oxide) to cover the substrate 100 between the source terminal 101 and the drain terminal 102. The floating gate polysilicon layer 103 is disposed on the gate dielectric layer 105. In some embodiments, the inner polysilicon dielectric 106 disposed on the floating gate polysilicon layer 103 uses a multilayer structure including silicon oxide, silicon nitride, and silicon oxide layer (ONO). The control gate polysilicon layer 104 is disposed on the inner polysilicon dielectric 106. The contact layer 109 is formed on the control gate polysilicon layer 104. The sidewall structure (not numbered) is formed along the sidewall of the gate stack.

The structure shown in FIG. 4 can be implemented using floating gate cell manufacturing technology and modified by additional doping steps to form buried implant resistor 110. The buried implant resistor 110 connects the source terminal 101 and the drain terminal 102 as a passive resistor. In this way, the floating gate device and the buried implant resistor 110 provide a programmable threshold transistor and a parallel resistor between the first current carrying terminal-source terminal 101 and the second current carrying terminal-drain terminal 102 .

In FIG. 4, a current path 112 is shown. The current path 112 passes through a buried implant resistor 110 between the source terminal 101 and the drain terminal 102. The current path 114 is also shown in FIG. 4. When the gate voltage is combined with the trapped charge and the source voltage V _S in the floating gate, the current path 114 is activated to allow current to flow through the channel of the transistor.

Therefore, the device has a variable resistance (or variable conductance), which is a function of the resistance of the buried implant resistor 110 and the resistance of the floating gate device channel. The resistance of the floating gate device channel is a function of the gate voltage and the charge trapped in the floating gate.

FIG. 5 is a simplified cross-sectional view of a dielectric charge trapping device having a resistor connected in parallel to a channel, and is implemented using an ion implantation method to produce a buried implant resistor 210.

In this example, the device is implemented on a substrate 200, which may be a p-type substrate. The source terminal 201 and the drain terminal 202 are implemented by n-type ion implantation in the substrate 200. The source terminal 201 and the drain terminal 202 have contacts 207, 208 formed by them, and are coupled to a source node having a voltage V _S and a drain node having a voltage V _D. The p-type channel region 213 is provided between the buried implant resistor 210 and the gate dielectric layer 205 (channel oxide) to cover the substrate 200 between the source terminal 201 and the drain terminal 202. The dielectric charge trap layer 203 is provided on the channel dielectric layer 205. The blocking dielectric layer 206 is disposed on the dielectric charge trapping layer 203, and the control gate polysilicon layer 204 is disposed on the blocking dielectric layer 206. The contact layer 209 is formed on the control gate polysilicon layer 204. The sidewall structure (not numbered) is formed along the sidewall of the gate stack.

The structure shown in FIG. 5 can be implemented using a dielectric charge trapping memory cell manufacturing technique, which can be modified through additional doping steps to form a buried implant resistor 210. The buried implant resistor 210 connects the source terminal 201 and the drain terminal 202 as a passive resistance. In this manner, the dielectric charge trapping device and the buried implant resistor 210 provide a programmable threshold transistor and a parallel resistance between the source terminal 201 and the drain terminal 202.

In FIG. 5, a current path 212 is shown, and the current path 212 passes through the buried implant resistor 210 between the source terminal 201 and the drain terminal 202. Figure 5 also shows the current The path 214, when the gate voltage and the trapped charge are combined in the dielectric charge trapping layer, the current path 214 is activated to allow current to flow through the device channel.

Therefore, the device has a variable resistance (or conductance), which is a function of the resistance of the buried implant resistor 110 and the resistance of the channel of the dielectric charge trapping device. The resistance of the channel of the dielectric charge trapping device is a function of the gate voltage and the charge trapped in the dielectric charge trapping gate.

In the two embodiments of FIG. 4 and FIG. 5, a unit composed of a transistor and a resistor (1T-1R) is shown. In addition, the embodiments of FIGS. 4 and 5 can implement the resistor in a buried variable resistor within the coverage area of a single variable threshold transistor layout, and effectively manufacture an array of transistor (1T) cells to Configured in a very compact layout with product and operation of voltage sensing.

In operation, the units depicted in Figures 4 and 5 can be represented as follows.

When the gate-to-source voltage V _{GS is} less than the threshold voltage V _t , current can flow into the buried implant resistor, but it is not formed in the transistor channel (“surface channel”), and only the current I _B is allowed to be in the buried implant resistor . Therefore, the current in the cell is equal to I _B , and the resistance of the cell is equal to the drain-to-source voltage V _DS divided by the current I _B.

When the gate-to-source voltage V _{GS is} greater than the threshold voltage V _t , both the surface channel current _IS and the hidden resistance current I _B are induced. Channel resistance can be much smaller than the resistance of resistor hidden, and when the transistor is turned on, I _s can be controlled. Accordingly, the current row is divided into unit I _n, I _n is equal to the sum of such currents I _S + I _B, and the cell resistance is equal to the drain to source voltage V _DS divided by the current I _n.

Since the floating gate threshold or dielectric charge trapping unit is programmable, the cell resistance can simulate the parameter X(i) represented by the gate voltage, as well as the charge trapping in the cell, the resistance of the resistor and the cell current The product of the parameter W(i). The parameter W(i) can be a binary number, where the unit operates in one of two states (I _B only higher resistance state and I _B + _IS lower resistance state). If the cell operates in a linear region of field-effect transistor behavior, the parameter W(i) may be an analog and vary within the range according to charge trapping in the cell.

Figures 6-9 show a manufacturing flow chart that can be used to implement a unit similar to Figure 4. In FIG. 6, after the shallow trench isolation structures 301 and 302 providing the dielectric boundary of the cell are depicted, the substrate 300 is shown. And implanted a p-type well that has been used to form the boundary 303 of the area in the substrate 300 formed by providing the unit. The different blocks of the cells in the array can be implemented in separate blocks to allow the independent bias of the well to be used to separate the blocks.

FIG. 7 illustrates the stage after n-type dopants (such as phosphorus and arsenic) are used to form the buried implant resistor 304 between the shallow trench isolation structures 301 and 302.

Figure 8 shows the formation of the gate stack structure (floating gate 315, control gate 316, channel dielectric and polysilicon dielectric along the sidewall 320) and the source region implanted using n-type dopants The stage after the formation of the drain regions 310 and 311.

FIG. 9 illustrates the manufacturing stage after the formation of the interconnect dielectric 322 and the interconnect contacts 325 and 326. This structure is formed in the illustrated example using the method of forming silicide contacts on the source and drain regions, followed by the thin dielectric above the gate stack and the source and drain regions 310 and 311质和刻止层321。 Quality and etching stop layer 321. The interconnect dielectric 322 is deposited, and the hole is etched to form an opening, where the interconnect contacts 325 and 326 are formed by tungsten deposition or other techniques.

It can be seen that the variable resistance unit shown in FIG. 4 is manufactured according to these procedures. These same procedures can be modified for the purpose of manufacturing cells as shown in Figure 5, these phases The same procedure is modified by the gate stack including the gate dielectric, charge trapping layer, barrier layer and control gate.

The variable resistance units having the structure shown in FIGS. 4 and 5 can be arranged in series using the pattern conductor layer connected to the interconnection contacts 325, 326.

10A and 10B are cross-sectional and layout views of variable resistance cells arranged in series in a 2D NAND-like (NAND-Like) structure.

FIG. 10A shows a simplified cross section of the substrate, in which the series string line 400 of the variable resistance unit is formed. A word line gate stack 410-415 including a charge trapping layer (floating gate or dielectric) and a word line is stacked on the substrate and extends to a word line element perpendicular to the page direction. In a representative implementation, there may be, for example, 32 or 64 active character lines. In some embodiments, the series string line may include a smaller number of active word lines or a larger number of active word lines to suit a particular implementation. In some cases, there may be one or more dummy word lines, which may be on opposite ends of the string line, typical examples are high-density NAND flash memory. The virtual word line can be used for manufacturing quality or offset purposes, but it is not used for the product and operation of serial lines.

In this example, the substrate is a p-type substrate, and the current-carrying terminals (ie, source/drain terminals) of the variable resistance unit are implemented by n-type implants 420-427. In some high-density embodiments, implants are not used for current-carrying terminals between cells, so the current-carrying terminals rely on the inversion of charge carriers in the channel region. In the illustrated NAND-like embodiment, no contacts are directly formed between current-carrying terminals between all cells.

The string line selected character lines 401 and 402 are provided at opposite ends of the series string line. The active regions 504 and 505 in the substrate include n-type implants for connecting bit lines and common source lines of a serial string. The active regions 504 and 505 can be compared with the current-carrying terminals of the variable resistance unit It is a deeper implant or a higher conductivity implant. The bit line contact 502 connects the active area 504 to the bit line in the pattern conductor layer. The source line contact 503 connects the active area 505 to the source line in the pattern conductor layer.

An n-type buried implant resistor 451 is implemented. In this example, the channel edge from the selected gate controlled by the selected word line 401 on the bit line side string line selection extends to the controlled by the string line selected word line 402 on the source line side. The channel edge of the selected gate. In this manner, the selected gate is operated to connect and not connect the buried implant resistor 451 to the active regions 504, 505.

In this example, a p-type protective layer 450 having a higher p-type impurity concentration than the channel region of the variable resistance unit is disposed between the channel and the buried implant resistor 451. The p-type protective layer 450 helps shield the buried implant resistor 451 from the gate voltage and maintain the stability of the parallel resistance value.

Fig. 10B is a plan view of a series string line implementing the variable resistance unit shown in Fig. 10A. Common reference numbers (401, 402, 410-415) are given to the gate stack (including the word line) and the selected line. Likewise, common reference numbers 502, 503 are given to the bit line and source line contacts.

FIG. 10B shows that the two series strings are arranged on the parallel bit lines 500 and 501, which are implemented on the patterned conductor layer covered on the word line gate stacks 410-415.

Figure 27 shows that a U-shaped vertical NAND-like string line 2700 as described herein includes a variable resistance unit with a resistance (eg, 2701) in parallel to a programmable threshold, an operable charge trapping memory cell (eg, 2702) as a product And accelerator schematics. In FIG. 27, the NAND-type string line includes one U-shaped string line coupled to the bit line BL, which includes a series of line selection switches SSL connected in series, and a plurality of first cells coupled to respective word lines WL on the right side Knot The auxiliary gate AG at the bottom of the structure. The plurality of second cells are coupled to respective word lines WL on the left side, and the ground selection switch GSL is coupled to the source reference line CS. The input of the operation is applied to the word line WL as described herein and configured as explained. Use voltage and current sensing techniques or other sensing techniques to sense the output on the bit line or reference line.

FIG. 28 is a schematic diagram of an alternative vertical structure including a first NAND-type string line 2800 and a second NAND-type string line 2801, which includes a variable resistance unit having a resistance in parallel to a programmable threshold, charge trapping memory cell, such as The product and accelerator actions described in this article. In FIG. 29, the first NAND-type string line extends between the first bit line BL and the source reference line CS, and includes a string line selection gate SSL, a plurality of word lines WL, and a series ground selection gate Very GSL. Similarly, the second NAND-type string line extends between the second bit line BL and the source reference line CS, and includes a string line selected gate SSL, a plurality of word lines WL, and a series-connected ground selected gate GSL. The operation input is applied to the word line WL and configuration as described herein, and the output on the bit line or the reference line can be sensed using current sensing technology or other sensing technology.

Figures 29-35 illustrate various structures that can be used to implement vertical NAND-like embodiments. In FIG. 29, a U-shaped NAND string circuit similar to FIG. 27 is implemented in a dense 3D array. The structure includes a first pattern metal layer 2901 implemented by bit lines, and a second pattern metal layer 2902 including reference lines. The selected gate layer includes a string line selection line 2903 and a ground selection line 2904. The vertical channel structure 2905 extends through the word lines to multiple layers. The vertical channel structure is connected to the U-shaped pattern supported by the auxiliary gate structure 2906. The vertical channel structure includes a data storage layer with natural resistance, such as a charge trapping structure, and an N-type polysilicon doped vertical channel. The vertical channel structure is surrounded by word lines in each layer of the structure, thereby forming a so-called full gate variable resistance cell. Therefore, when the input on the word line is not conducted to the charge trap unit, the resistance To determine the resistivity. When the input on the word line is conducted to the charge trap unit, the resistance is determined by the parallel resistance of the charge trap unit and the resistivity of the vertical channel. See Tanaka, H., et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory," 2007 Symp.VLSI Tech., Digest of Tech.Papers, pp 14-15.

Figure 30 shows a single U-shaped NAND-like string circuit, which can be implemented in an array similar to Figure 29. The bit line 3001 is connected to a series of variable resistance units on the left side of the vertical channel structure 3005a via the selected gate 3004, and is connected to the variable resistance of the opposite vertical channel structure 3005b through the horizontal extension of the vertical channel structure and the rear gate 3007 The second vertical string line of the unit. The second vertical string line of the variable resistance unit is coupled to the source line 3002 through the selected gate 3003. Each string includes a plurality of word lines (for example, 3006), and is operated and input in the configuration as described herein. The vertical channel structures 3005a, 3005b on both sides of the U-shaped NAND-like string circuit may include n-type doped polysilicon to provide hidden resistance, which is formed by in-situ doping or implantation.

Figure 31 shows an alternative vertical NAND-like string circuit that implements the circuit of Figure 28. In the structure of FIG. 31, the bit line 3101 is implemented in the first pattern metal layer. The bit line 3101 is connected to the vertical channel structure 3103 through the interconnection 3102. The vertical channel structure 3103 includes a thin film of semiconductor material 3111 extending along the side of the vertical channel structure. In this embodiment, the interior of the vertical channel structure 3103 includes doped polysilicon 3112 to provide hidden resistance. The vertical channel structure 3103 extends between a plurality of conductor stacks, which are disposed on the string line selection line 3106 and the ground selection line 3107 between the opposite ends of the string line and the character line 3108. The vertical channel structure 3103 is coupled to the common source line diffusion 3104 and the substrate 3105. The charge trapping layer 3110 is provided in the vertical channel structure 3103 as a conductor of a word line (for example, 3108) and a thin film of semiconductor material 3111 between. The dielectric layer 3109 separates the string line of conductive material to serve as a character line and a string line selection line. Since the string line selection lines 3106 on opposite sides of the vertical channel structure 3103 are separated, these vertical NAND-like string lines can share a single bit line 3101. See Jang, et al., "Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory", 2009 Symposium on VLSI Technology Digest of Technical Papers.

FIG. 32 shows a dense 3D array including a single gate as described herein, a U-shaped vertical NAND-like string circuit including variable resistance cells in parallel with a charge trapping memory cell. In this structure, the bit line is implemented on the first pattern metal layer 3201, and the source line is implemented on the second pattern metal layer 3202. The bit line and the source line are connected to the vertical channel structure of the U-shaped film containing semiconductor material through the interconnection connector. The vertical channel structure is used for the channel and the hidden resistor as described in the embodiments of the present invention. The vertical channel structure extends between the plurality of conductors, and the vertical channel structure is configured as a string line selected line 3208 or a ground selected line 3203, a character line (eg, 3205), and an auxiliary gate line 3204. These conductors are separated by insulating materials. The vertical channel structure includes a charge trap layer 3206 and a thin film channel layer 3207 extending in a U-shaped pattern. This structure covers the insulating layer 3209. The thin film channel layer 3207 may include doped polysilicon. The thin film channel layer 3207 is formed by in-situ doping of the polysilicon film or deposition of doped polysilicon. See US Patent No. US 9,698,156 and US Patent No. 9,524,980.

FIG. 33 shows two vertical channel variable resistance units coupled to the word line 3205. Each variable resistance unit includes a charge trap layer 3206 and a doped thin film channel layer 3207.

The conductors in the stack are configured as word lines, which can be used to apply input to NAND-like string line array operations as a product accelerator structure.

Figure 34 also illustrates another vertical NAND-type structure including variable resistance cells as described herein. In this example, the series of cells is coupled between the bit line 3401 and the source line 3402. The pile of conductors includes conductors configured as conductors of selected gates 3403 and 3404, and conductors configured as word lines (eg, 3405a and 3405b). A common floating gate structure (eg 3406) is provided between conductors configured as word lines (eg 3405a, 3405b). The vertical channel structure includes a tunneling dielectric layer 3408 and a doped semiconductor core 3409, such as n-type doped polysilicon. The vertical channel structure doping is expressed as the hidden resistance of the variable resistance unit. The inter-polysilicon dielectric layer 3407 separates the conductors configured as word lines from the vertical channel structure and the floating gate.

Figure 35 shows the structure of block 3410 from Figure 34. It can be seen that the vertical channel structure is arranged and surrounded by the doped semiconductor core 3409 and the tunneling dielectric layer 3408. The conductors are configured as word lines 3405a and 3405b, and a common floating gate structure 3406. The polysilicon dielectric layer 3407 separates the conductors configured as word lines 3405a and 3405b from the vertical channel structure (including the doped semiconductor core 3409) and the common floating gate structure 3406, see Seo, et al., "A Novel 3 -D Vertical FG NAND Flash Memory Cell Arrays Using the Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation", 2011 IEEE.

Product and array embodiments utilizing variable resistance cells can have very large arrays, including arrays with thousands or millions of variable resistance cells. The manufacturing technology used for large-scale 2D and 3D NAND devices can be applied. The manufacturing technology has additional steps for buried implant resistors or other resistive structures, such as Figures 10A, 10B, and 27-36 The illustrated NAND structure is implemented in the manufacture of a large number of products and arrays. Operating techniques used to apply write (program and erase) weights to programmable resistance cells, similar to those using large-scale NAND The operating technology of the device. As mentioned above, the programmable resistance unit can be operated in an analog mode. In analog mode, the peripheral circuits used for sensing circuits and signal routing can be complex.

Peripheral circuits can be simplified by configuring programmable resistance cells in the cell array to operate in "binary" mode. Programmable threshold transistors can store binary states. The current applied to the row can be constant or a fixed number of binary levels can be applied. The resistance in the programmable resistance unit can be constant throughout the array, or implemented in a fixed number of binary-level resistances.

Binary mode operation can allow the simplification of peripheral circuits by reducing the complexity of programmable algorithms that need to be programmed into thresholds in cells, current sources for applying current to rows in the array, and sensing circuits for generating output values.

Fig. 11A shows a schematic circuit diagram of a single programmable resistance unit. Figure 11B can be understood by providing the IV curve (current-voltage curve) through the unit operation in one bit per unit, the binary mode. Units act as current-carrying nodes 600 and 601. The input node 602 is connected to the programmable transistor gate as described above. The resistance of the parallel resistors in the cell is set to a value R _mn , where m corresponds to the column of the cell and n corresponds to the row of the cell.

Figure 11B shows two voltage vs. current curves. The first voltage versus current curve corresponds to the "1" cell weight w _mn , where the cell has a low threshold V _t . The second curve corresponds to the "0" cell weight w _mn , where the cell has a high threshold V _t . When the input value is low and therefore the low V _{t is} greater than the input voltage, the transistor in the cell is turned off and conducts very low current to the cell's binary weight. When the input value is high, the low V _{t is} less than the input voltage, and the input voltage is less than the high V _t . If the weight corresponding to the low V _t cell is “1”, the transistor in the cell is turned on, and if the high V _t cell The weight of is "0", the transistor in the cell is cut off.

When the transistor is turned off, a larger voltage drop V _dLg dominated by the voltage drop caused by the current flowing through the resistance I*R _mn is induced. When the transistor is turned on, the smaller voltage drop V _dSm dominated by the voltage drop caused by the current flowing through the transistor channel is induced, which can be regarded as a smaller voltage drop V _dSm close to 0V caused by the current through the transistor channel Is governed by the voltage drop. This relationship is illustrated by Table 1 below.

The binary operation can be extended to the variable resistance unit string circuit shown in FIG. In Figure 12, three cells are depicted on a single string in an n-row array. This row receives the fixed current I _n and the input values X ₁ to X ₃ on each column. The voltage drop in the row depends on the weights W _1n , W _2n and W _3n of the cells in the row and the input values. In this example, three independent units are used to implement the three terms X _i W _{i of the} product sum operation i from 1 to 3 to generate the voltage V _n representing the sum.

The three input variables shown in the first row and the three potential weights shown in the second column of the table, and assuming a fixed current and fixed resistance value for each cell, the voltage drop V _n in the row The change can be seen in Table 2 (assuming that V _{dSm is} close to (“~”) at zero).

By setting the sensing reference voltage based on these four V _n levels, the voltage across the row can be converted to a digital output between 0 and 3, as shown in Table 3 below.

As the number of columns and cell rows providing unique inputs increases, the array can produce a composite product sum that depends on the "binary" operation of a single programmable resistance cell (ie, programming the transistor to a low or high threshold).

In some embodiments, multi-bit binary weights may be stored in some or all cells in the array to increase the further resolution of the programmable weights of the cells.

FIG. 13 is a block diagram of a sensing circuit that can be used with voltage sensing as described above with a variable resistance cell array arranged in a product-sum operation. The sensing circuit in this example includes a sense amplifier 650 implemented in an example using an operational amplifier or other types of comparators. The input of the sense amplifier 650 includes the voltage v _n on line 652 and the reference voltage V _ref . The voltage v _n is generated on the selected line and can be transmitted through the buffer 651. The buffer 651 may be implemented in an example of unity gain of an operational amplifier or a voltage of a voltage amplifier. The reference voltage V _ref on line 652 is provided by a reference voltage circuit 655 configured to pass a set of reference voltages corresponding to the voltage levels distinguished by the sense amplifier 650 in response to the sequence signal on line 656 sequence. The reference voltage circuit 655 may receive the input voltages V _max and V _min , and the reference voltage circuit 655 may decide that the minimum and maximum voltages generated on the line 652 are the reference voltage V _ref .

Fig. 13A is a revelation diagram of the sensing operation. The specific voltages V _max and V _{min of the} circuit of FIG. 14 can generate a reference voltage having a sensing range as shown in the graph in multiple stages. In the array generated on the selected row voltage level Vn may fall within the sensing range, the voltage V _n has a voltage different from the voltage V _min of. The sensing circuit determines the level of the voltage V _n . In this case, the voltage V _{n is} higher than the respective reference voltages V ₁ to V ₅ and lower than the reference voltage V ₆ . Therefore, the voltage value V _n corresponding to the reference voltage V ₆ can be specified.

The output of the sense amplifier 650 includes signal sequencing corresponding to the input reference voltage level. These signals may be stored in a temporary register 660, which is provided to an arithmetic logic unit 661 or other similar general-purpose processor, where the arithmetic operation may further perform a product-sum operation. For example, based on how the programmable resistance cell array discussed below is configured to produce The output on multiple rows of the array can be combined for the purpose of generating a single item of the product sum operation.

Fig. 14 is a block diagram of a reference voltage circuit that can be used with the sense amplifier device arranged as in Fig. 13. In FIG. 14, a reference row or a plurality of reference rows 665 in the programmable resistance cell array, or using a cell structure such as those applied in the array, can be arranged to provide one or both of the voltages V _max and V _min . The voltages V _max and V _{min of} this example are applied to a resistive voltage divider 666 that generates multiple reference voltage levels at the nodes between the resistors in the resistive voltage divider 666. The node responsive to the reference voltage level is coupled to the selector 667. A selector 667 coupled to the sense amplifier 650 in the configuration of FIG. 13 is responsive to the sequence signal on line 656 to provide a sequence of reference voltages V _ref on line 652.

FIG. 15 shows a configuration of the reference line configured for the purpose of generating the voltage V _min , which can be used for the purpose of generating the reference voltage in the sensing circuit as described in the reference of FIGS. 13 and 14. In this example, three unit operation string lines 680 on n rows are configured for product-sum operation, where the unit has inputs X ₁ to X ₃ and weights W _1n , W _2n and W _3n . The weight is programmed into the operation string circuit 680 according to the product sum operation term to be executed. The voltage generated by the current I _n flowing through the string line is expressed as V _n .

The row reference string line 681 is implemented in an array. The row reference string line 681 uses three cells, which can have electrical characteristics matching those of the three cells used in the operation string line 680. In order to generate the voltage V _min , the line reference string line 681 is represented as W _1ref , and the cell weights of W _2ref and W _3ref are both set to values corresponding to the low threshold state (“1” in this case). The inputs of the cells in the row reference string line 681 are tied together and are coupled to the voltage V _ON during operation, so that all the cells in the row reference string line 681 are turned on, and a small voltage drop V _{dSm is generated} . Therefore, in this example, the voltage V _{min is} approximately equal to 3*V _dSm , or three times the small voltage drop of the unit cell used in the operation string circuit 680. Table 4 below shows an example of the operation of the weight configuration (calculation row) and reference row for specific input and operation string lines.

In an embodiment where the reference string circuit is only used to generate V _min , the value V _max for the reference voltage circuit can be set to a sufficiently high value to provide a good operating range for the device. The example shown in FIG. 15 is based on a string circuit including three variable resistance units.

In the embodiments of the present technology, the variable resistance unit may be implemented in a large-scale array using NAND-like technology. Therefore, any particular row unit coupled into the string line may have, for example, 16, 32, 64 or more units. In any particular product-sum operation configuration, fewer than all cells in a particular row can be used.

FIG. 16 shows an example configuration of the operation string line 690 including the operation line n and the reference string line 691 in the operation line having a plurality of unused cells in the area 692 on the operation line and the reference line. In this example, the reference line is configured for the purpose of generating the voltage V _min , which can be used for the purpose of generating the reference voltage in the sensing circuit as described in the reference of FIGS. 13 and 14.

In the example shown, the three unit operation string lines 690 on operation line n are configured for product-sum operation, where the units on operation string line 690 have inputs X ₁ to X ₃ and weights W _1n , W _2n and W _3n . These weights are programmed into the operation string circuit 690 according to the product sum operation term to be executed. The unused cells on operation line n are specific inputs Y ₁ and Y ₂ and weights W _4n and W _5n . The voltage generated by the current I _n flowing through the string line is expressed as V _n . The inputs Y ₁ and Y ₂ and the weights W _4n and W _5n are configured so that the unused cells in the operation row n are turned on during the product-sum operation.

The reference string line 691 is implemented in an array or a reference array, and the reference string line 691 using three cells in the reference row may have electrical characteristics matching those of the three cells used in the operation string line 690. Unused cells including reference string line 691 on the reference line have weights W _4ref and W _5ref . In order to generate the voltage V _min , the unit weights in the reference string line 691 are expressed as W _1ref , W _2ref and W _3ref , and the unit weights with weights W _4ref and W _5ref in the unused portion of the row are set to correspond to low The value of the threshold state ("1" in this case). The resistance in the cell of the reference string line 691 in the unused portion of the row in the region 692 on the reference row may have a fixed value R. The resistance matching value R is for the cell in the operation string line 690 and the cell value R for the region 692 on the reference line in the same line is the operation string line 690. During operation, the cell inputs of the reference string line 691 including unused cells are tied together and coupled to the voltage V _ON , so that all cells in the row including the reference string line 691 are turned on, and a small voltage drop V _{dSm is generated} . Therefore, the voltage V _min with five cells in the string line of this example is approximately equal to 5*V _dSm , or five times the small voltage drop of the unit cell used in the string line 680. As there are more units in the string line, the V _min value will shift accordingly.

Table 5 below shows an example of the operation of the weight configuration (calculation line) and reference line for the specific input and operation string lines configured in FIG. 16.

Form 5

FIG. 17 shows an example configuration in which both voltages V _min and V _max are generated. In this configuration, the operation string line 700 in the operation row n includes three units as in the examples of FIGS. 15 and 16. Therefore, the operation line n is configured in a product-sum operation, in which the cells in the operation string line 700 have inputs X1 to X3 and weights W _1n , W _2n and W _3n . The weight is programmed into the operation string circuit 700 according to the product sum operation term to be executed. Unused cells on operation line n are represented as inputs Y1 and Y2 and weights W _4n and W _5n . The voltage generated by the current I _n flowing through the string line is expressed as V _n . The inputs Y1 and Y2 and the weights W _4n and W _5n are configured to turn on the unused cells in the operation row n during the product-sum operation.

和

。為了產生電壓V_min，參考串線路701中的單元權重表示為

、

和

，以及在行的未使用部分中具有權重

和

的未使用單元的權重都被設定為對應於低閾值狀態的數值(在這種情況下“1”)。在參考串線路701的單元和行的未使用部分中的電阻可以具有一固定值R。該電阻匹配數值R於操作串線路700中的單元以及在陣列區域703的單元 數值R是操作行n。在操作期間的V_min參考行中包含參考串線路701和未使用單元的單元輸入被綁在一起並且耦接到電壓V_ON，使得在V_min參考行中包括參考串線路701的所有單元都導通，並假設I_ref等於I_n，以產生小電壓降V_dSm。因此，在該範例的串線路中具有五個單元的電壓V_min約等於5 * V_dSm，或是操作串線路700中使用的單位單元之小電壓降的五倍。隨著串線路中有更多單元，V_min值將相應地轉移。 The V _min reference line in the array area 703 includes a reference string line 701 and unused cells. The reference string line 701 contains electrical characteristics that can be matched to those three units used in operating the string line 700. Unused cells on V _min reference line include reference string line 691 weight

with

. To generate the voltage V _min , the unit weight in the reference string line 701 is expressed as

,

with

, And have weight in the unused portion of the row

with

The weights of unused cells are all set to the value corresponding to the low threshold state ("1" in this case). The resistance in the unused portions of the cells and rows of the reference string line 701 may have a fixed value R. The resistance matching value R is for the cell in the operation string line 700 and the cell value R in the array area 703 is the operation line n. The cell inputs containing the reference string line 701 and unused cells in the V _min reference line during operation are tied together and coupled to the voltage V _ON so that all cells including the reference string line 701 in the V _min reference line are turned on , and assuming that I _ref equal to I _n, to generate a small voltage drop V _dSm. Therefore, the voltage V _min with five cells in the string circuit of this example is approximately equal to 5*V _dSm , or five times the small voltage drop of the unit cells used in the string circuit 700. As there are more units in the string line, the V _min value will shift accordingly.

和

。為了產生電壓V_max，參考串線路702中的單元權重表示為

、

和

，以及在V_max參考行的未使用部分中具有權重W4_Href和W5_Href的未使用單元的權重在V_min行中都被設定為對應於高閾值狀態的數值(在這種情況下“0”)。在參考串線路701的單元和行的未使用部分中的電阻可以具有一固定值R。該電阻匹配數值R於操作串線路700中的單元以及在陣列區域703的單元數值R是操作行n。在操作期間V_max參考行中包含參考串線路702的單元輸入被綁在一起並且耦接到電壓V_OFF，以及未使用部分耦接到電壓V_ON，使得在行的三個單元中包括V_max參考串線路701的電晶體都導通，並假設I_ref等於I_n，以產生大電壓降V_dLg。因此，在此範例的串線路中具有五個單元的電壓V_max約等於3 * V_dLg，或是操作串線路700中使用的單位單元之大電壓降的三倍。隨著串線路中有更多單元，V_max值將相應地轉移。 The V _max reference line in the array area 703 includes the reference string line 702 and unused cells. The reference string line 702 includes electrical characteristics that can be matched to those three units used in operating the string line 700. The unused unit weights of the reference string line 702 on the V _max reference line

with

. To generate the voltage V _max , the unit weight in the reference string line 702 is expressed as

,

with

, And the weights of unused cells with weights W4 _Href and W5 _Href in the unused portion of the V _max reference line are set to values corresponding to the high threshold state in the V _min line (in this case "0" ). The resistance in the unused portions of the cells and rows of the reference string line 701 may have a fixed value R. The resistance matching value R is for the cell in the operation string line 700 and the cell value R in the array area 703 is the operation line n. During operation, the inputs of the cells containing the reference string line 702 in the V _max reference row are tied together and coupled to the voltage V _OFF , and the unused part is coupled to the voltage V _ON , so that V _max is included in the three cells of the row reference crystal string line 701 are turned on, and assuming that I _ref equal to I _n, to generate a large voltage drop _V dLg. Therefore, the voltage V _max with five cells in the string circuit in this example is approximately equal to 3*V _dLg , or three times the large voltage drop of the unit cell used in the string circuit 700. As there are more cells in the string, the V _max value will shift accordingly.

Table 6 below shows the specific input and operation strings for the configuration in Figure 17 Example of operation of line weight configuration (calculation line) and reference line.

In the embodiments described with reference to FIGS. 12 and 15-17, the programmable resistance cell array is configured as a functional group with an input X _i and includes a member cell, and each cell in the operation row is implemented with one bit binary metadata item weights W _{i X i W i, X i W} i is determined by the threshold of the programmable threshold transistor unit. The resistance R of the resistor in the cell and the current In in the string line are constant.

In some embodiments, the programmable resistance cell array may be configured as a functional group with one input and multiple members to implement the product sum operation X _i W _i , where the The weight W _{i of} a single bit value may be a value other than a binary “0” or “1”, for example, a multi-bit binary value.

Figures 18-22 illustrate some examples of functional groups that implement multi-bit binary values Configuration.

Figure 18 illustrates the inclusion of three member cell functional groups on a single string in n rows of the array. This row receives a fixed current I _n . The input value X _{m is} connected to the transistor gates in the cells in all three columns. In this example, the resistances of the resistors R _1,mn , R _2,mn, and R _3,mn in the three cells in the group are different. Therefore, the resistor R3 has the resistance R, the resistor R2 has the resistance 2*R, and the resistor R1 has the resistance 4*R. Therefore, the weight of the combined function group based on the effective resistance ranging from 0*R (all transistors in the function group turned on) to 7*R (all transistors in the function group turned off) has a three-bit binary Value, ranging from 0 to 7. The product and operation terms implemented using the function group in Figure 18 can be expressed as X _m (W1 * 4R+W2 * 2R+W3 * R). In other embodiments, the unit function group as in the unit of FIG. 18 may have more than three members, and the three members are connected in a row with the common input X _m .

The cell array as discussed above can be configured using logic circuits to implement the product-sum operation, and the cell array as discussed above can be configured using multiple functional groups to form the calculation terms.

Figure 19 shows a functional group of three member cells in an array of three different rows n1, n2, and n3 of the array. Each of the three rows receives a fixed current In. The input value X _{m is} connected to the transistor gate in the cell in the column. In this example, the resistances R _{1 mn} , R _2,mn, and R _3,mn of the resistors in the three cells in the group are different. Therefore, the resistor R3 has the resistance R, the resistor R2 has the resistance 2*R, and the resistor R1 has the resistance 4*R. The voltages V _n1 , V _n2 and V _n3 generated in each row are summed in the peripheral circuit to provide a sum output term.

The product and operation terms implemented using the functional group of FIG. 19 can be expressed as X _m (W1 * I4R+W2 * I2R+W3 * IR), which has rows that generate a part of the voltage of the representative term. Therefore, the weight of the combined function group based on a voltage ranging from 0*IR (all transistors in the function group turned on) to 7*IR (all transistors in the function group turned off) has a three-bit binary value , Ranging from 0 to 7.

The peripheral circuit configured to perform the sum may include an analog sum amplifier or digital logic. In one example, the voltage on each row can be sensed in sequence, and the result of each sensing step added to the arithmetic logic is shown in the example shown in FIG. 13.

In other embodiments, the unit function group as in the array of FIG. 19 may have more than three members, and the three members are connected in a row with the common input _Xm .

Figure 20 shows a functional group including three member cells in an array on three different rows n1, n2, and n3 of the array. The input value X _{m is} connected to the transistor gate in the cell in the column. In this example, the resistances R _{1 mn} , R _2,mn, and R _3,mn of the resistors in the three cells in the group are the same, and each of the three rows receives a different fixed current I _n . Therefore, the current source provides I ₃ to row 3 with current I, the current source provides I ₂ to row 2 with current 2*I, and the current source provides I ₁ to row 1 with current 4*I. The voltages V _n1 , V _n2 and V _n3 generated in the rows of the function group are summed to the peripheral circuit to provide a sum output term. Therefore, the combined function group weights generated based on outputs ranging from 0*IR (all transistors in the function group turned on) to 7*IR (all transistors in the function group turned off) have a three-bit binary value , Ranging from 0 to 7.

The product sum operation term implemented using the function group of FIG. 20 can be expressed as X _m (W1 * 4IR+W2 * 2IR+W3 * IR), which has rows that generate a part of the voltage of the representative term.

The peripheral circuit configured to perform the sum may include an analog sum amplifier or digital logic. In one example, the voltage on each row can be sensed in sequence and added to the arithmetic The result of each sensing step in the logic is the example shown in Figure 13.

In other embodiments, the unit function group as in the array of FIG. 20 may have more than three members, and the three members are connected in a row with the common input _Xm .

Figure 21 shows a functional group including three member cells in an array on three different rows n1, n2, and n3 of the array. The input value X _{m is} connected to the transistor gate in the cell in the column. In this example, the resistances R _{1 mn} , R _2,mn and R _3,mn of the resistors in the three units in the group are the same, each of the three rows receives a different fixed current I _n , in the function The voltages _Vn1 , _Vn2, and _Vn3 generated in the rows of the group are divided by 4, 2, and 1, respectively, and then summed to the peripheral circuit to provide a summed output term. Therefore, the combined function group weights generated based on outputs ranging from 0*IR (all transistors in the function group turned on) to 7*IR (all transistors in the function group turned off) have a three-bit binary value , Ranging from 0 to 7.

The product and operation terms implemented using the functional group of FIG. 21 can be expressed as X _m (W1 * 4IR+W2 * 2IR+W3 * IR), which has rows that generate voltages divided into peripheral circuits to represent a part of the terms.

The peripheral circuit configured to perform the sum may include an analog sum amplifier or digital logic. In one example, the voltage on each row can be sensed in sequence, and the result of each sensing step added to the arithmetic logic is shown in the example shown in FIG. 13.

In other embodiments, the unit function group as in the array of FIG. 21 may have more than three members, and the three members are connected in a row with the common input _Xm .

FIG. 22 shows the functional group of two member cells contained in one array of two different rows n1 and n2 of the array and two member cells of the second column of the array. The input value X _{m is} connected to the transistor gates in all units of the two columns of the function group. In this example, the resistances R _{1 mn} , R _2,mn , R _3,mn and R _4,mn of the resistors in the four cells in the group are different. Therefore, resistors R3 and R4 have resistance R, and resistors R1 and R2 have resistance 4*R. Each of the two rows receives a different fixed current I _n . Therefore, the current source provides I ₂ to row 2 with current I, and the current source provides I ₁ to row 1 with current 2*I. The voltages V _n1 and V _n2 generated in the two rows of the function group are summed in the peripheral circuit to provide a sum output item.

4*I*R)，其具有產生代表項的一部分電壓之各行。因此，依據從0 *IR(功能組中的所有電晶體導通)至15 *IR(功能組中的所有電晶體截止)不等的輸出所產生的組合之功能組權重具有一個四位元二進制值，範圍從0到15。 The product and operation terms implemented using the function group in Figure 22 can be expressed as X _m (W1*2I*4R+W2*I*4R+W3*2I*R+W

4*I*R), which has rows that generate a portion of the voltage representing the term. Therefore, the combined function group weights generated from outputs ranging from 0*IR (all transistors in the function group turned on) to 15*IR (all transistors in the function group turned off) have a four-bit binary value , Ranging from 0 to 15.

The peripheral circuit configured to perform the sum may include an analog sum amplifier or digital logic. In one example, the voltage on each row can be sensed in sequence, and the result of each sensing step added to the arithmetic logic is shown in the example shown in FIG. 13.

In other embodiments, as shown in FIG. 22, the functional group of the cells in the array may have more than three members, and the functional group of the cells and the common input X _{m are} connected in a row.

Other functional group configurations can also be used.

A huge array of programmable resistance cells can be configured between operations to perform complex product sum operations of various functions with sum terms, as required for the execution of each calculation. In addition, the coefficient of the sum term (that is, the weight) can be set in the transistor of the cell in a non-volatile form, and the coefficient of the sum term is changed by performing the required programming and erasing operations as in each calculation.

FIG. 23 is a simplified chip block diagram of an integrated circuit 901, which includes a product and an array with voltage sensing, and as shown in FIGS. 5 and 6 and FIGS. 10A/10B The hidden channel unit shown is configured as a neuromorphic memory array 960.

The word line driver 940 is coupled to a plurality of word lines 945. The driver includes a digital analog converter that generates an input variable x(i) for each selected line as in some embodiments, or in the alternative, a binary word line driver can be applied to the binary input. The row decoder 970 is coupled to one or more serial cell string lines arranged in a row in the neuromorphic memory array 960 via line 965 for selecting the reading product and data string lines and writing the parameter data to Neuromorphic memory array 960. The address from the control logic (controller) 910 on the bus 930 is provided to the row decoder 970 and the word line driver 940. The voltage sense sense amplifier is coupled to the row decoder via line 975, and the voltage sense amplifier is sequentially coupled to the buffer circuit 980. Applying a load current I _n current source is coupled to the sensing circuit. The programming buffer may be included in the sense amplifier in the buffer circuit 980 to store the programming data in the two-level or multi-level programming of the programming threshold transistor in the cell. In addition, the control logic 910 may include circuitry for selectively using programming and disabling string line voltages in the array in response to programming data values in the programming buffer.

The sensed data from the sense amplifier is provided to the data buffer 990 via the second data line 985, and the data buffer 990 is sequentially coupled to the input/output circuit 991 via the data path 993. The sense amplifier may include an operational amplifier configured to apply unity gain or a desired gain level, and provide an analog signal to digital analog converter or other signal processing or signal routing circuit. Additional arithmetic units and routing circuits can be included to provide the arrangement of multi-layer cell strings in neuromorphic circuits.

In addition, an arithmetic unit and a routing circuit may be included to provide a serial line layer arrangement in the matrix multiplication unit.

The input/output circuit 991 drives data to an external destination of the integrated circuit 901. Input/output data and control signals are moved via the data bus 905 to the input/output circuit 991, control logic 910, and input/output ports on the integrated circuit 901 or other internal data sources or external to the integrated circuit 901, such as a general-purpose processor Or a dedicated application circuit, or a module that provides the system chip function supported by the neuromorphic memory array 960.

In the example shown in FIG. 23, the control logic 910 using the bias configuration state machine controls the application of the supply voltage generated or provided by the voltage supply or the supply at block 920 via the voltage source for product and read Fetch operations, as well as parameter writing operations that set parameters, such as the cell weights represented by charge trap levels including charge trapping cells and floating gate cells, erase, verify, and program bias. The control logic 910 is coupled to the data buffer 990 and the neuromorphic memory array 960.

The control logic 910 can be implemented using dedicated logic circuits known in the art. In alternative embodiments, the control logic includes a general-purpose processor, and the control logic may be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In other embodiments, a combination of dedicated logic circuits and general-purpose processors may be used for the implementation of control logic.

24-26 show the configuration of the system 1000, which includes a memory array 1002 and a product and accelerator array 1001 interconnected using a data path controller 1003. The product and accelerator array 1001 includes a programmable resistance cell array according to any of the embodiments described above. The memory array may include a NAND flash array, an SRAM array, a DRAM array, a NOR flash array, or other types of memory that can be used in coordination with the product and accelerator array 1001.

The system can receive input/output data from outside the system as shown in Figure 24 and route the data to the memory array. The data may include information for configuring one or more products The configuration data of the unit function group of the sum operation item, the weight of the function group used for operation in the array, and the input value used for the product and operation.

As shown in FIG. 25, data from the memory array 1002 can be transferred to the product and accelerator array 1001, which can be controlled using the direct data path used by the data path controller 1003. Alternatively, the data path through the data path controller 1003 can be used to transfer data from the memory array 1002 to the product and accelerator array 1001, as applicable to a particular implementation.

As shown in FIG. 26, the output data from the product accelerator array can be applied to the input and output data paths of the system 1000 through the data path controller 1003. The input and output data path of the system 1000 may be coupled to a processing unit configured to calculate weights to provide input and utilize the output of the product accelerator array.

In addition, the output data from the product accelerator array 1001 can be routed back to the memory array 1002 through the data path controller 1003 for iterative product and operation.

In some embodiments, the system 1000 including memory, product and accelerator arrays, and data path logic may be implemented in a single integrated circuit. In addition, the system 1000 may include the same or different integrated circuits, arithmetic logic units, digital signal processors, general-purpose CPUs, state machines, and the use of similar product and accelerator arrays 1001 configured during the execution of computer processing.

A method of using a programmable resistance cell array according to any of the embodiments described herein can be performed using the system as shown in Figures 24-26, using logic implemented on the same integrated circuit, coupled to the integrated circuit, or performing configuration The two of the steps are combined, in which the cell function groups with respective weights in the array are programmed, as well as the operation steps, and the array is used to generate product and data.

A method for operating an array of variable resistance cells to generate product and data includes programming a programmable threshold transistor having a threshold value corresponding to a weighting factor value of the corresponding cell in the array; selectively applying input to column cells in the array , Apply current to one of the rows in the array corresponding to the row of cells; and sense the voltage on one or more rows of cells in the array.

This method may include configuring the cells in the array to include one or more functional cell groups; wherein the functional groups implement representative products and function terms. Each functional group can receive a corresponding input item and can be programmed with weights that are a function of programmable thresholds for one or more functional groups of the functional group. The functional groups can be configured in various ways, such as the references in Figures 18-22 above. In this way, a programmable resistance unit having a weight configured to use a one-bit binary mode as an individual unit in the array can be configured as a functional group having a multi-bit weight, and can be configured to have a multi-bit weight Functional group of weights. Multi-bit weights can be configured in the unit functional group using resistors with different resistances, using different current levels during sensing on different rows in the functional group, and using arithmetic logic to combine in the functional group Voltages sensed on respective rows with different weights, and other methods as described herein.

Furthermore, in some embodiments, the system may be operated to use a reference row unit to generate a row reference voltage, or a low row reference voltage and a high row reference voltage are suitable for a particular implementation. The method may include generating a sensed reference voltage as a function of one or more row reference voltages. The sensing operation may include comparing the voltage on the selected row cell with the sensing reference voltage to produce an output that represents the voltage level on the selected row.

Although the invention has been disclosed by reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended to be illustrative and not limiting. It is expected that those skilled in the art will easily think of modifications and combinations, which will be within the spirit of the invention and the appended claims In the range.

12‧‧‧Programmable threshold transistor

14‧‧‧Resistance

21, 22, 23, 24 ‧‧‧ current source

26‧‧‧Ground

Claims (10)

A semiconductor element includes a variable resistance cell array disposed in a vertical NAND-like string line (String), the variable resistance cell array has a plurality of variable resistance cells, and each of the variable resistance cell arrays The variable resistance unit includes a programmable threshold transistor and a first resistor connected in parallel; wherein a variable resistance of each of the variable resistance units is a voltage applied to a control gate of each of the variable resistance units 2. A threshold of the programmable threshold transistor, a current of each variable resistance unit and a function of the first resistance. The semiconductor device as described in item 1 of the patent application range, wherein the variable resistance cell array includes a plurality of NAND-like string circuits of the variable resistance cells connected in series. The semiconductor device as described in item 2 of the patent application scope includes: a plurality of word lines, the NAND-like string lines coupled to the variable resistance unit connected in series; and a plurality of word line drivers, connected to the The word line is used to apply a variable gate voltage to the programmable threshold transistors in the variable resistance cells. The semiconductor device as described in item 1 of the patent application range, wherein the programmable threshold transistor in each of the variable resistance units includes a floating gate charge trapping storage transistor, and in each of the variable resistance units The first resistor includes a buried implant resistor in the floating gate charge trapping storage transistor. The semiconductor device as described in item 1 of the patent application range, wherein the programmable threshold transistor in each of the variable resistance units includes a dielectric charge trapping storage transistor, and the The first resistor includes a buried implant resistor in the dielectric charge trapping storage transistor. The semiconductor device as described in item 1 of the patent application scope includes: a sense amplifier connected to the variable resistance cell array in response to an applied current and the variable resistances in the variable resistance cell array A voltage generated by a sum of cells. A semiconductor element includes an array of a plurality of variable resistance units arranged in a vertical NAND-like string line, each of the variable resistance units in the array includes a programmable threshold transistor and a resistor in parallel, wherein the array The programmable threshold transistor of each of the variable resistance units in includes a separate gate transistor; Wherein a variable resistance of each of the variable resistance units is a voltage applied to a control gate of each of the variable resistance units, a threshold of the programmable threshold transistor, and each of the variable resistance units A function of current and resistance. A semiconductor element includes: a plurality of vertical string lines, the vertical string lines having a plurality of variable resistance units; each variable resistance unit in the vertical string lines has a first current-carrying node, a first Two current-carrying nodes and a control terminal, and includes a programmable threshold transistor and a resistor connected in parallel to the first current-carrying node and the second current-carrying node, the programmable threshold transistor has a connection to the control terminal A gate; wherein: the variable resistance of each of the variable resistance units in the vertical string lines is a function of a voltage applied to the gate, the threshold of the programmable threshold transistor, and the resistance. The semiconductor device as described in item 8 of the patent application range, wherein the resistance in each of the variable resistance units includes a buried implanted resistance in a charge trapping storage transistor. The semiconductor device as described in item 9 of the patent application includes a circuit for programming the threshold of the charge trapping storage transistor having multiple stages.

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