TWI678814B - Solar cell and method for fabricating the same - Google Patents

Abstract

A solar cell and a manufacturing method thereof. The solar cell includes a silicon substrate, a passivation stack layer, a barrier layer, a first electrode, and a second electrode. The silicon substrate includes a first surface and a second surface opposite to each other, and the first surface is a light-facing surface. The passivation stack layer is disposed on the second surface of the silicon substrate. The passivation stack layer has a plurality of contact holes, and each contact hole penetrates the passivation stack layer. The barrier layer covers the sidewall of each contact hole. The first electrode is disposed on the first surface of the silicon substrate. The second electrode is disposed on the passivation stack and extends into the contact holes to directly contact the silicon substrate. In each contact hole, the barrier layer is located between the second electrode and the passivation stack.

Description

Solar cell and manufacturing method thereof

The invention relates to a solar cell and a manufacturing method thereof, and in particular to a solar cell capable of improving photoelectric conversion efficiency and a manufacturing method thereof.

Solar cells, also called photovoltaic cells, are a device that converts solar energy into electricity. Solar cells usually form a p-n junction near the surface of a semiconductor substrate. When sunlight is irradiated on a solar cell, the semiconductor substrate can generate electron-hole pairs due to the role of light energy. These electron-holes are affected by a built-in electric field formed at the P-N junction, and are gathered at both ends of the negative electrode and the positive electrode, respectively, so that a voltage is generated at both ends of the solar cell. At this time, if the two ends of the solar cell are connected with an external electrode, electric energy can be output.

However, solar cells still suffer from poor photoelectric conversion efficiency. Therefore, how to improve the photoelectric conversion efficiency of solar cells has become one of the development directions of the current industry.

The invention relates to a solar cell and a manufacturing method thereof, which can improve the photoelectric conversion efficiency of the solar cell.

According to an aspect of the present invention, a solar cell is provided. The solar cell includes a silicon substrate, a passivation stack layer, a barrier layer, a first electrode, and a second electrode. The silicon substrate includes a first surface and a second surface opposite to each other, and the first surface is a light-facing surface. The passivation stack layer is disposed on the second surface of the silicon substrate. The passivation stack layer has a plurality of contact holes, and each contact hole penetrates the passivation stack layer. The barrier layer covers the sidewall of each contact hole. The first electrode is disposed on the first surface of the silicon substrate. The second electrode is disposed on the passivation stack and extends into the contact holes to directly contact the silicon substrate. In each contact hole, the barrier layer is located between the second electrode and the passivation stack.

According to another aspect of the present invention, a method for manufacturing a solar cell is provided. The method includes the following steps. A silicon substrate is provided. The silicon substrate includes a first surface and a second surface opposite to each other. The first surface is a light-facing surface. A passivation stack is formed on the second surface of the silicon substrate. A plurality of contact holes are formed through the passivation stack. A barrier layer is formed on the side walls and the end faces of the contact holes. The barrier layer on the end face of each contact hole is removed. A first electrode is formed on the first surface of the silicon substrate. A second electrode is formed on the passivation stack, and the second electrode extends into the contact holes to directly contact the silicon substrate. In each contact hole, the barrier layer is located between the second electrode and the passivation stack.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

1, 2‧‧‧ solar cells

10, 20‧‧‧ Silicon substrate

10S1, 20S1‧‧‧First surface

10S2, 20S2‧‧‧Second surface

11, 21‧‧‧ Emitter layer

12, 22‧‧‧ passivation stack

121, 221‧‧‧ tunneling layer

122, 222‧‧‧ Patch

123, 223‧‧‧ negatively charged layer

124, 224‧‧‧ protective layer

12B, 22B‧‧‧End face of contact hole

12H, 22H‧‧‧ contact hole

12L, 22L‧‧‧ sidewall of contact hole

13, 23‧‧‧ passivation layer

14, 24‧‧‧ Bund layer

16, 26‧‧‧ the first electrode

16’‧‧‧metal glue

18, 28‧‧‧Second electrode

18’‧‧‧metal glue

19, 29‧‧‧ back electric field area

FIG. 1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention.

Figures 2A to 2I illustrate a manufacturing embodiment of a solar cell according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a solar cell according to another embodiment of the present invention.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same or similar reference numerals indicate the same or similar elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on," "connected to," or "contacting" another element, it can be directly on or in contact with another element. An element connection, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly contacting" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" can mean that there are other components between the two components.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, unless the content clearly indicates, Otherwise the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one". "Or" means "and / or". The term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "including" and / or "including" specify the stated features, regions, wholes, steps, operations, presence of elements and / or components, but do not exclude one or more The presence or addition of other features, areas as a whole, steps, operations, elements, components, and / or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "down" may include orientations of "down" and "up", depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" may include orientations above and below.

As used herein, "about," "approximately," or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurements and A specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. again In addition, "about," "approximately," or "substantially" used herein may select a more acceptable range of deviations or standard deviations based on optical properties, etching properties, or other properties, and all properties may not be applied without one standard deviation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic views of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the particular shape of the area as shown herein, but include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be round. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Please refer to FIG. 1, which is a schematic cross-sectional view of a solar cell 1 according to an embodiment of the present invention. The solar cell 1 includes a silicon substrate 10. The silicon substrate 10 may be a single crystal silicon substrate, an amorphous silicon substrate, a polycrystalline silicon substrate, or other silicon substrates having different lattice arrangements. In the embodiment, the silicon substrate 10 may be formed of a silicon wafer with an n-type or p-type substrate, and the present invention does not limit the type of doping of the silicon substrate 10.

The silicon substrate 10 includes a first surface 10S1 and a second surface 10S2 opposite to each other. The first surface 10S1 is a light-facing surface, which can be defined as the front surface of the solar cell 1 as the main light-receiving surface. The first surface 10S1 may have a textured surface, or may have pyramid structures of different sizes, as shown in the jagged surface in FIG. 1 to increase the probability of secondary reflection of incident light and avoid incident light. It returns only after the first reflection, thereby increasing the amount of incident light.

The second surface 10S2 may be defined as a back surface of the solar cell 1. In the embodiment of FIG. 1, the second surface 10S2 is a backlight surface, so the solar cell 1 is a single-sided light-receiving solar cell. However, the present invention is not limited to this.

The solar cell 1 may include an emitter layer 11, a passivation layer 13 and a first electrode 16. The emitter layer 11 is formed on the first surface 10S1 of the silicon substrate 10 to form a pn junction between the emitter layer 11 and the silicon substrate 10, thereby establishing a built-in electric field to separate the electron-hole pair . For example, taking a silicon wafer with a p-type substrate as an example, an n-type (n +) emitter layer 11 can be formed on the first surface 10S1.

The passivation layer 13 is formed on the emitter layer 11, and is formed conformally on the emitter layer 11, for example. The passivation layer 13 may be a single-layer material structure or a stacked structure including a plurality of different materials. For example, the material of the passivation layer 13 may be silicon oxide (SiOx), silicon nitride (SiNx), a stacked layer thereof, or other suitable materials, which is not limited in the present invention. The passivation layer 13 can be used as an anti-reflection coating (ARC), which can have both passivation and anti-reflection effects to reduce the amount of incident light reflected by the first surface 10S1, so that more light enters the silicon substrate 10, The performance of the solar cell 1 is further improved.

The first electrode 16 is disposed on the first surface 10S1 of the silicon substrate 10. Furthermore, the first electrode 16 may pass through the passivation layer 13 and contact the emitter layer 11 of the first surface 10S1, and then be electrically connected to the emitter layer 11 to collect the electrons separated by the built-in electric field.

The solar cell 1 further includes a passivation stack layer 12 and a second electrode 18. The passivation stack layer 12 is disposed on the second surface 10S2 of the silicon substrate 10. The passivation stack layer 12 may be a stacked structure including multiple layers of different materials to improve the photoelectric conversion efficiency of the solar cell 1.

In the embodiment, the passivation stack layer 12 has a plurality of contact holes 12H, and each contact hole 12H penetrates the passivation stack layer 12. The second electrode 18 is disposed on the passivation stack layer 12 and extends into the contact hole 12H to directly contact the silicon substrate 10 to form a plurality of back electric field regions on the second surface 10S2 of the silicon substrate 10 adjacent to each contact hole 12H. 19 (Back Surface Field, BSF). The second electrode 18 is electrically connected to the back electric field regions 19 through the contact holes 12H.

It is worth mentioning that, in various embodiments, the solar cell 1 further includes a barrier layer 14. The barrier layer 14 covers the side wall 12L of each contact hole 12H. In detail, in each contact hole 12H, the barrier layer 14 is located between the second electrode 18 and the passivation stack layer 12 so as to protect the passivation stack layer 12 and prevent defects in the passivation stack layer 12 from affecting the solar cell 1. Photoelectric conversion efficiency.

In an embodiment, the passivation stack layer 12 may include a tunneling layer 121, a repair layer 122, a negatively charged layer 123, and a protective layer 124. The tunneling layer 121 is disposed on the second surface 10S2 of the silicon substrate 10. The material of the tunneling layer 121 may be The oxide may include, for example, silicon oxide (SiOx). The thickness of the tunneling layer 121 may be about 1 nanometer (nm) to about 2 nanometers, for example, it may be about 1.5 nanometers, so that the tunneling layer 121 has good selectivity, while allowing electrons to pass through, it also reduces its Compound probability of holes.

The repair layer 122 is disposed on the tunneling layer 121. The material of the repair layer 122 may include polycrystalline silicon, such as intrinsic polycrystalline silicon or doped polycrystalline silicon. Since the repair layer 122 is rich in hydrogen ions during the manufacturing process, the hydrogen ions can diffuse to the silicon substrate 10, thereby repairing defects in the silicon substrate 10 and improving the performance of the solar cell 1. In addition, since the repair layer 122 is subjected to a high-temperature (about 500 ° C. to 600 ° C.) polycrystallization process, the repair layer 122 also has good thermal stability.

The negatively-charged layer 123 is disposed on the repair layer 122. The material of the negatively-charged layer 123 may be aluminum oxide (AlOx). After being heat-treated at a high temperature (about 400 ° C. to 450 ° C.), the negatively-charged layer 123 can generate a fixed negative charge, which has a negative electrical property, and promotes the hole to move toward the second electrode 18. Therefore, the interface between the repair layer 122 and the negatively-charged layer 123 can generate a p + electric field directed to the interior of the silicon substrate 10, reducing the chance of recombination of electrons and holes.

The protective layer 124 is disposed on the negatively-charged layer 123. The material of the protective layer 124 may be silicon nitride (SiNx) to protect the negatively-charged layer 123. Further, during the sintering process to form the second electrode 18, the protective layer 124 can protect the negatively-charged layer 123 and ensure that the negatively-charged layer 123 is not destroyed during the formation of the second electrode 18 Structure.

Each contact hole 12H can penetrate the protective layer 124, the negatively charged layer 123, the repair layer 122, and the tunneling layer 121. The barrier layer 14 covers the contact hole 12H. Sidewall 12L. In this way, the second electrode 18 can be isolated from the tunneling layer 121, the repair layer 122, and the negatively-charged layer 123 by the barrier layer 14, thereby preventing the material of the second electrode 18 from diffusing laterally (that is, toward the sidewall 12L) to passivate the stack. The layer 12 is defective.

More clearly, the material of the second electrode 18 may be aluminum, aluminum alloy, other suitable metals, or alloys thereof. During the high-temperature sintering of the solar cell, the aluminum in the second electrode 18 may cause lateral diffusion between the silicon substrate 10, the tunneling layer 121, and / or the repair layer 122, thereby further causing the silicon substrate 10 and the tunneling layer. Defects such as multiple spikes are generated on the interface between 121 and / or repair layer 122, which causes the tunneling layer 121 and / or repair layer 122 to lose their original functions and affects the overall photoelectric conversion efficiency of the solar cell.

Therefore, by providing a barrier layer 14 on the sidewall of each contact hole 12H, the second electrode 18 is isolated from the tunneling layer 121, the repair layer 122, and the negatively charged layer 123, and the material of the second electrode 18 can be prevented from diffusing laterally. It is ensured that the tunneling layer 121 and / or the repairing layer 122 maintain their original functions.

In some embodiments, the material of the barrier layer 14 may be titanium, tantalum, ruthenium, titanium, tantalum, ruthenium, molybdenum, tungsten, indium, copper, or an alloy of any combination of the foregoing materials. Alternatively, the material of the barrier layer 14 may be a carbide, a nitride, a fluoride, an oxide, a silicide, or a compound of the foregoing materials to effectively block the lateral diffusion of the material of the second electrode 18. For example, the material of the barrier layer 14 may be titanium nitride (TiN). The thickness of the barrier layer 14 may be about 1 nanometer to about 50 meters, for example, about 20 nanometers, and it is more effective to protect the tunneling layer 121, the repair layer 122, and / or the negatively charged layer 123 from the second electrode. The material of 18 has spread and invaded. In addition, it passes through the side wall 12L of each contact hole 12H. The provision of the barrier layer 14 can further reduce the contact area between the second electrode 18 and the silicon substrate 10, and prevent the formed back electric field region 19 from being too large and causing the silicon substrate 10 to have too many defects, thereby affecting the photoelectric conversion efficiency of the solar cell 1. .

Figures 2A to 2I illustrate a manufacturing embodiment of a solar cell 1 according to an embodiment of the present invention.

First, referring to FIG. 2A, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface 10S1 and a second surface 10S2 opposite to each other. The first surface 10S1 of the silicon substrate 10 may be a surface having an undulating structure, which may selectively form a roughened surface, or may be surface-treated to form pyramid structures of different sizes.

In this step, the emitter layer 11 may be formed on the first surface 10S1 of the silicon substrate 10 by a diffusion method. For example, on the first surface 10S1 of the silicon substrate 10 having an undulating structure, phosphorus oxychloride (POCl3) can be used to diffuse phosphorus to diffuse phosphorus to perform phosphorus doping to form the emitter layer 11.

Next, a passivation stack layer 12 (labeled in FIG. 2D) is formed on the second surface 10S2 of the silicon substrate 10. Referring to FIG. 2B, in one embodiment, a tunneling layer 121 may be formed on the second surface 10S2 of the silicon substrate 10. For example, a silicon dioxide film can be formed on the second surface 10S2 of the silicon substrate 10. For example, the second surface 10S2 of the silicon substrate 10 is oxidized to form a silicon dioxide film to form the tunneling layer 121.

Referring to FIG. 2C, a repair layer 122 is formed on the tunneling layer 121. For example, an intrinsic polycrystalline silicon or a doped polycrystalline silicon can be formed on the tunneling layer 121 in a deposition manner to form the repair layer 122.

Referring to FIG. 2D, a negatively charged layer 123 is formed on the repair layer 122, and a protective layer 124 is formed on the negatively charged layer 123 to form a passivation stack layer 12. For example, an aluminum oxide film may be formed on the repair layer 122 by deposition to form a negatively charged layer 123; then a silicon nitride film may be formed on the negatively charged layer 123 by deposition to form Protective layer 124.

Please refer to Figure 2E. After the passivation stack layer 12 is formed, a passivation layer 13 is formed on the first surface 10S1 of the silicon substrate 10. For example, a silicon nitride film can be formed on the first surface 10S1 of the silicon substrate 10 by deposition, so that the passivation layer 13 is conformally formed on the emitter layer 11.

Thereafter, as shown in FIG. 2F, a plurality of contact holes 12H penetrating through the passivation stack layer 12 are formed. For example, a plurality of through contact holes 12H can be formed on the passivation stack layer 12 by means of laser ablation. In one embodiment, the contact hole 12H is, for example, a penetrating protective layer 124, a negatively charged layer 123, a repair layer 122, and a tunneling layer 121. Each contact hole 12H includes a side wall 12L and an end surface 12B connected to each other. The end surface 12B can be regarded as the bottom of the contact hole 12H, and the end surface 12B can be formed in the silicon substrate 10.

Next, referring to FIG. 2G, a barrier layer 14 is formed on the sidewall 12L and the end surface 12B of the contact hole 12H. For example, vacuum deposition methods such as plasma-assisted chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering can be used to passivate the stack. A titanium alloy layer is formed on the layer 12 and in the contact hole 12H to form the barrier layer 14. In an embodiment In this case, the barrier layer 14 is formed on the protective layer 124 and covers the sidewall 12L and the end surface 12B of the contact hole 12H.

Then, as shown in FIG. 2H, the barrier layer 14 located on the end surface 12B of each contact hole 12H is removed to expose the end surface 12B of the contact hole 12H. For example, the barrier layer 14 located on the end surface 12B of the contact hole 12H can be removed by using laser ablation, and the barrier layer 14 located on the side wall 12L of the contact hole 12H is left. In other embodiments, the barrier layer 14 on the protective layer 124 may be removed together, leaving only the barrier layer 14 on the side wall 12L of the contact hole 12H.

Referring to FIG. 2I, a metal paste 18 'is coated on the barrier layer 14, and the metal paste 18' extends into the contact hole 12H to directly contact the silicon substrate 10. For example, a metal paste 18 '(for example, aluminum paste) can be applied on the barrier layer 14 by printing (for example, Screen Print), and a metal paste 18' (for example, aluminum paste). It can also flow and fill into the contact hole 12H, and directly contact the silicon substrate 10.

In other embodiments, when the barrier layer 14 on the passivation stack layer 12 is removed in the previous step, a metal paste 18 ′ may be applied on the passivation stack layer 12 (for example, on the protective layer 124). Moreover, the metal glue 18 'extends into the contact hole 12H to directly contact the silicon substrate 10.

In these embodiments, the solar cell 1 is a single-sided light-receiving solar cell, which can be printed on the entire surface of the barrier layer 14 or the entire surface of the passivation stack layer 12 (for example, on a protective layer). On the surface of 124), a whole surface of metal paste 18 '(for example, aluminum paste) is applied.

In this step, a metal paste 16 'may also be coated on the passivation layer 13. For example, a metal paste 16 ′ (such as a silver paste) can be applied on the passivation layer 13 by printing (such as screen printing), such as forming a plurality of straight lines on the passivation layer 13, Fingerprints (eg, silver glue) of geometrical figures such as silver glue, these metal glues 16 '(eg, silver glue) extend in a direction orthogonal to the drawing surface of FIG. 2I.

Then, a heat treatment such as a sintering process is performed, and an annealing treatment is performed at the end to form the solar cell 1 shown in FIG. 1.

Please refer to FIG. 2I and FIG. 1. During the sintering process, the metal paste 16 ′ (for example, silver paste) can pass through the anti-passivation layer 13 to form a metal-semiconductor ohmic contact with the emitter layer 11. To form a first electrode 16. And the metal glue 18 '(for example, aluminum glue) is also sintered at high temperature and metallized, and forms a metal-semiconductor ohmic contact with the silicon substrate 10 (for example, formed between the end surface 12B and the silicon substrate 10) To form a second electrode 18.

During the sintering process, the metal paste 18 '(for example, aluminum paste) can eutecticly react with the silicon substrate 10 through the contact hole 12H to generate, for example, an aluminum-silicon alloy to form a plurality of back electric field regions 19, and the metal The glue 18 ′ (for example, aluminum glue) is further electrically connected to the back electric field region 19. In this process, since the barrier layer 14 covering the sidewall 12L of each contact hole 12H can further reduce the contact area between the metal glue 18 '(for example, aluminum glue) and the silicon substrate 10, the barrier layer 14 can block the metal glue 18' ( For example, aluminum glue) extends along the interface between the passivation stack layer 12 (for example, the tunneling layer 121 and / or the repair layer 122) and the silicon substrate 10. The extension and diffusion make the back electric field region 19 formed to be within the outer diameter range of the contact hole 12H, so as to avoid the range of the back electric field region 19 being too large and causing the silicon substrate 10 to generate excessive defects.

At the same time, the barrier layer 14 can further exert a good shielding effect, and can prevent the metal glue 18 '(for example, aluminum glue) from diffusing to the passivation stack layer 12 (for example, the tunneling layer 121, the repair layer 122, and And / or in the negatively charged layer 123).

The above embodiment is described by taking the single-sided light-receiving solar cell 1 as an example, but the present invention is not limited to this.

Please refer to FIG. 3, which is a schematic cross-sectional view of a solar cell 2 according to another embodiment of the present invention. In FIG. 3, the solar cell 2 is a double-sided light-receiving solar cell, and similar elements are denoted by similar reference numerals. In addition, in this embodiment, the solar cell 2 can be fabricated in a manner similar to that in FIGS. 2A to 2I, and similar process steps are not described herein again.

The solar cell 2 includes a silicon substrate 20. The first surface 20S1 of the silicon substrate 20 is a light-facing surface, which can be defined as the front surface of the solar cell 2 as the main light-receiving surface. The second surface 20S2 of the silicon substrate 20 is also a light-facing surface, which can be defined as the back surface of the solar cell 2 and the light-receiving surface on the back surface. Moreover, the second surface 20S2 is similar to the first surface 20S1, and both have a roughened surface, a pyramid structure of a different size, or a nanostructure of another shape, as shown in the jagged surface in FIG. 3, In order to increase the probability of the secondary reflection of the incident light, to prevent the incident light from returning only after the first reflection, thereby increasing the amount of incident light.

The solar cell 2 may include an emitter layer 21, a passivation layer 23 and a first electrode 26. The emitter layer 21, the passivation layer 23, and the first electrode 26 are disposed on one side of the first surface 20S1 of the silicon substrate 20, and their structures, materials, manufacturing methods, or functions are similar to the emitter layer 11 of the solar cell 1 in FIG. 1 The passivation layer 13 and the first electrode 16 are not repeated here.

The solar cell 1 further includes a passivation stack layer 22 and a second electrode 28. In this embodiment, the number of the second electrodes 28 may be plural. These second electrodes 28 may be arranged in a plurality of geometric shapes such as straight lines and fingers, and extend in a direction orthogonal to the drawing surface of FIG. 3.

The passivation stack layer 22 and the second electrode 28 are disposed on the second surface 20S2 of the silicon substrate 20. In an embodiment, the passivation stack layer 22 may include a tunneling layer 221, a repair layer 222, a negatively charged layer 223, and a protective layer 224, and its structure, material, manufacturing method, or function is similar to that of the solar energy of FIG. The tunneling layer 121, the repairing layer 122, the negatively charged layer 123, and the protective layer 124 of the battery 1 are not described herein again.

Similarly, the solar cell 2 further includes a barrier layer 24 which has a structure, material, manufacturing method, or function similar to the barrier layer 14 of the solar cell 1 in FIG. 1. The passivation stack layer 22 also has a plurality of contact holes 22H, each contact hole 22H penetrates the passivation stack layer 22, and its structure or manufacturing method is similar to the contact hole 12H of the solar cell 1 in FIG. 1. The second electrode 28 is disposed on the passivation stack layer 22 and extends into the contact hole 22H. The barrier layer 24 covers the side wall 22L of each contact hole 22H. In other words, in each contact hole 22H, the barrier layer 24 is located between the second electrode 28 and the passivation stack layer 22 to play a role of protecting the passivation stack layer 22 and avoiding defects in the passivation stack layer 22. And affect the photoelectric conversion efficiency of the solar cell 2. In addition, the end surface 22B of each contact hole 22H is not covered by the barrier layer 24 so that the second electrode 28 extends into the contact hole 22H to directly contact the silicon substrate 20. In this way, a plurality of back electric field regions 29 can be formed on the second surface 20S2 of the silicon substrate 20 adjacent to each contact hole 22H, so that the second electrode 28 is electrically connected to the back electric field regions 29 through the contact holes 22H.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A solar cell includes a silicon substrate including a first surface and a second surface opposite to each other, the first surface being a light-facing surface, an emitter layer disposed on the first surface of the silicon substrate, and a passivation layer. A passivation stack layer disposed on the second surface of the silicon substrate, the passivation stack layer having a plurality of contact holes, each contact hole penetrating the passivation stack layer, wherein the passivation layer The stacked layer further includes: a tunneling layer disposed on the second surface of the silicon substrate; a repair layer disposed on the tunneling layer; a negatively charged layer disposed on the repair layer; and a protective layer Is disposed on the negatively charged layer; a barrier layer covers the side walls of each of the contact holes; a first electrode is disposed on the first surface of the silicon substrate; and a second electrode is disposed on the passivation stack The barrier layer is located between the second electrode and the passivation stack layer in each of the contact holes. The solar cell according to item 1 of the scope of patent application, wherein each of the contact holes penetrates the protective layer, the negatively charged layer, the repair layer, and the tunneling layer, and the second electrode communicates with the barrier layer through the barrier layer. The tunneling layer, the repair layer and the negatively charged layer are isolated. The solar cell according to item 1 of the patent application scope further includes a plurality of back electric field regions located on the second surface of the silicon substrate, wherein the second electrode contacts the back electric field regions through the contact holes. The solar cell according to item 1 of the patent application scope, wherein the second surface is a backlight surface. The solar cell according to item 1 of the patent application scope, wherein the second surface is a light-facing surface, and the solar cell further includes a plurality of the second electrodes. A solar cell includes a silicon substrate including a first surface and a second surface opposite to each other, the first surface being a light-facing surface, an emitter layer disposed on the first surface of the silicon substrate, and a passivation layer. A passivation stack layer disposed on the second surface of the silicon substrate, the passivation stack layer having a plurality of contact holes, each contact hole penetrating the passivation stack layer; a barrier layer Covering the sidewalls of each of the contact holes, wherein the material of the barrier layer is titanium, tantalum, ruthenium, molybdenum, tungsten, indium, copper, the aforementioned alloy, the aforementioned carbide, the aforementioned nitride, the aforementioned fluoride, the aforementioned An oxide, the aforementioned silicide; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the passivation stack layer and extending into the contact holes and the The silicon substrate is in direct contact, and in each of the contact holes, the barrier layer is located between the second electrode and the passivation stack layer. A method for manufacturing a solar cell includes: providing a silicon substrate, the silicon substrate including a first surface and a second surface opposite to each other, the first surface being a light-facing surface; and forming a first surface on the silicon substrate. An emitter layer; forming a passivation layer on the emitter layer; forming a passivation stack layer on the second surface of the silicon substrate, including: forming a tunneling layer on the second surface of the silicon substrate; A repair layer is formed on the tunneling layer; a negatively charged layer is formed on the repaired layer; a protective layer is formed on the negatively charged layer; a plurality of contact holes penetrating the passivation stack layer are formed; Forming a barrier layer on the side wall and the end surface of the hole; removing the barrier layer on the end surface of each of the contact holes; forming a first electrode on the first surface of the silicon substrate; and forming a second layer on the passivation stack layer An electrode, the second electrode extending directly into the contact holes and in direct contact with the silicon substrate, and in each of the contact holes, the barrier layer is located between the second electrode and the passivation stack layer. The method for manufacturing a solar cell according to item 7 of the scope of patent application, wherein in the step of forming the contact holes penetrating the passivation stack layer, the contact holes penetrate the protective layer, the negatively charged layer, and the repair Layer and the tunneling layer; and in the step of forming the second electrode on the passivation stack layer, the second electrode is formed on the protective layer, and the second electrode communicates with the tunneling layer through the barrier layer, The repair layer and the negatively charged layer are isolated. The method for manufacturing a solar cell according to item 7 of the scope of patent application, further comprises: performing a heat treatment to form a plurality of back electric field regions where the second electrode directly contacts the silicon substrate through the contact holes. The method for manufacturing a solar cell according to item 7 of the scope of patent application, wherein the material of the barrier layer is titanium, tantalum, ruthenium, molybdenum, tungsten, indium, copper, carbide, nitride, fluoride, oxide, silicidation Materials, or alloys or compounds of any combination of the foregoing.