TWI676105B - Dram-based storage device and associated data processing method - Google Patents

Abstract

A storage device using DRAM includes: a DRAM and a control circuit. The control circuit is connected to the DRAM. The DRAM includes a buffer and a host access area. The host access area stores data. Every time a predetermined time period passes, the control circuit copies a part of the data from the host access area to the buffer area. When the data in this part is successfully copied to the buffer, the control circuit confirms that the data in the part in the host access area is correct.

Description

Storage device using DRAM and related data processing method

The invention relates to a storage device and a related data processing method, and more particularly to a storage device using a DRAM and a related data processing method.

As we all know, solid state devices (SSDs) have been widely used in various electronic products, such as SD cards, solid-state hard disks, and so on.

Please refer to FIG. 1, which is a schematic diagram of a conventional solid-state storage device. In the computer system 180, the solid-state storage device 100 is connected to the host 150 via an external bus 110. The external bus 110 may be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U bus. .2 busbars and more.

Furthermore, the solid-state storage device 100 includes a control circuit 10, a buffer 30, and a non-volatile memory 20. The control circuit 10 is connected to the non-volatile memory 20 and the buffer 30, and the buffer 30 is a dynamic random access memory (DRAM).

When the solid-state storage device 100 is operating normally, the control circuit 10 may operate according to an instruction issued by the host 150. For example, when the host 150 issues a write command, the control circuit 10 receives the write data from the host 150 and temporarily stores the write data in the buffer 30. After that, the control circuit 10 performs ECC encoding on the write data temporarily stored in the buffer 30 at an appropriate timing, and stores the ECC encoded write data in the non-volatile memory 20.

Alternatively, when a read command is sent from the host 150, the control circuit 10 obtains the read data from the non-volatile memory 20 and performs ECC decoding, and then temporarily stores the read data in the buffer 30 and transfers the read data to the host 150.

Basically, the written data of the host 150 is stored in the non-volatile memory 20. The buffer 30 in the solid-state storage device 100 is only a component used by the control circuit 10 to temporarily store data. That is, the host 150 can only access the data in the non-volatile memory 20, but cannot directly access the data in the buffer 30.

As is known to all, the efficiency of the non-volatile memory 20 during writing and erasing operations is low, resulting in longer data writing time. Therefore, the performance of the solid-state storage device 100 cannot be effectively improved.

The invention relates to a storage device using DRAM. The storage device using DRAM includes: a DRAM, wherein the DRAM includes a buffer area and a host access area, and the host access area stores data; and a control circuit, Connected to the DRAM; wherein each time a predetermined time period elapses, the control circuit copies a part of the data from the host access area to the buffer, and when the part of the data is successfully copied to the buffer, the control circuit confirms the The data in this part of the host access area is correct.

The invention relates to a data processing method for a storage device using DRAM. The storage device using DRAM includes: a control circuit and a DRAM, wherein the DRAM includes a buffer area and a host access area, and the host accesses A piece of data is stored in the area. The data processing method includes the following steps: (a) after a predetermined period of time, the host access area copies a portion of the data to the buffer area; (b) when the portion of the data is successfully copied to In the buffer, confirm that the data in the part of the host access area is correct; (c) When the data in the part is not successfully copied to the buffer, an error occurs in the data in the part where the bit is incorrect Corrective action; (d) when the error correcting action is successful, write the corrected data into the host access area again; and (e) mark the host access area when the error correcting action is unsuccessful The storage location of the data in which the error bit occurs in the data in that part.

In order to have a better understanding of the above and other aspects of the present invention, the embodiments are exemplified below and described in detail with the accompanying drawings as follows.

10, 210‧‧‧ control circuit

20, 220‧‧‧ Non-volatile memory

30‧‧‧ buffer

100‧‧‧ solid state storage device

110‧‧‧External bus

150‧‧‧host

160‧‧‧Backup power

180, 280‧‧‧Computer system

200‧‧‧Storage device using DRAM

230‧‧‧DRAM

212‧‧‧Buffer Zone

214‧‧‧Host Access Area

FIG. 1 is a schematic diagram of a conventional solid-state storage device.

FIG. 2 is a schematic diagram of a storage device using DRAM according to the present invention.

FIG. 3 is a flowchart of a data processing method of the present invention.

In order to improve the performance of conventional storage devices, the present invention proposes a storage device using DRAM and its related data processing method.

Please refer to FIG. 2, which shows a schematic diagram of a storage device using DRAM. In the computer system 280, the storage device 200 using DRAM is connected to the host 150 via an external bus 110, wherein the external bus 110 may be a USB bus, a SATA bus, a PCIe bus, an M.2 bus, or a U. 2 busbars and more.

Furthermore, the storage device 200 using DRAM includes a control circuit 210, a DRAM 230, and a non-volatile memory 220. The control circuit 210 is connected to the non-volatile memory 220 and the DRAM 230. The DRAM 230 includes a buffer area 212 and a host access area 214. The host access area 214 is used for storing data.

According to an embodiment of the present invention, when the host 150 is connected to the storage device 200 using DRAM, the host 150 can detect that the storage device 200 using DRAM includes two accessible regions, that is, non-volatile. The memory 220 and the host access area 214 in the DRAM 230. That is, in the computer system 280, the host 150 detects that there are two storage devices in the storage device 200 using DRAM, and the host 110 can access any one of the storage devices to write data to it. Or read.

For example, in the storage device 200 using DRAM, the capacity of the non-volatile memory 220 is 256G bytes, and the capacity of the DRAM 230 is 2G bytes. The DRAM 230 includes a host access area 214 of 1.5 G bytes and a buffer area 212 of 0.5 G bytes.

Since the access speed of the DRAM 230 is relatively fast, the host 150 can store write data requiring high-speed access or frequent access in the host access area 214 and store other write data in the non-volatile memory 220 . This will effectively improve the overall performance of the storage device 200 using DRAM. However, the data stored in the host access area 214 is not limited to the written data sent by the host 150, and may also store other data, such as a form required for the control circuit 210 to write data to the non-volatile memory 220. This is the limit.

When the host 150 sends a write command to store the written data in the storage device 200 using the DRAM, the control circuit 210 can operate according to the command issued by the host 150.

For example, when the host 150 sends a write command to store the write data in the non-volatile memory 220, the control circuit 210 receives the write data from the host 150 and temporarily stores the write data in the buffer 212. After that, the control circuit 210 performs ECC encoding on the write data temporarily stored in the buffer 212 at an appropriate timing, and stores the ECC encoded write data into the non-volatile memory 220.

When the host 150 sends a write instruction to store the write data in the host access area 214, the control circuit 210 receives the write data from the host 150 and performs memory protection ECC (referred to as abbreviation) on the written data. MPECC) is stored in the host access area 214 after encoding. Among them, the MPECC encoding and the ECC encoding performed by the write data storage non-volatile memory 220 have different encoding methods.

When the host 150 sends a read instruction to read the data in the non-volatile memory 220, the control circuit 210 obtains the read data from the non-volatile memory 220 and performs ECC decoding, and then decodes the read data after the ECC is decoded. Temporarily stored in the buffer 212 and passed to the host 150.

In addition, when the host 150 issues a read instruction to read the data in the host access area 214, the control circuit 210 obtains the read data from the host access area 214 and performs MPECC decoding, and then passes the read data to the host 150 .

Similarly, the buffer area 212 in the DRAM 230 is only an area used by the control circuit 210 to temporarily store data. That is, the host 150 cannot directly access the data in the buffer area 212 in the DRAM 230.

As is known to all, when the DRAM 230 is powered off, all stored data in the DRAM 230 will disappear. Therefore, when the computer system 280 is normally shut down, the host 150 sends a power off command to the storage device 200 using the DRAM. When the control circuit 210 receives the shutdown command, the control circuit 210 transfers the data written in the host access area 214 of the DRAM 230 to the non-volatile memory 220 to avoid data loss. The host access area 214 The data will be decoded by MPECC, and then stored in non-volatile memory 220 after being ECC encoded. The computer system 280 can be turned off only after it is confirmed that the write data of the storage device 200 using the DRAM has been successfully transferred.

In addition, when the computer system 280 has a sudden power failure, the storage device 200 using DRAM has a backup power supply 160, and the backup power supply 160 starts to supply power to enable the storage device 200 using DRAM to operate normally. At this time, the control circuit 210 turns the DRAM 230 on. The data written in the host access area 214 is transferred to the non-volatile memory 220, so even if the computer system 280 is powered off suddenly, the data in the host access area 214 will not disappear. The backup power source 160 may be a large-capacity capacitor (such as a super capacitor) or a battery, which is not limited herein.

When the computer system 280 is turned on again, the control circuit 210 reads out the written data stored in the host access area 214 in the non-volatile memory 220 before the shutdown, and performs ECC decoding, and the ECC decoded data passes MPECC. Loaded into host access area 214 after encoding. After the loading is completed, the storage device 200 using the DRAM can operate normally, and the host 150 can arbitrarily access the data in the non-volatile memory 220 or the host access area 214. In addition, an area is set in the non-volatile memory 220 for storing only the data in the host access area 214. When the computer system 280 is turned off, all the data in the host access area 214 will be stored in this area. When booting, the data in this area will be saved back to the host access area 214.

However, when the computer system 280 is turned on, the host 150 may not access the written data in the host access area 214 for a long time. Since there is no appropriate method to judge the status of the written data stored in the host access area 214, if the written data is lost or wrong, it will have a significant impact on the storage device 200 using DRAM.

For example, after the host 150 stores the written data in the host access area 214, the host 150 keeps the written data for more than one year without performing any access. When the computer system 280 is shut down, the control circuit 210 transfers the written data in the host access area 214 to the non-volatile memory 220.

However, if the control circuit 210 only finds that there is an error bit in the write data in the host access area 214 during the process of writing the data, the control circuit 210 will take a considerable time to write. The data is corrected for errors, and the corrected data is written into the non-volatile memory 220. At this time, it may happen that the written data is too late to be transferred to the non-volatile memory 220. Therefore, once the computer system 280 is shut down, the unwritten data in the host access area 214 will be lost and there is no way to recover it.

When the computer system 280 is turned on again, the computer system 280 cannot operate normally because part of the written data in the host access area 214 before the shutdown is lost.

Therefore, in order to ensure the accuracy of the data in the host access area 214 of the DRAM 230, the present invention proposes a data processing method.

Please refer to FIG. 3, which shows a flowchart of the data processing method of the present invention. When the storage device 200 using the DRAM is operating normally, the control circuit 210 counts time. Each time a predetermined period of time passes (step S310), the control circuit 210 performs a data confirmation operation on the host access area 214. For example, the predetermined time may be 1 minute.

When the predetermined time has elapsed (step S310), the control circuit 210 copies a part of the written data from the host access area 214 of the DRAM 230 to the buffer area 212 (step S312).

If the control circuit 210 can copy successfully (step S314), it is confirmed that the data written in the part in the host access area 214 is correct. Therefore, the control circuit 210 returns to step S310 and continues to wait for the next predetermined time period to continue the data confirmation operation for writing another part of the data.

Conversely, if the control circuit 210 cannot copy successfully (step S314), it means that there is an error bit in the written data of the part in the host access area 214. At this time, the control circuit 210 needs to perform error correction on the data written in the part of the host access area 214 (step S316).

Moreover, if the control circuit 210 can be successfully corrected (step S318), it means that the error bit has been corrected, and the control circuit 210 rewrites the part of the written data in the host access area 214 (step S320). ) To ensure that the information written in this section is correct. After that, the control circuit 210 returns to step S310 and waits for the next predetermined time period before continuing the next data confirmation operation.

Conversely, if the control circuit 210 cannot be successfully corrected (step S318), it means that there are too many error bits in the data written in the part, and it cannot be recovered. Therefore, the control circuit 210 marks the storage position of the written data in the part (step S322), and the storage position of the mark indicates the data in question. After that, the control circuit 210 returns to step S310, and waits for the next predetermined time period before proceeding to the next Data confirmation actions. In the above data processing method, the write data sent by the host 150 stored in the host access area 214 is taken as an example. However, other data in the host access area 214 that is not related to the write data sent by the host 150 can also be used for data confirmation. Actions. The following uses an example to illustrate the data processing method of the present invention.

It is assumed that the data in the host access area 214 is set as a part of data with a specific capacity and the part of the data is further divided into a plurality of unit data. For example, the host access area 214 is set as a part of data with 128k bytes and a part of the data is divided into a plurality of unit data with a unit of 512bytes. At this time, a part of the data is divided into 256 unit data.

When the storage device 200 using DRAM is operating normally, the control circuit 210 performs a data confirmation operation on a part of the written data (128k bytes) every one minute time period.

When performing the data confirmation operation, the control circuit 210 executes a direct memory access copy function (DMAC function), and copies the written data of the first part (128k bytes) in the host access area 214 To buffer 212.

If the written data of the first part (128k bytes) can be successfully copied to the buffer 212, the control circuit 210 confirms that the written data of the first part in the host access area 214 is correct. Therefore, after the next 1 minute time period, the control circuit 210 performs a data confirmation operation on the written data of the second part (128k bytes). By analogy, the control circuit 210 may sequentially (128k bytes) write data, the fourth part (128k bytes) write data ... and so on to confirm the data.

Of course, if the written data of the first part cannot be successfully copied to the buffer 212, the control circuit 210 confirms that the written data of the first part in the host access area 214 has an error bit. Therefore, the control circuit 210 performs an error correction operation on the unit data in which an error bit occurs in the first part of the written data.

Furthermore, if the control circuit 210 can successfully correct (step S318), it means that the error bit of the unit data in the first part of the written data has been corrected. At this time, the control circuit 210 is about to write the written data of the unit into the host access area 214 again after correction. In this way, the correctness of the unit data in which the error bit occurs in the first part can be ensured. After that, the control circuit 210 uses the following 256 unit data of the unit data with the error bit as the second part of the written data after the next 1 minute time period, and confirms the data of the second part of the written data. And so on.

Conversely, if the control circuit 210 cannot be successfully corrected (step S318), it means that there are too many error bits of the unit data in the first part of the written data, and it cannot be recovered. Therefore, the control circuit 210 marks the storage location of the unit data in the first part of the written data, which is indicated as the problematic data. After that, the control circuit 210 continues the data confirmation operation of the second part of the written data after the next 1 minute time period. And so on.

As can be seen from the above description, the present invention provides a storage device using DRAM and a related data processing method. During the normal operation process of the storage device 200 using DRAM, the control circuit 210 continuously performs data confirmation on the host access area 214, so the data in the host access area 214 in the DRAM 230 can be guaranteed to be correct.

When the computer system 280 is shut down, since the correctness of the data in the host access area 214 has been continuously ensured, the control circuit 210 can transfer the data written in the host access area 214 to the non-volatile memory 220. During the transfer, the marked problematic data will also be transferred to the non-volatile memory 220 together.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (9)

A storage device using DRAM includes: a DRAM, wherein the DRAM includes a buffer area and a host access area, and the host access area stores data; and a control circuit connected to The DRAM; wherein, after a predetermined period of time, the control circuit copies a part of the data from the host access area to the buffer, and when the part of the data is successfully copied to the buffer, the control circuit confirms that the host stores The information in this part of the selection is correct. The storage device using DRAM according to item 1 of the scope of patent application, wherein when the data in the part cannot be successfully copied to the buffer, the control circuit performs an error correction on the data in which the wrong bit occurs in the data in the part action. The storage device using DRAM as described in the second item of the scope of patent application, wherein when the error correcting action is successful, the control circuit writes the data of the part after correction to the host access area again. The storage device using DRAM according to item 2 of the scope of patent application, wherein when the error correcting action is unsuccessful, the control circuit marks the storage location of the data in which the error bit occurs in the data in the part of the host access area. . The storage device using DRAM according to item 1 of the scope of patent application, wherein the control circuit executes a direct memory access copy function, and the host access area copies the part of the data to the buffer area. The storage device using DRAM described in item 1 of the scope of patent application, further includes a backup power source, which is a large-capacity capacitor or a battery. A data processing method for a storage device using DRAM. The storage device using DRAM includes: a control circuit and a DRAM, wherein the DRAM includes a buffer area and a host access area, and the host access area stores a Data, the data processing method includes the following steps: (a) after a predetermined period of time, a portion of the data is copied from the host access area to the buffer; (b) when the portion of the data is successfully copied to the buffer To confirm that the data in the part of the host access area is correct; (c) when the data in the part is not successfully copied to the buffer, perform an error correction action on the data with the wrong bit in the data in the part; d) when the error correcting action is successful, write the data of the part after correction to the host access area again; and (e) when the error correcting action is unsuccessful, mark the part of the host access area Where the data in which the error occurred is stored. The data processing method as described in item 7 of the scope of patent application, wherein step (a) includes performing a direct memory access copy function, and the host access area copies the part of the data to the buffer area. The data processing method according to item 7 of the scope of patent application, wherein after performing step (b), step (d) or step (e), return to step (a).