TWI665869B - Input receiver circuit and adaptive feedback method - Google Patents

Abstract

The invention provides an adaptive feedback method for a memory device. The memory device includes a first input receiver circuit and a plurality of second input receiver circuits. The method includes: providing a clock signal and an inverse Phase clock signal to the first input receiver circuit; use the first input receiver circuit to generate a uniform energy control signal to control the feedback path in the first input receiver circuit; when the clock signal and the feedback The frequency of the phase clock signal is higher than or equal to a predetermined frequency, and the feedback path in the first input receiver circuit is turned on according to the enable control signal; and when the frequency of the clock signal and the inverted clock signal is low At a predetermined frequency, the feedback path in the first input receiver circuit is closed according to the enable control signal.

Description

Input receiver circuit and adaptive feedback method

The present invention relates to electronic circuits, and in particular, to an input receiver circuit and an adaptive feedback method.

With the development of technology, the operating frequency of today's memory has become higher and higher, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). Above 100 MHz. In addition, each signal received by the memory device has a corresponding high-speed input receiver. However, when operating on low-frequency clock signals or when the conversion rate of the clock signals is very low, the output signals of these high-speed input receivers will oscillate, so the back-end circuits will not easily be able to capture the corresponding instructions and bits. Address, and data signals, causing the memory device to fail to function properly or to malfunction.

Therefore, an input receiver circuit and an adaptive feedback method are needed to solve the above problems.

The invention provides an input receiver circuit, which includes a first input receiver, a second input receiver, and a control signal output stage. The first input receiver includes: a first differential amplifier for receiving a clock signal and outputting an amplified clock signal; a first buffer circuit for buffering the amplified clock signal and outputting an output A clock signal, wherein a first feedback path is provided between the first buffer circuit and the first differential amplifier; and a first delay circuit for delaying the amplified clock signal to generate a A first delayed signal. The second input receiver includes: a second differential amplifier for receiving an inverting clock signal and outputting an amplified inverting clock signal; and a second buffer circuit for buffering the amplified inverting clock signal. Pulse signal and output an inverting clock signal, wherein a second feedback path is provided between the second buffer circuit and the second differential amplifier; and a second delay circuit is used for the amplification The inverse clock signal performs the time delay to generate a second delayed signal. The control signal output stage generates a uniform energy control signal according to the first delay signal and the second delay signal, wherein the enable control signal controls the opening or closing of the first feedback path and the second feedback path. .

The invention further provides an adaptive feedback method for a memory device. The memory device includes a first input receiver circuit and a plurality of second input receiver circuits. The method includes: providing a clock signal and a Invert the clock signal to the first input receiver circuit; use the first input receiver circuit to generate a uniform energy control signal to control the feedback path in the first input receiver circuit; when the clock signal and the The frequency of the inverted clock signal is higher than or equal to a predetermined frequency, and the feedback path in the first input receiver circuit is turned on according to the enable control signal; and when the clock signal and the frequency of the inverted clock signal are Below the predetermined frequency, the feedback path in the first input receiver circuit is closed according to the enable control signal.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

FIG. 1A is a schematic diagram showing a memory device according to an embodiment of the present invention.

As shown in FIG. 1A, the memory device 100 includes a plurality of input receiver circuits 110, an input receiver circuit 200, a control logic 120, and a plurality of memory cell arrays 130.

In one embodiment, the memory device 100 receives a clock signal, an instruction signal, an address signal, and a data signal from a host (for example, a central processing unit). The clock signals include, for example, a clock signal CK_t, an inverted clock signal CK_c, and a clock enable signal CKE. The clock signal CK_t and the inverted clock signal CK_c correspond to the input receiver circuit 200.

The command signals include, for example, a Chip Select (CS) signal, a Row Address Strobe (RAS) signal, a Row Address Strobe (CAS) signal, and a Write Enable (WE) Signals and more. The address signal includes, for example, an instruction address A [13: 0] and a bank address address BA [2: 0], where the size of N can be determined according to the actual situation. The data signals include, for example, a data signal DQ [31: 0] and a data strobe signal DQS [3: 0]. The number of bits of the data signal DQ and the data strobe signal DQS may also depend on actual conditions, and the present invention is not limited thereto. The above-mentioned number of command signals, address signals, and data signals.

In detail, in addition to the clock signal CK_t and the inverted clock signal CK_c, each bit of the above signals requires a corresponding input receiver circuit 110 to adjust the voltage swing of the corresponding bit signal to suit The voltage swing of the memory device 100 is convenient for subsequent circuit operations. The clock signal includes, for example, a clock signal CK_t and an inverted clock signal CK_c, which correspond to the input receiver circuit 200. The input receiver circuit 200 can control the opening or closing of the feedback path of each input receiver circuit 110 in the range 10, the details of which will be described later.

The control logic 120 is used to control the memory cell array 130 according to a command from the host. The memory cell array 130 is, for example, a dynamic random access memory (DRAM) cell array, and can be divided into a plurality of memory banks.

FIG. 1B is a schematic diagram showing an input receiver circuit 110 according to an embodiment of the present invention. FIG. 1C is a circuit diagram showing a differential amplifier 111 according to an embodiment of the present invention.

The input receiver circuit 110 includes a differential amplifier 111 and a buffer circuit 112. The differential amplifier 111 receives an input signal IN and a reference voltage Vref, and generates a first signal at its output terminal (for example, the node N1). For example, the differential amplifier 110 is, for example, a wide-swing differential amplifier. The input signal IN is, for example, one bit of a command signal, an address signal, or a data signal.

The differential amplifier 111 may be, for example, the differential amplifier circuit in FIG. 1C, which is composed of transistors M0 to M10 and inverters 1101 to 1103, where the input signal DQ (that is, the input signal IN in FIG. 1B) It can be one of the command signal, the address signal, or the data signal. After passing through the differential amplifier 110, the output signal DQo is generated. The enable signal EN may be, for example, an inverted clock enable signal CKE_c. Those with ordinary knowledge in the field of the present invention can understand the operation of the wide-swing differential amplifier circuit in FIG. 1C, so details thereof will not be repeated here.

The buffer circuit 112 includes inverters 1121 and 1122, as shown in FIG. 1B. The output signal INo is generated after the first signal of the node N1 passes through the inverters 1121 and 1122. For example, if the input signal IN of the input receiver circuit 110 is a command signal CAS, the output signal generated by it is CASo. If the input signal IN of the input receiver circuit 110 is the address signal A [0] (or A0), the output signal generated by it is Ao [0], and so on.

It should be noted that there is a feedback path (or a feedback circuit) 113 between the differential amplifier 111 and the buffer circuit 112. The feedback path 113 includes, for example, a three-state inverter 1123 and a resistor. R1.

For example, after the first signal at the node N1 passes through the inverter 1121, a second signal is generated at the node N2. The second signal is fed back to the node N1 through the tri-state inverter 1123 and the resistor R1. It should be noted that the control signal En_c and the reverse control signal En_t of the tri-state inverter 1123 are from the enable control signal ENext_t generated by the input receiver circuit 200 via the signal generation circuit 250 (as shown in FIG. 2C). produce.

FIG. 2A is a schematic diagram showing an input receiver circuit according to an embodiment of the present invention. Fig. 2B is a circuit diagram showing a differential amplifier in the embodiment according to Fig. 2A of the present invention. FIG. 2C is a schematic diagram showing a signal generating circuit according to an embodiment of the present invention.

As shown in FIG. 2A, the input receiver circuit 200 includes input receivers 210 and 220 and a control signal output stage 230.

The input receiver 210 includes a differential amplifier 211, a buffer circuit 212, and a delay circuit 214. For example, the differential amplifier 211 is, for example, a wide-swing differential amplifier. The inputs are a clock signal CK_t and a reference voltage Vref, and a first clock signal is output at the node N11. For example, the differential amplifier 211 can be implemented by the circuit of FIG. 2B, which includes transistors M51-M67, resistors R51-R56, and a plurality of inverters 2110. The transistors M51 to M53 and resistors R51 to R52 form an electrostatic-discharge (ESD) protection circuit, and the inputs of the transistor M56 and the transistor M57 are the clock signal CK_t and the reverse phase, respectively. Pulse signal CK_c.

It should be noted that the circuit of the differential amplifier 221 is the same as the differential amplifier 211. The difference is that the inputs of the transistor M56 and the transistor M57 in the differential amplifier 221 are the inverted clock signal CK_c and the reference voltage Vref, respectively. The enable signal EN * may be, for example, a clock enable signal CKE. Those with ordinary knowledge in the field of the present invention can understand the operation of the wide-swing differential amplifier circuit in FIG. 2B, so details thereof will not be repeated here.

The buffer circuit 212 includes an inverter 2121 and 2122. After the first signal of the node N11 passes through the inverters 2121 and 2122, an output clock signal CKo_t is generated.

It should be noted that there is a feedback path (or a feedback circuit) 213 between the differential amplifier 211 and the buffer circuit 212. The feedback path 213 includes a three-phase inverter 2123 and a resistor. R11.

For example, the first signal at the node N11 passes through the inverter 2121 to generate a second clock signal at the node N12, and the second clock signal is fed back to the node N11 through the tri-state inverter 2123 and the resistor R11. . The three-state inverter 2123 is controlled by the control signals EN_c and EN_t. For example, the control signals EN_c and EN_t are generated by the enable control signal ENext_t. For example, the enable control signal ENext_t can generate the control signals EN_c and EN_t through the signal generation circuit 250 shown in FIG. 2C, where the control signal En_c Is the output of the inverter 251, and the control signal EN_t is the output signal of the control signal En_c through the inverter 252. In some embodiments, the signal generating circuit 250 in FIG. 2C is integrated into the input receiver circuit 200.

It should be noted that when the control signal EN_c is in a low logic state and the control signal EN_t is in a high logic state, the tri-state inverter 2123 is turned on. When the control signal EN_c is in a high logic state and the control signal EN_t is in a low logic state, the tri-state inverter 2123 is turned off (for example, a high-impedance state), so the tri-state inverter 2123 can be regarded as an open circuit.

In addition, the control signals EN_c and EN_t generated by the signal generating circuit 250 are provided to the tri-state inverters 2123 and 2223 to control the tri-state inverters 2123 and 2223 to be turned on or off, and are also provided to the memory device 100 The tri-state inverter 1123 of each input receiver circuit 110 controls its turning on or off. In detail, the opening or closing of the feedback path in the input receiver circuit 200 and each input receiver circuit 110 is controlled synchronously by the enable control signal ENext_t generated by the input receiver circuit 200.

The delay circuit 214 may, for example, generate a first delayed signal at the node N15 after the RC delay of the first clock signal of the node N11, and output the first delayed signal to the control signal output stage 230. The delay circuit 224 may, for example, generate a second delay signal at the node N25 after outputting the second clock signal of the node N21 through the same RC delay as the delay circuit 214, and output the second delay signal to the control signal output stage 230. The delay circuit 214 includes a P-type transistor M11, an N-type transistor M12, a resistor R12, a capacitor C11, and an inverter 2141.

For example, when the first clock signal of the node N11 is in a low logic state, the N-type transistor M12 will be open, and the node N13 will be in a high logic state. After the inverter 2141, the node N15 will be in a low logic state. Logical state. At this time, the power source VDD charges the capacitor C11 via the resistor R12.

When the first clock signal of the node N11 is in a high logic state, the N-type transistor M12 will be turned on, and the nodes N13 and N14 will be in a low logic state. After the inverter 2141, the node N15 will be in a high logic state. At this time, the capacitor C11 is discharged through the N-type transistor M2.

In addition, the operation of each element in the input receiver 220 is similar to that of the input receiver 210. The difference is that the input receiver 210 receives a clock signal CK_t, and the input receiver 220 receives its inverted clock signal CK_c. Details are not repeated here.

The control signal output stage 230 includes an XNOR gate X1, a P-type transistor M31, an N-type transistor M32, a resistor R31, a capacitor C31, and an inverter 2301.

The inputs of the anti-mutual OR gate X1 are the first delayed signal output from the delay circuit 214 of the input receiver 210 at node N15, and the second delayed signal output from the delay circuit 224 of the input receiver 220 at node N25. The first delay signal and the second delay signal generate an operation signal at the node N31 through the anti-mutex OR gate X1, and the operation signal passes through a CMOS inverter composed of a P-type transistor M31 and an N-type transistor M32, and An inverted operation signal is output at the node N32. After the inverting operation signal of the node N32 has undergone the RC delay (for example, composed of the resistor R31 and the capacitor C31) and the inverter 2301, an enable control signal ENext_t is generated at the output of the inverter 2301.

For example, when the output signal of the anti-mutex or gate X1 at the node N31 is in a low logic state, the P-type transistor M31 is turned on, and the node N32 is in a high logic state, and the capacitor C31 is charged through the resistor R31. Finally, the node N33 will be in a high logic state, and after passing the inverter 2301, an enable control signal ENext_t in a low logic state will be obtained.

When the output signal of the anti-mutex or gate X1 at the node N31 is in a high logic state, the N-type transistor M32 is turned on, the node N32 is in a low logic state, and the capacitor C31 is discharged through the resistor R31. Finally, the node N33 will be in a low logic state. After passing the inverter 2301, an enable control signal ENext_t in a high logic state will be obtained. It should be noted that the operations of the RC delay circuits in the above embodiments are in a steady state.

In one embodiment, the enable control signal ENext_t output by the input receiver circuit 200 can control the feedback paths (such as the feedback paths 213 and 223) in the input receiver circuit 200 and each of the memory devices 100. The feedback path of the group input receiver circuit 110 (for example, the feedback path 113 in FIG. 1B) is turned on or off.

In an embodiment, taking the input receiver 210 as an example, assuming that the frequency of the input clock signal CK_t of the input receiver 210 is quite high (for example, 400 MHz, unlimited), the capacitance C11 in the delay circuit 214 will be due to the node N11 The logic state of the fast transition is too late to fully discharge, so node N13 will always be in a high logic state. Similarly, the input inverted clock signal CK_c of the input receiver 220 also has a relatively high frequency, and the capacitor C21 in the delay circuit 224 will also have no time to fully discharge, so the node N23 will also always be in a high logic state.

At this time, the nodes N15 and N25 will be in a low logic state, and the output of the anti-mutex or gate X1 will be a high logic state, causing the N-type transistor M32 to be turned on and the capacitor C31 to be fully discharged through R31. Therefore, the node N33 will be in a low logic state, so the enable control signal ENext_t generated after passing through the inverter 2301 will be in a high logic state. This means that the tri-state inverters in the input receiver circuits are turned on, so the feedback path will be turned on.

In an embodiment, taking the input receiver 210 as an example, it is assumed that the frequency of the input clock signal CK_t of the input receiver 210 is relatively low (for example, less than a predetermined frequency, such as 50 MHz) and the slew rate is normal (for example, high At a predetermined conversion rate). If the clock signal CK_t is in a low logic state, the node N11 is also in a low logic state, and then the P-type transistor M11 in the delay circuit 214 is turned on. Therefore, the node N13 will be in a high logic state, and after passing through the inverter 2141, the node N15 will be in a high logic state.

At the same time, the input inverting clock signal CK_c of the input receiver 220 will be in a high logic state, and the node N21 is also in a high logic state, so that the N-type transistor M22 in the delay circuit 224 is turned on and the capacitor C21 is fully discharged. . Therefore, the node N23 will be in a low logic state, and after passing through the inverter 2241, the node N25 will be in a low logic state.

Therefore, the output of the anti-mutex OR gate X1 at the node N31 is in a low logic state, so that the P-type transistor M31 is turned on, and the node N32 is in a high logic state, and the capacitor C31 is charged. This means that the node N33 will be in a high logic state, and the enable control signal ENext_t generated by the inverter 2301 will be in a low logic state. That is, the tri-state inverters in the input receiver circuits 110 and 200 are turned off (high impedance state), so the feedback path is cut off.

Similarly, in this embodiment, if the clock signal CK_t is in a low logic state and the inverted clock signal CK_c is in a high logic state, then the output of the last anti-mutex OR gate X1 at the node N31 is also in a low logic state. At this time, the P-type transistor M31 is turned on, and the node N32 is in a high logic state, and the capacitor C31 is charged. This means that the node N33 will be in a high logic state, and the enable control signal ENext_t generated by the inverter 2301 will be in a low logic state. This means that the tri-state inverters in each input receiver circuit are turned off (high impedance state), so the feedback path will be cut off.

In summary, when the frequency of the clock signal / inverted clock signal is low and the conversion rate is normal, the control signal ENext_t will be in a low logic state, so the feedback path in each input receiver circuit will be cut off.

In one embodiment, when the memory device enters a power-saving state, the clock signal CK_t stops (for example, the clock enable signal CKE in FIG. 1A is a low logic state), and the clock signal CK_t is maintained at a low level. Logic state. At this time, the inverted clock signal CK_c is maintained in a high logic state. Therefore, it can be deduced in a similar way that node N15 will be in a high logic state and node N25 will be in a low logic state. Therefore, the output of the anti-mutex OR gate X1 at the node N31 is in a low logic state, so that the P-type transistor M31 is turned on, and the node N32 is in a high logic state, and the capacitor C31 is charged. This means that the node N33 will be in a high logic state, and the enable control signal ENext_t generated by the inverter 2301 will be in a low logic state. This means that the tri-state inverters in each input receiver circuit are turned off (high impedance state), so the feedback path will be cut off.

In one embodiment, the RC delay designs in the delay circuits 214 and 224 are matched with each other. If the memory device is used for an operating frequency of 400 MHz, for example, the period of the clock signal tCK = 2.5 ns. At this time, for example, the RC delay can be designed to be 1.25ns, where the resistor R (such as resistors R12 and R22) can be 2KΩ, and the capacitor C (such as capacitors C11 and C21) can be 625fF, but the present invention is not limited to the above values .

Generally, if the frequency of the clock signal is fast enough, its conversion rate will not be too low. Usually a lower frequency clock signal will have a lower conversion rate. For example, the design of the critical value of the RC delay in the present invention can, for example, use a clock signal of a predetermined frequency and its conversion rate is not low enough to cause the next-stage circuit to oscillate, even if the feedback path is turned on or off It will not affect the performance of the input receiver circuit. Although the enable control signal ENext_t may cause a brief logic state change due to the RC delay of the control signal output stage 230, it will not affect the operation of the input receiver circuit 200.

FIG. 3 is a timing diagram illustrating an enable control signal according to an embodiment of the present invention.

In the foregoing embodiment, when the frequency of the clock signal / inverted clock signal is low and the conversion rate is normal, the control signal ENext_t will be in a low logic state, and the feedback paths in each input receiver circuit will be cut off. .

In an embodiment, it is assumed that the frequencies of the input clock signal CK_t and the inverted clock signal CK_c of the input receivers 210 and 220 are relatively low (less than a predetermined frequency, such as 50 MHz) and the conversion rate is less than a predetermined conversion rate. In this embodiment, because the conversion rate of the input clock signal CK_t is quite low, and coupled with the design of the RC delay of the control signal output stage 230, the control signal ENext_t cannot always be maintained in a low logic state.

For example, as shown in Fig. 3, when the output clock signal CKo_t is at a positive edge change, during the voltage rise of the output clock signal CKo_t, the voltage of the output clock signal CKo_t will oscillate due to the feedback path. For example, in the interval 310, it is an oscillation range. Similarly, when the output clock signal CKo_t has a negative edge change, during the period when the voltage of the output clock signal CKo_t decreases, the voltage of the output clock signal CKo_t will oscillate due to the feedback path. For example, the interval 320 is the oscillation range. . A similar situation occurs with the output inverted clock signal CKo_c.

The design of the RC delay of the control signal output stage 230 will enable the control signal ENext_t to temporarily switch from the low logic when the output clock signal CKo_t is in a high logic state (or the output inverted clock signal CKo_c is in a low logic state). The state switches to a high logic state. However, because the memory device is a digital circuit, its instructions, addresses, and data acquisition operations are performed when the positive or negative edge of the clock signal CKo_t or the inverted clock signal CKo_c is output. .

In detail, when the enable control signal ENext_t is temporarily switched from a low logic state to a high logic state, and does not change when the positive or negative edge of the clock signal CKo_t or the output inverted clock signal CKo_c is changed, the back-end circuit is at When the instructions, addresses, and data are retrieved, the temporary high logic state of the enable control signal ENext_t is not retrieved, so it will not affect the operation of the memory device 100.

FIG. 4 is a flowchart illustrating an adaptive feedback method according to an embodiment of the present invention. Please refer to Figure 4 and Figure 2A at the same time.

In step S410, a clock signal and an inverted clock signal are provided to a first input receiver circuit. The first input receiver circuit is, for example, an input clock receiver circuit 200.

In step S420, the first input receiver circuit is used to generate a uniform energy control signal to control the feedback path in the first input receiver circuit. For example, the input clock receiver circuit 200 includes input receivers 210 and 220, and the input receivers 210 and 220 respectively delay the output signals of the differential amplifiers 211 and 221 through their delay circuits 214 and 224, respectively, after RC delay. The first delay signal and the second delay signal are generated and then transmitted to the control signal output stage 230. The first delay signal and the second delay signal are delayed by the anti-mutex OR gate X1 and RC in the control signal output stage 230 to generate the enable control signal ENext_t. The enable control signal may be generated by the signal generating circuit 250 in FIG. 2C to generate the control signals EN_c and EN_t.

In step S430, when the frequencies of the clock signal and the inverted clock signal are higher than or equal to a predetermined frequency, the enable control signal turns on the first input receiver circuit and the second input receiver circuit. Grant path.

In step S440, when the frequencies of the clock signal and the inverted clock signal are lower than a predetermined frequency, the enable control signal closes the feedback paths of the first input receiver circuit and each second input receiver circuit.

In summary, the present invention provides an input receiver circuit and an adaptive feedback method, wherein the input receiver circuit can use the clock signal and the reverse clock signal to generate a corresponding delayed signal, and then perform logical operations and appropriate After the RC delay, an enabling control signal can be generated, and when the frequency of the clock signal is higher than or equal to the predetermined frequency, the feedback of the input receiver circuit and other receiver circuits in the memory device can be turned on according to the enabling control signal. path. When the frequency of the clock signal is lower than the predetermined frequency, the feedback path of the input receiver circuit and other receiver circuits in the memory device can be closed according to the enable control signal, so that the rear device in the memory device is in the clock When the frequency of the signal is low, the corresponding input signal will not be captured during the period when the clock signal is oscillating to ensure that the memory device can operate normally.

The use of words such as "first", "second", "third" in claims is used to modify elements in the claims, and is not used to indicate that there is a priority order, antecedent relationship, or an element between claims Preceding another element, or chronological order when performing a method step, is only used to distinguish elements with the same name.

Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the scope of the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧Memory device

110‧‧‧input receiver circuit

120‧‧‧Control logic

130‧‧‧memory cell array

200‧‧‧ input receiver circuit

250‧‧‧ signal generating circuit

CK_t‧‧‧clock signal

CK_c‧‧‧ Inverted clock signal

CKE‧‧‧Clock enable signal

CS‧‧‧Chip Select Signal

RAS‧‧‧column address strobe signal

CAS‧‧‧row address strobe signal

WE‧‧‧ write enable signal

A0－A13‧‧‧Command address

BA0－BA2‧‧‧Memory group address

DQ0－DQ31‧‧‧Data signal

DQS0－DQS3‧‧‧Data strobe signal

IN‧‧‧Input signal

INo‧‧‧ output signal

Vref‧‧‧Reference voltage

111‧‧‧ Differential Amplifier

112‧‧‧Buffer circuit

1121, 1122‧‧‧ Inverter

1123‧‧‧Three-state inverter

N1, N2‧‧‧nodes

113‧‧‧ Feedback Path

R1‧‧‧ resistance

EN_c‧‧‧Control signal

EN_t‧‧‧Reverse control signal

M0－M10‧‧‧Transistors

VDD‧‧‧Voltage

EN‧‧‧Enable signal

1101－1103‧‧‧ Inverter

DQ‧‧‧ input signal

DQo‧‧‧ output signal

210, 220‧‧‧ input receiver

211, 221‧‧‧ Differential amplifier

212, 222‧‧‧Buffer circuit

213, 223‧‧‧ feedback path

214, 224‧‧‧ Delay circuit

230‧‧‧Control signal output stage

2121-2122, 2221-2222, 2141, 2241, 2301, 251, 252‧‧‧ inverters

2123, 2223‧‧‧ three-state inverter

R11, R12, R21, R22, R31‧‧‧ resistance

N11-N15, N21-N25, N31-N33‧‧‧nodes

M11, M12, M21, M22, M31, M32 ‧‧‧ Transistors

CKo_t‧‧‧Output clock signal

CKo_c‧‧‧ output inverted clock signal

X1‧‧‧Anti-mutual exclusion or brake

C11, C21, C31‧‧‧Capacitors

EN * ‧‧‧Enable signal

M51－M67‧‧‧Transistors

R51－R56‧‧‧Resistor

21‧‧‧ Electrostatic discharge protection circuit

ENext_t‧‧‧ Enable control signal

310, 320‧‧‧ range

S410－S440‧‧‧Steps

FIG. 1A is a schematic diagram showing a memory device according to an embodiment of the present invention.

FIG. 1B is a schematic diagram showing an input receiver circuit 110 according to an embodiment of the present invention. FIG. 1C is a circuit diagram showing a differential amplifier 111 according to an embodiment of the present invention. FIG. 2A is a schematic diagram showing an input receiver circuit 200 according to an embodiment of the present invention. Fig. 2B is a circuit diagram showing a differential amplifier in the embodiment according to Fig. 2A of the present invention. FIG. 2C is a schematic diagram showing a signal generating circuit according to an embodiment of the present invention. FIG. 3 is a timing diagram illustrating an enable control signal according to an embodiment of the present invention. FIG. 4 is a flowchart illustrating an adaptive feedback method according to an embodiment of the present invention.

Claims (11)

An input receiver circuit includes: a first input receiver including: a first differential amplifier for receiving a clock signal and outputting an amplified clock signal; a first buffer circuit for buffering the clock signal; Amplifies the clock signal and outputs an output clock signal, wherein a first feedback path is provided between the first buffer circuit and the first differential amplifier; and a first delay circuit is used to amplify the clock signal. The clock signal undergoes a time delay to generate a first delayed signal; a second input receiver includes: a second differential amplifier for receiving an inverted clock signal and outputting an amplified inverted clock signal A second buffer circuit for buffering the amplified inverted clock signal and outputting an output inverted clock signal, wherein a second is provided between the second buffer circuit and the second differential amplifier; A feedback path; and a second delay circuit for performing the time delay on the amplified inverted clock signal to generate a second delay signal; and a control signal output stage for responding to the first delay signal The second delay control signal to generate an enable signal, wherein the enable control signal line for controlling the first and the second feedback path of the feedback path on or off. The input receiver circuit according to item 1 of the scope of patent application, wherein the first differential amplifier and the second differential amplifier are a wide swing differential amplifier. The input receiver circuit according to item 1 of the scope of patent application, wherein the first buffer circuit includes a first inverter and a second inverter connected in series, and the output of the first inverter is The terminal is electrically connected to the output terminal of the first differential amplifier through a first tri-state inverter and a first resistor to form the first feedback path; wherein the second buffer circuit includes a series connection A third inverter and a fourth inverter, and an output terminal of the third inverter is electrically connected to the second differential through a second tri-state inverter and a second resistor. The output of the amplifier forms the second feedback path. The input receiver circuit according to item 1 of the patent application scope, wherein the control signal output stage includes: an anti-mutex or gate, a third delay circuit, and an inverter, wherein the anti-mutex or gate Receiving the first delay signal and the second delay signal to generate an operation signal, and the operation signal passes through the third delay circuit and the inverter to generate the enable control signal. The input receiver circuit described in item 3 of the patent application scope further includes: a signal generating circuit for converting the enable control signal into a control signal and an inverted control signal, and the first three-state inversion The opening and closing of the phase inverter and the second tri-state inverter are controlled by the control signal and the inversion control signal. The input receiver circuit according to item 5 of the patent application scope, wherein the signal generating circuit includes a fifth inverter and a sixth inverter, and the fifth inverter receives the enable control signal and The control signal is generated at the output terminal of the fifth inverter, and the sixth inverter receives the control signal, and generates the inverted control signal at the output terminal of the sixth inverter. The input receiver circuit according to item 5 of the scope of patent application, wherein when the enable control signal is in a high logic state, the control signal is in a low logic state and the inverting control signal is in the high logic state to Turn on the first three-state inverter and the second three-state inverter, and the corresponding first feedback path and the second feedback path; wherein when the enable control signal is in the low logic state, the The control signal is in the high logic state and the inversion control signal is in the low logic state to turn off the first tri-state inverter and the second tri-state inverter, and the corresponding first feedback path and The second feedback path. The input receiver circuit according to item 1 of the scope of patent application, wherein when the frequencies of the clock signal and the inverted clock signal are higher than or equal to a predetermined frequency, the enable control signal is in a high logic state; When the frequencies of the clock signal and the inverted clock signal are less than the predetermined frequency, the enable control signal is in a low logic state. The input receiver circuit according to item 1 of the scope of patent application, wherein the input receiver circuit is provided in a memory device, and a command signal, a bit address signal, and a data signal are received in the memory device. Each of the element signals has a corresponding third input receiver circuit, and the third input receiver circuit includes a third differential amplifier for receiving the corresponding bit signal and outputting an amplified bit Signal; and a third buffer circuit for buffering the amplified bit signal and outputting an output bit signal, wherein a third feedback is provided between the third buffer circuit and the third differential amplifier. Path; wherein the enable control signal controls the opening or closing of the third feedback path in the third input receiver circuit corresponding to each element signal. An adaptive feedback method for a memory device. The memory device includes a first input receiver circuit and a plurality of second input receiver circuits. The method includes: providing a clock signal and an inverted clock Signal to the first input receiver circuit; use the first input receiver circuit to generate a uniform energy control signal to control the feedback path in the first input receiver circuit; when the clock signal and the inverted clock The frequency of the signal is higher than or equal to a predetermined frequency, and the feedback path in the first input receiver circuit is turned on according to the enable control signal; and when the frequency of the clock signal and the inverted clock signal is lower than the predetermined frequency Frequency, shut down the feedback path in the first input receiver circuit according to the enable control signal. The adaptive feedback method according to item 10 of the scope of patent application, wherein each of the second input receiver circuits corresponds to each of a command signal, a bit address signal, and a data signal received in the memory device. Meta signals, and the opening or closing of the feedback path in each second input receiver circuit is controlled by the enable control signal generated by the first input receiver circuit.