TWI665803B - Semiconductor device comprising a transistor including a first field plate and a second field plate - Google Patents

Semiconductor device comprising a transistor including a first field plate and a second field plate Download PDF

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TWI665803B
TWI665803B TW106118285A TW106118285A TWI665803B TW I665803 B TWI665803 B TW I665803B TW 106118285 A TW106118285 A TW 106118285A TW 106118285 A TW106118285 A TW 106118285A TW I665803 B TWI665803 B TW I665803B
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field plate
semiconductor device
drift region
transistor
region
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TW106118285A
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TW201810650A (en
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安德烈亞斯 麥斯爾
法蘭茨 希爾勒
提爾 施勒塞爾
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英飛凌科技股份有限公司
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    • H01L29/402—Field plates
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    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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Abstract

一種半導體裝置（1）包含在半導體基板（100）中的電晶體（10）。電晶體（10）包含鄰接於汲極區域（205）的第一傳導類型的漂移區（259）、第一場板（250）以及鄰接於漂移區（259）的第二場板（252）。第二場板（252）被配置在第一場板（250）以及汲極區域（205）之間。第二場板電連接至被配置在漂移區（259）中接觸部分（263）。半導體裝置進一步包含低於接觸部分（263）以及汲極區域（205）之間的漂移區（259）的較低摻雜濃度的第一傳導類型的中間部分（261）。A semiconductor device (1) includes a transistor (10) contained in a semiconductor substrate (100). The transistor (10) includes a first conductivity type drift region (259) adjacent to the drain region (205), a first field plate (250), and a second field plate (252) adjacent to the drift region (259). The second field plate (252) is disposed between the first field plate (250) and the drain region (205). The second field plate is electrically connected to a contact portion (263) arranged in the drift region (259). The semiconductor device further includes a first conductive type intermediate portion (261) having a lower doping concentration lower than the contact portion (263) and the drift region (259) between the drain region (205).

Description

包含包括第一場板和第二場板電晶體的半導體裝置Semiconductor device including first field plate and second field plate transistor

常在汽車、工業以及消費電子產品中使用的功率電晶體需要低通路狀態電阻（Ron x A），同時確保高電壓阻斷能力。例如，取決於應用需求，MOS（「金屬氧化物半導體」）功率電晶體應能夠阻斷數十至數百或數千伏特的汲極至源極電壓Vds 。MOS功率電晶體典型地傳導非常大的電流，其在大約2至20V的典型閘極-源極電壓下可上至數百安培。Power transistors commonly used in automotive, industrial, and consumer electronics products require low on-state resistance (Ron x A) while ensuring high-voltage blocking capability. For example, depending on application requirements, MOS ("metal oxide semiconductor") power transistors should be able to block the drain-to-source voltage V ds of tens to hundreds or thousands of volts. MOS power transistors typically conduct very large currents, which can go up to hundreds of amps at a typical gate-source voltage of about 2 to 20V.

大體而言，正在尋找具有進一步降層通路狀態電阻的電晶體的概念。In general, the concept of a transistor with further reduced path state resistance is being sought.

本發明的目的是提供一種包含具有進一步降層通路狀態電阻的電晶體的半導體裝置。An object of the present invention is to provide a semiconductor device including a transistor having a further reduced path state resistance.

根據本發明，藉由根據獨立申請專利範圍所主張的標的來達成上述目的。在附屬申請專利範圍中定義了進一步的發展。According to the present invention, the above object is achieved by the subject matter claimed in the scope of the independent patent application. Further developments are defined in the scope of the attached patent application.

根據一個實施方式，半導體裝置包含在半導體基板中的電晶體。電晶體包含鄰接於汲極區域的第一傳導類型的漂移區、第一場板以及鄰接於漂移區的第二場板。第二場板被配置在第一場板以及汲極區域之間。第二場板電連接至配置在漂移區中接觸部分。電晶體進一步包含低於接觸部分以及汲極區域之間的漂移區的較低摻雜濃度的第一傳導類型的中間部分。According to one embodiment, a semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift region of a first conductivity type adjacent to the drain region, a first field plate, and a second field plate adjacent to the drift region. The second field plate is disposed between the first field plate and the drain region. The second field plate is electrically connected to a contact portion disposed in the drift region. The transistor further includes a middle portion of the first conductivity type that has a lower doping concentration than the contact portion and the drift region between the drain regions.

根據進一步的實施方式，半導體裝置包含在半導體基板中的電晶體。電晶體包含由第一傳導類型的材料構成的漂移區、第一場板、第二場板、第三場板以及在漂移區中的第一接觸部分。第一、第二以及第三場板在第一方向中以相距源極區域的不同距離被配置在漂移區中。第三場板至源極區域的距離大於第一或第二場板至源極區域的距離，且第三場板電連接至第一接觸部分。According to a further embodiment, the semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift region composed of a first conductivity type material, a first field plate, a second field plate, a third field plate, and a first contact portion in the drift region. The first, second, and third field plates are arranged in the drift region at different distances from the source region in the first direction. The distance from the third field plate to the source region is greater than the distance from the first or second field plate to the source region, and the third field plate is electrically connected to the first contact portion.

在閱讀下述詳細描述並在看到所附圖式之後，本領域的技術人員將識別額外的特徵以及優勢。After reading the following detailed description, and after seeing the attached drawings, those skilled in the art will recognize additional features and advantages.

在下述詳細描述中，參照了形成其一部分並利用示出其中可實施本發明的特定實施方式的方式所示出的附圖。在此方面，參照所描述圖式的方向使用了例如「頂部」、「底部」、「前」、「後」、「前導的」、「尾隨的」等等之類的方向性術語。由於可以許多不同的方位放置本發明實施方式的組件，方向性術語是用於示例的目的且絕非限制性。要了解的是，可使用其他的實施方式，且可做出結構或合理的改變而不悖離申請專利範圍所定義的範圍。In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and which are shown by way of illustration of specific embodiments in which the invention can be implemented. In this regard, directional terms such as "top", "bottom", "front", "back", "leading", "trailing", etc. are used with reference to the direction of the described drawings. Since components of embodiments of the present invention can be placed in many different orientations, the directional terminology is used for illustrative purposes and is by no means limiting. It is understood that other embodiments may be used, and structural or reasonable changes may be made without departing from the scope defined by the scope of the patent application.

實施方式的描述不具限制性。特別地，此後所描述的實施方式的元件可與不同實施方式的元件結合。The description of the embodiments is not restrictive. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

如本文中所使用的，用語「具有」、「含有」、「包括」、「包含」以及諸如此類是開放式的用語，指出了所主張的元件或特徵的存在，但不排除額外的元件或特徵。冠詞「一（a）」、「一（an）」以及「該」意欲包括複數以及單數，除非上下文清楚地另外指出。As used herein, the terms "having," "containing," "including," "including," and the like are open-ended terms that indicate the existence of stated elements or features, but do not preclude additional elements or features. . The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

如同此說明書中所使用的，用語「耦合」及/或「電耦合」不意欲意指元件必須直接耦合在一起-在「耦合」或「電耦合」元件之間可提供居中的元件。用語「電連接」意欲描述電連接在一起的元件之間的低歐姆電連接。As used in this specification, the terms "coupled" and / or "electrically coupled" are not intended to mean that the elements must be directly coupled together-a centered element may be provided between the "coupled" or "electrically coupled" elements. The term "electrical connection" is intended to describe a low-ohmic electrical connection between components that are electrically connected together.

如同此說明書中所使用的用語「側向」以及「水平」意欲描述平行於半導體基板或半導體本體的第一表面的方位。這可例如為晶圓或晶粒的表面。The terms "lateral" and "horizontal" as used in this specification are intended to describe an orientation parallel to a first surface of a semiconductor substrate or a semiconductor body. This may be, for example, the surface of a wafer or die.

如同此說明書中所使用的用語「垂直」意欲描述被配置垂直於半導體基板或半導體本體的第一表面的方位。The term "vertical" as used in this specification is intended to describe an orientation that is arranged perpendicular to a first surface of a semiconductor substrate or a semiconductor body.

在下述描述中所使用的用語「晶圓」、「基板」或「半導體基板」可包括具有半導體表面的任何半導體基礎結構。晶圓以及結構被了解為包括矽、絕緣體上矽（SOI）、藍寶石上矽（SOS）、摻雜以及未摻雜半導體、由基礎半導體基座支撐的矽磊晶層、以及其他的半導體結構。半導體不需要是矽基礎的。半導體也可為矽-鍺、鍺、或砷化鎵。根據其他的實施方式、碳化矽（SiC）或氮化鎵（GaN）可形成半導體基板材料。The terms "wafer", "substrate" or "semiconductor substrate" used in the following description may include any semiconductor infrastructure having a semiconductor surface. Wafers and structures are known to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, silicon epitaxial layers supported by a base semiconductor base, and other semiconductor structures. Semiconductors need not be silicon-based. The semiconductor may also be silicon-germanium, germanium, or gallium arsenide. According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form a semiconductor substrate material.

本說明書提及半導體部分摻雜所用之「第一」以及「第二」傳導類型的摻雜物。第一傳導類型可為p型且第二傳導類型可為n型或反過來。如一般所知的，取決於摻雜類型或源極與汲極區域的極性，例如金屬氧化物半導體場效應電晶體（MOSFET）之類的絕緣閘極場效應電晶體（IGFET）可為n通道或p-通道MOSFET。例如，在n通道MOSFET中，源極以及汲極區域摻雜有n型摻雜物。在p通道MOSFET中，源極以及汲極區域摻雜有p型摻雜物。如同要清楚了解的，在本說明書的上下文內，摻雜類型可為相反的。如果使用方向性語言來描述特定的電流路徑，此描述僅被了解用以指出路徑且非電流的極性，即電流是否從源極流至汲極或反過來。圖式可包括極性敏感組件，例如二極體。如同要清楚了解的，這些極性敏感組件的特定配置被給出作為範例，且取決於第一傳導類型是否意指n型或p型而可為顛倒的以達成所描述的功能性。This specification refers to dopants of the "first" and "second" conductivity type used for semiconductor partial doping. The first conductivity type may be p-type and the second conductivity type may be n-type or vice versa. As generally known, depending on the type of doping or the polarity of the source and drain regions, an insulated gate field effect transistor (IGFET) such as a metal oxide semiconductor field effect transistor (MOSFET) can be an n-channel Or p-channel MOSFET. For example, in an n-channel MOSFET, the source and drain regions are doped with n-type dopants. In a p-channel MOSFET, the source and drain regions are doped with a p-type dopant. As should be clearly understood, the type of doping may be reversed within the context of this specification. If directional language is used to describe a specific current path, this description is only understood to indicate the path and not the polarity of the current, ie whether the current flows from the source to the drain or vice versa. The schema may include polarity sensitive components, such as diodes. As should be clearly understood, the specific configuration of these polarity sensitive components is given as an example, and depending on whether the first conductivity type means n-type or p-type may be reversed to achieve the described functionality.

在下述中，將描述包含在半導體基板中的電晶體（例如功率電晶體）的半導體裝置的元件。下述描述將特別地著重在設置於電晶體漂移區中的元件。如會容易被領略的，電晶體包含例如閘極電極、源極區域、汲極區域以及本體區域之類的進一步元件。如會清楚了解的，可以各種方式實施這些元件，以形成MOSFET（「金屬氧化物半導體場效應電晶體」）、IGBT（「包含絕緣閘極的雙極電晶體」）以及其他。In the following, elements of a semiconductor device of a transistor (such as a power transistor) contained in a semiconductor substrate will be described. The following description will focus specifically on the elements provided in the transistor drift region. As will be readily appreciated, the transistor includes further elements such as a gate electrode, a source region, a drain region, and a body region. As will be clearly understood, these elements can be implemented in various ways to form MOSFETs ("metal oxide semiconductor field effect transistors"), IGBTs ("bipolar transistors with insulated gates"), and others.

第1A圖示出了根據一個實施方式包含電晶體的半導體裝置的水平截面圖。如將在下述中解釋的，包含電晶體的半導體裝置被形成在半導體基板中。半導體裝置包含鄰接於汲極區域205的第一傳導類型的漂移區259。電晶體進一步包含第一場板250以及鄰接於漂移區的第二場板252。第二場板252被設置在第一場板250以及汲極區域205之間。第一以及第二場板被配置在第一方向中，例如x方向。第二場板電連接至被配置在漂移區259中的接觸部分。半導體裝置進一步包含低於漂移區的較低摻雜濃度的第一傳導類型的中間區域261。中間部分被配置在接觸部分以及汲極區域205之間。FIG. 1A illustrates a horizontal cross-sectional view of a semiconductor device including a transistor according to an embodiment. As will be explained below, a semiconductor device including a transistor is formed in a semiconductor substrate. The semiconductor device includes a first conductivity type drift region 259 adjacent to the drain region 205. The transistor further includes a first field plate 250 and a second field plate 252 adjacent to the drift region. The second field plate 252 is disposed between the first field plate 250 and the drain region 205. The first and second field plates are arranged in a first direction, for example, the x direction. The second field plate is electrically connected to a contact portion arranged in the drift region 259. The semiconductor device further includes a first conductive type intermediate region 261 having a lower doping concentration than the drift region. The middle portion is disposed between the contact portion and the drain region 205.

第1A圖中所示的電晶體包含第一傳導類型（例如n型）的源極區域201以及第一傳導類型的汲極區域205。源極區域201以及汲極區域205可沿著平行於半導體基板主要表面的第一方向（例如x方向）被配置。第二傳導類型（例如p型）的本體區域220可被設置鄰接於源極區域201。閘極電極210被設置鄰接於本體區域220，閘極電極210利用閘極介電層211與本體區域220絕緣。The transistor shown in FIG. 1A includes a source region 201 of a first conductivity type (eg, n-type) and a drain region 205 of the first conductivity type. The source region 201 and the drain region 205 may be arranged along a first direction (for example, the x direction) parallel to the main surface of the semiconductor substrate. The body region 220 of the second conductivity type (for example, p-type) may be disposed adjacent to the source region 201. The gate electrode 210 is disposed adjacent to the body region 220, and the gate electrode 210 is insulated from the body region 220 by a gate dielectric layer 211.

漂移區259被設置在本體區域220以及汲極區域205之間。漂移區259以低於汲極區域205的較低摻雜濃度的第一傳導類型摻雜。半導體裝置包含沿著第一方向被配置在本體區域以及汲極區域205之間的第一場板250以及第二場板252，以鄰接於漂移區259。第一以及第二場板分別利用場介電層249、253與漂移區259絕緣。第二場板252電連接至配置在漂移區中的接觸部分263。例如，接觸部分263可藉由具有高於漂移區259的較高摻雜濃度的第一傳導類型的摻雜部分來實施。The drift region 259 is provided between the body region 220 and the drain region 205. The drift region 259 is doped with a first conductivity type having a lower doping concentration than the drain region 205. The semiconductor device includes a first field plate 250 and a second field plate 252 disposed between the body region and the drain region 205 along the first direction so as to be adjacent to the drift region 259. The first and second field plates are insulated from the drift region 259 by the field dielectric layers 249, 253, respectively. The second field plate 252 is electrically connected to a contact portion 263 arranged in the drift region. For example, the contact portion 263 may be implemented by a doped portion of a first conductivity type having a higher doping concentration than the drift region 259.

當例如藉由將相對應的電壓施加至閘極電極210來打開電晶體時，在本體區域220以及閘極介電層211之間的邊界形成傳導反轉層。因此，電晶體處於傳導狀態。當例如藉由將相對應的電壓施加至閘極電極210來關閉電晶體時，在本體區域220以及閘極介電層211之間的界面沒有形成傳導通道。此外，由於場板的存在，漂移區的載體被補償。根據第1A圖中所示的實施方式，第一場板250可電連接至源極端151。因此，第一場板250可被維持在源極電位。此外，第二場板252電連接至配置在漂移區259中的接觸部分。因此，第二場板252不被維持在固定電位，但被維持在取決於橫跨漂移區259的壓降的可變電位。因此，相較於第二場板252被維持在源極電位的例子，可降低第二場板252以及汲極區域205之間的壓降、並因此降低電場的強度。因此，可降低場介電層249、253的厚度，導致漂移區的增加寬度。此外，相較於傳統裝置，可增加漂移區259的摻雜濃度。因此，可進一步降低通路狀態電阻Ron x A。When the transistor is turned on, for example, by applying a corresponding voltage to the gate electrode 210, a conduction inversion layer is formed at a boundary between the body region 220 and the gate dielectric layer 211. Therefore, the transistor is in a conductive state. When the transistor is turned off, for example, by applying a corresponding voltage to the gate electrode 210, no conductive channel is formed at the interface between the body region 220 and the gate dielectric layer 211. In addition, due to the presence of the field plate, the carrier in the drift region is compensated. According to the embodiment shown in FIG. 1A, the first field plate 250 may be electrically connected to the source terminal 151. Therefore, the first field plate 250 may be maintained at a source potential. In addition, the second field plate 252 is electrically connected to a contact portion disposed in the drift region 259. Therefore, the second field plate 252 is not maintained at a fixed potential, but is maintained at a variable potential depending on the voltage drop across the drift region 259. Therefore, compared with the case where the second field plate 252 is maintained at the source potential, the voltage drop between the second field plate 252 and the drain region 205 can be reduced, and thus the strength of the electric field can be reduced. Therefore, the thickness of the field dielectric layers 249 and 253 can be reduced, resulting in an increased width of the drift region. In addition, compared with the conventional device, the doping concentration of the drift region 259 can be increased. Therefore, the on-state resistance Ron x A can be further reduced.

如所示出的，第二場板252經由傳導元件264電連接至接觸部分263。例如，接觸部分263可藉由第一傳導類型的重度摻雜部分來實施。傳導元件264可藉由金屬或重度摻雜的多晶矽構件來實施。接觸部分263可被配置在第一以及第二場板250、252之間。例如，接觸部分263可沿著第二方向（例如y方向）具有側向延伸，其小於第一場板25的側向延伸。此外，接觸部分263可被配置以不延伸超過第一以及第二場板250、252。此外，第一以及第二場板可沿著第一方向對準。例如，第一以及第二場板250、252可具有在正交於第一方向的側向方向中（例如在y方向中）測量的相同寬度。As shown, the second field plate 252 is electrically connected to the contact portion 263 via the conductive element 264. For example, the contact portion 263 may be implemented by a heavily doped portion of the first conductivity type. The conductive element 264 may be implemented by a metal or a heavily doped polycrystalline silicon structure. The contact portion 263 may be disposed between the first and second field plates 250 and 252. For example, the contact portion 263 may have a lateral extension along the second direction (eg, the y direction), which is smaller than the lateral extension of the first field plate 25. In addition, the contact portion 263 may be configured not to extend beyond the first and second field plates 250, 252. In addition, the first and second field plates may be aligned along a first direction. For example, the first and second field plates 250, 252 may have the same width as measured in a lateral direction orthogonal to the first direction (eg, in the y direction).

當接觸部分263不延伸超過第一以及第二場板250、252時，橫跨漂移區259的載體之流動可不受接觸部分263的存在所擾亂。處於低於漂移區的較低摻雜濃度的第一傳導類型的中間部分261可被配置在接觸部分263以及汲極區域205之間。例如，中間部分可被設置在第一以及第二場板250、252之間的區域，且可與第一場板250及/或第二場板252重疊。根據進一步的實施方式，中間部分261不與第一場板250重疊。接觸部分263可被配置鄰接於中間部分261。根據進一步的實施方式，漂移區259可包含第一漂移區部分260、第二漂移區部分262以及被配置在第一漂移區部分260以及第二漂移區部分262之間的中間部分261。第一漂移區部分260可被配置鄰接於第一場板251，且第二漂移區部分262可被配置鄰接於第二場板252。When the contact portion 263 does not extend beyond the first and second field plates 250, 252, the flow of the carrier across the drift region 259 may not be disturbed by the presence of the contact portion 263. The intermediate portion 261 of the first conductivity type at a lower doping concentration lower than the drift region may be disposed between the contact portion 263 and the drain region 205. For example, the middle portion may be disposed in a region between the first and second field plates 250, 252 and may overlap the first field plate 250 and / or the second field plate 252. According to a further embodiment, the middle portion 261 does not overlap the first field plate 250. The contact portion 263 may be configured to be adjacent to the intermediate portion 261. According to a further embodiment, the drift region 259 may include a first drift region portion 260, a second drift region portion 262, and an intermediate portion 261 disposed between the first drift region portion 260 and the second drift region portion 262. The first drift region portion 260 may be configured to be adjacent to the first field plate 251, and the second drift region portion 262 may be configured to be adjacent to the second field plate 252.

由於中間部分的存在，可產生第二場板252的電位以及汲極電位之間的電壓差。因此，可有效率地補償鄰接於第二場板252的第二漂移區部分262。Due to the existence of the middle portion, a voltage difference between the potential of the second field plate 252 and the drain potential can be generated. Therefore, the second drift region portion 262 adjacent to the second field plate 252 can be efficiently compensated.

根據第1A圖的實施方式，閘極電極210被設置以沿著第二方向位在兩個鄰接第一場板250之間的位置。本體區域220可經由本體接觸部分225電連接至被設置鄰接於源極區域201的源極接觸溝槽207的傳導填充物150。汲極區域205電連接至填充例如汲極接觸溝槽208的汲極接觸填充物152。According to the embodiment of FIG. 1A, the gate electrode 210 is disposed at a position between two adjacent first field plates 250 in the second direction. The body region 220 may be electrically connected to the conductive filler 150 disposed adjacent to the source contact trench 207 of the source region 201 via the body contact portion 225. The drain region 205 is electrically connected to a drain contact fill 152 that fills, for example, a drain contact trench 208.

第1B圖示出了第1A圖中所示的半導體裝置的垂直截面圖。半導體裝置1被形成在具有第一主要表面110的半導體基板100中。例如，半導體基板100可包含可具有第二傳導類型的基板層130。第一傳導類型的埋層131可被形成在基板層130上，接著形成第一傳導類型的磊晶層132。如第1B圖中進一步所示，可在磊晶層132中形成第一傳導類型的井部分133。此外，可在磊晶層132中形成第二傳導類型的井部分134。閘極電極210可被配置在由虛線指出的閘極溝槽212中，且可被形成在圖式中所繪的平面之前以及之後的平面中。如第1B圖中所指出，閘極電極210在深度方向（例如z方向）中延伸。本體區域220被配置在第二傳導類型的井部分134中。第一傳導類型的源極區域201可被形成以在深度方向中延伸。例如，源極區域201可形成源極接觸溝槽207的摻雜側壁。例如，如第1A圖中所指出，源極接觸溝槽207的側壁可交替地以不同的傳導類型摻雜，以交替地形成第一傳導類型的源極區域201以及第二傳導類型的本體接觸部分225。根據一個實施方式，本體接觸部分225可被形成在源極接觸溝槽207的底側。源極接觸填充物，例如例如金屬或重度摻雜多晶矽之類的傳導材料可被填充於源極接觸溝槽207中。源極接觸填充物150電連接至源極端151。根據進一步的實施方式，源極接觸溝槽可進一步延伸於半導體基板的深度方向中。例如，源極接觸可被配置鄰接於第二主要表面120，且沒有電接觸可被設置鄰接於第一主要表面110。根據此實施方式，源極區域201至源極端151的接觸可被實施為背側接觸。FIG. 1B is a vertical cross-sectional view of the semiconductor device shown in FIG. 1A. The semiconductor device 1 is formed in a semiconductor substrate 100 having a first main surface 110. For example, the semiconductor substrate 100 may include a substrate layer 130 that may have a second conductivity type. A buried layer 131 of a first conductivity type may be formed on the substrate layer 130, and then an epitaxial layer 132 of a first conductivity type is formed. As further shown in FIG. 1B, a well portion 133 of a first conductivity type may be formed in the epitaxial layer 132. In addition, a well portion 134 of a second conductivity type may be formed in the epitaxial layer 132. The gate electrode 210 may be configured in a gate trench 212 indicated by a dotted line, and may be formed in a plane before and after a plane drawn in the drawing. As indicated in FIG. 1B, the gate electrode 210 extends in a depth direction (for example, the z direction). The body region 220 is configured in the well portion 134 of the second conductivity type. The source region 201 of the first conductivity type may be formed to extend in the depth direction. For example, the source region 201 may form a doped sidewall of the source contact trench 207. For example, as indicated in Figure 1A, the sidewalls of the source contact trench 207 may be alternately doped with different conductivity types to alternately form source regions 201 of the first conductivity type and body contacts of the second conductivity type Section 225. According to one embodiment, the body contact portion 225 may be formed on the bottom side of the source contact trench 207. A source contact fill, such as a conductive material such as a metal or heavily doped polycrystalline silicon, may be filled in the source contact trench 207. The source contact filler 150 is electrically connected to the source terminal 151. According to a further embodiment, the source contact trench may further extend in a depth direction of the semiconductor substrate. For example, a source contact may be configured to abut the second major surface 120, and no electrical contact may be provided to abut the first major surface 110. According to this embodiment, the contact from the source region 201 to the source terminal 151 may be implemented as a backside contact.

如第1B圖中進一步示出的，漂移區259可被配置在第一傳導類型的磊晶層132中。漂移區259可包含由中間部分261彼此分開的第一漂移區部分260以及第二漂移區部分262，中間部分261形成部分的第一傳導類型的磊晶層132。As further shown in FIG. 1B, the drift region 259 may be configured in the epitaxial layer 132 of the first conductivity type. The drift region 259 may include a first drift region portion 260 and a second drift region portion 262 that are separated from each other by an intermediate portion 261, and the intermediate portion 261 forms a portion of the epitaxial layer 132 of the first conductivity type.

如第1B圖中進一步示出的，第一場板250可被配置在第一場板溝槽251中，且第二場板252可被配置在第二場板溝槽254中。第一以及第二場板溝槽251、254被形成在第一主要表面110中，且由第1B圖中的虛線指出。第一場板250以及第二場板252可具有在第一方向中測量的相同長度。然而，根據進一步的實施方式，第一場板的長度可與第二場板的長度不同。藉由設定第一場板的長度，第二場板252以及汲極區域205之間的電位差可以自控的方式確定。如第1B圖中所指出的，第一場板溝槽251以及第二場板溝槽254可延伸至第一傳導類型的井部分133內的深度。根據進一步的實施方式，第一場板溝槽251以及第二場板溝槽254可延伸更深，例如至磊晶層132。As further shown in FIG. 1B, the first field plate 250 may be configured in the first field plate trench 251, and the second field plate 252 may be configured in the second field plate trench 254. First and second field plate trenches 251, 254 are formed in the first major surface 110, and are indicated by dashed lines in FIG. 1B. The first field plate 250 and the second field plate 252 may have the same length as measured in the first direction. However, according to a further embodiment, the length of the first field plate may be different from the length of the second field plate. By setting the length of the first field plate, the potential difference between the second field plate 252 and the drain region 205 can be determined in a self-controlled manner. As indicated in FIG. 1B, the first field plate trench 251 and the second field plate trench 254 may extend to a depth within the well portion 133 of the first conductivity type. According to a further embodiment, the first field plate trench 251 and the second field plate trench 254 may extend deeper, for example, to the epitaxial layer 132.

汲極區域205可由汲極接觸溝槽208的摻雜側壁部分來實施。汲極接觸溝槽208可由汲極接觸材料152填充，汲極接觸材料152可為例如金屬或重度摻雜多晶矽材料。汲極接觸材料152電連接至汲極端153。根據實施方式，汲極端153可電連接至在半導體基板的第一主要表面110的汲極接觸材料152。根據進一步的實施方式，汲極接觸溝槽208可深入地延伸至半導體基板中，且汲極端153可電連接至半導體基板的背側或第二主要表面120。例如，汲極區域205至汲極端153的接觸可被實施為背側接觸。The drain region 205 may be implemented by a doped sidewall portion of the drain contact trench 208. The drain contact trench 208 may be filled by a drain contact material 152, which may be, for example, a metal or a heavily doped polycrystalline silicon material. The drain contact material 152 is electrically connected to the drain terminal 153. According to an embodiment, the drain terminal 153 may be electrically connected to the drain contact material 152 on the first major surface 110 of the semiconductor substrate. According to a further embodiment, the drain contact trench 208 may extend deeply into the semiconductor substrate, and the drain terminal 153 may be electrically connected to the back side or the second major surface 120 of the semiconductor substrate. For example, the contact from the drain region 205 to the drain terminal 153 may be implemented as a backside contact.

第1C圖示出了被設置在閘極溝槽212中的閘極電極210的配置範例。在III以及III'之間取得第1C圖的截面圖，以相交多個閘極溝槽212。如第1C圖中所示，閘極電極210可被設置鄰接於本體區域220的側壁。因此，傳導通道215可被設置鄰接於本體區域的側壁220b以及鄰接於本體區域220的頂側220a。FIG. 1C illustrates a configuration example of the gate electrode 210 provided in the gate trench 212. A cross-sectional view of FIG. 1C is obtained between III and III ′ to intersect a plurality of gate trenches 212. As shown in FIG. 1C, the gate electrode 210 may be disposed adjacent to a sidewall of the body region 220. Therefore, the conductive passage 215 may be provided adjacent to the side wall 220b of the body region and the top side 220a adjacent to the body region 220.

第1D圖示出了II以及II'之間的半導體裝置截面圖，以相交第一場板溝槽251以及第二場板溝槽254。與第1B圖中所示的截面圖不同，第二傳導類型的本體接觸部分225被設置在鄰接於源極接觸溝槽207的側壁。此外，第一場板溝槽251以及第二場板溝槽254被配置在半導體基板的第一主要表面110，並以傳導材料填充。接觸部分263被設置在第一場板溝槽251以及第二場板溝槽254之間。FIG. 1D shows a cross-sectional view of the semiconductor device between II and II ′ to intersect the first field plate trench 251 and the second field plate trench 254. Unlike the cross-sectional view shown in FIG. 1B, the body contact portion 225 of the second conductivity type is provided on a side wall adjacent to the source contact trench 207. In addition, the first field plate trench 251 and the second field plate trench 254 are disposed on the first main surface 110 of the semiconductor substrate and filled with a conductive material. The contact portion 263 is provided between the first field plate trench 251 and the second field plate trench 254.

第1E圖示出了半導體裝置的進一步實施方式。與第1A圖中所示的實施方式不同，閘極電極210被實施為平面閘極電極。特別地，閘極電極210整個被設置在半導體基板的第一主要表面110上。此外，源極接觸填充物150不被設置在形成於半導體基板100中的源極接觸溝槽中，但被設置在半導體基板100的第一主要表面110上。以相對應的方式，汲極接觸填充物被設置在半導體基板100上，且不延伸至半導體基板100中。FIG. 1E shows a further embodiment of the semiconductor device. Unlike the embodiment shown in FIG. 1A, the gate electrode 210 is implemented as a planar gate electrode. Specifically, the gate electrode 210 is entirely provided on the first main surface 110 of the semiconductor substrate. In addition, the source contact filler 150 is not provided in the source contact trench formed in the semiconductor substrate 100, but is provided on the first main surface 110 of the semiconductor substrate 100. In a corresponding manner, the drain contact filler is disposed on the semiconductor substrate 100 and does not extend into the semiconductor substrate 100.

第2A圖以及第2B圖示出了根據進一步實施方式的半導體裝置的視圖。如下述中將解釋的，在第2A圖以及第2B圖中示出的半導體裝置包含電晶體，電晶體包含由第一傳導類型材料構成的漂移區270。半導體裝置進一步包含第一場板280、第二場板283以及第三場板286。電晶體進一步包含在漂移區270中的第一接觸部分273。第一、第二以及第三場板以離源極區域201不同的距離在第一方向中被配置在漂移區270中。第三場板286至源極區域201的距離大於第一280或第二場板283至源極區域201的距離。此外，第三場板286電連接至第一接觸部分273。2A and 2B illustrate views of a semiconductor device according to a further embodiment. As will be explained later, the semiconductor device shown in FIGS. 2A and 2B includes a transistor including a drift region 270 made of a first conductive type material. The semiconductor device further includes a first field plate 280, a second field plate 283, and a third field plate 286. The transistor further includes a first contact portion 273 in the drift region 270. The first, second, and third field plates are disposed in the drift region 270 in the first direction at different distances from the source region 201. The distance from the third field plate 286 to the source region 201 is greater than the distance from the first 280 or the second field plate 283 to the source region 201. In addition, the third field plate 286 is electrically connected to the first contact portion 273.

第2A圖中所示的電晶體包含與第1A圖中所示的電晶體類似的元件，例如源極區域201、本體接觸部分225、源極接觸填充物150、本體區域220、閘極電極210以及汲極區域205，以至於將省略其詳細的描述。與第1A圖以及第1B圖中所示的實施方式不同，電晶體包含可例如電連接至源極端151的第一場板280以及第二場板283。此外，可例如被設置在第二場板286以及汲極區域205之間的第三場板287電連接至被配置在漂移區中的第一接觸部分273。例如，第一接觸部分273可被設置在第一場板280以及第二場板283之間。以如同已在上述參照第1A圖討論的類似方式，第一接觸部分263可被配置以至於其不沿著第二方向（例如y方向）延伸超過第一場板280以及第二場板283。因此，第一接觸部分273不影響漂移區270的可操作性。第一接觸部分可以如同已在上述參照第1A圖至第1E圖討論的類似方式藉由第一傳導類型的重度摻雜部分來實施。根據進一步的實施方式，第一接觸部分可被配置在鄰接於本體區域220的第一場板280的一側上。根據一個實施方式，第一、第二以及第三場板280、283以及286可具有在第二側向方向中（例如在y方向中）測量的相同寬度。The transistor shown in FIG. 2A includes elements similar to the transistor shown in FIG. 1A, such as the source region 201, the body contact portion 225, the source contact filler 150, the body region 220, and the gate electrode 210. And the drain region 205, so that a detailed description thereof will be omitted. Unlike the embodiment shown in FIGS. 1A and 1B, the transistor includes a first field plate 280 and a second field plate 283 that can be electrically connected to the source terminal 151, for example. Further, for example, a third field plate 287 which may be disposed between the second field plate 286 and the drain region 205 is electrically connected to the first contact portion 273 arranged in the drift region. For example, the first contact portion 273 may be disposed between the first field plate 280 and the second field plate 283. In a similar manner as has been discussed above with reference to FIG. 1A, the first contact portion 263 may be configured so that it does not extend beyond the first field plate 280 and the second field plate 283 in a second direction (eg, the y direction). Therefore, the first contact portion 273 does not affect the operability of the drift region 270. The first contact portion may be implemented by a heavily doped portion of the first conductivity type in a manner similar to that discussed above with reference to FIGS. 1A to 1E. According to a further embodiment, the first contact portion may be configured on a side of the first field plate 280 adjacent to the body region 220. According to one embodiment, the first, second, and third field plates 280, 283, and 286 may have the same width as measured in the second lateral direction (eg, in the y-direction).

第2B圖示出了第2A圖中所示的半導體裝置的垂直截面圖。在第2B圖中，與第1B圖中所示相同的元件由相同的元件符號標示，且為了簡單，將省略其詳細描述。根據第2B圖的實施方式，漂移區270可缺少較低摻雜濃度的中間部分261。此外，漂移區270由第一傳導類型的材料構成。在本揭露內容的上下文內，用語「由第一傳導類型材料構成的漂移區」意欲意指，漂移區不包含第二傳導類型的部分。如第2A圖以及第2B圖中所示，第一傳導類型的第一接觸部分以及場板可被配置在漂移區270中。場板可被配置在形成在半導體基板100的第一主要表面110中的相對應的場板溝槽282、285、288中。場板溝槽282、285、288由虛線指出，且被配置在所示圖式平面之前以及之後。例如，第一場板280以及第二場板283可具有在第一方向中測量的相同長度。此外，第一以及第二場板的長度可小於第三場板286的長度。以如同已參照第1B圖所解釋的相對應方式，藉由設定場板溝槽的長度，第三場板286以及汲極區域205之間的電位差可以自控的方式設定。FIG. 2B is a vertical cross-sectional view of the semiconductor device shown in FIG. 2A. In FIG. 2B, the same elements as those shown in FIG. 1B are denoted by the same element symbols, and a detailed description thereof will be omitted for simplicity. According to the embodiment of FIG. 2B, the drift region 270 may lack the middle portion 261 with a lower doping concentration. In addition, the drift region 270 is made of a first conductivity type material. In the context of this disclosure, the term "drift region composed of a material of a first conductivity type" is intended to mean that the drift region does not include a portion of a second conductivity type. As shown in FIGS. 2A and 2B, the first contact portion of the first conductivity type and the field plate may be disposed in the drift region 270. The field plates may be arranged in corresponding field plate trenches 282, 285, 288 formed in the first major surface 110 of the semiconductor substrate 100. The field plate trenches 282, 285, 288 are indicated by dashed lines and are arranged before and after the illustrated plane. For example, the first field plate 280 and the second field plate 283 may have the same length as measured in the first direction. In addition, the length of the first and second field plates may be smaller than the length of the third field plate 286. In a corresponding manner as already explained with reference to FIG. 1B, by setting the length of the field plate trench, the potential difference between the third field plate 286 and the drain region 205 can be set in a self-controlled manner.

根據一個實施方式，漂移區270不包含低較摻雜濃度的中間部分261。因此，可進一步降低電晶體的通路狀態電阻。例如，當第一接觸部分273被設置在第一場板280以及第二場板283之間時，可達成在第三場板的電位以及汲極電位之間的想要差異，以至於鄰接於第三場板286的漂移區可被有效率地補償。第三場板286可利用第一傳導元件275電連接至第一接觸部分273，第一傳導元件275可由金屬構件或重度摻雜多晶矽的構件來實施。According to one embodiment, the drift region 270 does not include a middle portion 261 with a lower doping concentration. Therefore, the on-state resistance of the transistor can be further reduced. For example, when the first contact portion 273 is disposed between the first field plate 280 and the second field plate 283, a desired difference between the potential of the third field plate and the drain potential can be achieved so as to be adjacent to The drift region of the third field plate 286 can be efficiently compensated. The third field plate 286 may be electrically connected to the first contact portion 273 by using a first conductive element 275, and the first conductive element 275 may be implemented by a metal member or a member heavily doped with polycrystalline silicon.

可將參照第2A圖以及第2B圖解釋的概念延伸至包含進一步場板的半導體裝置。例如，如第3A圖以及第3B圖中所示，半導體裝置可進一步包含可例如利用第二傳導元件276電連接至第二接觸部分274的第四場板289。第二場板289可利用第二場介電層290與漂移區270絕緣。如第3B圖中所示，第四場板289可被配置在第四場板溝槽291中。第二接觸部分274可被配置在第二場板283以及第三場板286之間。The concept explained with reference to FIGS. 2A and 2B can be extended to a semiconductor device including a further field plate. For example, as shown in FIGS. 3A and 3B, the semiconductor device may further include a fourth field plate 289 that can be electrically connected to the second contact portion 274 using, for example, the second conductive element 276. The second field plate 289 may be insulated from the drift region 270 using the second field dielectric layer 290. As shown in FIG. 3B, the fourth field plate 289 may be disposed in the fourth field plate trench 291. The second contact portion 274 may be disposed between the second field plate 283 and the third field plate 286.

根據第4A圖以及第4B圖中所示的實施方式，半導體裝置進一步包含第五場板292。根據進一步的修飾，與之前示出的實施方式不同，第一接觸部分273可被配置在第一場板280以及本體區域220之間。以相對應的方式，第二接觸部分被配置在第一場板280以及第二場板283之間。第三接觸部分278被配置在第二場板283以及第三場板286之間。因此，可進一步增加各自場板以及汲極區域205之間的電位差，導致鄰接於各自場板的漂移區部分的更有效率的補償。根據進一步的實施方式，半導體裝置包含第五場板292，且第一接觸部分以如同已參照第3A圖以及第3B圖所描述的類似方式被配置在第一場板280以及第二場板283之間。According to the embodiment shown in FIGS. 4A and 4B, the semiconductor device further includes a fifth field plate 292. According to a further modification, unlike the embodiment shown previously, the first contact portion 273 may be disposed between the first field plate 280 and the body region 220. In a corresponding manner, the second contact portion is disposed between the first field plate 280 and the second field plate 283. The third contact portion 278 is disposed between the second field plate 283 and the third field plate 286. Therefore, the potential difference between the respective field plates and the drain regions 205 can be further increased, resulting in more efficient compensation of the drift region portions adjacent to the respective field plates. According to a further embodiment, the semiconductor device includes a fifth field plate 292, and the first contact portion is configured on the first field plate 280 and the second field plate 283 in a similar manner as described with reference to FIGS. 3A and 3B. between.

第5A圖示出了根據一個實施方式的積體電路20的示意性水平截面圖。積體電路20包含可形成在單一半導體基板100中的第一功率電晶體10以及第二功率電晶體15。例如，可以如同已參照第1A圖至第1E圖所描述的方式來實施第一電晶體10。為第5A圖的積體電路20的組件的第一電晶體10的組件可具有已參照第1A圖至第1E圖描述的相對應元件，以至於省略了其詳細的描述。例如，可選擇漂移區259的長度以達成相對應第一電壓等級的崩潰特徵。第二電晶體15可與第一電晶體10不同。例如，第二電晶體15可包含沿著漂移區559延伸的單一場板550。可選擇第二電晶體15的漂移區559的長度以達成相對應第二電壓等級的崩潰特徵。例如，第二電晶體的漂移區559的長度可比第一電晶體10的漂移區259的長度短。根據一個實施方式，可使用共同或聯合的處理方法來形成第一以及第二電晶體。例如，第一電晶體10的漂移區259以及第二電晶體15的漂移區559可具有相同的摻雜程度。此外，第一電晶體10的第一場介電層249以及第二場介電層253的厚度可等於第二電晶體15的場介電層551的厚度。因此，可使用簡化的製程來製造包含第一電晶體10以及第二電晶體15（每個具有不同的崩潰特徵）的積體電路20。FIG. 5A shows a schematic horizontal cross-sectional view of the integrated circuit 20 according to an embodiment. The integrated circuit 20 includes a first power transistor 10 and a second power transistor 15 that can be formed in a single semiconductor substrate 100. For example, the first transistor 10 may be implemented in the same manner as has been described with reference to FIGS. 1A to 1E. The components of the first transistor 10, which are the components of the integrated circuit 20 of FIG. 5A, may have corresponding components that have been described with reference to FIGS. 1A to 1E, so that detailed descriptions thereof are omitted. For example, the length of the drift region 259 may be selected to achieve a collapse characteristic corresponding to the first voltage level. The second transistor 15 may be different from the first transistor 10. For example, the second transistor 15 may include a single field plate 550 extending along the drift region 559. The length of the drift region 559 of the second transistor 15 can be selected to achieve the collapse characteristic corresponding to the second voltage level. For example, the length of the drift region 559 of the second transistor may be shorter than the length of the drift region 259 of the first transistor 10. According to one embodiment, the first and second transistors may be formed using a common or combined processing method. For example, the drift region 259 of the first transistor 10 and the drift region 559 of the second transistor 15 may have the same degree of doping. In addition, the thickness of the first field dielectric layer 249 and the second field dielectric layer 253 of the first transistor 10 may be equal to the thickness of the field dielectric layer 551 of the second transistor 15. Therefore, the integrated circuit 20 including the first transistor 10 and the second transistor 15 (each having different breakdown characteristics) can be manufactured using a simplified process.

第5B圖示出了根據進一步實施方式的積體電路20的示意性水平截面圖。積體電路20包含可形成在單一半導體基板100中的第一功率電晶體25以及第二功率電晶體30。例如，可以如同已參照第2A圖至第4B圖所描述的方式來實施第一電晶體25。為第5B圖的積體電路20的組件的第一電晶體25的組件可具有已參照第2A圖至第4B圖所描述的相對應元件，以至於省略了其詳細描述。例如，可選擇漂移區259的長度以達成相對應第一電壓等級的崩潰特徵。第二電晶體30可與第一電晶體25不同。例如，第二電晶體30可包含沿著漂移區659延伸的單一場板650。可選擇第二電晶體30的漂移區659的長度以達成相對應第二電壓等級的崩潰特徵。例如，第二電晶體30的漂移區659的長度可比第一電晶體10的漂移區259的長度短。根據一個實施方式，可使用共同或聯合的處理方法來形成第一以及第二電晶體。例如，第一電晶體25的漂移區259以及第二電晶體30的漂移區659可具有相同的摻雜程度。此外，第一電晶體25的第一場介電層281、第二場介電層284以及第三場介電層287的厚度可等於第二電晶體30的場介電層651的厚度。因此，可使用簡化的製程來製造包含第一電晶體25以及第二電晶體30（每個具有不同的崩潰特徵）的積體電路20。FIG. 5B shows a schematic horizontal cross-sectional view of the integrated circuit 20 according to a further embodiment. The integrated circuit 20 includes a first power transistor 25 and a second power transistor 30 that can be formed in a single semiconductor substrate 100. For example, the first transistor 25 may be implemented as described with reference to FIGS. 2A to 4B. The components of the first transistor 25 which are the components of the integrated circuit 20 of FIG. 5B may have corresponding components already described with reference to FIGS. 2A to 4B, so that detailed descriptions thereof are omitted. For example, the length of the drift region 259 may be selected to achieve a collapse characteristic corresponding to the first voltage level. The second transistor 30 may be different from the first transistor 25. For example, the second transistor 30 may include a single field plate 650 extending along the drift region 659. The length of the drift region 659 of the second transistor 30 may be selected to achieve a collapse characteristic corresponding to the second voltage level. For example, the length of the drift region 659 of the second transistor 30 may be shorter than the length of the drift region 259 of the first transistor 10. According to one embodiment, the first and second transistors may be formed using a common or combined processing method. For example, the drift region 259 of the first transistor 25 and the drift region 659 of the second transistor 30 may have the same degree of doping. In addition, the thickness of the first field dielectric layer 281, the second field dielectric layer 284, and the third field dielectric layer 287 of the first transistor 25 may be equal to that of the field dielectric layer 651 of the second transistor 30. Therefore, the integrated circuit 20 including the first transistor 25 and the second transistor 30 (each having different breakdown characteristics) can be manufactured using a simplified process.

例如，第5A圖以及第5B圖中所示的積體電路20可實施為智能電源應用。積體電路20可用以作為轉換器或驅動器，例如硬碟驅動器。For example, the integrated circuit 20 shown in FIGS. 5A and 5B may be implemented as a smart power application. The integrated circuit 20 can be used as a converter or driver, such as a hard disk drive.

如同本文之前已描述的，半導體裝置包含利用被設置在漂移區中的接觸元件而可電連接至源極端的第一場板以及可電連接至可變電位的進一步場板。因此，可增加漂移區的摻雜濃度，且因此，可顯著地降低電晶體的通路狀態電阻。此外，可降低場介電層的厚度，導致漂移區的增加有效寬度。因此，可進一步增加電晶體的通路狀態電阻。作為一般概念，場板被劃分成包含電連接至源極端的第一場板的數個子場板。進一步的場板可被維持在可變電位。根據進一步的實施方式，第一場板可電連接至與源極端不同的一端。此外，可將具有不同電壓等級的數個電晶體結合在單一積體電路中，而不需對於每個單一電晶體執行額外的處理步驟。As has been described herein before, a semiconductor device includes a first field plate electrically connectable to a source terminal with a contact element disposed in a drift region, and a further field plate electrically connectable to a variable potential. Therefore, the doping concentration of the drift region can be increased, and therefore, the path state resistance of the transistor can be significantly reduced. In addition, the thickness of the field dielectric layer can be reduced, resulting in an increased effective width of the drift region. Therefore, the on-state resistance of the transistor can be further increased. As a general concept, a field plate is divided into several sub-field plates that include a first field plate electrically connected to a source terminal. Further field plates can be maintained at a variable potential. According to a further embodiment, the first field plate may be electrically connected to an end different from the source terminal. In addition, several transistors with different voltage levels can be combined in a single integrated circuit without performing additional processing steps for each single transistor.

雖然已在上述描述了本發明的實施方式，顯而易見的是，可實施進一步的實施方式。例如，進一步的實施方式可包含申請專利範圍中所列舉的任何子組合或上面給出範例中所描述的元件的任何子組合。因此，所附申請專利範圍的精神以及範圍不應限於本文中所包含的實施方式的描述。Although the embodiments of the present invention have been described above, it is apparent that further embodiments can be implemented. For example, further embodiments may include any sub-combination enumerated in the scope of the patent application or any sub-combination of elements described in the examples given above. Therefore, the spirit and scope of the scope of the appended patent applications should not be limited to the description of the embodiments contained herein.

1‧‧‧半導體裝置1‧‧‧ semiconductor device

10、25‧‧‧第一電晶體10.25‧‧‧first transistor

20‧‧‧積體電路20‧‧‧Integrated Circuit

15、30‧‧‧第二電晶體15, 30‧‧‧Second transistor

100‧‧‧半導體基板100‧‧‧ semiconductor substrate

110‧‧‧第一主要表面110‧‧‧ first major surface

120‧‧‧第二主要表面120‧‧‧Second major surface

130‧‧‧基板層130‧‧‧ substrate layer

131‧‧‧埋層131‧‧‧ buried layer

132‧‧‧磊晶層132‧‧‧Epitaxial layer

133‧‧‧第一傳導類型的井部分133‧‧‧well section of the first conductivity type

134‧‧‧第二傳導類型的井部分134‧‧‧well section of the second conductivity type

150‧‧‧傳導填充物150‧‧‧ conductive filler

151‧‧‧源極端151‧‧‧source extreme

152‧‧‧汲極接觸材料152‧‧‧Drain contact material

153‧‧‧汲極端153‧‧‧ Extreme

201‧‧‧源極區域201‧‧‧Source area

205‧‧‧汲極區域205‧‧‧Drain region

207‧‧‧源極接觸溝槽207‧‧‧Source contact trench

208‧‧‧汲極接觸溝槽208‧‧‧ Drain contact trench

210‧‧‧閘極電極210‧‧‧Gate electrode

211‧‧‧閘極介電層211‧‧‧Gate dielectric layer

212‧‧‧閘極溝槽212‧‧‧Gate Trench

215‧‧‧傳導通道215‧‧‧conducting channel

220‧‧‧本體區域220‧‧‧Body area

220a‧‧‧頂側220a‧‧‧Top side

220b‧‧‧側壁220b‧‧‧ sidewall

225‧‧‧本體接觸部分225‧‧‧ body contact part

249、281‧‧‧第一場介電層249, 281‧‧‧‧First field dielectric layer

250、280‧‧‧第一場板250, 280‧‧‧ first game board

251‧‧‧第一場板溝槽251‧‧‧The first field board groove

252、283‧‧‧第二場板252, 283‧‧‧ Second Board

253、284、290‧‧‧第二場介電層253, 284, 290‧‧‧ second field dielectric layer

254‧‧‧第二場板溝槽254‧‧‧Second Field Plate Groove

259、270‧‧‧漂移區259, 270‧‧‧ drift zone

260‧‧‧第一漂移區部分260‧‧‧The first drift zone

261‧‧‧中間區域261‧‧‧Middle area

262‧‧‧第二漂移區部分262‧‧‧Second drift zone

263‧‧‧接觸部分263‧‧‧Contact Section

264、275、276‧‧‧傳導元件264, 275, 276‧‧‧ conductive elements

273‧‧‧第一接觸部分273‧‧‧First contact

274‧‧‧第二接觸部分274‧‧‧Second Contact Section

278‧‧‧第三接觸部分278‧‧‧third contact

282、285、288‧‧‧場板溝槽282, 285, 288

286‧‧‧第三場板286‧‧‧ third board

287‧‧‧第三場介電層287‧‧‧ third field dielectric layer

289‧‧‧第四場板289‧‧‧ Game 4

292‧‧‧第五場板292‧‧‧Game 5

550、650‧‧‧單一場板550, 650‧‧‧ single field board

551、651‧‧‧場介電層551, 651‧‧‧field dielectric layer

559、659‧‧‧漂移區559, 659‧‧‧ drift zone

所附圖式被包括以提供本發明實施方式的進一步了解，並被併入於此說明書中並構成此說明書的一部分。這些圖式示出了本發明的實施方式，並與描述一起用以解釋原理。隨著藉由參照下述詳細描述而更了解本發明的其他實施方式以及許多意欲的優勢，它們將被立即領略。圖式的元件不一定相對於彼此按比例繪示。類似的元件符號標出了相對應的類似部分。 第1A圖示出了示出了根據一個實施方式的半導體裝置的水平截面圖。 第1B圖示出了根據一個實施方式的半導體裝置的垂直截面圖。 第1C圖示出了沿著第二方向取得的半導體裝置的垂直截面圖。 第1D圖示出了第1A圖中所示的半導體裝置的進一步截面圖。 第1E圖示出了第1B圖以及第1D圖中所示的半導體裝置之修飾的截面圖。 第2A圖示出了根據進一步實施方式的半導體裝置的水平截面圖。 第2B圖示出了第2A圖中所示的半導體裝置的垂直截面圖。 第3A圖示出了根據進一步實施方式的半導體裝置的水平截面圖。 第3B圖示出了第3A圖中所示的半導體裝置的垂直截面圖。 第4A圖示出了根據進一步實施方式的半導體裝置的水平截面圖。 第4B圖示出了第4A圖中所示的半導體裝置的垂直截面圖。 第5A圖以及第5B圖示出了根據實施方式的積體電路的示意圖。The drawings are included to provide a better understanding of the embodiments of the invention, and are incorporated in and constitute a part of this specification. These drawings illustrate embodiments of the invention and together with the description serve to explain the principles. As other embodiments of the invention and many of its intended advantages become more understood by reference to the following detailed description, they will be immediately appreciated. Elements of the drawings are not necessarily drawn to scale with respect to each other. Similar component symbols indicate corresponding similar parts. FIG. 1A shows a horizontal cross-sectional view showing a semiconductor device according to an embodiment. FIG. 1B illustrates a vertical cross-sectional view of a semiconductor device according to an embodiment. FIG. 1C shows a vertical cross-sectional view of the semiconductor device taken along the second direction. FIG. 1D shows a further cross-sectional view of the semiconductor device shown in FIG. 1A. FIG. 1E is a cross-sectional view showing a modification of the semiconductor device shown in FIGS. 1B and 1D. FIG. 2A shows a horizontal cross-sectional view of a semiconductor device according to a further embodiment. FIG. 2B is a vertical cross-sectional view of the semiconductor device shown in FIG. 2A. FIG. 3A illustrates a horizontal cross-sectional view of a semiconductor device according to a further embodiment. FIG. 3B is a vertical cross-sectional view of the semiconductor device shown in FIG. 3A. FIG. 4A illustrates a horizontal cross-sectional view of a semiconductor device according to a further embodiment. FIG. 4B is a vertical cross-sectional view of the semiconductor device shown in FIG. 4A. 5A and 5B are schematic diagrams of the integrated circuit according to the embodiment.

Claims (20)

一種在一半導體基板中包含一電晶體的半導體裝置，該電晶體包含： 一第一傳導類型的一漂移區，鄰接於一汲極區域； 一第一場板以及鄰接於該漂移區的一第二場板，該第二場板被配置在該第一場板以及該汲極區域之間，該第二場板電連接至被配置在該漂移區中一接觸部分，以及 低於該漂移區的一較低摻雜濃度的該第一傳導類型的一中間部分，該中間部分以及該汲極區域之間的一距離小於該接觸部分以及該汲極區域之間的一距離。A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes: a drift region of a first conductivity type adjacent to a drain region; a first field plate and a first region adjacent to the drift region; Two field plates, the second field plate is disposed between the first field plate and the drain region, the second field plate is electrically connected to a contact portion disposed in the drift region, and is lower than the drift region A middle portion of the first conductivity type with a lower doping concentration, a distance between the middle portion and the drain region is smaller than a distance between the contact portion and the drain region. 如申請專利範圍第1項所述的半導體裝置，其中該漂移區以及該汲極區域被配置在平行於該半導體基板的一第一主要表面的一第一方向中，該第一以及該第二場板被配置在該第一方向中。The semiconductor device according to item 1 of the patent application range, wherein the drift region and the drain region are arranged in a first direction parallel to a first main surface of the semiconductor substrate, the first and the second The field plate is arranged in the first direction. 如申請專利範圍第1項所述的半導體裝置，其中該接觸部分被設置在該第一場板以及該第二場板之間。The semiconductor device as described in claim 1, wherein the contact portion is disposed between the first field plate and the second field plate. 如申請專利範圍第1項至第3項任一項所述的半導體裝置，其中在正交於該第一方向的一側向方向中該接觸部分的一側向延伸小於該第一以及第二場板任一的一側向延伸。The semiconductor device according to any one of claims 1 to 3, wherein a lateral extension of the contact portion in a lateral direction orthogonal to the first direction is smaller than the first and second directions. The field plate extends either side. 如申請專利範圍第1項至第3項任一項所述的半導體裝置，其中該第一場板以及該第二場板具有在該第一方向中測量的相同長度。The semiconductor device according to any one of claims 1 to 3, wherein the first field plate and the second field plate have the same length measured in the first direction. 如申請專利範圍第1項至第3項任一項所述的半導體裝置，其中該第一場板以及該第二場板具有在正交於該第一方向的一第二側向方向中測量的相同寬度。The semiconductor device according to any one of claims 1 to 3, wherein the first field plate and the second field plate have a measurement in a second lateral direction orthogonal to the first direction. Of the same width. 如申請專利範圍第1項至第3項任一項所述的半導體裝置，其中該第一場板被配置在該第一主要表面中的一第一場板溝槽中，以及該第二場板被配置在該第一主要表面中的一第二場板溝槽中，該第一場板溝槽的一深度等於該第二場板溝槽的一深度。The semiconductor device according to any one of claims 1 to 3, wherein the first field plate is arranged in a first field plate groove in the first main surface, and the second field plate The plate is disposed in a second field plate groove in the first main surface, and a depth of the first field plate groove is equal to a depth of the second field plate groove. 如申請專利範圍第1項至第3項任一項所述的半導體裝置，其中該中間部分被設置以與該第一場板以及該第二場板重疊。The semiconductor device according to any one of claims 1 to 3, wherein the middle portion is disposed to overlap the first field plate and the second field plate. 一種在一半導體基板中包含一電晶體的半導體裝置，該電晶體包含： 由一第一傳導類型的一材料構成的一漂移區； 一第一場板； 一第二場板； 一第三場板，以及 在該漂移區中的一第一接觸部分，該第一、該第二以及該第三場板以離一源極區域的不同距離在一第一方向中被配置在該漂移區中，該第三場板至該源極區域的該距離大於該第一或第二場板至該源極區域的該距離，該第三場板電連接至該第一接觸部分。A semiconductor device including a transistor in a semiconductor substrate, the transistor comprising: a drift region composed of a material of a first conductivity type; a first field plate; a second field plate; a third field Plate, and a first contact portion in the drift region, the first, the second, and the third field plates are disposed in the drift region in a first direction at different distances from a source region The distance from the third field plate to the source region is greater than the distance from the first or second field plate to the source region, and the third field plate is electrically connected to the first contact portion. 如申請專利範圍第9項所述的半導體裝置，其中該第一接觸部分被設置在該第一場板以及該第二場板之間。The semiconductor device according to item 9 of the scope of patent application, wherein the first contact portion is disposed between the first field plate and the second field plate. 如申請專利範圍第9項所述的半導體裝置，其中該第一場板以及該第二場板具有在該第一方向中測量的相同長度。The semiconductor device according to item 9 of the scope of patent application, wherein the first field plate and the second field plate have the same length measured in the first direction. 如申請專利範圍第11項所述的半導體裝置，其中該第一或第二場板（280、283）的該長度小於該第三場板的一長度。The semiconductor device according to item 11 of the scope of patent application, wherein the length of the first or second field plate (280, 283) is smaller than a length of the third field plate. 如申請專利範圍第9項至第12項任一項所述的半導體裝置，其中該第一場板、該第二場板以及該第三場板具有在正交於該第一方向的一第二側向方向中測量的相同寬度。The semiconductor device according to any one of claims 9 to 12, wherein the first field plate, the second field plate, and the third field plate have a first field plate orthogonal to the first direction. The same width measured in both lateral directions. 如申請專利範圍第9項至第12項任一項所述的半導體裝置，其中該第一場板被配置在該半導體基板的一第一主要表面中的一第一場板溝槽中，且該第二場板被配置在該半導體基板的該第一主要表面中的一第二場板溝槽中，該第一場板溝槽的一深度等於該第二場板溝槽的一深度。The semiconductor device according to any one of claims 9 to 12, wherein the first field plate is disposed in a first field plate groove in a first major surface of the semiconductor substrate, and The second field plate is disposed in a second field plate groove in the first main surface of the semiconductor substrate, and a depth of the first field plate groove is equal to a depth of the second field plate groove. 如申請專利範圍第9項至第12項任一項所述的半導體裝置，進一步包含一第四場板，該第四場板電連接至該漂移區中的一第二接觸部分。The semiconductor device according to any one of claims 9 to 12, further comprising a fourth field plate electrically connected to a second contact portion in the drift region. 如申請專利範圍第9項以及第11項至第12項任一項所述的半導體裝置，其中該第一接觸部分被設置在該本體區域以及該第一場板之間。The semiconductor device according to item 9 of the patent application scope and any one of items 11 to 12, wherein the first contact portion is disposed between the body region and the first field plate. 如申請專利範圍第9項至第12項任一項所述的半導體裝置，其中該第一場板（280）以及該第二場板電連接至一源極端。The semiconductor device according to any one of claims 9 to 12, wherein the first field plate (280) and the second field plate are electrically connected to a source terminal. 一種積體電路，包含如申請專利範圍第1項至第3項任一所述的半導體裝置。An integrated circuit includes the semiconductor device according to any one of claims 1 to 3 of the scope of patent application. 如申請專利範圍第18項所述的積體電路，進一步包含形成在該半導體基板中的一第二電晶體。The integrated circuit according to item 18 of the scope of patent application, further comprising a second transistor formed in the semiconductor substrate. 如申請專利範圍第19項所述的積體電路，其中該電晶體的該漂移區的一長度與該第二電晶體的該漂移區的一長度不同。The integrated circuit according to item 19 of the application, wherein a length of the drift region of the transistor is different from a length of the drift region of the second transistor.
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