TWI664633B - Programming method for memory device - Google Patents

Abstract

The programming method for a memory device includes: programming a target memory cell with a programming voltage and a programming code; applying a first verification voltage and a second verification voltage to the target memory cell, and Obtaining a first read data and a second read data; and judging whether the target memory cell passes a truly programmatic verification based on the programmed code, the first read data, and the second read data And / or a virtual stylized verification.

Description

Stylized method of memory device

The invention relates to a programming method for a memory device.

Flash memory is a type of non-volatile memory device. By applying a stylized voltage pulse to the memory cell, data can be stored in the memory cell.

In order to tighten the critical voltage distribution of the memory cell, during the incremental step pulse programming (ISPP) process, a program step and one or more verify steps can be performed, where Each stylized pulse can increase the critical voltage of the memory cell. In addition, between each of the programmed pulses of the ISPP, a program verify (PV) pulse can be applied to verify whether the critical voltage of the memory cell exceeds the verification voltage to check whether the programming is successful. With this, ISPP can be used to achieve a tighter threshold voltage distribution.

In addition, flash memory may have time dependent relaxation characteristics. This characteristic makes it possible for the critical voltage of the memory cell to drift downward or upward, causing the critical voltage of the memory cell to fail verification and making the critical voltage distribution wider.

Therefore, there is a need for a stylized method of a memory device to reduce the critical voltage distribution of the memory cell.

An example of the present case proposes a programming method for a memory device, which includes: programming a target memory cell with a programming voltage and a programming code; applying a first verification voltage and a second verification voltage to the target; A memory cell, and obtain a first read data and a second read data; and determine whether the target memory cell is based on the programmed code, the first read data and the second read data Pass a true programmatic verification and / or a virtual programmatic verification.

Another example of the present case proposes a stylized method of a memory device, which includes: performing a stylized operation and a stylized-verified operation on a target memory cell. The stylized operation and the stylized-verified operation include: applying A plurality of stylized voltages, a plurality of first verification voltages, and a plurality of second verification voltages on the target memory cell, wherein a voltage difference between each of the first verification voltages and each of the second verification voltages Related to a time-dependent drift characteristic; and determining whether a threshold voltage of the target memory cell exceeds each of the first verification voltages and / or each of the second verification voltages to determine whether the target memory cell is Stylized successfully.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

105-130, 405-450, 705-740‧‧‧ steps

P (0) ~ P (n + 2) ‧‧‧ stylized voltage

VR1, VR2, VR1_A, VR2_A, ..., VR1_G, VR2_G‧‧‧ Verification voltage

L1-L8‧‧‧ curve

605-620, 905-940‧‧‧ range

FIG. 1 shows a flowchart of a method for programming a memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a stylized sequence according to the first embodiment of the present invention.

Figure 3 shows the critical voltage distribution of the SLC memory cell.

FIG. 4 shows a flowchart of a method for programming a memory device according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of a stylized sequence according to the second embodiment of the present invention.

Figure 6 shows the critical voltage distribution of MLC.

FIG. 7 shows a flowchart of a method for programming a memory device according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a stylized sequence according to a third embodiment of the present invention.

Figure 9 shows the critical voltage distribution of TLC.

The technical terms in this specification refer to the customary terms in the technical field. If some terms are described or defined in this specification, the interpretation of these terms is subject to the description or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those with ordinary knowledge in the technical field may selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.

Please refer to FIG. 1, which shows a flowchart of a method for programming a memory device according to a first embodiment of the present invention. Fig. 1 is applicable to a single-level cell (SLC).

As shown in FIG. 1, in step 105, data is input to a target memory cell, which is one of a plurality of memory cells to be programmed. For example, to program all the memory cells of a page, all the memory cells of the page are programmed synchronously, but all the memory cells of the page are determined based on the potentials on the respective bit lines. Whether to run the program In the programming operation, a programming operation is performed if the potential of the bit line is 0V, and a programming operation is not performed if the potential of the bit line is Vcc (Vcc is the power provided by the system).

In step 110, the target memory cell is programmed with a programmed voltage P (n) and a programmed code PgmCode (n), where n is a positive integer and the initial value of n is, for example, but not limited to 0. . Refer to Figure 2 for the programmed voltage P (n).

FIG. 2 is a schematic diagram of a program sequence according to the first embodiment of the present invention. Figure 3 shows the critical voltage distribution of the SLC memory cell. The curves L1-L8 represent the critical voltage distributions obtained after different programmed voltages are applied. As shown in FIG. 2 and FIG. 3, since the first embodiment of the present case uses ISPP, the programmed voltages are gradually increasing, such as, but not limited to, increasing at a fixed step. For example, within the programmed voltage range used by ISPP, each programmed voltage is increased by 0.5V. That is, assuming that the stylized voltage P (n) is 17V, the stylized voltage P (n + 1) is 17.5V. As shown in FIG. 2, in the first embodiment of the present case, after the stylized voltage P (n) is applied once, the verification voltages VR2 and VR1 are applied twice (that is, the first embodiment of the present case belongs to 1P2V). Among them, as described above, the stylized voltage P (n) is gradually increased, and the verification voltages VR2 and VR1 are fixed.

How to decide which code to write will be explained below. For example, but not limited to, in the first programming, the target memory cell is programmed with an initial programming voltage P (0) (n = 0) and an initial programming code PgmCode (0), where, The program code PgmCode (0) is determined by the data input in step 105.

Then, in step 115, the verification voltages VR2 and VR1 are applied to the target memory cell to read the target memory cell to obtain two read data.

In step 120, the next stylized code PgmCode (n + 1) = INV (R1) | INV (R2) | PgmCode (n) (that is, PgmCode (n + 1) = {INV (R1) or INV (R2) or PgmCode (n)}, where R1 and R2 represent the data read by the verification voltage VR1 and VR2, and INV (R1) and INV (R2) represent the verification voltage respectively The inversion of the data read by VR1 and VR2. If PgmCode (n + 1) is logic 1, it means that the target memory cell has passed pseudo program verify. In detail, when When PgmCode (n) is logic 0, if at least one of INV (R1) or INV (R2) is logic 1. That is, verify the data read by the voltages VR1 and VR2 on the target memory cell. At least one of them is logic 0, which means that the target memory cell has passed the virtual programming verification. That is, after ISPP, if the critical voltage of the target memory cell has exceeded the verification voltages VR1 and VR2 The smaller one means that the target memory cell has passed the virtual programming verification.

In addition, in the first embodiment of the present case, the verification voltage VR2 may be used to verify / read the target memory cell, and then the verification voltage VR1 may be used to verify / read the target memory cell (as shown in FIG. 2). The programming sequence is shown), wherein the verification voltage VR2 can also be called a real verification voltage, and the verification voltage VR1 can also be called a virtual verification voltage.

In the first embodiment of the present invention, after the stylized voltage is applied to the target memory cell, if the threshold voltage of the target memory cell has exceeded the verification voltage VR2 (true verification voltage), it represents the target memory cell. Cells have been truly programmatically verified. If the target memory cell has passed the true stylized verification, in the first embodiment of the present invention, the stylized operation on the target memory cell may be stopped.

In addition, after the stylized voltage is applied to the target memory cell, if the critical voltage of the target memory cell does not exceed the verification voltage VR2 (real verification voltage) but exceeds the verification voltage VR1 (virtual verification voltage), it means The target memory cell has not passed the true stylized verification but has passed the virtual stylized verification. In the first embodiment of the present invention, after the stylized voltage is applied to the target memory cell, if the threshold voltage of the target memory cell exceeds the verification voltage VR1 (virtual verification voltage), the threshold of the target memory cell The voltage may be due to the time-dependent drift characteristic, and at a later point in time, the critical voltage of the target memory cell drifts upward, causing the critical voltage of the target memory cell to change from below the verification voltage VR2 (true verification voltage) to Above verification voltage VR2 (true verification voltage). Therefore, in the first embodiment of the present case, when it is determined that the threshold voltage of the target memory cell exceeds the verification voltage VR1 (virtual verification voltage), it is considered that the target memory cell has passed the virtual programming verification. If the target memory cell has passed the virtual stylized verification, in the first embodiment of the present invention, the stylized operation on the target memory cell may be stopped.

As mentioned above, in the first embodiment of the present case, the programmed voltage is no longer applied to the target memory cell that has passed the true programmatic verification or has passed the virtual programmatic verification.

In step 125, it is determined whether the applied programming voltage has reached the maximum programming voltage, or it is determined that all the memory cells to be programmed have passed the programmatic verification. If step 125 is YES, the process ends. If step 125 is no, the process proceeds to step 130, increasing the stylized voltage P (n) to the stylized voltage P (n + 1) (for example, increasing at a fixed step), and changing the stylized code PgmCode (n ) Updated to stylized code PgmCode (n + 1). After that, the flow returns to step 110 to program the target memory cell with the program voltage P (n + 1) and the program code PgmCode (n + 1).

Specifically, in step 125, determining whether the maximum programmed voltage has been reached refers to whether the applied programmed voltage has reached the maximum programmed voltage within the programmed voltage range.

In addition, in step 125, "determining whether all the memory cells to be programmed have passed the programmatic verification" means, for example, that programming all the memory cells of a page determines all the Whether the respective threshold voltages of the memory cell are higher than either VR2 or VR1. If the respective critical voltages of all the memory cells of the page are higher than any of VR2 or VR1, it means that all the memory cells of the page have passed the programmatic verification, so the process ends. If the page still has at least one memory cell's respective critical voltages that are still lower than VR2 and VR1, the at least one memory cell has not passed the stylized verification, so the process continues to address the memory that has not passed the stylized verification. The unit cell is stylized and verified.

In addition, in FIGS. 2 and 3, the real verification voltage VR2 is greater than the virtual verification voltage VR1. However, in other possible embodiments of the present case, the real verification voltage VR2 may be less than or equal to the virtual verification voltage VR1. This is also within the spirit of this case.

In addition, in step 115 of the flowchart of FIG. 1, the real verification voltage VR2 is used for reading, and then the virtual verification voltage VR1 is used for reading. However, in other possible embodiments of the present case, the virtual verification voltage VR1 can also be used for reading, and then the real verification voltage VR2 can be used for reading, which is also within the spirit of the present case.

In addition, in the first embodiment of the present case, the difference between the verification voltages VR2 and VR1 may be related to the threshold voltage drift amount due to the time-dependent drift characteristic.

As described above, in order to solve the time-dependent drift characteristic of the flash memory, the first embodiment of the present invention can be solved in the manner of FIGS. 1 to 3. Therefore, this implementation is easy to integrate with existing circuits.

In the first embodiment of the present case, the critical voltage distribution of the memory cell can be made more compact through the 1P2V stylized operation.

Second embodiment

Please refer to FIG. 4, which shows a flowchart of a stylized method of a memory device according to a second embodiment of the present invention. FIG. 4 is applicable to a multi-level cell (MLC). Steps 405 and 410 are similar to steps 105 and 110 in FIG. 1, so descriptions thereof are omitted.

FIG. 5 is a schematic diagram of a stylized sequence according to the second embodiment of the present invention. Figure 6 shows the critical voltage distribution of MLC. In FIG. 6, a range 605 represents an erased state. If the critical voltage of the memory cell falls within the range 605, it means that the memory cell is programmed into an erased state (storage logic 11). The range 610 represents the first programmed state. If the critical voltage of the memory cell falls within the range 610, it means that the memory cell is programmed to the first programmed state (storage logic 10). The range 615 represents the second stylized state. If the critical voltage of the memory cell falls within the range 615, it means that the memory cell is programmed to the second stylized state (storage logic 00). The range 620 represents the third stylized state. If the critical voltage of the memory cell falls within the range 620, it means that the memory cell is programmed to the third stylized state (storage logic 01).

As shown in Figures 5 and 6, in the second embodiment of the present case, after the stylized voltage P (n) is applied once, the verification voltages VR2_A, VR1_A, VR2_B, VR1_B, VR2_C, and VR1_C (that is, the second The examples also belong to 1P2V). The verification voltages VR2_A and VR1_A can be used to verify whether the threshold voltage of the memory cell falls within the range 610, for example. The verification voltages VR2_B and VR1_B can be used to verify whether the threshold voltage of the memory cell falls within the range 615, for example. The verification voltages VR2_C and VR1_C can be used to verify whether the threshold voltage of the memory cell falls within the range 620, for example.

Of course, the stylized voltage P (n) is gradually increasing, and the verification voltages VR2_A, VR1_A, VR2_B, VR1_B, VR2_C, and VR1_C are fixed.

How to decide which code to write will be explained below. For example, but not limited to, during the first programming, the memory cells are programmed with an initial programming voltage P (0) (n = 0) and an initial programming code PgmCode (0), where, The program code PgmCode (0) is determined by the data input in step 405.

Next, in step 415, the verification voltages VR2_A and VR1_A are applied to the target memory cell to read the target memory cell to obtain read data R2_A and R1_A.

In step 420, the next stylized code PgmCode (n + 1) = INV (R1_A) | INV (R2_A) | PgmCode (n) (that is, PgmCode (n + 1) = {INV (R1_A) or INV (R2_A) or PgmCode (n)}, where R1_A and R2_A represent the data read by the verification voltages VR1_A and VR2_A, and INV (R1_A) and INV (R2_A) represent the verification voltage Inverted data read by VR1_A and VR2_A. If PgmCode (n + 1) is logic 1, then This means that the target memory cell has passed the virtual stylization verification. R1_B, R2_B, INV (R1_B), INV (R2_B), R1_C, R2_C, INV (R1_C) and INV (R2_C) represent the same meaning.

In addition, in the second embodiment of the present case, it is determined whether the PgmCode (n + 1) obtained in step 420 is to be used according to the user data input in step 405. That is, if the user data is 10, it means that the memory cell should be programmed to 10 (range 610 in FIG. 6), and the PgmCode (n + 1) obtained in step 420 can be used to determine the memory. The unit's next stylized code, PgmCode (n + 1). Conversely, if the user data is not 10, the PgmCode (n + 1) obtained in step 420 is not used to determine the next programmed code PgmCode (n + 1) of the memory cell (that is, obtained in step 420 PgmCode (n + 1) is skipped).

Similarly, steps 425, 430, 435, and 440 are similar to steps 415 and 420. Similarly, according to the user data input in step 405, it is determined whether the PgmCode (n + 1) obtained in step 430 is to be used. That is, if the user data is 00, it means that the memory cell should be programmed as 00 (range 615 in FIG. 6), then the PgmCode (n + 1) obtained in step 430 can be used to determine the memory. The unit's next stylized code, PgmCode (n + 1). Conversely, if the user data is not 00, the PgmCode (n + 1) obtained in step 430 is not used to determine the next stylized code PgmCode (n + 1) of the memory cell (that is, obtained in step 430 PgmCode (n + 1) is skipped).

Similarly, according to the user data input in step 405, it is determined whether the PgmCode (n + 1) obtained in step 440 is to be used. That is, if the user data is 01, it means that the memory cell should be programmed as 01 (range 620 in Figure 6), then The PgmCode (n + 1) obtained in step 440 can be used to determine the next stylized code PgmCode (n + 1) of the memory cell. Conversely, if the user data is not 01, the PgmCode (n + 1) obtained in step 440 is not used to determine the next programmed code PgmCode (n + 1) of the memory cell (that is, obtained in step 440 PgmCode (n + 1) is skipped).

Steps 445 and 450 are similar to steps 125 and 130 of FIG.

Similarly, in Figures 5 and 6, the true verification voltage VR2_A / VR2_B / VR2_C is greater than the virtual verification voltage VR1_A / VR1_B / VR1_C. However, in other possible embodiments of this case, the true verification voltage VR2_A / VR2_B / VR2_C may Less than or equal to the virtual verification voltage VR1_A / VR1_B / VR1_C. This is also within the spirit of this case.

In addition, in steps 415, 425, and 435 of the flowchart of FIG. 4, the real verification voltage VR2_A / VR2_B / VR2_C is used for reading, and then the virtual verification voltage VR1_A / VR1_B / VR1_C is used for reading. However, in other possible embodiments of the present case, the virtual verification voltage VR1_A / VR1_B / VR1_C may also be used for reading before the real verification voltage VR2_A / VR2_B / VR2_C is used for reading, which is also within the spirit of the present case.

In the second embodiment of the present invention, the critical voltage distribution of the plurality of memory cell units can be made more compact through the 1P2V stylized operation.

Third embodiment

Please refer to FIG. 7, which shows a flowchart of a stylized method of a memory device according to a third embodiment of the present invention. FIG. 7 is applicable to a triple-level cell (TLC). Steps 705 and 710 are similar to steps 105 and 110 in FIG. 1, so descriptions thereof are omitted.

FIG. 8 is a diagram illustrating a stylized sequence according to a third embodiment of the present invention. Figure 9 shows the critical voltage distribution of TLC. In Figure 9, the ranges 905-940 represent different states, respectively. For example, if the critical voltage of the memory cell falls within the range 915, it means that the memory cell is programmed as logic 101, and the rest can be deduced by analogy.

As shown in FIGS. 8 and 9, in the third embodiment of the present case, after the stylized voltage P (n) is applied once, multiple verification voltages VR2_A, VR1_A, ..., VR2_G, and VR1_G (that is, the present case) The third embodiment also belongs to 1P2V). The verification voltages VR2_A and VR1_A can be used to verify whether the threshold voltage of the memory cell falls within the range 910, and the rest can be deduced by analogy.

Of course, the stylized voltage P (n) is gradually increasing, and the verification voltages VR2_A, VR1_A, ..., VR2_G and VR1_G are fixed.

How to decide which code to write will be explained below. For example, but not limited to, during the first programming, the memory cells are programmed with an initial programming voltage P (0) (n = 0) and an initial programming code PgmCode (0), where, The program code PgmCode (0) is determined by the data input in step 705.

Next, in step 715, the verification voltages VR2_i and VR1_i (i = A-G) are applied to the target memory cell to read the target memory cell to obtain read data R2_i and R1_i.

In step 720, the next stylized code PgmCode (n + 1) = INV (R1_i) | INV (R2_i) | PgmCode (n) (that is, PgmCode (n + 1) = {INV (R1_i) or INV (R2_i) or PgmCode (n)}, where R1_i and R2_i represent the data read by verifying the voltages VR1_i and VR2_i, and INV (R1_i) and INV (R2_i) represent the inversion of the data read by the verification voltages VR1_i and VR2_i, respectively. If PgmCode (n + 1) is logic 1, it means that the target memory cell has passed the virtual programming verification.

In addition, in the third embodiment of the present case, similarly, according to the input data, it is determined whether the PgmCode (n + 1) (i = A to G) obtained in step 720 is to be used. The details are as described in the second embodiment. I will not repeat them here. That is, if the user data is 110, which means that the memory cell should be programmed to 110 (range 910 in Figure 9), then the PgmCode (n + 1) (i = A) obtained in step 720 is available The next stylized code PgmCode (n + 1) is used to determine the memory cell, and the remaining PgmCode (n + 1) (i = B to G) is not used to determine the next stylized code of the memory cell. Code PgmCode (n + 1).

In step 725, it is determined whether i reaches the upper limit (the upper limit is G). If step 725 is no, then i is updated in step 730 (ie, if the previous i is A, then it is updated to B, and so on). If YES in step 725, the flow proceeds to step 735. Steps 735 and 740 are similar to steps 125 and 130 of FIG.

Similarly, in FIGS. 8 and 9, the real verification voltage VR2_i is greater than the virtual verification voltage VR1_i. However, in other possible embodiments of the present case, the real verification voltage VR2_i may be less than or equal to the virtual verification voltage VR1_i. This is also within the spirit of this case.

In addition, in step 715 of the flowchart of FIG. 7, the real verification voltage VR2_i is used for reading, and then the virtual verification voltage VR1_i is used for reading. However, in other possible embodiments of the present case, the virtual verification voltage VR1_i can also be used for reading before the real verification voltage VR2_i is used for reading, which is also within the spirit of the present case.

In the third embodiment of the present invention, the critical voltage distribution of the plurality of memory cell units can be made more compact through the 1P2V stylized operation.

In addition, the above-mentioned several embodiments also propose: performing a stylized operation and a stylized-verified operation on the target memory cell, the stylized operation and the stylized-verified operation include: applying a plurality of stylized voltages P ( n), a plurality of first verification voltages (such as VR1, VR1_A ... VR1_G, etc.) and a plurality of second verification voltages (such as VR2, VR2_A ... VR2_G, etc.) in the target memory cell, the details of which are as described above I will not repeat them here.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (10)

A programming method for a memory device includes: programming a target memory cell with a programming voltage and a programming code; applying a first verification voltage and a second verification voltage to the target memory cell And obtain a first read data and a second read data; and determine whether the target memory cell passes a real program according to the programmed code, the first read data and the second read data Verification and / or a virtual programmatic verification. The method for stylizing a memory device according to item 1 of the scope of patent application, wherein an inverted data of the first read data, an inverted data of the second read data, or the program code is used. Obtaining a stylized code; and determining whether to perform a stylized operation on the target memory cell according to a bit line potential of the target memory cell. The method for stylizing a memory device according to item 2 of the scope of patent application, wherein if the applied stylized voltage does not reach a maximum stylized voltage, or the target memory cell fails the true stylized verification Also does not pass the virtual stylized verification, increase the stylized voltage, and update the stylized code to the next stylized code to program the target with the increased stylized voltage and the next stylized code Memory unit cell. According to the stylized method of the memory device described in item 1 of the scope of patent application, when a threshold voltage of the target memory cell does not exceed the second verification voltage, but has exceeded the first verification voltage, it is regarded as The target memory cell has passed the virtual stylization verification, and the stylized operation on the target memory cell is stopped. As the stylized method of the memory device described in the first item of the patent application scope, when a threshold voltage of the target memory cell has exceeded the second verification voltage, the target memory cell has passed the real Programmatically verify and stop programmatic operation on the target memory cell. A stylized method of a memory device includes: performing a stylized operation and a stylized-verified operation on a target memory cell, the stylized operation and the stylized-verified operation include: applying a plurality of stylized voltages A plurality of first verification voltages and a plurality of second verification voltages on the target memory cell, wherein a voltage difference between each of the first verification voltages and each of the second verification voltages is related to a time Drift characteristics; and determining whether a threshold voltage of the target memory cell exceeds one of the first verification voltages and each of the second verification voltages to determine whether the target memory cell is successfully programmed. The stylized method of the memory device according to item 6 of the patent application scope, wherein when the threshold voltage of the target memory cell does not exceed each of the second verification voltages, but has exceeded each of the first verification voltages Voltage, it is considered that the target memory cell has passed a virtual stylization verification, and the programming operation of the target memory cell is stopped. According to the stylized method of the memory device described in item 6 of the patent application scope, when the threshold voltage of the target memory cell has exceeded each of the second verification voltages, the target memory cell has passed A truly stylized verification and stop the stylized operation on the target memory cell. The method for stylizing a memory device according to item 6 of the scope of the patent application, wherein whether to perform the stylized operation on the target memory cell is determined according to a bit line potential of the target memory cell. The method for stylizing a memory device according to item 6 of the scope of patent application, wherein the first verification voltages are greater than or equal to the second verification voltages.