TWI663602B - Memory system and programming method - Google Patents

Abstract

The present invention discloses a mechanism that prohibits programming of cells in memory cells of unselected strings. Roughly speaking, during the precharge phase, a forbidden voltage is established in a channel connected to a word line selected for programming but located in a memory cell in an unselected string. In subsequent programming stages, the channels of the cells in the selected string are kept at a low voltage, while the channels of the cells in the unselected string are allowed to float. A programming voltage Vpgm is applied to a selected word line conductor, a first pass voltage VpassP1 is applied to a first word line conductor different from the selected word line conductor, and a second pass voltage VpassP is applied to a second word line conductor. The first word line conductor is located between the selected word line conductor and the second word line conductor, and Vpgm> VpassP1> VpassP.

Description

Memory system and programming method

The invention relates to a program prohibition scheme for a high-density memory device.

As the critical size of devices in integrated circuits has shrunk to the limits of general memory cell technology, designers have been seeking to stack memory cells on multiple planes to achieve greater storage capacity and lower cost per bit ( cost per bit). For example, the "Multilayer Stackable Thin Film Transistor (TFT)" made by Lai et al. At the IEEE Int'l Electron Devices Meeting held on December 11-13, 2006. "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", and IEEE International, which was held by Jung et al. From December 11 to 13, 2006 "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal on ILD and TANOS Structures for Nodes Exceeding 30 Nanometers Using Stacked Single Crystal Silicon Layers" Si Layers on ILD and TANOS Structure for Beyond 30nm Node) ", and applied thin film transistor technology to charge trapping memory technology. The content of the above-mentioned journal is incorporated herein by reference.

"Tubular BiCS flash memory with 16 stacked layers and its use in the 2009 Symposium on VLSI Technology Digest of Technical Papers" held by Katsumate et al. In 2009 Another structure is described in "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices". This article provides vertical reaction cells, and the contents of the above journals are incorporated herein by reference. The structure described in the journal Katsuya et al. Includes vertical reverse gates, which use silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to generate storage sites at each gate / vertical channel interface ( storage site). The memory structure is based on a column of semiconductor material arranged as a vertical channel for the gate, and has a lower selection gate adjacent to the substrate and an upper selection gate on the top. A plurality of horizontal word lines are formed by using a flat word line layer that intersects the pillar, thereby forming a so-called gate all around cell at each layer.

Figure 1 is a horizontal cross-sectional view of a row of tubular BiCS flash cells (for example, as described in Katsuya et al.'S publication) at the character line level. The structure includes a pillar 15 having a central core 110 that is made of a semiconductor material and extends vertically through a stack of word line layers. The core 110 may have an intermediate seam 111 produced by a sunken technique. A dielectric charge trapping structure (referred to as ONO) including, for example, a first layer 112 made of silicon oxide, a layer 113 made of silicon nitride, and a second layer 114 made of silicon oxide, or another A layer of dielectric charge trapping structure surrounds the core 110. Gate full-circle word lines are crossed by the posts. The frustum of the pillar at each layer is combined with the gate full ring character line structure at the layer to form a memory cell.

FIG. 2 is a perspective view of a memory array 700 in an exemplary 3D semiconductor memory device. It includes a multi-layer stack of each of the following: a character line conductive layer 11, each parallel to a substrate (not shown in the figure); a plurality of pillars 15, oriented perpendicular to the substrate, each of the pillars including the pillars and Multiple serially connected memory cells at the intersection between the conductive layers; and multiple string select lines (SSL) 12 oriented parallel to the substrate and located above the conductive layer 11, each of the strings The selection line crosses the corresponding column of the column. Each intersection of a pillar and a string selection line defines a string select gate (SSG) of the pillar. Depending on the memory page and block architecture, there may be more than one string selection line crossing the column and more than one string selection gate. The structure also includes a ground select line (GSL) 13 (sometimes referred to as a lower select line (LSL)), especially in some embodiments as shown in FIG. (Lower end), the ground selection line 13 is oriented parallel to the substrate and forms a layer below the word line conductive layer 11. Each intersection of the pillar and the ground selection line 13 defines a ground select gate (GSG) of the pillar (sometimes also referred to as a lower select gate (LSG)). Again, some memory architectures may include more than one ground selection line layer and more than one ground selection gate per pillar. A common source line (CSL) 10 is formed in a layer parallel to the substrate and below the GSL.

The structure also includes a plurality of parallel bit line conductors 20 in a layer parallel to the substrate and above the string selection line. Each of the bit line conductors is stacked on a corresponding row of pillars, and each pillar is located below each of the bit line conductors. In some architectures, the bit line conductors are located below the pillars, and in other other architectures, some bit line conductors are located below the pillars and some bit line conductors are located above the pillars. No matter which way it is set up, each post is connected to the bit line at one or the other end of the post. The post may be configured as described above with reference to FIG. 1.

FIG. 3 is a simplified circuit diagram showing a memory cell and an access transistor in two columns of the memory array shown in FIG. 2. As shown, each column supports a corresponding string 310 or 311 of "i" memory cells connected in series. Memory cells in string 310 are labeled 318 (0) ... 318 (i-1) (representatively labeled 318), while memory cells in string 311 are labeled 319 (0) ... 319 ( i-1) (typically labeled 319). Each of the memory cells 318 and 319 is constructed as shown in FIG. 1, and the electrical properties include a source, a drain, and a control gate. Due to the interchangeability of the electrical source and drain in many transistors, these two terminals are sometimes collectively referred to herein as "current path terminals." The series connection of the transistors in the string is the series connection of the current path terminals of the transistors in the string.

The string 310 also includes a string selection gate and a lower selection gate connected in series on opposite sides of the memory cell 318 of the string. More specifically, each selection gate 314 and lower selection gate 320 includes a control gate electrode and two current path terminals, and the current path terminal and the current path terminal of the memory cell 318 of the string are connected in series . Similarly, the string 311 also includes a string selection gate 315 and a lower selection gate 321 connected in series on opposite sides of the memory cell 319 of the string. More specifically, each string of selection gates 315 and lower selection gates 321 includes a control gate electrode and two current path terminals, and the current path terminals are connected in series with the current path terminals of the memory cells 319 of the string. . The two strings share a single bit line conductor 322 connected to the drain terminals of the two string selection gates. The control gates of the two string selection gates are connected to separate string selection lines (314 in string 310 and 315 in string 311), thereby allowing bit line 322 to communicate with corresponding memory cell 310 And 311 for optional communication. The two strings also share a single common selection line 328 connected to the source terminals of the two lower selection gates and a common lower selection line 320 connected to the control gates of the two lower selection gates. Note that in different embodiments, for some strings in the embodiment, the bit line conductor 322 may be connected to the lower end of the string, and the common source line may be connected to the upper end of the string.

The memory also includes i individual word line conductors WL (0) ... WL (i-1) (representatively WL), each of which is located in a separate one of the memory array shown in FIG. 2 In the plane, and one of the word line conductors corresponds to each of the memory cells 318 in the string 310. The corresponding memory cells 319 in the string 311 are located in a plane corresponding to the memory cells in the string 310. Each of the word line conductors WL is connected to a control gate electrode of a corresponding memory cell 318 in the string 310 and is also connected to a control gate electrode of a corresponding memory cell 319 in the string 311. Therefore, it can be seen that each string crosses the word line conductor, and the memory cells of the string are located at the intersection between the word line conductor and the string.

To program the cells in the memory, the control circuit system 326 first erases the entire cell block, which consumes any charge on the capture layer. Control circuitry 326 then programs one plane at a time by applying the appropriate voltages to the selected and unselected string selection lines, bit lines, and word lines. The cell is programmed when the voltage is configured such that the electric field across the capture layer from the control gate electrode to the channel in the dielectric charge capture structure is high enough to achieve tunneling of electrons from the channel to the Flowler Nordheim on the capture layer. Programming is inhibited by configuring the voltage so that the electric field is too small to cause such tunneling.

In early anti-flash devices, in order to program the cell, a low voltage (for example, 0 volts) was placed on the bit line to be programmed, and a higher "forbidden" voltage (for example, 3 volts) To 5 volts) on the bit line that will remain in the erased state. The string selection line gate in the selected string 310 is activated, and the word lines for the cells of the selected plane are raised to a high programming voltage Vpgm which may be about 18 volts to 24 volts. Pass voltage VpassP is placed on all unselected word lines. The pass voltage is high enough to transfer the low bit line voltage from the bit line 322 to the cells of the selected plane via the serially connected channels in the column. In such a device, VpassP may be, for example, 5 volts to 10 volts. The string selection line gate in the unselected string 311 is disabled, thereby floating the channels of the transistors 319 in the unselected string 311. These channels are therefore coupled high by VpassP or Vpgm applied to the corresponding word line. The cell to be programmed therefore experiences a high programming voltage on its control gate and a low voltage delivered by a low voltage on the self-selected positioning element line 322 in its channel. The resulting electric field across the capture layer in the selected string 310 causes electrons from the channel to tunnel onto the capture layer, where the electrons are stored. Cells in the same plane but in an unselected string experience the same high programming voltage on their control gates, but also experience slightly higher voltages in their channels due to the higher inhibit voltage coupled to their bit line 322 . The voltage is designed so that the resulting electric field across the capture layer is insufficient to tunnel electrons, so the cells in the unselected string remain in their erased state. Programming of other cells located in the same string as the selected string 310 but on different planes of the structure is prohibited because the voltage VpassP applied to the corresponding word line is low enough that the voltage across the capture layer from the gate electrode to the channel The difference is sufficiently reduced to prevent tunneling.

Recently, a precharge scheme has been developed to provide forbidden voltages in the channels of cells in unselected strings. Referring to FIG. 3, in the pre-charging scheme, the programming cycle includes both a pre-charging phase and a subsequent programming phase. During the pre-charge phase, the bit line 322 is raised to a high voltage that may be approximately equal to Vcc. The string selection line 315 of the unselected string is also raised to a high voltage that can be approximately equal to the bit line voltage, thereby connecting the unselected string 311 to the bit line 322. The string selection line 314 of the selected string is maintained at a low voltage that can be 0 volts, thereby isolating the selected string 310 from the bit line 322. Each of the channels of the memory cells in the unselected string is therefore charged to a corresponding level (which is referred to herein as the "inhibit voltage") to turn off each cell. The prohibition voltage may be approximately (-Vt), for example.

During the programming phase, the bit line voltage is reduced to a low voltage that can be 0 volts, and the string selection line 315 of the unselected string 311 is also reduced to a low voltage that can be the same as the low bit line voltage, thereby making the unselected The string 311 is disconnected from the bit line 322. The channels of the cells in the unselected string are therefore floating relative to the supply voltage, and each cell in the unselected string is floating independently of the neighboring cells in the unselected string. The string selection line 314 of the selected string is raised to a higher voltage in order to connect the selected string 310 to the low voltage of the bit line 322, thus establishing a low voltage on the channel of the cell in the selected string 310. A high Vpgm voltage is applied to the selected word line WL (n), and the selected word line WL (n) therefore applies Vpgm to the control of all cells 318 (n) and 319 (n) connected to WL (n) Gate. As in the above non-precharge scheme, the pass voltage VpassP is placed on all unselected word lines. Therefore, in the selected string 310, the cell 318 (n) to be programmed experiences a high programming voltage on its control gate and a low voltage in its channel, and spans the selected cell 318 (n) in the selected string 310. The resulting electric field of the trapping layer causes electrons to tunnel from the channel onto the trapping layer, where the electrons are stored. As in the above non-precharge scheme, the pass voltage VpassP on all unselected word lines is high enough to transfer the low bit line voltage from the bit line 322 to the cells of the selected plane via the serially connected channels in the selected string 310, but The pass voltage VpassP is not high enough to allow other cells located in the selected string 310 but in unselected planes to be programmed.

In the unselected string 311, since the channels of all the memory cells 319 in the unselected string 311 are independent and floating, the potential on the channel of the unselected cell 319 is also related to the increased control gate voltage. Increased by capacitive coupling. With the additional increase of the forbidden voltage in the unselected string 311, the programming voltage applied to the control gate of the selected cell 319 (n) in the unselected string 311 raises the channel voltage on the cell 319 (n) to approximately Vpgm voltage. Therefore, the potential difference between the voltage Vpgm on the control gate of the unselected cell and the rising voltage of its channel remains relatively small, thereby inhibiting programming. That is, the programming interference of the selected cells 319 (n) in the unselected string 311 is suppressed.

However, it has been found that in a memory array utilizing the above-mentioned precharge scheme, an undesired degree of programming disturbance sometimes occurs on the target cell of the selected word line WL (n) in the unselected string 311. It is desirable to reduce or eliminate programming interference on such cells.

It has been determined that there is a risk of programming interference with the target cell in the unselected string 311 due to the following: during the programming phase, the elevated potential in the channel of the selected cell 319 (n) in the unselected string 311 approaches Vpgm The potential on adjacent cells 319 (n ± 1) is much lower and closer to VpassP. Therefore, there is a large potential difference between the two voltages, which can induce band to band leakage to reduce the channel potential of the target cell 319 (n) in the unselected string 311.

It can be considered that such programming interference can be reduced by increasing VpassP to reduce the potential difference between adjacent cell 319 (n ± 1) and the increased channel potential of cell 319 (n) in the unselected string. However, a higher VpassP will increase the control gate-to-channel potential difference of the neighboring cells 318 (n ± 1) in the selected string 310, thereby increasing the charge in the selected string 310 Possibility of tunneling from its own channel onto the capture layer of the cell 318 (n ± 1). On the other hand, it can be considered that the programming interference of the unselected cells 318 (n ± 1) in the selected string 310 can be reduced by the opposite approach, that is, reducing VpassP. But this again increases the potential difference between the adjacent cell 319 (n ± 1) and the increased channel potential of the cell 319 (n) in the unselected string 311, which again increases the selected cell 319 (n) in the unselected string 311. ) And the potential difference between neighboring cells 319 (n ± 1). This condition again increases the likelihood that the charge tunnels in the unselected string 311 onto the capture layer of the target cell 319 (n).

According to the present invention, roughly speaking, two levels of pass voltages are used instead of applying a higher VpassP to all word lines including the word line immediately adjacent to the selected word line WL (n). The conventional pass voltage VpassP can be applied to the word lines separated from WL (n) by one or more word line layers, while an intermediate pass voltage lower than Vpgm but higher than the conventional pass voltage VpassP is applied to the WL (n) Adjacent word lines.

More specifically, after the precharge phase, a programming phase occurs in which the control circuit applies a programming voltage Vpgm to a selected word line conductor. The control circuit also applies a first pass voltage VpassP1 to the first word line conductor among the word line conductors adjacent to the selected word line conductor, and applies a second pass voltage VpassP to the word line conductor. A second word line conductor, the first word line conductor being located between the selected word line conductor and the second word line conductor, where Vpgm> VpassP1> VpassP.

There can be many changes to this concept, and other aspects and advantages of the present invention can be seen by looking at the following drawings, detailed description, and patent application scope.

The above summary of the invention is provided to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key or essential elements of the invention or to delineate the scope of the invention. The summary is provided merely to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The specific aspects of the present invention are explained in the scope of patent application, the specification and the drawings.

The following description is presented to enable any person skilled in the art to make and use the invention, and the description is provided in the context of a specific application and its requirements. Various retouches to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Therefore, the invention is not intended to be limited to the embodiments shown, but is intended to conform to the widest scope consistent with the principles and features disclosed herein.

FIG. 4 is a simplified circuit diagram of FIG. 3 showing versions of the memory cells and the access transistors in the two columns of the memory array of FIG. 2. However, FIG. 4 is different from FIG. 3 in that, in the programming phase of the programming cycle, when the programming voltage Vpgm is applied to the selected word line WL (n), it is applied to the line adjacent to the selected word line. The voltage of the two word lines (WL (n-1) and WL (n + 1)) is an intermediate voltage VpassP1. The voltage VpassP1 is less than Vpgm, but greater than the voltage VpassP applied to all other unselected word lines. That is, Vpgm> VpassP1> VpassP.

More specifically, as in the pre-charging scheme, the programming cycle includes both a pre-charging phase and a subsequent programming phase. During the pre-charge phase, the bit line 322 is raised to a high voltage that may be approximately equal to Vcc. The string selection line 315 of the unselected string is also raised to a high voltage that can be approximately equal to the bit line voltage, thereby connecting the unselected string 311 to the bit line 322. The string selection line 314 of the selected string is maintained at a low voltage that can be 0 volts, thereby isolating the selected string 310 from the bit line 322. Each of the channels of the memory cells in the unselected string is therefore charged to a corresponding inhibit voltage to turn off each cell. The prohibition voltage may be approximately (-Vt), for example.

Then during the programming phase, the bit line voltage is reduced to a low voltage that can be 0 volts, and the string selection line 315 of the unselected string 311 is also reduced to a low voltage that can be the same as the low bit line voltage, thereby making the unselected The selected string 311 is disconnected from the bit line 322. The channels of the cells in the unselected string are therefore floating relative to the supply voltage, and each cell in the unselected string is floating independently of the neighboring cells in the unselected string. The string selection line 314 of the selected string is raised to a higher voltage in order to connect the selected string 310 to the low voltage of the bit line 322, thus establishing a low voltage on the channel of the cell in the selected string 310. A high Vpgm voltage is applied to the selected word line WL (n), and the selected word line WL (n) therefore applies Vpgm to the control of all cells 318 (n) and 319 (n) connected to WL (n) Gate. However, unlike the scheme shown in FIG. 3, the pass voltage VpassP is not placed on all unselected word lines. In contrast, a first intermediate pass voltage VpassP1 is applied to two word lines (ie, applied to WL (n-1) and WL (n + 1)) immediately adjacent to the selected word line. The pass voltage VpassP is applied to all other unselected word lines (ie, WL (0) .. WL (n-2) and WL (n + 2) .. WL (i-1)). The voltage VpassP1 is less than Vpgm, but greater than the voltage VpassP.

Therefore, in the selected string 310, the cell 318 (n) to be programmed experiences a high programming voltage on its control gate and a low voltage in its channel, and spans the selected cell 318 (n) in the selected string 310. The resulting electric field of the trap layer causes the electrons from the channel to tunnel onto the trap layer, where the electrons are stored. The pass voltage VpassP on all unselected word lines except WL (n ± 1) is high enough to transfer the low bit line voltage from the bit line 322 to the cells of the selected plane via the serially connected channels in the selected string 310, but The pass voltage VpassP is not high enough to allow other cells located in the selected string 310 but in unselected planes to be programmed. The first intermediate pass voltage VpassP1 is higher than VpassP, so it is also high enough to transfer the low bit line voltage from the bit line 322 to the cells of the selected plane via the serially connected channels in the selected string 310. In some embodiments, VpassP1 may be high enough to increase the possibility of programming interference in cells 318 (n ± 1) in the selected string 310, but since these cells only receive this comparison when neighboring cells receive the programming voltage High pass voltage, so accumulated programming disturbances can be tolerated.

In the unselected string 311, since the channels of all the memory cells 319 in the unselected string 311 are independent and floating, the potential on the channel of the unselected cell 319 is also related to the increased control gate voltage. Increased by capacitive coupling. As shown in the scheme in FIG. 3, this means that when the programming voltage Vpgm is applied to the control gate of the selected cell 319 (n) in the unselected string 311, the channel voltage on the cell 319 (n) is also capacitively coupled. To a voltage close to Vpgm. Therefore, the potential difference between the voltage Vpgm on the control gate of the unselected cell and the rising voltage of its channel remains relatively small, thereby inhibiting programming. Similar behavior prevents the programming of cells 319 in the unselected string 311 that receive the pass voltage VpassP. In the scheme shown in FIG. 4, VpassP1 is higher than VpassP, but again, similar behavior prevents programming of cells 319 (n ± 1) in the unselected string 311 that receive the first intermediate pass voltage VpassP1. That is, when the first intermediate pass voltage VpassP1 is applied to the control gate of the adjacent cell 319 (n ± 1) in the unselected string 311, the channel voltage on the cell 319 (n ± 1) is also capacitively coupled to close to VpassP1. The voltage rises. Therefore, the potential difference between the voltage VpassP1 on the control gate of the cell 319 (n ± 1) and the rising voltage of its channel remains relatively small, thereby inhibiting programming.

FIG. 5 is a simplified timing diagram illustrating an exemplary voltage waveform applied by the control circuitry 326 to the device shown in FIG. 4 during a portion of a programming cycle. The programming cycle begins in one embodiment with a pre-charge phase, followed by a programming phase. In some embodiments, if, for example, incremental step pulse programming (ISPP) is implemented, the programming loop then continues with one or more additional programming stages; however, only the first programming stage is shown in the drawing . Many different strategies can be used in the pre-charging phase, and only one of the different strategies is shown in FIG. 5 as an example.

During the pre-charge phase, the bit line voltage Vb1 322 increases from a low voltage (eg, 0 volts) to a high voltage (eg, 3 volts to 5 volts) that can be equal to Vcc. The bit line voltage Vb1 then returns to a low voltage (eg, 0 volts) for the programming phase. The string selection line 314 of the selected string 310 is kept low for the pre-charging stage, thereby isolating the selected string 310 from the high bit line voltage. The string selection line 314 is raised for the programming phase, thereby connecting the selected string 310 to the lower bit line voltage during the programming phase. The string selection line 315 of the unselected string 311 experiences the opposite behavior to the string selection line 314. The string selection line 315 is raised (for example, to Vcc) for the precharge stage to turn on the string selection gate and connect the high voltage on the bit line 322 to the unselected string 311, thereby performing the channel selection on the unselected string. Pre-charge to turn off the channel. For the programming phase, the string selection line 315 is lowered (eg, to 0 volts) to isolate the unselected string 311 from the low bit line voltage, thereby enabling the channel of the cell 319 in the unselected string 311 to float. During the pre-charge phase, the word line voltage is kept low. For the programming phase, the selected word line WL (n) is raised to the programming voltage Vpgm. The word line WL (n ± 1) adjacent to the selected word line WL (n) is raised to the first intermediate pass voltage VpassP1, and the remaining word lines WL (0) .. WL (n-2) and WL (n + 2) .. WL (i-1) is raised to the pass voltage VpassP. Vpgm is higher than VpassP1, VpassP1 is then higher than VpassP, and VpassP is then higher than zero. [Some changes]

The concept of applying a middle pass voltage to a word line closer to the selected word line and applying a lower pass voltage to a word line farther from the selected word line allows multiple variations.

It should first be understood that the cells located at different layers of the string will have different characteristics, such as parasitic capacitance and resistance to the charge source and drain. Such differences can arise, for example, from the relative depth of the cells in the multilayer structure, which will typically result in the cells having different structural dimensions. Parasitic capacitances of different levels can be generated according to the distance between the cell and the overlying conductive structure and the underlying conductive structure. The difference in the distance from the cell to the bit line at the end of its string can also cause a difference in the amount of charge that reaches its channel when driven by the potential on the bit line. In addition, the presence of dummy cells at either end of the memory string may have a greater impact on the characteristics of the memory cells near the dummy cells on the string than on the characteristics of the memory cells farther from the dummy cells on the string. Depending on the level of the cell within the three-dimensional stack of word line layers, many other factors can affect cell characteristics. Therefore, in conventional devices, the programming voltage and the pass voltage VpassP are often optimized for their specific level in the stack.

The adjustment concept can also be extended to embodiments of the invention. Specifically, it is not necessary to make VpassP the same voltage no matter where the indicator “VpassP” appears in FIG. 4. According to a specific character line, a specific embodiment may be designed in which VpassP is slightly changed for different character lines. For the same reason, specific embodiments may be designed in which VpassP1 applied to WL (n + 1) is slightly different from VpassP1 applied to WL (n-1). In some embodiments, the following settings are still correct: all VpassP1 voltages are always less than Vpgm, and all VpassP voltages are always less than all VpassP1 voltages. In some embodiments, the highest VpassP voltage is still lower than the lowest VpassP1. Because the change is small, if the difference between the pass voltages applied to two different word lines in the word line is only due to adjustments to different word lines in the array or due to manufacturing tolerances, then the Pass voltages are considered herein to be "substantially" the same.

Secondly, it should be understood that even if VpassP1 is used on one side of the selected word line and VpassP1 is not used on the other side of the selected word line, some advantageous effects of the concept can still be obtained. For example, FIG. 4 may be changed such that the voltage applied to WL (n-1) is VpassP1, but the voltage applied to WL (n + 1) is only VpassP (or vice versa). Usually this is not a better setting, but it is a setting that will still get some beneficial effects from the concepts in this article.

Thirdly, it should be understood that, in the embodiment shown in FIG. 4, as the distance from the selected word line increases, the voltages applied to the various word lines during the programming phase are self-applied to the selected word line WL (n). Vpgm to VpassP applied to the character line farther from the selected character line WL (n) is decreased in two steps. But the concept can be extended to incorporate more than two stepwise reductions. An example of such an embodiment is shown in FIG. 6. FIG. 6 is similar to the embodiment shown in FIG. 4 except that during the programming phase, the control circuit system applies a voltage VpassP1 to each WL (n ± 1). But it also applies a voltage VpassP2 to each WL (n ± 2). VpassP is applied to all WL (k), where k is between 0 and n-3 including 0 and n-3, or between n + 3 and i-1 including n + 3 and i-1. In this embodiment, Vpgm> VpassP1> VpassP2> VpassP. Another embodiment may implement stepwise reduction of more than three pass voltages, and so on.

In addition, it is not required that in each embodiment, each stepwise reduction of the pass voltage is limited to a single layer. Examples can be described as follows: § WL (n): Vpgm § WL (n ± 1): VpassP1 § WL (n ± 2): WL (n ± 3): VpassP2 § WL (n ± 4) and later: VpassP

In general, a different pass voltage can be applied to each word line on one side of the selected word line, as long as VpassP is applied to the word line furthest from the selected word line and to each word line located in the middle. The pass voltage of one word line may be less than Vpgm and greater than or substantially equal to VpassP. The same applies to the other side of the selected character line. Preferably, but not necessarily, the passing voltage applied to a specific word line during the programming phase monotonically decreases as the distance between the specific word line and the selected word line increases. That is, the pass voltage applied to each successive word line is substantially the same as the pass voltage applied to the next word line farther from the selected word line, or higher than the pass voltage applied to the next farther word line from the selected word line. The pass voltage of the word line. In addition, it can be said that the pass voltage (VpassP) applied to the furthest word line is smaller than the pass voltage (VpassPk) applied to at least one word line located between the furthest word line and the selected word line, the pass voltage (VpassPk) is then less than the programming voltage Vpgm.

Another change is caused by the floating nature of the channels in the memory cells relative to the substrate on which the memory array is formed. Specifically, although FIG. 2 shows a “gate-all-circle” 3D memory array in which strings of memory cells extend vertically through the column, the aspect of the present invention is also applied to strings in which memory cells are horizontal on multiple layers. Extended 3D memory array. The aspect of the present invention is also applied to a two-dimensional memory array including a floating body. Many other changes will be apparent.

FIG. 7 illustrates an integrated circuit 750 including a memory array 700 (eg, as shown in FIG. 2). Integrated circuit 750 includes a set of pads 761, 762, and 765 in this figure. The bonding pad is a structure configured on an integrated circuit for connecting to an external wiring, and the external wiring is configured to carry a signal such as an address, a control signal such as a chip selection signal, a clock signal, and a data signal. Wait.

The memory array includes a plurality of access lines 712 and 713. In some embodiments, the memory array includes a first access line 713 (eg, a bit line) and a second access line 712 (eg, a word line or a source line). In some embodiments in which the second access line 712 is a source line, a word line for controlling a switching element in a memory cell shown in FIG. 2 is additionally provided.

The first access line decoder 703 is coupled to the plurality of first access lines 713 and is in electrical communication with the plurality of first access lines 713. The plurality of first access lines 713 are in a memory. The plan view of the array 700 is arranged in rows for reading data from the memory cells in the memory array 700 and writing the data into the memory cells in the memory array 700. The first access line decoder 703 may include a first access line driver. A second access line decoder 702 is coupled to and electrically communicates with the plurality of second access lines 712, and the plurality of second access lines 712 are arranged as A conductive layer in the memory array 700. The second access line decoder 702 may include a second access line driver that applies a bias voltage to the word line 712 under the control of the controller 709 and the address decoding. The addresses are supplied to the first access line decoder 703 and the second access line decoder 702 on the bus 705. In this embodiment, the sense amplifier and other supporting circuitry (eg, a pre-charge circuit, etc.) are coupled to the first access line decoder 703 via a bus 707.

The data is supplied via the data input line 721 to the input / output driver 723 or other data source of the pad (765) on the integrated circuit 750 to the data input structure in block 706. The data is supplied via the data output line 722 from the sense amplifier in block 706 to the input / output driver 723 on the integrated circuit 750, or to other data destinations located inside or outside the integrated circuit 750.

The state machine or other logic in the controller 709 controls the bias arrangement supply circuit 708 to perform memory operations such as write (set and reset, or program and erase) and read operations. The bias array supply circuit 708 may include a voltage regulator, a level shifter, or a charge pump to provide a bias array with different voltage levels, and provide the first access line decoder 703 for a program operation and a read operation. And the second access line decoder 702 delivers the desired offset arrangement as described herein. In addition, the control circuit system in the controller 709 coordinates the operation of the sensing circuit system in block 706 for reading operations and programming operations. The circuit system may be implemented by using dedicated logic, general logic, or a combination thereof.

The controller 709 is configured to execute a programming loop in response to the command decoding. In a programming operation as described herein, the controller 709 is configured to apply a bias voltage to the array in response to the precharge phase and the programming phase of the read operation, including Vpgm, VpassP, and all VpassPk (for All character lines except n) k). In some embodiments, the controller 709 includes logic to cause the functions described with reference to FIGS. 4 to 6 to be performed. The control circuit system 326 in FIGS. 4 and 6 includes all components shown in FIG. 7 except the memory array 700 itself. [Other implementation methods]

Other implementations of the methods described herein may include non-transitory computer-readable storage media storing instructions executable by a processor to apply the voltage waveform described above. Another implementation of the methods described herein may include a system including a memory and one or more processors, the processors being operable to execute instructions stored in the memory to apply the voltage waveform described above .

Any of the data structures and codes explained or referenced above are stored on non-transitory computer-readable media according to a number of implementation methods, and the non-transitory computer-readable media may be codes and / or can be stored for use by a computer system Any device or media. This includes, but is not limited to, volatile memory, non-volatile memory, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), magnetic and optical storage Device (eg, disk drive, magnetic tape, compact disc (CD), digital versatile disc or digital video disc (DVD)), or capable of storing now known or later developed Computer can read media from other media. It may also include more than one medium that can be used together as non-transitory computer-readable media.

A given signal, event, or value used herein "responses" to a predecessor signal, event, or value if the preamble signal, event, or value affects the given signal, event, or value. If there are intermediate processing elements, steps or time periods, the given signal, event or value may still "respond" to the preamble signal, event or value. If more than one signal, event, or value is combined by an intermediate processing element or step, the signal output of the processing element or step is considered to be "responsive to" each of the signal, event, or value inputs. If the given signal, event, or value is the same as the preamble signal, event, or value, then this is only a degradation situation, where the given signal, event, or value can still be considered to be "responsive to" the preamble signal, event, or value. A given signal, event or value "depends on" another signal, event or value is defined in a similar way.

"Identification" of an item of information used in this article does not necessarily require a direct indication of the item in question. Information in a field can be "identified" simply by referring to actual information through one or more layers of indirection, or by identifying one or more items of different information sufficient to determine the actual items of information together. In addition, the term "indication" is used herein to mean the same as "identification."

The applicant hereby discloses each of the individual features described herein and any combination of two or more of these features in isolation to the extent that such features or combinations can be based on this specification based on those skilled in the art. The common general knowledge is implemented as a whole, regardless of whether such features or combinations of features solve any problems disclosed herein, and do not limit the scope of patent application scope. The applicant indicates that aspects of the invention may consist of any such feature or combination of features. From the foregoing description, it will be apparent to those skilled in the art that various modifications can be made within the scope of the invention.

The foregoing description of the preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exclusive or to limit the invention to the precise form disclosed herein. Obviously, many retouches and changes will be apparent to practitioners familiar with this technology. Specifically and without limitation, any and all variations set forth, suggested or incorporated by reference in the background section of this patent application are specifically incorporated herein by reference to the embodiments of the present invention. Instructions. In addition, any and all changes set forth, suggested, or incorporated by reference herein with respect to any one embodiment will also be considered to be taught relative to all other embodiments. The embodiments described herein were chosen and explained in order to best explain the principles of the invention and its practical application, thereby enabling those skilled in the art to target various embodiments and apply various finishes suitable for the specific use envisaged. Understand the invention. The scope of the present invention is intended to be defined by the following patent applications and their equivalents.

10‧‧‧ shared source line

11‧‧‧Character line conductive layer

12‧‧‧string selection line

13‧‧‧ ground selection line

15‧‧‧columns

20‧‧‧bit wire conductor

110‧‧‧core

111‧‧‧Seams

112‧‧‧First floor

113‧‧‧ floors

114‧‧‧Second floor

310‧‧‧Selected String

311‧‧‧No strings selected

314, 315‧‧‧‧Serial selection gate (string selection line)

318 (0), 318 (n-2), 318 (n-1), 318 (n), 318 (n + 1), 318 (n + 2), 318 (i-2), 318 (i-1 ), 319 (0), 319 (n-2), 319 (n-1), 319 (n), 319 (n + 1), 319 (n + 2), 319 (i-2), 319 (i -1) ‧‧‧Memory Cell

320‧‧‧ Lower selection gate (lower selection line)

322‧‧‧bit line conductor (bit line)

326‧‧‧Control circuit system

328‧‧‧share selection line

700‧‧‧Memory Array

702‧‧‧Second Access Line Decoder

703‧‧‧first access line decoder

705‧‧‧Bus

706‧‧‧block

707‧‧‧bus

708‧‧‧Offset arrangement supply circuit

709‧‧‧controller

712‧‧‧Second Access Line (Character Line)

713‧‧‧first access line

721‧‧‧ data input line

722‧‧‧Data output line

723‧‧‧input (output driver)

750‧‧‧Integrated Circuit

761, 762, 765‧‧‧ pads

CSL‧‧‧ Shared Source Line

LSG‧‧‧Bottom selection gate

LSL‧‧‧Lower selection line

SSG‧‧‧ String Select Gate

SSL‧‧‧ String Selection Line

Vb1‧‧‧bit line voltage

VpassP‧‧‧pass voltage (second pass voltage)

VpassP1‧‧‧First intermediate pass voltage

VpassP2‧‧‧Third pass voltage

Vpgm‧‧‧ Programming voltage

WL (0), WL (n-2), WL (n-1), WL (n), WL (n + 1), WL (n + 2), WL (i-2), WL (i-1 ) ‧‧‧Character line conductor (character line)

The present invention will be explained with regard to specific embodiments of the present invention, and with reference to the drawings, in which: FIG. 1 is a horizontal cross-sectional view of a row of tubular BiCS flash cells. FIG. 2 is a perspective view of a memory array in an exemplary 3D semiconductor memory device. FIG. 3 is a simplified circuit diagram showing a memory cell and an access transistor in two columns of the memory array shown in FIG. 2. 4 and 6 show versions of the circuit diagram of FIG. 3 showing aspects of the present invention. FIG. 5 is a simplified timing diagram illustrating an exemplary voltage waveform applied by the control circuitry to the device shown in FIG. 4. FIG. 7 is a block diagram of an integrated circuit memory device including the memory array shown in FIG. 2 and the control circuit system shown in FIGS. 4 and 6.

Claims (8)

A programming method for programming selected memory cells in a memory array while prohibiting programming of cells in memory cells of an unselected string in a memory array, the memory array comprising: a plurality of word lines A conductor, a plurality of strings of memory cells connected in series, the string crossing the word line conductor, and the memory cell being located at the intersection between the word line conductor and the string, each string having Respective first and second ends, and a plurality of bit line conductors are respectively connected to respective first ends of respective different subsets of the strings, wherein one of the multiple strings of memory cells Is a selected string, and another string of the plurality of strings of memory cells is the unselected string, and a selected one of the word line conductors is at the selected memory cell with the selected string The word line conductor crossed by a string, the programming method comprising: establishing a channel of the memory cell in the unselected string crossing the selected word line during a precharge phase of a programming cycle Forbidden voltage; and in the precharge stage During the programming phase of the programming cycle that follows, while the channels of the memory cells in the unselected string crossing the selected word line are floating: while crossing the selected word line A low channel voltage is established in a channel of the memory cell in the selected string, and a programming voltage is applied to the selected word line conductor, and a difference between the programming voltage and the low channel voltage is sufficient to enable the The programming of the memory cells in the selected string where the selected word line intersects is applied to a first word line conductor of the word line conductors which intersects the selected string at a first memory cell. A first pass voltage, a second pass voltage is applied to a second word line conductor of the word line conductors crossing the selected string at a second memory cell, the first word line conductor is located in the Applying a third pass between the selected word line conductor and the second word line conductor, and a third word line conductor in the word line conductor crossing the selected string at a third memory cell Voltage, the third word line conductor is located on the first Element line between word line conductor and the second conductor, wherein the programming voltage> by the first voltage> third voltage by> the second pass voltage. The programming method as described in claim 1, wherein the first word line conductor is adjacent to the selected word line conductor. The programming method according to item 2 of the scope of patent application, further comprising: during the programming phase, the fourth word line in the word line conductor crossing the selected string at the fourth memory cell A fourth pass voltage substantially equal to the first pass voltage is applied to the conductor, the fourth word line conductor is adjacent to the selected word line conductor and the selected word line conductor is located in the first word Between the element line conductor and the fourth word element line conductor. The programming method according to item 3 of the scope of patent application, further comprising: during the programming phase, the fifth word line in the word line conductor crossing the selected string at a fifth memory cell A fifth pass voltage substantially equal to the second pass voltage is applied to the conductor, the fifth word line conductor is adjacent to the fourth word line conductor and the fourth word line conductor is located at the first Between a five-character line conductor and the selected character line conductor. The programming method according to item 1 of the scope of patent application, wherein the selected character line is the n-th character line among i character lines numbered WL (0) ... WL (i-1) , Wherein applying the second passing voltage to a second word line conductor of the word line conductors includes applying the second passing voltage to a word line numbered WL (0), and the programming method includes: During the programming phase, a respective intermediate pass voltage is applied to each of the word lines numbered WL (1) ... WL (n-1) including the first word line conductor, said The intermediate pass voltage is less than the programming voltage and greater than or substantially equal to the second pass voltage. The programming method according to item 5 of the scope of patent application, further comprising: during the programming phase, applying to each of the word lines numbered WL (n + 1) ... WL (i-1) A corresponding intermediate pass voltage, the intermediate pass voltage being less than the programming voltage and greater than or substantially equal to the second passing voltage. The programming method according to item 5 of the scope of patent application, wherein, for each k-th word line, a pass voltage applied to the k-th word line is greater than or substantially equal to being applied to the k-1th line The pass voltage of the word line, where k = 1 ... (n-1). A memory system includes: a memory array having: a plurality of word line conductors, a plurality of strings of memory cells connected in series, the string crossing the word line conductors, and the memory cells located in the characters At the intersections between the line conductors and the strings, each of the strings has respective opposite first and second ends, and a plurality of bit line conductors are connected to respective different subsets of the strings. Respective first ends, wherein one of the plurality of strings of memory cells is a selected string, and the other string of the plurality of strings of memory cells is an unselected string, the selected one of the word line conductors The word line conductor is the word line conductor crossing the selected string at the selected memory cell; and a control circuit system for: during a pre-charge phase of a programming cycle, A forbidden voltage is established in a channel of the memory cell in the unselected string crossing the line; and during a programming phase of the programming cycle after the precharge phase, at a location crossing the selected word line The memory cell in the unselected string When the channel is floating: a low channel voltage is established in a channel of the memory cell in the selected string crossing the selected word line, a programming voltage is applied to the selected word line conductor, and the programming The difference between the voltage and the low channel voltage is sufficient to enable programming of the memory cell in the selected string that intersects the selected word line; to cross the selected string at a first memory cell A first pass voltage is applied to a first word line conductor in the word line conductors; a second word line conductor in the word line conductors crossing the selected string at a second memory cell is applied A second passing voltage, the first word line conductor is located between the selected word line conductor and the second word line conductor; and the second word line conductor crossing the selected string at a third memory cell A third word line conductor of the word line conductors applies a third passing voltage, the third word line conductor is located between the first word line conductor and the second word line conductor, wherein the Program voltage> the first pass voltage> the third pass voltage> all The second pass voltage.