TWI659554B - Organic thin film transistor - Google Patents

Organic thin film transistor Download PDF

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TWI659554B
TWI659554B TW106115494A TW106115494A TWI659554B TW I659554 B TWI659554 B TW I659554B TW 106115494 A TW106115494 A TW 106115494A TW 106115494 A TW106115494 A TW 106115494A TW I659554 B TWI659554 B TW I659554B
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layer
source
drain
thin film
film transistor
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TW201901996A (en
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林冠嶧
唐文忠
陳柏煒
許毓麟
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元太科技工業股份有限公司
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Abstract

一種有機薄膜電晶體包含基板、源極/汲極層、第一緩衝層、半導體層、閘極絕緣層與閘極。源極/汲極層位於基板上。源極/汲極層具有源極區與汲極區。第一緩衝層位於源極區與汲極區之間,且第一緩衝層覆蓋至少部分的源極區與至少部分的汲極區。半導體層位於源極/汲極層與第一緩衝層上。第一緩衝層位於半導體層、源極區、汲極區與基板之間。閘極絕緣層覆蓋源極/汲極層與半導體層。閘極位於閘極絕緣層上,且閘極絕緣層的一部分位於閘極與半導體層之間。 An organic thin film transistor includes a substrate, a source / drain layer, a first buffer layer, a semiconductor layer, a gate insulating layer, and a gate. The source / drain layer is on the substrate. The source / drain layer has a source region and a drain region. The first buffer layer is located between the source region and the drain region, and the first buffer layer covers at least part of the source region and at least part of the drain region. The semiconductor layer is located on the source / drain layer and the first buffer layer. The first buffer layer is located between the semiconductor layer, the source region, the drain region, and the substrate. The gate insulating layer covers the source / drain layer and the semiconductor layer. The gate is located on the gate insulation layer, and a part of the gate insulation layer is located between the gate and the semiconductor layer.

Description

有機薄膜電晶體    Organic thin film transistor   

本案是有關於一種有機薄膜電晶體。 This case relates to an organic thin film transistor.

一般而言,有機薄膜電晶體的源極/汲極層的材質為金、銀或其他能與自組裝單分子膜(Self-assembly monolayer;SAM)反應的金屬,其中自組裝單分子膜為有機薄膜電晶體的半導體層。 Generally speaking, the material of the source / drain layer of an organic thin film transistor is gold, silver, or other metal capable of reacting with a self-assembly monolayer (SAM). The self-assembly monolayer is organic. Semiconductor layer of a thin film transistor.

在製作有機薄膜電晶體時,會先圖案化源極/汲極層以形成相隔間距的源極區與汲極區,接著塗佈半導體層在靠近間距的源極區與汲極區上與源極區與汲極區之間的間距中。然而,受限於源極/汲極層的材質,在圖案化源極/汲極層後,會在源極區與汲極區靠近間距的位置產生楔形底切(taper undercut)結構。如此一來,在間距中的半導體層其靠近楔形底切結構的位置會具有較大的厚度,而較大厚度的半導體層會影響分子排列。也就是說,半導體層不均勻的厚度將會對有機薄膜電晶體的電性穩定性造成不利的影響。 When fabricating an organic thin film transistor, the source / drain layer is first patterned to form a source and drain region with an interval, and then a semiconductor layer is coated on the source and drain regions near the pitch and the source. The distance between the pole and drain regions. However, due to the material of the source / drain layer, after patterning the source / drain layer, a tapered undercut structure is generated at a position close to the distance between the source region and the drain region. In this way, the semiconductor layer in the pitch will have a larger thickness near the wedge-shaped undercut structure, and the semiconductor layer with a larger thickness will affect the molecular arrangement. In other words, the uneven thickness of the semiconductor layer will adversely affect the electrical stability of the organic thin film transistor.

本發明之一技術態樣為一種有機薄膜電晶體。 One aspect of the present invention is an organic thin film transistor.

根據本發明一實施方式,一種有機薄膜電晶體包含基板、源極/汲極層、第一緩衝層、半導體層、閘極絕緣層與閘極。源極/汲極層位於基板上。源極/汲極層具有源極區與汲極區。第一緩衝層位於源極區與汲極區之間,且第一緩衝層覆蓋至少部分的源極區與至少部分的汲極區。半導體層位於源極/汲極層與第一緩衝層上。第一緩衝層位於半導體層、源極區、汲極區與基板之間。閘極絕緣層覆蓋源極/汲極層與半導體層。閘極位於閘極絕緣層上,且閘極絕緣層的一部分位於閘極與半導體層之間。 According to an embodiment of the present invention, an organic thin film transistor includes a substrate, a source / drain layer, a first buffer layer, a semiconductor layer, a gate insulating layer, and a gate. The source / drain layer is on the substrate. The source / drain layer has a source region and a drain region. The first buffer layer is located between the source region and the drain region, and the first buffer layer covers at least part of the source region and at least part of the drain region. The semiconductor layer is located on the source / drain layer and the first buffer layer. The first buffer layer is located between the semiconductor layer, the source region, the drain region, and the substrate. The gate insulating layer covers the source / drain layer and the semiconductor layer. The gate is located on the gate insulation layer, and a part of the gate insulation layer is located between the gate and the semiconductor layer.

在本發明一實施方式中,上述有機薄膜電晶體更包含保護層。保護層沿半導體層設置。半導體層位於保護層與源極/汲極層之間,及保護層與第一緩衝層之間。 In one embodiment of the present invention, the organic thin film transistor further includes a protective layer. A protective layer is provided along the semiconductor layer. The semiconductor layer is located between the protection layer and the source / drain layer, and between the protection layer and the first buffer layer.

在本發明一實施方式中,上述有機薄膜電晶體更包含光阻層。光阻層位於保護層上,且位於閘極絕緣層與保護層之間。 In one embodiment of the present invention, the organic thin film transistor further includes a photoresist layer. The photoresist layer is located on the protection layer, and is located between the gate insulation layer and the protection layer.

在本發明一實施方式中,上述有機薄膜電晶體更包含阻障層。阻障層位於基板上。第一緩衝層位於半導體層、源極區、汲極區與阻障層之間。 In one embodiment of the present invention, the organic thin film transistor further includes a barrier layer. The barrier layer is on the substrate. The first buffer layer is located between the semiconductor layer, the source region, the drain region, and the barrier layer.

在本發明一實施方式中,上述有機薄膜電晶體更包含第二緩衝層。第二緩衝層位於阻障層上。第一緩緩衝層位於半導體層、源極區、汲極區與第二緩衝層之間。 In one embodiment of the present invention, the organic thin film transistor further includes a second buffer layer. The second buffer layer is on the barrier layer. The first buffer layer is located between the semiconductor layer, the source region, the drain region, and the second buffer layer.

在本發明一實施方式中,上述源極區具有相對的第一表面與第二表面,且具有鄰接第一表面與第二表面的側壁,第一表面朝向基板,且側壁與第一表面夾鈍角。 In an embodiment of the present invention, the source region has a first surface and a second surface opposite to each other, and has a sidewall adjacent to the first surface and the second surface, the first surface faces the substrate, and the sidewall and the first surface are at an obtuse angle .

在本發明一實施方式中,上述第一緩衝層具有中央部與延伸部,中央部位於源極區與汲極區之間,延伸部位於源極區的第二表面上。 In an embodiment of the present invention, the first buffer layer has a central portion and an extension portion, the central portion is located between the source region and the drain region, and the extension portion is located on the second surface of the source region.

在本發明一實施方式中,上述至少部分的源極區位於延伸部與中央部之間。 In an embodiment of the present invention, the at least part of the source region is located between the extending portion and the central portion.

在本發明一實施方式中,上述第一緩衝層接觸源極區的側壁。 In an embodiment of the present invention, the first buffer layer is in contact with a sidewall of the source region.

在本發明一實施方式中,上述汲極區具有相對的第一表面與第二表面,且具有鄰接第一表面與第二表面的側壁,第一表面朝向基板,且側壁與第一表面夾鈍角。 In an embodiment of the present invention, the drain region has a first surface and a second surface opposite to each other, and has a sidewall adjacent to the first surface and the second surface, the first surface faces the substrate, and the sidewall and the first surface are at an obtuse angle. .

在本發明上述實施方式中,由於第一緩衝層位於源極區與汲極區之間且覆蓋至少部分的源極區與至少部分的汲極區,因此半導體層可位於源極/汲極層與第一緩衝層上。這樣的設計,第一緩衝層可用來填補源極區與汲極區之間的空間,避免半導體層形成在源極區與汲極區的楔形底切(taper undercut)結構上而產生較大的厚度。如此一來,半導體層可具有均勻的厚度,不會影響分子排列,能提升有機薄膜電晶體的電性穩定性。 In the above embodiment of the present invention, since the first buffer layer is located between the source region and the drain region and covers at least part of the source region and at least part of the drain region, the semiconductor layer may be located at the source / drain layer With the first buffer layer. In this design, the first buffer layer can be used to fill the space between the source region and the drain region, so as to prevent the semiconductor layer from being formed on the tapered undercut structure of the source region and the drain region to produce a larger thickness. In this way, the semiconductor layer can have a uniform thickness without affecting the molecular arrangement, and can improve the electrical stability of the organic thin film transistor.

100、100a、100b、100c、100d‧‧‧有機薄膜電晶體 100, 100a, 100b, 100c, 100d‧‧‧ organic thin film transistor

110‧‧‧基板 110‧‧‧ substrate

120‧‧‧源極/汲極層 120‧‧‧Source / Drain Layer

122‧‧‧源極區 122‧‧‧Source area

124‧‧‧汲極區 124‧‧‧ Drain

125a‧‧‧第一表面 125a‧‧‧first surface

125b‧‧‧第二表面 125b‧‧‧Second surface

126‧‧‧側壁 126‧‧‧ sidewall

127a‧‧‧第一表面 127a‧‧‧first surface

127b‧‧‧第二表面 127b‧‧‧Second surface

128‧‧‧側壁 128‧‧‧ sidewall

130‧‧‧第一緩衝層 130‧‧‧first buffer layer

132‧‧‧中央部 132‧‧‧ Central

134、136‧‧‧延伸部 134, 136‧‧‧ extension

140‧‧‧半導體層 140‧‧‧Semiconductor layer

150‧‧‧閘極絕緣層 150‧‧‧Gate insulation

160‧‧‧閘極 160‧‧‧Gate

170‧‧‧保護層 170‧‧‧ protective layer

180‧‧‧光阻層 180‧‧‧Photoresistive layer

190‧‧‧阻障層 190‧‧‧ barrier layer

210‧‧‧鈍化層 210‧‧‧ passivation layer

220‧‧‧畫素電極 220‧‧‧pixel electrode

230‧‧‧第二緩衝層 230‧‧‧Second buffer layer

θ1、θ2‧‧‧鈍角 θ1, θ2‧‧‧ obtuse angle

第1圖繪示根據本發明一實施方式之有機薄膜電晶體的剖面圖。 FIG. 1 is a cross-sectional view of an organic thin film transistor according to an embodiment of the present invention.

第2圖繪示根據本發明一實施方式之有機薄膜電晶體的剖 面圖。 FIG. 2 is a cross-sectional view of an organic thin film transistor according to an embodiment of the present invention.

第3圖繪示根據本發明一實施方式之有機薄膜電晶體的剖面圖。 FIG. 3 is a cross-sectional view of an organic thin film transistor according to an embodiment of the present invention.

第4圖繪示根據本發明一實施方式之有機薄膜電晶體的剖面圖。 FIG. 4 is a cross-sectional view of an organic thin film transistor according to an embodiment of the present invention.

第5圖繪示根據本發明一實施方式之有機薄膜電晶體的剖面圖。 FIG. 5 is a cross-sectional view of an organic thin film transistor according to an embodiment of the present invention.

以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.

第1圖繪示根據本發明一實施方式之有機薄膜電晶體100的剖面圖。如圖所示,有機薄膜電晶體100包含基板110、源極/汲極層120、第一緩衝層130、半導體層140、閘極絕緣層150與閘極160。其中,源極/汲極層120位於基板110的表面上。源極/汲極層120具有源極區122與汲極區124,且源極區122與汲極區124相隔一間距。第一緩衝層130填補了此間距,也就是位於源極區122與汲極區124之間。此外,第一緩衝層130還延伸到源極區122與汲極區124上,以覆蓋至少部 分的源極區122與至少部分的汲極區124。上述第一緩衝層130的材料可以是高分子聚合物。 FIG. 1 is a cross-sectional view of an organic thin film transistor 100 according to an embodiment of the present invention. As shown, the organic thin film transistor 100 includes a substrate 110, a source / drain layer 120, a first buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, and a gate 160. The source / drain layer 120 is located on the surface of the substrate 110. The source / drain layer 120 has a source region 122 and a drain region 124, and the source region 122 and the drain region 124 are separated by a distance. The first buffer layer 130 fills this gap, that is, it is located between the source region 122 and the drain region 124. In addition, the first buffer layer 130 extends to the source region 122 and the drain region 124 to cover at least a portion of the source region 122 and at least a portion of the drain region 124. The material of the first buffer layer 130 may be a polymer.

半導體層140位於源極/汲極層120與第一緩衝層130上,使得第一緩衝層130位於半導體層140、源極區122、汲極區124與基板110之間。也就是說,第一緩衝層130由半導體層140、源極區122、汲極區124與基板110圍繞。閘極絕緣層150覆蓋源極/汲極層120與半導體層140。閘極160位於閘極絕緣層150上,且閘極絕緣層150的一部分位於閘極160與半導體層140之間。 The semiconductor layer 140 is located on the source / drain layer 120 and the first buffer layer 130, so that the first buffer layer 130 is located between the semiconductor layer 140, the source region 122, the drain region 124 and the substrate 110. That is, the first buffer layer 130 is surrounded by the semiconductor layer 140, the source region 122, the drain region 124 and the substrate 110. The gate insulating layer 150 covers the source / drain layer 120 and the semiconductor layer 140. The gate 160 is located on the gate insulating layer 150, and a part of the gate insulating layer 150 is located between the gate 160 and the semiconductor layer 140.

在本實施方式中,源極/汲極層120的材質可以為銀或金。在圖案化源極/汲極層120時(例如蝕刻製程),會在源極區122與汲極區124產生楔形底切(taper undercut)結構,而產生鈍角θ1、θ2。此外,閘極絕緣層150的材質可以包含有機材料,成為有機閘極絕緣體(Organic Gate Insulator;OGI)。 In this embodiment, the material of the source / drain layer 120 may be silver or gold. When the source / drain layer 120 is patterned (eg, an etching process), a tapered undercut structure is generated in the source region 122 and the drain region 124, and obtuse angles θ1 and θ2 are generated. In addition, the material of the gate insulating layer 150 may include an organic material to become an organic gate insulator (Organic Gate Insulator; OGI).

半導體層140可採旋轉塗佈(Spin coating)或狹縫塗佈(Slit coating)的方式形成,但並不用以限制本發明。由於第一緩衝層130位於源極區122與汲極區124之間且覆蓋至少部分的源極區122與至少部分的汲極區124,因此半導體層140可位於源極/汲極層120與第一緩衝層130上。這樣的設計,第一緩衝層130可用來填補源極區122與汲極區124之間的空間,避免因半導體層140形成在源極區122與汲極區124的楔形底切結構區,而產生較大的厚度,導致半導體層140整體的厚度不均勻,進而對電性穩定性造成影響。藉由第一緩衝層 130位於半導體層140的下方,使半導體層140形成時,可具有均勻的厚度,以提升有機薄膜電晶體100的電性穩定性。 The semiconductor layer 140 may be formed by spin coating or slit coating, but it is not intended to limit the present invention. Since the first buffer layer 130 is located between the source region 122 and the drain region 124 and covers at least a portion of the source region 122 and at least a portion of the drain region 124, the semiconductor layer 140 may be located at the source / drain layer 120 and On the first buffer layer 130. With this design, the first buffer layer 130 can be used to fill the space between the source region 122 and the drain region 124 to avoid the semiconductor layer 140 being formed in the wedge-shaped undercut structure region of the source region 122 and the drain region 124. The larger thickness results in uneven thickness of the entire semiconductor layer 140, which further affects the electrical stability. The first buffer layer 130 is located below the semiconductor layer 140, so that the semiconductor layer 140 can have a uniform thickness when it is formed to improve the electrical stability of the organic thin film transistor 100.

在本實施方式中,源極區122具有相對的第一表面125a與第二表面125b,且具有鄰接第一表面125a與第二表面125b的側壁126。汲極區124具有相對的第一表面127a與第二表面127b,且具有鄰接第一表面127a與第二表面127b的側壁128。源極區122的第一表面125a與汲極區124的第一表面127a均朝向基板110,源極區122的第二表面125b與汲極區124的第二表面127b均背對基板110。源極區122的側壁126與第一表面125a夾鈍角θ1,且汲極區124的側壁128與第一表面127a夾鈍角θ2。 In this embodiment, the source region 122 has a first surface 125 a and a second surface 125 b opposite to each other, and has a sidewall 126 adjacent to the first surface 125 a and the second surface 125 b. The drain region 124 has a first surface 127a and a second surface 127b opposite to each other, and has a sidewall 128 adjacent to the first surface 127a and the second surface 127b. The first surface 125a of the source region 122 and the first surface 127a of the drain region 124 both face the substrate 110, and the second surface 125b of the source region 122 and the second surface 127b of the drain region 124 both face away from the substrate 110. The sidewall 126 of the source region 122 is at an obtuse angle θ1 with the first surface 125a, and the sidewall 128 of the drain region 124 is at an obtuse angle θ2 with the first surface 127a.

此外,第一緩衝層130具有中央部132與延伸部134、136,中央部132位於源極區122與汲極區124之間。延伸部134位於源極區122的第二表面125b上,且延伸部136位於汲極區124的第二表面127b上。此外,第一緩衝層130接觸源極區122的側壁126與第二表面125b,且第一緩衝層130接觸汲極區124的側壁128與第二表面127b。如此一來,至少部分的源極區122位於延伸部134與中央部132之間,且至少部分的汲極區124位於延伸部136與中央部132之間。這樣的設計,可確保靠近側壁126、128(楔形底切結構)的半導體層140可由第一緩衝層130隔開與支撐,避免半導體層140落入源極區122與汲極區124之間的空間中,而導致半導體層140的厚度不均勻。 In addition, the first buffer layer 130 has a central portion 132 and extension portions 134 and 136. The central portion 132 is located between the source region 122 and the drain region 124. The extension portion 134 is located on the second surface 125 b of the source region 122, and the extension portion 136 is located on the second surface 127 b of the drain region 124. In addition, the first buffer layer 130 contacts the sidewall 126 and the second surface 125b of the source region 122, and the first buffer layer 130 contacts the sidewall 128 and the second surface 127b of the drain region 124. As such, at least a portion of the source region 122 is located between the extension 134 and the central portion 132, and at least a portion of the drain region 124 is located between the extension 136 and the central portion 132. Such a design can ensure that the semiconductor layer 140 near the sidewalls 126 and 128 (wedge-shaped undercut structure) can be separated and supported by the first buffer layer 130 to prevent the semiconductor layer 140 from falling between the source region 122 and the drain region 124. In the space, the thickness of the semiconductor layer 140 is not uniform.

應瞭解到,已敘述過的元件連接關係、材料與功 效將不再重複贅述,合先敘明。在以下敘述中,將說明其他型式的有機薄膜電晶體。 It should be understood that the connection relationships, materials and functions of components that have already been described will not be repeated here, but they will be described together. In the following description, other types of organic thin film transistors will be described.

第2圖繪示根據本發明一實施方式之有機薄膜電晶體100a的剖面圖。有機薄膜電晶體100a包含基板110、源極/汲極層120、第一緩衝層130、半導體層140、閘極絕緣層150與閘極160。與第1圖實施方式不同的地方在於:有機薄膜電晶體100a還包含保護層170、光阻層180與阻障層190。其中,保護層170沿半導體層140的表面設置,半導體層140位於保護層170與源極/汲極層120之間,且半導體層140也位於保護層170與第一緩衝層130之間。 FIG. 2 is a cross-sectional view of an organic thin film transistor 100a according to an embodiment of the present invention. The organic thin film transistor 100a includes a substrate 110, a source / drain layer 120, a first buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, and a gate 160. The difference from the embodiment in FIG. 1 is that the organic thin film transistor 100a further includes a protective layer 170, a photoresist layer 180, and a barrier layer 190. The protection layer 170 is disposed along the surface of the semiconductor layer 140, the semiconductor layer 140 is located between the protection layer 170 and the source / drain layer 120, and the semiconductor layer 140 is also located between the protection layer 170 and the first buffer layer 130.

此外,光阻層180位於保護層170上,且位於閘極絕緣層150與保護層170之間。阻障層190位於基板110上且沿基板110的表面設置,因此有機薄膜電晶體100a的第一緩衝層130是位於半導體層140、源極區122、汲極區124與阻障層190之間。也就是說,第一緩衝層130由半導體層140、源極區122、汲極區124與阻障層190圍繞。 In addition, the photoresist layer 180 is located on the protective layer 170 and is located between the gate insulating layer 150 and the protective layer 170. The barrier layer 190 is located on the substrate 110 and is disposed along the surface of the substrate 110. Therefore, the first buffer layer 130 of the organic thin film transistor 100a is located between the semiconductor layer 140, the source region 122, the drain region 124, and the barrier layer 190 . That is, the first buffer layer 130 is surrounded by the semiconductor layer 140, the source region 122, the drain region 124 and the barrier layer 190.

在本實施方式中,保護層170的材質可以包含有機材料,成為有機保護層(Organic Protective Layer;OPL)。光阻層180的材質可以包含有機材料,成為有機光阻(Organic Photoresist;OPR)層。阻障層190的材質可以包含矽的氮化物(SiNx)或矽的氧化物(SiOx),但並不用以限制本發明。 In this embodiment, the material of the protective layer 170 may include an organic material, and becomes an organic protective layer (Organic Protective Layer (OPL)). The material of the photoresist layer 180 may include an organic material, and becomes an organic photoresist (Organic Photoresist; OPR) layer. The material of the barrier layer 190 may include silicon nitride (SiNx) or silicon oxide (SiOx), but it is not intended to limit the present invention.

第3圖繪示根據本發明一實施方式之有機薄膜電晶體100b的剖面圖。有機薄膜電晶體100b包含基板110、源極/汲極層120、第一緩衝層130、半導體層140、閘極絕緣層 150與閘極160、保護層170、光阻層180與阻障層190。與第2圖實施方式不同的地方在於:有機薄膜電晶體100b還包含鈍化層210與畫素電極220。鈍化層210覆蓋閘極160與閘極絕緣層150,而畫素電極220位於鈍化層210上。在本實施方式中,鈍化層210的材質可以包含有機材料,成為有機鈍化(Organic Passivation;OPV)層。 FIG. 3 is a cross-sectional view of an organic thin film transistor 100b according to an embodiment of the present invention. The organic thin film transistor 100b includes a substrate 110, a source / drain layer 120, a first buffer layer 130, a semiconductor layer 140, a gate insulating layer 150 and a gate 160, a protective layer 170, a photoresist layer 180, and a barrier layer 190. . The difference from the embodiment in FIG. 2 is that the organic thin film transistor 100b further includes a passivation layer 210 and a pixel electrode 220. The passivation layer 210 covers the gate electrode 160 and the gate insulation layer 150, and the pixel electrode 220 is located on the passivation layer 210. In this embodiment, a material of the passivation layer 210 may include an organic material, and becomes an organic passivation (OPV) layer.

第4圖繪示根據本發明一實施方式之有機薄膜電晶體100c的剖面圖。有機薄膜電晶體100c包含基板110、源極/汲極層120、第一緩衝層130、半導體層140、閘極絕緣層150、閘極160、保護層170、光阻層180與阻障層190。與第2圖實施方式不同的地方在於:有機薄膜電晶體100c還包含第二緩衝層230。第二緩衝層230位於阻障層190上,使得第一緩衝層130位於半導體層140、源極區122、汲極區124與第二緩衝層230之間。也就是說,第一緩衝層130由半導體層140、源極區122、汲極區124與第二緩衝層230圍繞。 FIG. 4 is a cross-sectional view of an organic thin film transistor 100c according to an embodiment of the present invention. The organic thin film transistor 100c includes a substrate 110, a source / drain layer 120, a first buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, a gate 160, a protective layer 170, a photoresist layer 180, and a barrier layer 190. . The difference from the embodiment in FIG. 2 is that the organic thin film transistor 100c further includes a second buffer layer 230. The second buffer layer 230 is located on the barrier layer 190 such that the first buffer layer 130 is located between the semiconductor layer 140, the source region 122, the drain region 124 and the second buffer layer 230. That is, the first buffer layer 130 is surrounded by the semiconductor layer 140, the source region 122, the drain region 124 and the second buffer layer 230.

第5圖繪示根據本發明一實施方式之有機薄膜電晶體100d的剖面圖。有機薄膜電晶體100d包含基板110、源極/汲極層120、第一緩衝層130、半導體層140、閘極絕緣層150、閘極160、保護層170、光阻層180、阻障層190與第二緩衝層230。與第4圖實施方式不同的地方在於:有機薄膜電晶體100d還包含鈍化層210與畫素電極220。鈍化層210覆蓋閘極160與閘極絕緣層150,而畫素電極220位於鈍化層210上。 FIG. 5 is a cross-sectional view of an organic thin film transistor 100d according to an embodiment of the present invention. The organic thin film transistor 100d includes a substrate 110, a source / drain layer 120, a first buffer layer 130, a semiconductor layer 140, a gate insulating layer 150, a gate 160, a protective layer 170, a photoresist layer 180, and a barrier layer 190. And the second buffer layer 230. The difference from the embodiment in FIG. 4 is that the organic thin film transistor 100d further includes a passivation layer 210 and a pixel electrode 220. The passivation layer 210 covers the gate electrode 160 and the gate insulation layer 150, and the pixel electrode 220 is located on the passivation layer 210.

雖然本發明已以實施方式揭露如上,然其並非用 以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope shall be determined by the scope of the attached patent application.

Claims (10)

一種有機薄膜電晶體,包含:一基板;一源極/汲極層,位於該基板上,該源極/汲極層具有一源極區與一汲極區;一第一緩衝層,位於該源極區與該汲極區之間,且覆蓋至少部分的該源極區與至少部分的該汲極區;一半導體層,位於該源極/汲極層與該第一緩衝層上,且該半導體層具有大致均勻的厚度,其中該第一緩衝層位於該半導體層、該源極區、該汲極區與該基板之間;一閘極絕緣層,覆蓋該源極/汲極層與該半導體層;以及一閘極,位於該閘極絕緣層上,且該閘極絕緣層的一部分位於該閘極與該半導體層之間。An organic thin film transistor includes: a substrate; a source / drain layer on the substrate; the source / drain layer has a source region and a drain region; a first buffer layer is disposed on the substrate; Between the source region and the drain region, and covering at least a portion of the source region and at least a portion of the drain region; a semiconductor layer on the source / drain layer and the first buffer layer, and The semiconductor layer has a substantially uniform thickness, wherein the first buffer layer is located between the semiconductor layer, the source region, the drain region and the substrate; a gate insulating layer covering the source / drain layer and The semiconductor layer; and a gate electrode located on the gate insulation layer, and a part of the gate insulation layer is located between the gate electrode and the semiconductor layer. 如請求項1所述的有機薄膜電晶體,更包含:一保護層,沿該半導體層設置,其中該半導體層位於該保護層與該源極/汲極層之間,及該保護層與該第一緩衝層之間。The organic thin film transistor according to claim 1, further comprising: a protective layer disposed along the semiconductor layer, wherein the semiconductor layer is located between the protective layer and the source / drain layer, and the protective layer and the Between the first buffer layers. 如請求項2所述的有機薄膜電晶體,更包含:一光阻層,位於該保護層上,且位於該閘極絕緣層與該保護層之間。The organic thin film transistor according to claim 2, further comprising: a photoresist layer on the protective layer and between the gate insulating layer and the protective layer. 如請求項1所述的有機薄膜電晶體,更包含:一阻障層,位於該基板上,其中該第一緩衝層位於該半導體層、該源極區、該汲極區與該阻障層之間。The organic thin film transistor according to claim 1, further comprising: a barrier layer on the substrate, wherein the first buffer layer is located on the semiconductor layer, the source region, the drain region, and the barrier layer. between. 如請求項4所述的有機薄膜電晶體,更包含:一第二緩衝層,位於該阻障層上,其中該第一緩緩衝層位於該半導體層、該源極區、該汲極區與該第二緩衝層之間。The organic thin film transistor according to claim 4, further comprising: a second buffer layer located on the barrier layer, wherein the first buffer layer is located on the semiconductor layer, the source region, the drain region, and Between the second buffer layers. 如請求項1所述的有機薄膜電晶體,其中該源極區具有相對的一第一表面與一第二表面,且具有鄰接該第一表面與該第二表面的一側壁,該第一表面朝向該基板,且該側壁與該第一表面夾鈍角。The organic thin film transistor according to claim 1, wherein the source region has a first surface and a second surface opposite to each other, and has a sidewall adjacent to the first surface and the second surface, the first surface It faces the substrate, and the side wall is at an obtuse angle with the first surface. 如請求項6所述的有機薄膜電晶體,其中該第一緩衝層具有一中央部與一延伸部,該中央部位於該源極區與該汲極區之間,該延伸部位於該源極區的該第二表面上。The organic thin film transistor according to claim 6, wherein the first buffer layer has a central portion and an extension portion, the central portion is located between the source region and the drain region, and the extension portion is located on the source electrode Area on the second surface. 如請求項7所述的有機薄膜電晶體,其中至少部分的該源極區位於該延伸部與該中央部之間。The organic thin film transistor according to claim 7, wherein at least part of the source region is located between the extension portion and the central portion. 如請求項6所述的有機薄膜電晶體,其中該第一緩衝層接觸該源極區的該側壁。The organic thin film transistor according to claim 6, wherein the first buffer layer contacts the sidewall of the source region. 如請求項1所述的有機薄膜電晶體,其中該汲極區具有相對的一第一表面與一第二表面,且具有鄰接該第一表面與該第二表面的一側壁,該第一表面朝向該基板,且該側壁與該第一表面夾鈍角。The organic thin film transistor according to claim 1, wherein the drain region has a first surface and a second surface opposite to each other, and a sidewall adjacent to the first surface and the second surface, the first surface It faces the substrate, and the side wall is at an obtuse angle with the first surface.
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