TWI658688B - Improved quasi radon source converter - Google Patents

Abstract

An improved quasi-Z source converter includes: a quasi-Z source converter circuit having an input terminal, four control terminals, and two output terminals. The input terminals are used for coupling with a DC voltage. The control terminal is used to receive four control signals to switch four switches to perform a commutation operation on the DC voltage to generate a first AC voltage. The two output terminals are used to output the first AC voltage. The four switches include a first upper arm switch, a second upper arm switch, a first lower arm switch, and a second lower arm switch; an inductor-capacitor filter is coupled to the two output terminals to connect the first An AC voltage performs a filtering operation to generate a second AC voltage to supply a load; and a digital controller for executing a firmware program, the firmware program includes: according to the second AC voltage and a desired The AC voltage performs an incremental proportional-integral-derivative operation to determine the value of an amplitude modulation coefficient m _a , where m _a is a positive real number, and the initial value of m _a is a preset value; change according to the quasi-Z source Voltage generation of Z impedance capacitor A boosting factor B, and a zero-state conduction factor B _duty generated according to the boosting factor B, where both B and B _duty are positive real numbers, and B _duty = (1/2) * (1-1 / B); and performing a modified space vector pulse width modulation operation by the amplitude modulation coefficient m _a and B _duty factor of the oN state to generate the four zero control signal, wherein the modified space vector pulse width modulation operation Including: when θ is between [0, π ], T ₂ = T * m _a * sin θ , T _sh = B _duty * T, and T ₀ = TT ₂ -T _sh ; when θ is between [ π , 2 π ], T ₁ = T * m _a * sin ( θ - π ), T _sh = B _duty * T, and T ₀ = TT ₁ -T _sh , where θ is a phase angle of the second AC voltage , T is one of the four control signal switching cycles; and when θ is between [0, π ], (the first upper arm switch, the first lower arm switch, the second upper arm switch, said second lower arm switching) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) state for T _sh (turned oN, OFF, oN) state / 2, Length T _2/2 (oN, OFF, OFF, oN) state for T _0/2 of (ON, OFF, ON, OFF) state for the T state _2/2 (ON, OFF, OFF, ON), the duration T _SH (turned ON, OFF, ON) / 2 state and duration T _0/4 is (OFF, oN, OFF, oN) state, and when the [π, 2 π] θ between the (upper arm of the first switch, the first lower arm switch, the second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) state for T _sh (conduction / 2 , ON, OFF, ON state, T _1/2 (ON, OFF, OFF, ON) state, T _0/2 (ON, OFF, ON, OFF) state , A state of T _1/2 (on, off, off, on), a state of T _Sh / 2 (on, on, off, on) and a state of T _0/4 (off, (On, off, on).

Description

Improved quasi-Z source converter

The invention relates to a quasi-Z source converter, in particular to a quasi-Z source converter that performs an improved space vector pulse width modulation operation to improve the distortion of the output waveform and the conversion efficiency.

Energy is a very important resource for national development. In addition to supplying fuel and power sources for industrial production, it is also an indispensable resource in life. After the industrial revolution in the 18th century, petrochemical energy has become the main resource for national development. However, when people enjoy the benefits brought by petrochemical energy and push civilization to the peak, they also face problems such as energy shortages and global warming.

According to the statistics of the global power generation energy consumption distribution ratio in 2016, the world's main power generation energy is not renewable energy, of which the proportion of petrochemical fuel power generation and nuclear power generation is the most significant. However, petrochemical fuels are facing a shortage. Currently, in the renewable energy sector, hydropower accounts for the highest proportion. However, hydropower needs to flood a large area of land, leading to the destruction of the ecological environment. In order to obtain energy without harming the environment, each country is actively developing new alternative energy sources, and new alternative energy sources must have the characteristics of inexhaustibility and environmental harm. With the vigorous promotion of governments in many countries, many Renewable energy sources are growing rapidly. Among them, solar power generation and wind power generation are developing most rapidly. Solar energy and wind power are inexhaustible clean energy sources. The reduction of costs has also led to the increase in production scale and production technology. Therefore, how to effectively use renewable energy has become an important issue.

Renewable energy usually exists in the form of DC power. In order to connect to the grid and provide general household appliances, it needs to be converted into AC power with a certain frequency. Therefore, DC / AC converters are also not available in renewable energy power generation systems Missing link.

Traditional two-stage converters must be placed in a dead-time in the upper and lower arm switches to avoid the short-circuit problem caused by the upper and lower arm switches being turned on at the same time, but the dead-time will cause Distortion of output waveform. On the other hand, because the voltage source is not enough to provide the voltage required for the output, an additional DC / DC boost converter is necessary, but it also indirectly increases the cost and control of the traditional two-stage converter. In order to overcome the complex control strategy, in order to overcome the above-mentioned problems, ZSI (Z-Source Inverter, Z source inverter) and qZSI (quasi-Z-source inverter, quasi-Z source inverter) have been proposed.

Traditional non-isolated bridge current source and voltage source converters are converters that can only step up or step down, but cannot become step-up / step-down converters. ZSI (Z-Source Inverter) differs from traditional converters in that the circuit input has more Z impedance (Z Impedance) composed of two inductors and two capacitors. This Z impedance (Z Impedance) ) Allow the upper and lower arm power switches of the bridge converter to be turned on at the same time, so that there is no need to set a dead-time for the upper and lower arm control signals. The advantage of this control strategy is that it can reduce the harmonic distortion of the output waveform. And there is one more controllable variable that turns on the zero state to achieve the functions of raising and lowering voltage.

In addition, in terms of modulation strategy, SVPWM (Space-Vector Pulse Width Modulation) technology is the mainstream of waveform modulation for frequency converters. SVPWM (Space-Vector Pulse Width Modulation) (Modulation) technology and SPWM (Sinusoidal Pulse Width Modulation, Sinusoidal Pulse Width Modulation) technology have low harmonics, good low frequency performance and high voltage utilization, and have less switching loss at the same switching frequency Etc.

The current improvements to ZSI (Z-Source Inverter) can be divided into two parts, which are described as follows:

1. Regarding the method of improving the switching timing of the modulation switch to achieve a larger boost ratio, there are literatures that regulate the length of the conduction zero state vector in different intervals to analyze the boost ratio, switching voltage stress, and system conversion efficiency of different modulation methods. And total harmonic distortion; there are also literatures that maintain the same amount of inductor current ripple through asymmetric switching operation timing; there are also literatures that optimize the number of switching times according to different quadrant timings, thereby achieving the purpose of improving system conversion efficiency.

2. In terms of changing the circuit architecture to reduce circuit cost, volume and improve system conversion efficiency, in the low-power single-phase converter part, there is literature to simplify the general bridge ZSI (Z-Source Inverter, Z source converter). The circuit only needs two power switches to achieve AC output. Its advantage is that it reduces two power switches, so the conduction loss is reduced by half, and the cost is reduced accordingly. In terms of high-power single-phase converters, there are The literature only needs three power switches to reach the general bridge Z source. ZSI (Z-Source Inverter, Z source converter) has the same output result, so it has improved in efficiency and cost. There are also literatures that change the qZSI (quasi-Z-source inverter, quasi-Z source inverter) In order to achieve the purpose of improving the boost ratio under the same modulation strategy, it can also effectively reduce the voltage stress of the components.

However, there is still room for improvement in the conversion efficiency of the aforementioned documents. Therefore, a novel quasi-Z source converter is urgently needed in the art.

One object of the present invention is to disclose an improved quasi-Z source converter, which adopts full digital control, which is not only easy to implement, but also can implement the functions of a finite impulse response filter and a proportional-integral-derivative controller with fewer components.

Another object of the present invention is to disclose an improved quasi-Z source converter that performs a modified space vector pulse width modulation operation to modulate the zero-state conduction factor B _duty and the amplitude modulation coefficient of the control signal. m _a to achieve _a wide range of input voltage 130V ~ 200V voltage input and stable control of the output voltage function.

Yet another object of the present invention is to disclose an improved quasi-Z source converter that performs an improved space vector pulse width modulation operation so that the conduction zero state is concentratedly placed on the first arm during a positive half cycle. The switch is placed on the second arm switch during the negative half cycle, which can reduce the distortion of the output waveform when the input voltage increases or the load is reduced without increasing the number of switching times and improve the circuit conversion efficiency.

Another object of the present invention is to disclose an improved quasi-Z source converter with a conversion efficiency higher than 93.95% and a maximum of 96.6%. Compared with the conventional technology, its average conversion efficiency and voltage distortion rate are both 0.482%. And an improvement of 1.125%.

Yet another object of the present invention is to disclose an improved quasi-Z source converter whose total harmonic distortion is in addition to the above-mentioned four operating points except for input 150V, output 350W; input 140V, output 300W and 350W; and input 130V and output 250W. , The rest are better than the conventional technology, the largest difference can reach 2.739%, the average difference is 1.125%.

In order to achieve the foregoing object, an improved quasi-Z source converter is proposed, which has: a quasi-Z source converter circuit having an input terminal, four control terminals, and two output terminals. The input terminal is used for connection with a DC voltage coupling, the four control terminals are used to receive four control signals to switch four switches to perform a commutation operation on the DC voltage to generate a first AC voltage, and the two output terminals are used to output In the first AC voltage, the four switches include a first upper arm switch, a second upper arm switch, a first lower arm switch, and a second lower arm switch; an inductor-capacitor filter, and the two The output terminal is coupled to perform a filtering operation on the first AC voltage, thereby generating a second AC voltage to supply a load; and a digital controller for executing a firmware program, the firmware program includes: the second alternating voltage, and performs a desired AC voltage by an increment proportional - integral - derivative calculation to determine the value of a variable amplitude modulation coefficient m _a, wherein m _a is a positive real number, and m _a a predetermined initial value based Value; according to the quasi-Z source commutation circuit A Z impedance of the capacitor voltage to generate a boost factor B, and generates a ZERO turned on by the boosting factor B _Duty factor B, wherein B and B _Duty are both positive real numbers, and B _duty = (1/2) * ( 1-1 / B); and performing a modified space vector pulse width modulation operation by the amplitude modulation coefficient m _a and B _duty factor of the oN state to generate the four zero control signal, wherein the modified space The vector pulse width modulation operation includes: when θ is between [0, π ], T ₂ = T * m _a * sin θ , T _sh = B _duty * T, and T ₀ = TT ₂ -T _sh ; when When θ is between [ π , 2 π ], T ₁ = T * m _a * sin ( θ - π ), T _sh = B _duty * T, and T ₀ = TT ₁ -T _sh , where θ is the first A phase angle of two AC voltages, T is a switching period of the four control signals; and when θ is between [0, π ], (the first upper arm switch, the first lower arm switch, so said second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 is (oFF, oN, oFF, oN) state for T _sh / 2 (oN, oN, oFF open, conducting) state for T _2/2 (oN, OFF, OFF, ON) state for T _0/2 (ON, OFF, ON, OFF) state for T _2/2 (ON, OFF, OFF, ON) state for T _sh / 2 (ON, ON, OFF, ON) state and T _0/4 (OFF, ON, OFF, ON) state, and when θ is between [ π , 2 π ], make (All said first switch arm, lower arm of the first switch, the second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) State of T _sh / 2 (ON, ON, OFF, ON), state of T _1/2 (ON, OFF, OFF, ON), T _0/2 (ON) , OFF, ON, OFF) state, T _1/2 (ON, OFF, OFF, ON) state, T _sh / 2 (ON, ON, OFF, ON) state And the state of T _0/4 (OFF, ON, OFF, ON).

In an embodiment, the value of the phase angle starts from 0 and gradually increases by 2 π / m _f , where m _f = f _s / f _m , where f _s is the inverse of the switching period, and f _m is the The frequency of the second AC voltage.

In one embodiment, the digital controller includes a microprocessor.

In one embodiment, the digital controller performs a filtering operation on the second AC voltage with a finite impulse response filter before performing the proportional-integral-derivative operation on the second AC voltage.

In order to enable your reviewers to further understand the structure, characteristics, and purpose of the present invention, drawings and detailed descriptions of the preferred embodiments are attached below.

100‧‧‧quasi-Z source converter circuit

110‧‧‧Inductive-Capacitive Filter

120‧‧‧digital controller

200‧‧‧ load

FIG. 1 is a block diagram showing an embodiment of an improved quasi-Z source converter according to the present invention.

FIG. 2a is a schematic diagram of a circuit structure of a quasi-Z source converter.

FIG. 2b is a schematic diagram of an equivalent circuit of a quasi-Z source converter operating in a conducting zero state.

FIG. 2c is a schematic diagram of an equivalent circuit of a quasi-Z source converter operating in a non-conducting zero state.

Fig. 3a shows the line-to-line voltage and structure diagram of the space vector coordinate system with single-phase space vector pulse width modulation.

FIG. 3b shows a single-phase voltage vector diagram in which a two-dimensional coordinate of a single-phase space vector pulse width modulation is rotated to a one-dimensional coordinate system.

FIG. 4 is a schematic diagram of a single-phase full-bridge converter circuit architecture.

FIG. 5 is a voltage vector diagram of a single-phase Z-source converter.

FIG. 6 a is a voltage vector distribution diagram of a single-phase space vector pulse width modulation of a quasi-Z source converter of the conventional technology.

FIG. 6b illustrates a switching mode according to an embodiment of the present invention.

FIG. 6c illustrates a switching mode according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of a control signal of a single-phase space vector pulse width modulation of a quasi-Z source converter of the conventional technology.

FIG. 8 is a schematic diagram of a control signal according to the present invention.

FIG. 9a is a flowchart of a main program for firmware design of the present invention.

FIG. 9b shows a flowchart of an ADC interrupt subroutine and a PWM interrupt subroutine of the firmware design of the present invention.

FIG. 10 is a flowchart of the calculation of the conduction zero state of the firmware design of the present invention.

FIG. 11 shows a flowchart of the firmware design of the present invention.

FIG. 12 shows a flow chart of incremental proportional-integral-derivative control of the firmware design of the present invention.

FIG. 13 a shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 110W.

FIG. 13b shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 150W.

FIG. 13c shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 200W.

FIG. 13d shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 250W.

FIG. 13e shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 300W.

FIG. 13f shows waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 170V and 350W.

FIG. 14a is a waveform diagram of the output voltage V _o and the output current I _{o of the} present invention at 170V and 110W.

FIG. 14b is a waveform diagram of the output voltage V _o and the output current I _o at 170V and 150W according to the present invention.

FIG. 14c is a waveform diagram of the output voltage V _o and the output current I _{o of the} present invention at 170V and 200W.

FIG. 14d is a waveform diagram of the output voltage V _o and the output current I _o at 170V and 250W according to the present invention.

FIG. 14e is a waveform diagram of the output voltage V _o and the output current I _o at 170V and 300W according to the present invention.

FIG. 14f is a waveform diagram of the output voltage V _o and the output current I _{o of the} present invention at 170V and 350W.

Figure 15a shows the waveforms of the output voltage V _o and output current I _{o of the} conventional technology at 200V and 110W (light load).

Figure 15b shows the waveforms of the output voltage V _o and output current I _{o of the} conventional technology at 200V and 350W (full load).

FIG. 16a is a waveform diagram showing the output voltage V _o and the output current I _{o of the} present invention at 200V and 110W (light load).

FIG. 16b is a waveform diagram of the output voltage V _o and the output current I _{o of the} present invention at 200 V and 350 W (full load).

FIG. 17 a shows the waveforms of the DC link voltage V _i and the output voltage V _o of the switching signals V _GS1 ~ V _GS4 at the non-zero crossing at 170V and output 300W in the conventional technology.

FIG. 17b shows the waveforms of the DC link voltage V _i and the output voltage V _o of the switching signals V _GS1 ~ V _GS4 at the zero crossing at 170V and 300W of the conventional technology.

FIG. 18 is a waveform diagram of the DC link voltage V _i and the output voltage V _o of the switching signals V _GS1 to V _GS4 at the zero crossing at 170V and output 300W according to the present invention.

FIG. 19a illustrates a conversion efficiency diagram of the conventional technique.

FIG. 19b is a graph showing the total harmonic distortion of the output voltage of the conventional technique.

FIG. 19c illustrates a conversion efficiency graph of the present invention.

FIG. 19d is a graph showing the total harmonic distortion of the output voltage of the present invention.

FIG. 19e illustrates the trend of the percentage difference in conversion efficiency between the present invention and the conventional technology.

FIG. 19f shows the trend of the percentage difference of the total harmonic distortion between the present invention and the conventional technology.

Please refer to FIG. 1, which illustrates a block diagram of an embodiment of an improved quasi-Z source converter according to the present invention.

As shown in the figure, the improved quasi-Z source converter has a quasi-Z source converter circuit 100, an inductor-capacitor filter 110, and a digital controller 120.

The quasi-Z source converter circuit 100 has an input terminal, four control terminals, and two output terminals. The input terminals are used for coupling with the DC voltage V _in . The four control terminals are used for receiving four control signals S _1. -S ₄ switches four switches to perform a commutation operation on the DC voltage V _in to generate a first AC voltage V _ac1 . The two output terminals are used to output the first AC voltage V _ac1 . The four switches include a first upper arm switch, a second upper arm switch, a first lower arm switch, and a second lower arm switch.

The inductor-capacitor filter 110 is coupled to the two output terminals to perform a filtering operation on the first AC voltage V _ac1 to generate a second AC voltage V _o to supply a load 200.

The digital controller 120 is configured to execute a firmware program. The firmware program includes: performing an incremental proportional-integral-derivative operation to determine an amplitude modulation coefficient according to the second AC voltage V _o and a desired AC voltage. _a value of m _a , where m _a is a positive real number, and the initial value of m _a is a preset value; a boosting factor B is generated according to the voltage V _C1 of the Z impedance capacitor of the quasi-Z source commutation circuit 100, and A zero-state conduction factor B _{duty is} generated according to the boosting factor B, where B and B _duty are both positive real numbers, and B _duty = (1/2) * (1-1 / B); and the amplitude modulation coefficient m _a and the zero-state conduction factor B _duty perform an improved space vector pulse width modulation operation to generate the four control signals, wherein the improved space vector pulse width modulation operation includes: when θ is between [ 0, π ], T ₂ = T * m _a * sin θ , T _sh = B _duty * T, and T ₀ = TT ₂ -T _sh ; when θ is between [ π , 2 π ], T ₁ = T * m _a * sin ( θ - π ), T _sh = B _duty * T, and T ₀ = TT ₁ -T _sh , where θ is a phase angle of the second AC voltage V _o and T is the One of the four control signals switching period; and when θ is between [0 When [pi]], so that (the first switch arm, lower arm of the first switch, the second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 (open , oN, OFF, oN) state for T _sh state (oN, oN, OFF, oN) / 2 for T _2/2 (oN, OFF, OFF, oN) state, Length T _0/2 (oN, OFF, oN, OFF) state for the T state _2/2 (oN, OFF, OFF, oN), and (conduction, the conduction duration T _SH / 2 , Off, and on) state and T _0/4 (off, on, off, and on) state, and when θ is between [ π , 2 π ], (the first upper arm switch , the first lower arm switch, the second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) state for T _sh / 2 (on, off, off, on) state, T _1/2 (on, off, off, on) state, T _0/2 (on, off, on) state , OFF) state for T _1/2 (ON, OFF, OFF, ON) state for T _sh (turned ON, OFF, ON) state / 2 and duration T _0/4 is (OFF, ON, OFF, ON) status.

The value of the phase angle is, for example, but not limited to, starting from 0 and gradually increasing by 2 π / m _f , where m _f = f _s / f _m , where f _s is the inverse of the switching period, and f _m is the first two frequency AC voltage V _o.

The digital controller 120 comprises, for example, but not limited to a microprocessor (not shown in the drawing), the digital controller 120 in proportion to the execution of the second alternating voltage V _o - integral - differential line prior to the first operation A finite impulse response filter performs a filtering operation on the second AC voltage V _o .

The principle of the present invention will be described below: Circuit structure and steady state analysis of a quasi-Z source converter: Please refer to FIGS. 2a to 2c together, where FIG. 2a is a schematic diagram of the circuit structure of the quasi-Z source converter. 2b shows an equivalent circuit diagram of a quasi-Z source converter operating in a conducting zero state, and FIG. 2c shows an equivalent circuit diagram of a quasi-Z source converter operating in a non-conducting zero state.

As shown in Figure 2a, qZSI (quasi-Z-source inverter) is a structure derived from ZSI (Z-Source Inverter). The circuit is mainly composed of two inductors. L ₁ and L ₂ are composed of two capacitors C ₁ and C ₂ and four power switches S ₁ to S ₄ .

qZSI (quasi-Z-source inverter) has the characteristics that the DC side and the power stage share the same ground, which can effectively reduce the safety and electromagnetic interference problems caused by leakage current. In the architecture, the inductance L at the input end ₁ Makes the input current a continuous current. This feature reduces the voltage stress on the input voltage source and is beneficial to extending the life of the input voltage source. Therefore, the qZSI (quasi-Z-source inverter) architecture is particularly suitable for regeneration. Energy generation system, and in the Z impedance (Z Impedance) part, the capacitance C ₂ withstand voltage value decreases, so the reliability of the capacitor can be improved. The circuit architecture can adjust the zero-state conduction factor B _duty and the amplitude modulation coefficient m _a In order to achieve the purpose of using a single-stage architecture to achieve boost, buck and output voltage regulation.

The single-phase qZSI (quasi-Z-source inverter) circuit operation is mainly divided into two states: the conducting zero state and the non-conducting zero state. The operation principle is described as follows: As shown in Figure 2b, In the conduction zero state, let the time occupied by this mode in the switching period T be T _sh , and the following equation can be derived.

V _L1 = V _DC + V _C2 (1)

V _L2 = V _C1 (2)

V _i = 0 (3)

I _C1 = -I _L2 (4)

I _C2 = -I _L1 (5)

Shown in Figure 2c, in a non-conducting state to zero, so that this pattern within the switching cycle time T occupied _NSH T, the following equation can be deduced.

V _L1 = V _DC -V _C1 (6)

V _L2 = -V _C2 (7)

V _i = V _C1 + V _C2 (8)

I _C1 = I _L1 -I _L2 + I _C2 (9)

I _C2 = I _L2 -I _i (10)

After substituting equation (10) into equation (9), equation (11) can be obtained.

I _C1 = I _L1 -I _i (11)

Because the switching period T = T _sh + T _nsh , the average inductor voltage and capacitor current of one cycle can be expressed by the following equation.

among them , . It is known from the volt-second balance that the average value of the inductor voltage of equations (12) and (13) is 0 under steady state, so the following equation can be obtained.

V _DC = ( -V _{C 2} ) D _sh + V _{C 1} D _nsh (16)

Substituting equation (17) into equation (16) gives equation (18).

Substituting equation (18) back to equation (17) gives equation (19).

Substituting equations (18) and (19) into equation (8), the peak voltage at the DC link end can be obtained This is shown in equation (20).

Among them, B is a boost factor, expressed as . If controlled by SPWM (Sinusoidal Pulse Width Modulation), the peak voltage of the output This is shown in equation (21).

Where m _a is the amplitude modulation coefficient, which can be expressed as , Is the amplitude of the triangle wave, Controls the amplitude of the sine wave signal.

Control strategy of space vector pulse width modulation applied by the present invention : SVPWM (Space-Vector Pulse Width Modulation, space vector pulse width modulation) applied by the present invention refers to a new coordinate axis through an appropriate transformation matrix Finding the vector in the base space, compared with the sinusoidal pulse width modulation (SPWM) technology, it has low harmonics, good low frequency performance and high voltage utilization, and it has better performance at the same switching frequency. Small switching loss and other advantages.

Three-phase SVPWM (Space-Vector Pulse Width Modulation) technology applied to ZSI (Z-Source Inverter, Z source converter) and the conventional technology VSI (voltage source inverter, voltage source) Comparing the three-phase SVPWM (Space-Vector Pulse Width Modulation) technology, they all have the same voltage vector. The difference is that ZSI (Z-Source Inverter) has Voltage vector to turn on the zero state.

In addition, due to the application of single-phase ZSI (Z-Source Inverter, Z-source inverter) and three-phase ZSI (Z-Source Inverter, Z-source inverter) SVPWM (Space-Vector Pulse Width Modulation) The voltage vector of the width modulation is different from the base space vector. It is first discussed that based on the three-phase SVPWM (Space-Vector Pulse Width Modulation) technology, a single-phase power supply and a single-phase PWM are used. (Pulse Width Modulation) analysis of the space voltage vector of the converter, and then applying SVPWM (Space-Vector Pulse Width Modulation) technology to qZSI (quasi-Z- source inverter).

Principle of space vector pulse width modulation for single-phase inverters: Because the voltage vector is different from the base space vector, the voltage vector of the three-phase SVPWM (Space-Vector Pulse Width Modulation) cannot be directly changed Applied directly to single-phase SVPWM (Space-Vector Pulse Width Modulation), the voltage vector for single-phase must first be derived according to the same concept. The output line voltage of single-phase full-bridge architecture is Equation (22) is shown.

Taking time t as a parameter, a two-dimensional space voltage vector u = [ u _AB , u _BA ] ^{T is} formed by equation (22), where [] ^T represents a transposed matrix.

Please refer to FIGS. 3a to 3b together, where FIG. 3a shows the line-to-line voltage and structure diagram of the space vector coordinate system of single-phase space vector pulse width modulation, and FIG. 3b shows the single-phase space vector pulse width Single-phase voltage vector diagram of the modulated two-dimensional coordinate rotation to a one-dimensional coordinate system.

When t is an arbitrary number, the vector u forms a plane voltage vector in a two-dimensional plane coordinate system, as shown in FIG. 3a. Similar to the three-phase space voltage vector, because u _AB + u _BA = 0, the single-phase space voltage vector u all falls on the plane straight line x + y = 0 . Vector space V of all vectors _u R u is composed of a ^{2-dimensional} linear subspace. Therefore, the three-dimensional spatial coordinate rotation transformation can be used to take the unit vectors in the positive directions of the α and β axes in Figure 3a as two new bases ( y ₁ , y ₂ ), as shown in equation (23), where [] ^T indicates the conversion Transposed matrix.

Among them, the base y ₂ is the unit normal vector of the line where V _u is located, and the coordinate component on the y ₂ axis under the new base will be zero. Since the amount of projection on the β axis is zero, the two-dimensional space voltage vector u = [ u _AB , u _BA ] ^{T of} equation (22) is converted to a one-dimensional space voltage vector, and the basis ( e ₁ , e ₂ ) is The transformation matrix T _{ab-α β of the} new base ( y ₁ , y ₂ ) is shown in equation (24), and the voltage vector of the new coordinate system is shown in equation (25).

( y ₁ , y ₂ ) = ( e ₁ , e ₂ ) T (24)

The conversion relationship between the single-phase space voltage vector u and the α and β planes is shown in equation (26).

Please refer to FIG. 4, which illustrates a schematic diagram of a single-phase full-bridge converter circuit architecture. As shown in the figure, the line-to-line voltage is shown in equation (27).

Among them, V _dc represents the DC power supply, a and b represent the switching state variables of the upper arm switches of each arm, non-zero is 1, and 1 indicates that the upper arm switch is on and the lower arm switch is off, and vice versa.

The switching state and output voltage of the single-phase VSI (voltage source inverter) are shown in Table 1. The vector v = [ V _ab , V _ba ] ^T forms four discrete voltage vectors in space, two of which are zero voltage vectors, S _a and S _b are two upper arm switches, V _ab and V _ba are corresponding line-to-line voltages respectively, and V _a is a vector voltage converted to the α axis.

Using T _{ab-α β of} equation (25), the voltage vector can be transformed into the new coordinate system α β plane. In the α reference coordinate axis, all the voltage vectors ( V ₀ ~ V ₃ ) have zero components on the β axis, so the voltage The vector [ V _α V _β ] ^T can be reduced to a one-dimensional vector [ V _α 0] ^T , as shown in equation (28), where [] ^T represents a transposed matrix.

On the α axis, two non-zero vectors V ₁ and V ₂ and two zero vectors V ₀ and V _{3 are used} . These four discrete voltage vectors constitute a one-dimensional coordinate voltage vector diagram as shown in FIG. 3b.

Based on the concept of space vectors, the output voltage of a single-phase full-bridge converter can be synthesized by a linear combination of one active vector and the remaining zero vectors, as shown in equation (29).

The amplitude modulation coefficient ma of _a single-phase converter can be defined as the ratio of the length of the desired output voltage vector to the length of the converter output voltage vector, as shown in equation (30).

Interval judgment of single-phase qZSI space vector pulse width modulation: SVPWM (Space-Vector Pulse Width Modulation) for single-phase ZSI (Z-Source Inverter) The control signal is similar to the SVPWM (Space-Vector Pulse Width Modulation) of the traditional single-phase VSI (voltage source inverter), but in the control aspect, the conduction zero-state vector V _{sh is added.} , That is, the on-time zero time T _sh for the upper and lower switches of one arm on the switching sequence at the same time. The on-state zero parameter T _sh is controlled by the boosting factor B, so it is used for single-phase ZSI ( The output voltage vector of Z-Source Inverter will be slightly different from equation (29), as shown in equation (31)

The on-state vectors V _sh1 , V _sh2 , V _sh3 , V _sh4 , V _sh5 and their corresponding action times T _sh are added to the equation.

Please refer to FIG. 5, which shows a voltage vector diagram of a single-phase Z-source converter.

As shown in the figure, the choice of active vectors V ₁ and V ₂ depends on the phase angle θ ( θ = ωt ), when 0 θ when selected V ₂ [pi]; [pi] when θ At 2π , V ₁ is used , and the action time of different voltage vector states is calculated according to these two conditions.

Interval 1: When 0 θ At π , the V ₂ active vector is used, and equation (32) is obtained from FIG. 5.

Combining equation (21), equation (22), and equation (26) gives equation (33).

The switching state and output voltage results are shown in Table 2.

And V ₂ can be expressed as equation (34).

among them It indicates the peak value of the DC link of the Z impedance (Z Impedance) output.

Substituting equation (33) and equation (34) into equation (32) gives equation (35).

Interval 2: When π θ At 2 π , the V ₁ active vector is used, and equation (36) can be obtained from Fig. 3b.

Substituting equation (33) and equation (34) into equation (36) gives equation (37).

Judgment of switching timing sequence interval for single-phase space vector pulse width modulation of quasi-Z source converter: It can be known from three-phase SVPWM (Space-Vector Pulse Width Modulation) technology. The position distribution of the voltage vector time of the current transformer can be used to obtain various SVPWM (Space-Vector Pulse Width Modulation) technologies that optimize the switching timing. This view can also be applied to single-phase SVPWM (Space- Vector Pulse Width Modulation).

In addition, a single-phase qZSI (quasi-Z-source inverter) has a conduction zero-state vector V _sh and its action time T _sh , so the vector distribution design is more diverse, and its placement method can be They are classified as symmetric and asymmetric.

Because the asymmetric vector distribution is likely to cause higher total harmonic distortion, there are many different vector distribution modes in the symmetric type. The three different switching timings in the symmetric type are discussed below, which are qZSI ( quasi-Z-source inverter (quasi-Z source inverter) single-phase SVPWM (Space-Vector Pulse Width Modulation) and the vector distribution design of the switch mode of the two embodiments of the present invention, The classification is based on the number of switching times of a single switching cycle.

Please refer to FIGS. 6a to 6c together, where FIG. 6a shows a voltage vector distribution diagram of a single-phase space vector pulse width modulation of a quasi-Z source converter of conventional technology, and FIG. 6b shows one of the inventions The switching mode of the embodiment, FIG. 6c illustrates the switching mode of another embodiment of the present invention.

It can be seen from FIG. 6a that when switching from each vector to the next state, only one switch is required to achieve the state switching. Among them, the number of switching times of both FIG. 6b and FIG. 6c in a single switching cycle is half of that of FIG. 6a. However, the harmonic content of both Figs. 6b and 6c is greater than that of Fig. 6a.

The improved space vector pulse width modulation strategy proposed by the present invention: Please refer to FIG. 7, which shows a schematic diagram of a control signal for a single-phase space vector pulse width modulation of a quasi-Z source converter of a conventional technology.

As shown in the figure, the qZSI (quasi-Z-source inverter) of the conventional technology is used to control the on-time of the on-state to achieve the boost and buck functions. Therefore, the control will turn on the zero-state. The vector V _{sh is} respectively placed between the zero vector V ₀ and the active vector V ₁ (or V ₂ ) and between the active vector V ₁ (or V ₂ ) and the zero vector V ₃ .

The present invention adopts the staggered conduction zero state placement. In order to improve the temperature performance of the switch, the present invention places the conduction zero state on different arm switches at different timings. When the circuit operates in interval one, the conduction zero state is placed in the first The arm switch, when the circuit operates in the interval two, places the conducting zero state on the second arm switch.

Please refer to FIG. 8, which is a schematic diagram of a control signal according to the present invention.

As shown in the figure, it can be known that the conduction zero state V _sh between the active vector V ₂ (or V ₁ ) and the zero vector V ₃ is removed without increasing the number of switching times. In addition, it is also removed The conduction zero state is embedded between the active vector V ₂ (or V ₁ ) of one arm and the zero vector V ₀ according to different intervals.

The control system architecture and firmware programming of the present invention : The present invention actually makes a 350W qZSI (quasi-Z-source inverter, quasi-Z source inverter). The system uses full digital control, which is mainly divided into two parts. The first part It is the hardware circuit architecture of the power stage. The second part is the system controller. It is controlled by the dsPIC33FJ16GS502 microprocessor introduced by Microchip. The input capacitor voltage V _{C1 is} read and the appropriate boost is calculated by the subroutine. Factor B; and the output voltage of the feedback converter, which is adjusted by the controller to adjust the amplitude modulation coefficient m _{a of the} space vector modulation, thereby realizing the function of adjusting the output voltage.

The system part captures the voltage of the quasi-Z impedance capacitor C ₁ and the converter output voltage signal. After analog-to-digital conversion and digital filter filtering, the signal is passed through digital proportional-integral-derivative (proportional-integral) and derivative (PID) control and SVPWM (Space-Vector Pulse Width Modulation) control signal operation of qZSI (quasi-Z-source inverter) to generate control signals To drive the power switch, in this way, the output voltage of qZSI (quasi-Z-source inverter) is controlled to achieve the purpose of stabilizing the output voltage.

In terms of firmware programming, the present invention uses a dsPIC33FJ16GS502 microprocessor to implement a finite impulse response (FIR) filter, incremental proportional-integral-derivative (proportional-integral and derivative, PID) controller, converter output voltage control and switch control signal generation.

Please refer to FIGS. 9a to 9b together, wherein FIG. 9a shows a flowchart of the main routine of the firmware design of the present invention, and FIG. 9b shows a flowchart of the ADC interrupt subroutine and the PWM interrupt subroutine of the firmware design of the present invention. .

The firmware design of the present invention is divided into three parts: a main routine, an ADC interrupt subroutine and a PWM interrupt subroutine.

As shown in Figure 9a, in the main program part, the program will first set the variable name, initialize the register, set the initial value of the register, set the input and output ports, and enable the module (PWM, ADC, TIMER, etc. ) And interrupt vector settings, then enter an infinite loop and wait for the interrupt vector to occur.

Shown in Figure 9b, the ADC interrupt subroutine filtering part is divided into sampling, adjust the amplitude modulation coefficient and the ratio of m _a Incremental - Integral - Derivative (proportional-integral and derivative, PID ) of operation.

Integrating the PWM interrupt subroutine zero conduction state B _duty factor of the amplitude modulation coefficient m _a to generate the control signal.

Please refer to FIG. 10, which illustrates a flowchart of conducting zero-state calculation of the firmware design of the present invention.

The invention has the functions of step-up and step-down. It can be known from equation (18) that the capacitor voltage V _{C1 is} proportional to the input voltage V _dc .

As shown in the figure, the present invention reads the output voltage and the capacitor voltage V _C1 at the input terminal, and calls the FIR subroutine to perform digital filtering to filter the signal noise, and calculates the appropriate boost factor in the PWM interrupt program. B , then the boosting factor B is scaled to the designed zero-state conduction factor B _duty (≡T _sh / T) to achieve an appropriate boosting ratio, and finally the calculation result of the zero-state conduction factor B _duty is output for Modified space vector pulse width modulation strategy operation.

The SPWM (Sinusoidal Pulse Width Modulation) of the conventional technology has a frequency modulation index ( m _f) , which is defined as the carrier frequency f _s (Carrier Frequency, also known as the switching frequency Switching Frequency). ) And the sine wave modulation frequency f _m , as shown in equation (38).

Among them, m _f is the number of segments to be divided by a 360 ° circle. Generally speaking, the larger m _{f is} , the smaller the angle of division is, and the better the resolution of the sine wave of the AC output is. Therefore, it is desirable to improve the frequency modulation ratio without considering the switching loss of the inverter. However, when the actual situation is implemented by a microprocessor, there will be some restrictions; for example, the calculation speed of the microprocessor, the internal memory size used for the sine look-up table and control program method, the character length and the quantization error caused by digital sampling Etc., so do not use a sine lookup table with too fine precision.

The switching frequency f _s of the present invention is 15 kHz, and the fundamental frequency of the output sine wave is 60 Hz. According to the above-mentioned frequency modulation ratio relationship, the ratio m _f is calculated to be 250. The program divides a 360 ° circle into 250 sections, and plans an imaginary signal θ in the program. The initial value of θ is 0 full grid is 250. In the entire sine table of 250 points, each interruption is used to read the sine. The value of the table.

Control signal generation of the improved space vector pulse width modulation strategy of the present invention : Please refer to FIG. 11, which illustrates a flowchart of the firmware design of the present invention.

As shown in the figure, after the main program is initialized, the system will enter an infinite loop. When a PWM interrupt occurs, first determine the current phase angle θ to determine the interval, and then read the amplitude modulation coefficient m calculated by the previous ADC interrupt subroutine. _a, calculate the voltage vector acting at different times _{(T 1, T 2, T} 0, T sh), then determines the oN time of the different switches.

Wherein, due to considerations of scaling parameters, product operation of equation (35) and equation (37) m _a trigonometric function of the realization, as shown in equation (39) shown in FIG.

Where, equation (39) in the (m _{a duty} -B) partly because the amplitude of the modulation coefficient m _a period of one week and the zero-state conduction _duty factor of the space B will be restricted to one another, so this equation also This prevents these two parameters from overlapping each other.

After the new duty cycle is calculated, the zero-state conduction factor B _duty calculated by the subroutine is placed in a specific arm according to different intervals, and the control signals V _GS1 ~ V _{GS4 of the} staggered conduction zero-state position can be obtained. The processor can achieve the function of stabilizing the system output voltage between the input voltage V _{in and} 130 ~ 200V.

The present invention uses incremental proportional-integral-derivative for digital control: Equation (40) is a continuous proportional-integral and derivative (PID) control algorithm.

Among them, K _p is the proportional gain, K _I is the integral gain, K _D is the differential gain, e is the system error amount, and t is the current time.

Because continuous proportional-integral and derivative (PID) cannot be directly implemented by a microprocessor, it is usually necessary to use a discretization method to sample and calculate, and then use the Euler integration method, differential approximate integration and differentiation method to discretize The proportional-integral and derivative (PID) control algorithm is shown in equation (41).

Among them, e (n) is the current system error amount, e (n-1) is the previous system error amount, and T is the sampling period.

If a digital microprocessor is used to implement the discrete proportional-integral and derivative (PID) control of equation (41), because it contains integral terms, considering that the memory width of the microprocessor is 16 bits, The numerical range that it can represent is limited, and in order to reduce the calculation amount of the microprocessor and improve the calculation efficiency, the present invention uses incremental proportional-integral and derivative (PID) for digital control, such as the equation ( 42).

△ u ( n ) = u ( n ) -u ( n -1) = K _P. [ e ( n ) -e ( n -1)] + K _I. e ( n ) + K _D. ( e ( n ) -2 e ( n -1) + e ( n (42)

Please refer to FIG. 12, which illustrates a flowchart of incremental proportional-integral-derivative control of the firmware design of the present invention.

As shown in the figure, ERROR ₀ is the current error value, ERROR ₁ is the previous error value, ERROR ₂ is the previous two error value, ERROR _(0-1) is (ERROR ₀ -ERROR ₁ ), and ERROR _{(0-2 * 1 + 2)} is ( ERROR ₀ -2 * ERROR ₁ + ERROR ₂ ). First subtract the output command value and the filter output value to get the error value ERROR ₀ , then to ERROR ₁ and ERROR ₂ respectively, and then calculate ERROR ₍₀₁₎ and ERROR _{(0-2 * 1 + 2)} , and multiply them in order. on K _P, K _I, K _D after adding, to obtain the output variation △ U, which is the original amplitude modulation coefficient m _a the sum of the output PID _OUT, if the output result is smaller than the minimum amplitude modulation system ( m _{a, min} ) or greater than the maximum amplitude modulation coefficient ( m _{a, max} ), the output results are equal to the minimum amplitude modulation coefficient or the maximum amplitude modulation coefficient, respectively, and the output results are finally stored in the planned variable space of m _a In order to provide a subsequent improved space vector pulse width modulation operation, the purpose of stabilizing the output voltage is achieved.

Experimental results and comparison of the present invention and the conventional technology: The following will test the physical circuit of the invention, and verify the conversion efficiency and total harmonic distortion (THD) of the present invention and the conventional technology based on the experimental results.

The specifications of the qZSI (quasi-Z-source inverter) developed by the present invention are shown in Table 3.

The inductor of the present invention is charged and discharged twice during the zero-state in one cycle, the frequency is 30kHz twice the switching frequency, and the zero-state conduction factor B _{duty is} set to 10%, the input voltage is 170V, and the Z impedance value of the present invention Select 2.2mH for the inductor, 470μF for the capacitor, 2.2μF for the output L _f -C _f low-pass filter capacitor, and 2mH for the inductor.

Please refer to FIG. 13a to FIG. 14f together, where FIG. 13a shows waveforms of the output voltage V _o and output current I _{o of the} conventional technology at 170V and 110W; FIG. 13b shows the output of the conventional technology at 170V and 150W Waveform diagram of voltage V _o and output current I _o ; FIG. 13c shows waveform diagram of output voltage Vo and output current I _{o of} conventional technology at 170V, 200W; FIG. 13d shows diagram of output voltage of conventional technique at 170V, 250W V _o and output current I _o waveform diagram; Figure 13e shows the conventional technology at 170V, 300W output voltage V _o and output current I _o waveform diagram; Figure 13f shows the conventional technology at 170V, 350W output voltage V _o and the output current I _o waveform diagram; FIG. 14a at 170V, the output voltage V _o and the output current I _o waveform diagram 110W of which illustrates the present invention; Figure 14b which illustrates the present invention in 170V, the output 150W of voltage V _o And output current I _o waveform diagram; FIG. 14c shows the output voltage V _o and output current I _{o of the} present invention at 170V, 200W; FIG. 14d shows the output voltage V _o and output of the present invention at 170V and 250W Waveform diagram of current I _o ; FIG. 14e shows waveform diagrams of output voltage V _o and output current I _{o of the} present invention at 170V and 300W; FIG. 14f is a waveform diagram of the output voltage V _o and the output current I _{o of the} present invention at 170V and 350W.

As shown in the figure, under the input technology of 170V and 110W ~ 350W in the conventional technology and the present invention, the waveforms of the output voltage V _o and output current I _o at light load have zero cross-point distortion. In some cases, the zero-crossing distortion of the present invention exists only at light load, and the zero-crossing distortion of the conventional technology, although it slows down as the load increases, still exists.

Please refer to FIG. 15a to FIG. 16b together, where FIG. 15a shows the waveforms of the output voltage V _o and the output current I _{o of the} conventional technology at 200V, 110W (light load); FIG. 15b shows the conventional technology at 200V , 350W (full load) output voltage V _o and output current I _o waveform diagram; Figure 16a shows the present invention at 200V, 110W (light load) output voltage V _o and output current I _o waveform diagram; Figure 16b The waveform diagrams of the output voltage V _o and output current I _{o of the} present invention at 200V and 350W (full load) are shown.

As shown in the figure, when the input is 200V, the conventional technology and the present invention have a zero-crossover distortion situation (that is, the circled part in the figure) regardless of 110W (light load) or 350W (full load). The distortion situation is more obvious, and it becomes more obvious as the input voltage increases.

In order to explore the cause of the distortion of the output voltage waveform at the zero-crossing point, and for the convenience of observation, the switching signals V _GS1 to V _GS4 and the DC link voltage V _i , and Output the voltage V _o waveform and observe the time axis.

Please refer to FIG. 17a to FIG. 17b together, wherein FIG. 17a shows the DC link voltage V _i and the output voltage V _o of the switching signals V _GS1 ~ V _GS4 at the non-zero crossing at 170V and 300W of the conventional technology. Waveform diagram; Figure 17b shows the DC link voltage V _i and output voltage V _o of the switching signals V _GS1 ~ V _GS4 at the zero crossing at 170V and output 300W in the conventional technology.

Among them, CH1 ~ CH6 are V _GS1 ~ V _GS4 , V _i and V _{o respectively} . As shown in Figure 17a, the width of the positive pulse wave of V _GS1 is greater than the width of the positive pulse wave of V _GS3 , so it is the positive half cycle (interval 1) of the output sine wave. At this time, the active vector is the action time T ₂ of V ₂ . When the chain voltage V _i is zero, it is the action time T _sh of the conducting zero state V _sh vector, and the rest are the zero vector action time T ₀ , where no energy is transmitted from the DC side to the AC side between T ₀ and T _sh .

As shown in FIG. 17b, the negative half-cycle of the designated area, the positive pulse width is greater than V _GS3 V _GS1 positive pulse width, the area marked in the positive half cycles, the positive pulse width is greater than V _GS1 of n V _GS3 The width of the pulse wave, so it is judged that the current time sequence is that the output sine wave has just entered from the negative half period (interval 2) to the zero crossing of the positive half period (interval 1).

According to the switching timing diagram of the conventional technology, it can be known that the gap between the edges of the positive pulses of V _GS2 and V _GS3 (in the range of the upright dotted line) is the active time T _{2 of} the active vector, and the positive pulses of V _GS1 and V _GS4 The gap between the edges (in the range of the upright dotted line) is the active time T _{1 of} the active vector. After entering the first cycle of the positive half cycle, the active vector active time T ₂ exists but is very short, corresponding to the red frame. The DC link voltage V _i is still zero, which means that no energy is transferred from the DC-side voltage to the AC-side, and it lasts 2 to 3 switching cycles, which affects the phenomenon that the output voltage waveform continues to be zero here.

Please refer to FIG. 18, which shows the waveforms of the DC link voltage V _i and the output voltage V _o of the switching signals V _GS1 to V _GS4 at zero crossing at 170V and output 300W according to the present invention.

As shown in the figure, the marked area of the negative half cycle can be seen. The positive pulse width of V _GS3 is greater than the positive pulse width of V _GS1 . In the marked area of the positive half cycle, the positive pulse width of V _GS1 is greater than that of V _GS3 . The width of the positive pulse wave, so it is judged that the current time sequence is that the output sine wave has just entered from the negative half cycle (interval 2) to the zero crossing of the positive half cycle (interval 1). Within the range of the upright dotted line is the active vector action time T ₁ or T _2. According to the control signal diagram of the present invention shown in FIG. 8, it can be known that the gap between the edges of the positive pulse wave V _GS1 and V _GS4 in the negative half cycle ( The range of the vertical dashed line) is the active time T ₁ of the active vector. At this time, the active vector time T ₁ exists but is very short. The DC link voltage V _i corresponding to CH5 is not zero, which means that the DC side voltage has energy transfer. To the AC side; in the first switching cycle after entering the positive half cycle, the gap between the edges of the positive pulses of V _GS2 and V _GS3 in the positive half cycle (the range of the upright dashed line) is the action time T _{2 of} the active vector, Even if it is very short, the V _i corresponding to CH5 is not zero, so the DC side voltage has energy transferred to the AC side at this time. This phenomenon explains that the output voltage has no zero-crossing distortion.

Please refer to FIG. 19a to FIG. 19f together, wherein FIG. 19a shows the conversion efficiency diagram of the conventional technology; FIG. 19b shows the total harmonic distortion diagram of the output voltage of the conventional technology; and FIG. 19c shows the present invention. Conversion efficiency diagram; Figure 191d shows the total harmonic distortion of the output voltage of the present invention; Figure 19e shows the trend of the percentage difference in conversion efficiency between the present invention and the conventional technology; Figure 19f shows the total of the present invention and the conventional technology Trend of percent difference in harmonic distortion.

As shown in Fig. 19a, the conversion efficiency of the conventional technology is higher than 93.61%, and the highest can reach 96.21%; and as shown in Fig. 19c, the conversion efficiency of the present invention is higher than 93.95%, and the highest can reach 96.6%. The conversion efficiency of the invention is better than the conventional technology.

As shown in FIG. 19e, the conversion efficiency of the present invention is better than the conventional technology, and can be improved by an average of 0.482%, up to 0.98%; as shown in FIG. 19f, the total harmonic distortion of the present invention is in addition to the input 150V and the output 350W; 140V, output 300W and 350W; and input 130V, output 250W above the four operating points, the rest are better than the conventional technology, the maximum difference can reach 2.739%, the average difference is 1.125%.

With the design disclosed above, the present invention has the following advantages: The improved quasi-Z source converter disclosed by the present invention adopts full digital control, which is not only easy to implement but also can implement a finite impulse response filter with fewer components. Function of proportional-integral-derivative controller.

The present invention discloses a modified quasi-Z-source inverter, which by performing a modified space vector pulse width modulation operation, the modulation control signal of the zero-state conduction factor B _duty and amplitude modulation coefficient m _a to reach the input A wide range of voltage input from 130V to 200V and the function of stably controlling the output voltage.

The improved quasi-Z source converter disclosed by the present invention performs a modified space vector pulse width modulation operation so that the conduction zero state is concentrated on the first arm switch during the positive half cycle and the negative half cycle When it is placed on the second arm switch, it can reduce the distortion of the output waveform when the input voltage rises or the load is reduced without increasing the number of switching times and improve the circuit conversion efficiency.

The improved quasi-Z source converter disclosed by the present invention has a conversion efficiency higher than 93.95% and a maximum of 96.6%. Compared with the conventional technology, its average conversion efficiency and voltage distortion rate are improved by 0.482% and 1.125% each. .

The total harmonic distortion of the improved quasi-Z source converter disclosed by the present invention is better than the above four operating points except input 150V, output 350W; input 140V, output 300W and 350W; and input 130V and output 250W. With the conventional technology, the maximum difference can reach 2.739%, and the average difference is 1.125%.

The disclosure of the present invention is a preferred embodiment, and any change or modification that is partly derived from the technical idea of the present invention and easily inferred by those skilled in the art will not depart from the scope of patent rights of the present invention.

To sum up, the present invention, regardless of the purpose, means and effect, is showing its technical characteristics that are quite different from the conventional ones, and its first invention is practical, and it also meets the patent requirements of the invention. Pray for granting patents at an early date.

Claims (2)

An improved quasi-Z source converter includes: a quasi-Z source converter circuit having an input terminal, four control terminals, and two output terminals. The input terminals are used for coupling with a DC voltage. The control terminal is used to receive four control signals to switch four switches to perform a commutation operation on the DC voltage to generate a first AC voltage. The two output terminals are used to output the first AC voltage. The four switches include a first upper arm switch, a second upper arm switch, a first lower arm switch, and a second lower arm switch; an inductor-capacitor filter is coupled to the two output terminals to connect the first An AC voltage performs a filtering operation to generate a second AC voltage to supply a load; and a digital controller for executing a firmware program, the firmware program includes: according to the second AC voltage and a desired The AC voltage performs an incremental proportional-integral-derivative operation to determine the value of an amplitude modulation coefficient m _a , where m _a is a positive real number, and the initial value of m _a is a preset value; change according to the quasi-Z source Voltage generation of Z impedance capacitor A boosting factor B, and a zero-state conduction factor B _duty generated according to the boosting factor B, where both B and B _duty are positive real numbers, and B _duty = (1/2) * (1-1 / B); and performing a modified space vector pulse width modulation operation by the amplitude modulation coefficient m _a and B _duty factor of the oN state to generate the four zero control signal, wherein the modified space vector pulse width modulation operation Including: when θ is between [0, π ], T ₂ = T * m _a * sin θ , T _sh = B _duty * T, and T ₀ = TT ₂ -T _sh ; when θ is between [ π , 2 π ], T ₁ = T * m _a * sin ( θ - π ), T _sh = B _duty * T, and T ₀ = TT ₁ -T _sh , where θ is a phase angle of the second AC voltage , T is one of the four control signal switching cycles; and when θ is between [0, π ], (the first upper arm switch, the first lower arm switch, the second upper arm switch, said second lower arm switching) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) state for T _sh (turned oN, OFF, oN) state / 2, Length T _2/2 (oN, OFF, OFF, oN) state for T _0/2 of (ON, OFF, ON, OFF) state for the T state _2/2 (ON, OFF, OFF, ON), the duration T _SH (turned ON, OFF, ON) / 2 state and duration T _0/4 is (OFF, oN, OFF, oN) state, and when the [π, 2 π] θ between the (upper arm of the first switch, the first lower arm switch, the second switch arm, the second lower arm switch) sequentially presented: duration T _0/4 is (OFF, oN, OFF, oN) state for T _sh (conduction / 2 , ON, OFF, ON state, T _1/2 (ON, OFF, OFF, ON) state, T _0/2 (ON, OFF, ON, OFF) state , A state of T _1/2 (on, off, off, on), a state of T _Sh / 2 (on, on, off, on) and a state of T _0/4 (off, ON, OFF, and ON) state; wherein the digital controller includes a microprocessor, and the digital controller executes the incremental proportional-integral-differential operation with a limited Impulse response filter performing a second alternating voltage to the filtering operation. The improved quasi-Z source converter according to item 1 of the scope of patent application, wherein the value of the phase angle starts from 0 and gradually increases by 2π / m _f , where m _f = f _s / f _m , f _s F _m is the frequency of the second AC voltage.